Texas Instruments CC430F6137, CC430F6135, CC430F6126, CC430F6125, CC430F5137 User Manual

...

ECCN 5E002 TSPA - Technology / Software Publicly Available

CC430F6137, CC430F6135, CC430F6127, CC430F6126, CC430F6125

CC430F5137, CC430F5135, CC430F5133

www.ti.com

SLAS554H –MAY 2009–REVISED SEPTEMBER 2013

MSP430™ SoC With RF Core

Check for Samples: CC430F6137, CC430F6135, CC430F6127, CC430F6126, CC430F6125, CC430F5137, CC430F5135, CC430F5133

FEATURES

• True System-on-Chip (SoC) for Low-Power Wireless Communication Applications

• Wide Supply Voltage Range: Core

3.6 V Down to 1.8 V

• Ultralow-Power Consumption: – CPU Active Mode (AM): 160 µA/MHz – Standby Mode (LPM3 RTC Mode): 2.0 µA 389 MHz to 464 MHz, and 779 MHz to – Off Mode (LPM4 RAM Retention): 1.0 µA – Radio in RX: 15 mA, 250 kbps, 915 MHz

• MSP430 System and Peripherals – 16-Bit RISC Architecture, Extended

Memory, up to 20-MHz System Clock

– Wake Up From Standby Mode in Less

Than 6 µs

– Flexible Power-Management System With

SVS and Brownout – Unified Clock System With FLL – 16-Bit Timer TA0, Timer_A With Five

Capture/Compare Registers – 16-Bit Timer TA1, Timer_A With Three

Capture/Compare Registers – Hardware Real-Time Clock (RTC) – Two Universal Serial Communication

Interfaces

– USCI_A0 Supports UART, IrDA, SPI Listen-Before-Talk Systems)

– USCI_B0 Supports I2C, SPI – Digital RSSI Output – 12-Bit Analog-to-Digital Converter (ADC) – Suited for Systems Targeting Compliance

With Internal Reference, Sample-and-Hold, With EN 300 220 (Europe) and

and Autoscan Features (CC430F613x and FCC CFR Part 15 (US)

CC430F513x Only) – Comparator With Wireless M-Bus Standard EN – Integrated LCD Driver With Contrast

Control for up to 96 Segments – Support for Asynchronous and

(CC430F61xx Only) Synchronous Serial Receive or Transmit – 128-Bit AES Security Encryption and

Decryption Coprocessor – 32-Bit Hardware Multiplier – Three-Channel Internal DMA – Serial Onboard Programming, No External

Programming Voltage Needed

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2MSP430 is a trademark of Texas Instruments. 3All other trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

– Embedded Emulation Module (EEM)

• High-Performance Sub-1-GHz RF Transceiver

– Same as in CC1101 – Wide Supply Voltage Range: 2.0 V to 3.6 V – Frequency Bands: 300 MHz to 348 MHz,

928 MHz

– Programmable Data Rate From 0.6 kBaud

to 500 kBaud

– High Sensitivity (–117 dBm at 0.6 kBaud,

–111 dBm at 1.2 kBaud, 315 MHz, 1% Packet Error Rate)

– Excellent Receiver Selectivity and Blocking

Performance

– Programmable Output Power Up to

+12 dBm for All Supported Frequencies

– 2-FSK, 2-GFSK, and MSK Supported as

Well as OOK and Flexible ASK Shaping

– Flexible Support for Packet-Oriented

Systems: On-Chip Support for Sync Word Detection, Address Check, Flexible Packet Length, and Automatic CRC Handling

– Support for Automatic Clear Channel

Assessment (CCA) Before Transmitting (for

– Suited for Systems Targeting Compliance

13757‑‑4:2005

Mode for Backward Compatibility With Existing Radio Communication Protocols

• Table 1 Summarizes Family Members

• For Complete Module Descriptions, See the CC430 Family User's Guide (SLAU259)

ECCN 5E002 TSPA - Technology / Software Publicly Available

CC430F6137, CC430F6135, CC430F6127, CC430F6126, CC430F6125 CC430F5137, CC430F5135, CC430F5133

SLAS554H –MAY 2009–REVISED SEPTEMBER 2013

APPLICATIONS

• Wireless Analog and Digital Sensor Systems

• Heat Cost Allocators

• Thermostats

• AMR or AMI Metering

• Smart Grid Wireless Networks

DESCRIPTION

The Texas Instruments CC430 family of ultralow-power microcontroller system-on-chip (SoC) with integrated RF transceiver cores consists of several devices featuring different sets of peripherals targeted for a wide range of applications. The architecture, combined with five low-power modes, is optimized to achieve extended battery life in portable measurement applications. The device features the powerful MSP430 16-bit RISC CPU, 16-bit registers, and constant generators that contribute to maximum code efficiency.

The CC430 family provides a tight integration between the microcontroller core, its peripherals, software, and the RF transceiver, making these true SoC solutions easy to use as well as improving performance.

The CC430F61xx series are microcontroller SoC configurations that combine the excellent performance of the state-of-the-art CC1101 sub-1-GHz RF transceiver with the MSP430 CPUXV2, up to 32KB of in-system programmable flash memory, up to 4KB of RAM, two 16-bit timers, a high-performance 12-bit analog-to-digital converter (ADC) with eight external inputs plus internal temperature and battery sensors on CC430F613x devices, a comparator, universal serial communication interfaces (USCIs), a 128-bit AES security accelerator, a hardware multiplier, a DMA, a real-time clock (RTC) module with alarm capabilities, an LCD driver, and up to 44 I/O pins.

The CC430F513x series are microcontroller SoC configurations that combine the excellent performance of the state-of-the-art CC1101 sub-1-GHz RF transceiver with the MSP430 CPUXV2, up to 32KB of in-system programmable flash memory, up to 4KB of RAM, two 16-bit timers, a high performance 12-bit ADC with six external inputs plus internal temperature and battery sensors, a comparator, universal serial communication interfaces (USCIs), a 128-bit AES security accelerator, a hardware multiplier, a DMA, an RTC module with alarm capabilities, and up to 30 I/O pins.

Typical applications for these devices include wireless analog and digital sensor systems, heat cost allocators, thermostats, metering (AMR or AMI), and smart grid wireless networks.

www.ti.com

Table 1 summarizes the available family members.

For complete module descriptions, see the CC430 Family User's Guide (SLAU259).

Product Folder Links: CC430F6137 CC430F6135 CC430F6127 CC430F6126 CC430F6125 CC430F5137

CC430F5135 CC430F5133

ECCN 5E002 TSPA - Technology / Software Publicly Available

CC430F6137, CC430F6135, CC430F6127, CC430F6126, CC430F6125

CC430F5137, CC430F5135, CC430F5133

www.ti.com

Table 1. Family Members

USCI

Device SRAM (KB) Timer_A

CC430F6137 32 4 5, 3 96 seg 1 1 8 ch. 44 64 RGC

CC430F6135 16 2 5, 3 96 seg 1 1 8 ch. 44 64 RGC CC430F6127 32 4 5, 3 96 seg 1 1 n/a 8 ch. 44 64 RGC

CC430F6126 32 2 5, 3 96 seg 1 1 n/a 8 ch. 44 64 RGC CC430F6125 16 2 5, 3 96 seg 1 1 n/a 8 ch. 44 64 RGC

CC430F5137 32 4 5, 3 n/a 1 1 6 ch. 30 48 RGZ

CC430F5135 16 2 5, 3 n/a 1 1 6 ch. 30 48 RGZ

CC430F5133 8 2 5, 3 n/a 1 1 6 ch. 30 48 RGZ

Program Package

(KB) Type

(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI

web site at www.ti.com. (2) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging. (3) Each number in the sequence represents an instantiation of Timer_A with its associated number of capture compare registers and PWM

output generators available. For example, a number sequence of 5, 3 would represent two instantiations of Timer_A, the first

instantiation having 5 and the second instantiation having 3 capture compare registers and PWM output generators, respectively. (4) n/a = not available

(3)

LCD_B

(4)

Channel A: Channel B: UART, LIN,

IrDA, SPI

SPI, I2C

SLAS554H –MAY 2009–REVISED SEPTEMBER 2013

(1)(2)

8 ext,

4 int ch.

8 ext,

4 int ch.

6 ext,

4 int ch.

6 ext,

4 int ch.

6 ext,

4 int ch.

(4)

Comp_B I/O

ADC12_A

Product Folder Links: CC430F6137 CC430F6135 CC430F6127 CC430F6126 CC430F6125 CC430F5137

CC430F5135 CC430F5133

RAM

4kB 2kB

Power Mgmt

LDO SVM/SVS Brownout

SYS

TA0

5 CC

Registers

EEM

(S: 3+1)

RTC_A

Comp_B

Flash

32kB

16kB

SMCLK

ACLK

MDB

MAB

XOUTXIN

Spy-Bi-

Wire

CRC16

Bus

Cntrl

Logic

MAB

MDB

MAB

MDB

MCLK

USCI_A0

(UART,

IrDA, SPI)

USCI_B0

(SPI, I2C)

LCD_B

Segments

1,2,3,4

Mux

I/O Ports

P1/P2

2x8 I/Os

1x16 I/Os

P1.x/P2.x

2x8

I/O Ports

P3/P4

2x8 I/Os

1x16 I/Os

P3.x/P4.x

2x8

I/O Ports

1x8 I/Os

P5.x

1x8

AES128

Security En-/Decryption

RF_XOUTRF_XIN

RF_NRF_P

TA1

3 CC

Registers

MODEM

RF/ANALOG

TX & RX

Frequency

Synthesizer

CPU Interface

Packet

Handler

Digital RSSI

Carrier Sense

PQI / LQI

CCA

Sub-1GHz

Radio

(CC1101)

MPY32

ADC12

(32kHz) (26MHz)

Unified

Clock

System

CPUXV2

incl. 16

Registers

JTAG

Interface

DMA

Controller

3 Channel

Port

Mapping

Controller

Watch-

dog

REF

Voltage

Reference

ECCN 5E002 TSPA - Technology / Software Publicly Available

CC430F6137, CC430F6135, CC430F6127, CC430F6126, CC430F6125 CC430F5137, CC430F5135, CC430F5133

SLAS554H –MAY 2009–REVISED SEPTEMBER 2013

CC430F613x Functional Block Diagram

www.ti.com

Product Folder Links: CC430F6137 CC430F6135 CC430F6127 CC430F6126 CC430F6125 CC430F5137

CC430F5135 CC430F5133

RGC PACKAGE

(TOP VIEW)

CC430F613x

P3.7/PM_SMCLK/S17

P2.0/PM_CBOUT1/PM_TA1CLK/CB0/A0

P3.6/PM_RFGDO1/S16

P2.1/PM_TA1CCR0A/CB1/A1

P3.5/PM_TA0CCR4A/S15

P2.2/PM_TA1CCR1A/CB2/A2

P2.3/PM_TA1CCR2A/CB3/A3

P3.4/PM_TA0CCR3A/S14

P2.4/PM_RTCCLK/CB4/A4/VREF-/VeREF-

P3.3/PM_TA0CCR2A/S13

P2.5/ /CB5/A5PM_SVMOUT /VREF+/VeREF+

P3.2/PM_TA0CCR1A/S12

DVCC

P4.4/S6

RST/NMI/SBWTDIO

P4.3/S5

TEST/SBWTCK

P4.2/S4

PJ.3/TCK

P4.1/S3

P2.6/PM_ACLK/CB6/A6

P3.1/PM_TA0CCR0A/S11

P2.7/ /CB7/A7PM_ADC12CLK/PM_DMAE0

P3.0/PM_CBOUT0/PM_TA0CLK/S10

AVCC

DVCC

P5.0/XIN

P4.7/S9

P5.1/XOUT

P4.6/S8

AVSS

P4.5/S7

P4.0/S2P1.0/PM_RFGDO0/S18

3316

P5.3/S1

P1.1/PM_RFGDO2/S19

3415

P5.2/S0

P1.2/PM_UCB0SOMI/PM_UCB0SCL/S20

RF_XINP1.3/PM_UCB0SIMO/PM_UCB0SDA/S21

3613

RF_XOUTP1.4/PM_UCB0CLK/PM_UCA0STE/S22

AVCC_RFDVCC

GUARD

LCDCAP/R33

PJ.0/TDO

P1.5/PM_UCA0RXD/PM_UCA0SOMI/R23

463

PJ.1/TDI/TCLK

P1.6/PM_UCA0TXD/PM_UCA0SIMO/R13/LCDREF

472

PJ.2/TMS

P1.7/PM_UCA0CLK/PM_UCB0STE/R03

AVCC_RF

VCORE

3910

RF_P

P5.4/S23

409

RF_NP5.5/COM3/S24

AVCC_RFP5.6/COM2/S25

AVCC_RF

P5.7/COM1/S26

436

R_BIAS

COM0

VSS Exposed die attached pad

www.ti.com

ECCN 5E002 TSPA - Technology / Software Publicly Available

CC430F6137, CC430F6135, CC430F6127, CC430F6126, CC430F6125

CC430F5137, CC430F5135, CC430F5133

SLAS554H –MAY 2009–REVISED SEPTEMBER 2013

NOTE: The secondary digital functions on ports P1, P2, and P3 are fully mappable. This pinout shows only the default

mapping. See Table 9 for details.

CAUTION: The LCDCAP/R33 must be connected to VSS if not used.

Product Folder Links: CC430F6137 CC430F6135 CC430F6127 CC430F6126 CC430F6125 CC430F5137

CC430F5135 CC430F5133

RAM

4kB 2kB 2kB

Power Mgmt

LDO SVM/SVS Brownout

TA0

5 CC

Registers

EEM

(S: 3+1)

RTC_A

Comp_B

Flash

32kB

16kB

SMCLK

ACLK

MDB

MAB

XOUTXIN

Spy-Bi-

Wire

CRC16

Bus

Cntrl

Logic

MAB

MDB

MAB

MDB

MCLK

USCI_A0

(UART,

IrDA, SPI)

USCI_B0

(SPI, I2C)

LCD_B

Segments

1,2,3,4

Mux

I/O Ports

P1/P2

2x8 I/Os

1x16 I/Os

P1.x/P2.x

2x8

I/O Ports

P3/P4

2x8 I/Os

1x16 I/Os

P3.x/P4.x

2x8

I/O Ports

1x8 I/Os

P5.x

1x8

AES128

Security En-/Decryption

RF_XOUTRF_XIN

RF_NRF_P

TA1

3 CC

Registers

MODEM

RF/ANALOG

TX & RX

Frequency

Synthesizer

CPU Interface

Packet

Handler

Digital RSSI

Carrier Sense

PQI / LQI

CCA

Sub-1GHz

Radio

(CC1101)

MPY32

(32kHz) (26MHz)

Unified

Clock

System

JTAG

Interface

DMA

Controller

3 Channel

SYS

Port

Mapping

Controller

Watch-

dog

REF

Voltage

Reference

CPUXV2

incl. 16

Registers

ECCN 5E002 TSPA - Technology / Software Publicly Available

CC430F6137, CC430F6135, CC430F6127, CC430F6126, CC430F6125 CC430F5137, CC430F5135, CC430F5133

SLAS554H –MAY 2009–REVISED SEPTEMBER 2013

CC430F612x Functional Block Diagram

www.ti.com

Product Folder Links: CC430F6137 CC430F6135 CC430F6127 CC430F6126 CC430F6125 CC430F5137

CC430F5135 CC430F5133

RGC PACKAGE

(TOP VIEW)

CC430F612x

P3.7/PM_SMCLK/S17

P2.0/PM_CBOUT1/PM_TA1CLK/CB0

P3.6/PM_RFGDO1/S16

P2.1/PM_TA1CCR0A/CB1

P3.5/PM_TA0CCR4A/S15

P2.2/PM_TA1CCR1A/CB2

P2.3/PM_TA1CCR2A/CB3

P3.4/PM_TA0CCR3A/S14

P2.4/PM_RTCCLK/CB4

P3.3/PM_TA0CCR2A/S13

P2.5/ /CB5PM_SVMOUT

P3.2/PM_TA0CCR1A/S12

DVCC

P4.4/S6

RST/NMI/SBWTDIO

P4.3/S5

TEST/SBWTCK

P4.2/S4

PJ.3/TCK

P4.1/S3

P2.6/PM_ACLK/CB6

P3.1/PM_TA0CCR0A/S11

P2.7/ /CB7PM_DMAE0

P3.0/PM_CBOUT0/PM_TA0CLK/S10

AVCC

DVCC

P5.0/XIN

P4.7/S9

P5.1/XOUT

P4.6/S8

AVSS

P4.5/S7

P4.0/S2P1.0/PM_RFGDO0/S18

3316

P5.3/S1

P1.1/PM_RFGDO2/S19

3415

P5.2/S0

P1.2/PM_UCB0SOMI/PM_UCB0SCL/S20

RF_XINP1.3/PM_UCB0SIMO/PM_UCB0SDA/S21

3613

RF_XOUTP1.4/PM_UCB0CLK/PM_UCA0STE/S22

AVCC_RFDVCC

GUARD

LCDCAP/R33

PJ.0/TDO

P1.5/PM_UCA0RXD/PM_UCA0SOMI/R23

463

PJ.1/TDI/TCLK

P1.6/PM_UCA0TXD/PM_UCA0SIMO/R13/LCDREF

472

PJ.2/TMS

P1.7/PM_UCA0CLK/PM_UCB0STE/R03

AVCC_RF

VCORE

3910

RF_P

P5.4/S23

409

RF_NP5.5/COM3/S24

AVCC_RFP5.6/COM2/S25

AVCC_RF

P5.7/COM1/S26

436

R_BIAS

COM0

VSS Exposed die attached pad

www.ti.com

ECCN 5E002 TSPA - Technology / Software Publicly Available

CC430F6137, CC430F6135, CC430F6127, CC430F6126, CC430F6125

CC430F5137, CC430F5135, CC430F5133

SLAS554H –MAY 2009–REVISED SEPTEMBER 2013

NOTE: The secondary digital functions on ports P1, P2, and P3 are fully mappable. This pinout shows only the default

mapping. See Table 9 for details.

CAUTION: The LCDCAP/R33 must be connected to VSS if not used.

Product Folder Links: CC430F6137 CC430F6135 CC430F6127 CC430F6126 CC430F6125 CC430F5137

CC430F5135 CC430F5133

RAM

4kB 2kB

Power Mgmt

LDO SVM/SVS Brownout

TA0

5 CC

Registers

EEM

(S: 3+1)

RTC_A

Comp_B

Flash

16kB

8kB

SMCLK

ACLK

MDB

MAB

XOUTXIN

Spy-Bi-

Wire

CRC16

Bus

Cntrl

Logic

MAB

MDB

MAB

MDB

MCLK

USCI_A0

(UART,

IrDA, SPI)

USCI_B0

(SPI, I2C)

I/O Ports

P1/P2

2x8 I/Os

1x16 I/Os

P1.x/P2.x

2x8

I/O Ports

1x8 I/Os

P3.x

1x8

I/O Ports

1x2 I/Os

P5.x

1x2

AES128

Security En-/Decryption

RF_XOUTRF_XIN

RF_NRF_P

MODEM

RF/ANALOG

TX & RX

Frequency

Synthesizer

CPU Interface

Packet

Handler

Digital RSSI

Carrier Sense

PQI / LQI

CCA

Sub-1GHz

Radio

(CC1101)

MPY32

ADC12

(32kHz) (26MHz)

Unified

Clock

System

JTAG

Interface

DMA

Controller

3 Channel

SYS

Port

Mapping

Controller

Watch-

dog

REF

Voltage

Reference

CPUXV2

incl. 16

Registers

TA1

3 CC

Registers

ECCN 5E002 TSPA - Technology / Software Publicly Available

CC430F6137, CC430F6135, CC430F6127, CC430F6126, CC430F6125 CC430F5137, CC430F5135, CC430F5133

SLAS554H –MAY 2009–REVISED SEPTEMBER 2013

CC430F513x Functional Block Diagram

www.ti.com

Product Folder Links: CC430F6137 CC430F6135 CC430F6127 CC430F6126 CC430F6125 CC430F5137

CC430F5135 CC430F5133

RGZ PACKAGE

(TOP VIEW)

14 15 16

17 181920

21 22

47 46 45

44 434241

40 39

P1.1/PM_RFGDO2

P1.2/PM_UCB0SOMI/PM_UCB0SCL

P1.7/PM_UCA0CLK/PM_UCB0STE

P2.0/PM_CBOUT1/PM_TA1CLK/CB0/A0

P2.1/PM_TA1CCR0A/CB1/A1

P2.2/PM_TA1CCR1A/CB2/A2

P1.3/PM_UCB0SIMO/PM_UCB0SDA

P1.4/PM_UCB0CLK/PM_UCA0STE

DVCC

VCORE

P1.5/PM_UCA0RXD/PM_UCA0SOMI

P1.6/PM_UCA0TXD/PM_UCA0SIMO

RF_XIN

RF_XOUT

AVCC_RF

GUARD

PJ.0/TDO

PJ.1/TDI/TCLK

AVCC_RF

RF_P

RF_N

AVCC_RF

R_BIAS

P2.3/PM_TA1CCR2A/CB3/A3

P2.4/PM_RTCCLK/CB4/A4/VREF-/VeREF-

RST/NMI/SBWTDIO

TEST/SBWTCK

PJ.3/TCK

PJ.2/TMS

P2.5/PM_SVMOUT/CB5/A5/VREF+/VeREF+

AVCC

P5.0/XIN

P5.1/XOUT

AVSS

DVCC

P1.0/PM_RFGDO0

P3.7/PM_SMCLK

P3.6/PM_RFGDO1

P3.5/PM_TA0CCR4A

P3.4/PM_TA0CCR3A

P3.3/PM_TA0CCR2A

P3.2/PM_TA0CCR1A

P3.1/PM_TA0CCR0A

P3.0/PM_CBOUT0/PM_TA0CLK

DVCC

P2.7/PM_ADC12CLK/PM_DMAE0

P2.6/PM_ACLK

VSS Exposed die attached pad

CC430F513x

www.ti.com

ECCN 5E002 TSPA - Technology / Software Publicly Available

CC430F6137, CC430F6135, CC430F6127, CC430F6126, CC430F6125

CC430F5137, CC430F5135, CC430F5133

SLAS554H –MAY 2009–REVISED SEPTEMBER 2013

NOTE: The secondary digital functions on ports P1, P2, and P3 are fully mappable. This pinout shows only the default

mapping. See Table 9 for details.

Product Folder Links: CC430F6137 CC430F6135 CC430F6127 CC430F6126 CC430F6125 CC430F5137

CC430F5135 CC430F5133

ECCN 5E002 TSPA - Technology / Software Publicly Available

CC430F6137, CC430F6135, CC430F6127, CC430F6126, CC430F6125 CC430F5137, CC430F5135, CC430F5133

SLAS554H –MAY 2009–REVISED SEPTEMBER 2013

Table 2. CC430F613x and CC430F612x Terminal Functions

TERMINAL

NAME NO.

P1.7/ PM_UCA0CLK/ PM_UCB0STE/ R03

P1.6/ PM_UCA0TXD/ Default mapping: USCI_A0 UART transmit data; USCI_A0 SPI slave in master out PM_UCA0SIMO/ R13/LCDREF Input/output port of third most positive analog LCD voltage (V3 or V4)

P1.5/ PM_UCA0RXD/ PM_UCA0SOMI/ R23

LCDCAP/ R33 4 I/O Input/output port of most positive analog LCD voltage (V1)

COM0 5 O LCD common output COM0 for LCD backplane

P5.7/ COM1/ S26 6 I/O LCD common output COM1 for LCD backplane

P5.6/ COM2/ S25 7 I/O LCD common output COM2 for LCD backplane

P5.5/ COM3/ S24 8 I/O LCD common output COM3 for LCD backplane

P5.4/ S23 9 I/O VCORE 10 Regulated core power supply

DVCC 11 Digital power supply P1.4/ PM_UCB0CLK/

PM_UCA0STE/ S22

P1.3/ PM_UCB0SIMO/ PM_UCB0SDA/ S21

P1.2/ PM_UCB0SOMI/ PM_UCB0SCL/ S20

P1.1/ PM_RFGDO2/ S19 15 I/O Default mapping: Radio GDO2 output

P1.0/ PM_RFGDO0/ S18 16 I/O Default mapping: Radio GDO0 output

P3.7/ PM_SMCLK/ S17 17 I/O Default mapping: SMCLK output

P3.6/ PM_RFGDO1/ S16 18 I/O Default mapping: Radio GDO1 output

P3.5/ PM_TA0CCR4A/ S15 19 I/O Default mapping: TA0 CCR4 compare output or capture input

P3.4/ PM_TA0CCR3A/ S14 20 I/O Default mapping: TA0 CCR3 compare output or capture input

P3.3/ PM_TA0CCR2A/ S13 21 I/O Default mapping: TA0 CCR2 compare output or capture input

1 I/O Default mapping: USCI_A0 clock input/output; USCI_B0 SPI slave transmit enable

2 I/O

3 I/O Default mapping: USCI_A0 UART receive data; USCI_A0 SPI slave out master in

12 I/O Default mapping: USCI_B0 clock input/output; USCI_A0 SPI slave transmit enable

13 I/O Default mapping: USCI_B0 SPI slave in master out; USCI_B0 I2C data

14 I/O Default mapping: USCI_B0 SPI slave out master in; UCSI_B0 I2C clock

(1)

I/O

General-purpose digital I/O with port interrupt and mappable secondary function Input/output port of lowest analog LCD voltage (V5)

General-purpose digital I/O with port interrupt and mappable secondary function

External reference voltage input for regulated LCD voltage General-purpose digital I/O with port interrupt and mappable secondary function

Input/output port of second most positive analog LCD voltage (V2) LCD capacitor connection

CAUTION: Must be connected to VSS if not used.

General-purpose digital I/O LCD segment output S26

General-purpose digital I/O LCD segment output S25

General-purpose digital I/O LCD segment output S24

General-purpose digital I/O LCD segment output S23

General-purpose digital I/O with port interrupt and mappable secondary function LCD segment output S22

General-purpose digital I/O with port interrupt and mappable secondary function LCD segment output S21

General-purpose digital I/O with port interrupt and mappable secondary function LCD segment output S20

General-purpose digital I/O with port interrupt and mappable secondary function LCD segment output S19

General-purpose digital I/O with port interrupt and mappable secondary function LCD segment output S18

General-purpose digital I/O with mappable secondary function LCD segment output S17

General-purpose digital I/O with mappable secondary function LCD segment output S16

General-purpose digital I/O with mappable secondary function LCD segment output S15

General-purpose digital I/O with mappable secondary function LCD segment output S14

General-purpose digital I/O with mappable secondary function LCD segment output S13

DESCRIPTION

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Table 2. CC430F613x and CC430F612x Terminal Functions (continued)

TERMINAL

NAME NO.

P3.2/ PM_TA0CCR1A/ S12 22 I/O Default mapping: TA0 CCR1 compare output or capture input

P3.1/ PM_TA0CCR0A/ S11 23 I/O Default mapping: TA0 CCR0 compare output or capture input

P3.0/ PM_CBOUT0/PM_TA0CLK/ S10

DVCC 25 Digital power supply P4.7/ S9 26 I/O

P4.6/ S8 27 I/O

P4.5/ S7 28 I/O

P4.4/ S6 29 I/O

P4.3/ S5 30 I/O

P4.2/ S4 31 I/O

P4.1/ S3 32 I/O

P4.0/ S2 33 I/O

P5.3/ S1 34 I/O

P5.2/ S0 35 I/O RF_XIN 36 I Input terminal for RF crystal oscillator, or external clock input

RF_XOUT 37 O Output terminal for RF crystal oscillator AVCC_RF 38 Radio analog power supply AVCC_RF 39 Radio analog power supply

RF_P 40

RF_N 41 AVCC_RF 42 Radio analog power supply

AVCC_RF 43 Radio analog power supply RBIAS 44 External bias resistor for radio reference current GUARD 45 Power supply connection for digital noise isolation

PJ.0/ TDO 46 I/O

PJ.1/ TDI/ TCLK 47 I/O

PJ.2/ TMS 48 I/O

PJ.3/ TCK 49 I/O

TEST/ SBWTCK 50 I

24 I/O Default mapping: Comparator_B output; TA0 clock input

(1)

I/O

General-purpose digital I/O with mappable secondary function LCD segment output S12

General-purpose digital I/O with mappable secondary function LCD segment output S11

General-purpose digital I/O with mappable secondary function LCD segment output S10

General-purpose digital I/O LCD segment output S9

General-purpose digital I/O LCD segment output S8

General-purpose digital I/O LCD segment output S7

General-purpose digital I/O LCD segment output S6

General-purpose digital I/O LCD segment output S5

General-purpose digital I/O LCD segment output S4

General-purpose digital I/O LCD segment output S3

General-purpose digital I/O LCD segment output S2

General-purpose digital I/O LCD segment output S1

General-purpose digital I/O LCD segment output S0

RF Positive RF input to LNA in receive mode I/O Positive RF output from PA in transmit mode

RF Negative RF input to LNA in receive mode I/O Negative RF output from PA in transmit mode

General-purpose digital I/O Test data output port

General-purpose digital I/O Test data input or test clock input

General-purpose digital I/O Test mode select

General-purpose digital I/O Test clock

Test mode pin – select digital I/O on JTAG pins Spy-Bi-Wire input clock

SLAS554H –MAY 2009–REVISED SEPTEMBER 2013

DESCRIPTION

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Table 2. CC430F613x and CC430F612x Terminal Functions (continued)

TERMINAL

NAME NO.

RST/NMI/ SBWTDIO 51 I/O Non-maskable interrupt input

DVCC 52 Digital power supply AVSS 53 Analog ground supply for ADC12

P5.1/ XOUT 54 I/O

P5.0/ XIN 55 I/O AVCC 56 Analog power supply

P2.7/ PM_ADC12CLK/ Default mapping: ADC12CLK output; DMA external trigger input PM_DMAE0/ CB7 (/A7) Comparator_B input CB7

P2.6/ PM_ACLK/ CB6 (/A6) 58 I/O

P2.5/ PM_SVMOUT/ CB5 Comparator_B input CB5 (/A5/ VREF+/ VeREF+) Analog input A5 – 12-bit ADC (CC430F613x only)

P2.4/ PM_RTCCLK/ CB4 Comparator_B input CB4 (/A4/ VREF-/ VeREF-) Analog input A4 – 12-bit ADC (CC430F613x only)

P2.3/ PM_TA1CCR2A/ CB3 (/A3) 61 I/O

P2.2/ PM_TA1CCR1A/ CB2 (/A2) 62 I/O

P2.1/PM_TA1CCR0A/CB1(/A1) 63 I/O

P2.0/ PM_CBOUT1/ PM_TA1CLK/ Default mapping: Comparator_B output; TA1 clock input CB0 (/A0) Comparator_B input CB0

VSS - Exposed die attach pad The exposed die attach pad must be connected to a solid ground plane as this is

57 I/O

59 I/O

60 I/O

64 I/O

(1)

I/O

Reset input active low Spy-Bi-Wire data input/output

General-purpose digital I/O Output terminal of crystal oscillator XT1

General-purpose digital I/O Input terminal for crystal oscillator XT1

General-purpose digital I/O with port interrupt and mappable secondary function

Analog input A7 – 12-bit ADC (CC430F613x only) General-purpose digital I/O with port interrupt and mappable secondary function

Default mapping: ACLK output Comparator_B input CB6 Analog input A6 – 12-bit ADC (CC430F613x only)

General-purpose digital I/O with port interrupt and mappable secondary function Default mapping: SVM output

Output of reference voltage to the ADC (CC430F613x only) Input for an external reference voltage to the ADC (CC430F613x only)

General-purpose digital I/O with port interrupt and mappable secondary function Default mapping: RTCCLK output

Negative terminal for the ADC's reference voltage for both sources, the internal reference voltage, or an external applied reference voltage (CC430F613x only)

General-purpose digital I/O with port interrupt and mappable secondary function Default mapping: TA1 CCR2 compare output or capture input Comparator_B input CB3 Analog input A3 – 12-bit ADC (CC430F613x only)

General-purpose digital I/O with port interrupt and mappable secondary function Default mapping: TA1 CCR1 compare output or capture input Comparator_B input CB2 Analog input A2 – 12-bit ADC (CC430F613x only)

General-purpose digital I/O with port interrupt and mappable secondary function Default mapping: TA1 CCR0 compare output or capture input Comparator_B input CB1 Analog input A1 – 12-bit ADC (CC430F613x only)

General-purpose digital I/O with port interrupt and mappable secondary function

Analog input A0 – 12-bit ADC (CC430F613x only) Ground supply

the ground connection for the chip.

DESCRIPTION

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Table 3. CC430F513x Terminal Functions

TERMINAL

NAME NO.

P2.2/ PM_TA1CCR1A/ CB2/ A2 1 I/O

P2.1/ PM_TA1CCR0A/ CB1/ A1 2 I/O

P2.0/ PM_CBOUT1/ PM_TA1CLK/ Default mapping: Comparator_B output; TA1 clock input CB0/ A0 Comparator_B input CB0

P1.7/ PM_UCA0CLK/ General-purpose digital I/O with port interrupt and mappable secondary function PM_UCB0STE Default mapping: USCI_A0 clock input/output / USCI_B0 SPI slave transmit enable

P1.6/ PM_UCA0TXD/ General-purpose digital I/O with port interrupt and mappable secondary function PM_UCA0SIMO Default mapping: USCI_A0 UART transmit data; USCI_A0 SPI slave in master out

P1.5/ PM_UCA0RXD/ General-purpose digital I/O with port interrupt and mappable secondary function PM_UCA0SOMI Default mapping: USCI_A0 UART receive data; USCI_A0 SPI slave out master in

VCORE 7 Regulated core power supply DVCC 8 Digital power supply P1.4/ PM_UCB0CLK/ General-purpose digital I/O with port interrupt and mappable secondary function

PM_UCA0STE Default mapping: USCI_B0 clock input/output / USCI_A0 SPI slave transmit enable P1.3/ PM_UCB0SIMO/ General-purpose digital I/O with port interrupt and mappable secondary function

PM_UCB0SDA Default mapping: USCI_B0 SPI slave in master out/USCI_B0 I2C data P1.2/ PM_UCB0SOMI/ General-purpose digital I/O with port interrupt and mappable secondary function

PM_UCB0SCL Default mapping: USCI_B0 SPI slave out master in/UCSI_B0 I2C clock P1.1/ PM_RFGDO2 12 I/O

P1.0/ PM_RFGDO0 13 I/O

P3.7/ PM_SMCLK 14 I/O

P3.6/ PM_RFGDO1 15 I/O

P3.5/ PM_TA0CCR4A 16 I/O

P3.4/ PM_TA0CCR3A 17 I/O

P3.3/ PM_TA0CCR2A 18 I/O

P3.2/ PM_TA0CCR1A 19 I/O

P3.1/ PM_TA0CCR0A 20 I/O

P3.0/ PM_CBOUT0/ PM_TA0CLK 21 I/O DVCC 22 Digital power supply

P2.7/ PM_ADC12CLK/ General-purpose digital I/O with port interrupt and mappable secondary function PM_DMAE0 Default mapping: ADC12CLK output; DMA external trigger input

P2.6/ PM_ACLK 24 I/O RF_XIN 25 I Input terminal for RF crystal oscillator, or external clock input

RF_XOUT 26 O Output terminal for RF crystal oscillator AVCC_RF 27 Radio analog power supply

3 I/O

4 I/O

5 I/O

6 I/O

9 I/O

10 I/O

11 I/O

23 I/O

(1)

I/O

General-purpose digital I/O with port interrupt and mappable secondary function Default mapping: TA1 CCR1 compare output or capture input Comparator_B input CB2 Analog input A2 – 12-bit ADC

General-purpose digital I/O with port interrupt and mappable secondary function Default mapping: TA1 CCR0 compare output or capture input Comparator_B input CB1 Analog input A1 – 12-bit ADC

General-purpose digital I/O with port interrupt and mappable secondary function

Analog input A0 – 12-bit ADC

General-purpose digital I/O with port interrupt and mappable secondary function Default mapping: Radio GDO2 output

General-purpose digital I/O with port interrupt and mappable secondary function Default mapping: Radio GDO0 output

General-purpose digital I/O with mappable secondary function Default mapping: SMCLK output

General-purpose digital I/O with mappable secondary function Default mapping: Radio GDO1 output

General-purpose digital I/O with mappable secondary function Default mapping: TA0 CCR4 compare output or capture input

General-purpose digital I/O with mappable secondary function Default mapping: TA0 CCR3 compare output or capture input

General-purpose digital I/O with mappable secondary function Default mapping: TA0 CCR2 compare output or capture input

General-purpose digital I/O with mappable secondary function Default mapping: TA0 CCR1 compare output or capture input

General-purpose digital I/O with mappable secondary function Default mapping: TA0 CCR0 compare output or capture input

General-purpose digital I/O with mappable secondary function Default mapping: Comparator_B output; TA0 clock input

General-purpose digital I/O with port interrupt and mappable secondary function Default mapping: ACLK output

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DESCRIPTION

(1) I = input, O = output

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Table 3. CC430F513x Terminal Functions (continued)

TERMINAL

NAME NO.

AVCC_RF 28 Radio analog power supply RF_P 29

RF_N 30 AVCC_RF 31 Radio analog power supply

AVCC_RF 32 Radio analog power supply RBIAS 33 External bias resistor for radio reference current GUARD 34 Power supply connection for digital noise isolation

PJ.0/ TDO 35 I/O

PJ.1/ TDI/ TCLK 36 I/O

PJ.2/ TMS 37 I/O

PJ.3/ TCK 38 I/O

TEST/ SBWTCK 39 I

RST/NMI/ SBWTDIO 40 I/O Non-maskable interrupt input

DVCC 41 Digital power supply AVSS 42 Analog ground supply for ADC12

P5.1/ XOUT 43 I/O

P5.0/ XIN 44 I/O AVCC 45 Analog power supply

P2.5/ PM_SVMOUT/ CB5/ Comparator_B input CB5 A5/ VREF+/ VeREF+ Analog input A5 – 12-bit ADC

P2.4/ PM_RTCCLK/ CB4/ Comparator_B input CB4 A4/ VREF-/ VeREF- Analog input A4 – 12-bit ADC

P2.3/ PM_TA1CCR2A/ CB3/ A3 48 I/O

VSS - Exposed die attach pad The exposed die attach pad must be connected to a solid ground plane as this is

46 I/O

47 I/O

(1)

I/O

RF Positive RF input to LNA in receive mode I/O Positive RF output from PA in transmit mode

RF Negative RF input to LNA in receive mode I/O Negative RF output from PA in transmit mode

General-purpose digital I/O Test data output port

General-purpose digital I/O Test data input or test clock input

General-purpose digital I/O Test mode select

General-purpose digital I/O Test clock

Test mode pin – select digital I/O on JTAG pins Spy-Bi-Wire input clock

Reset input active low Spy-Bi-Wire data input/output

General-purpose digital I/O Output terminal of crystal oscillator XT1

General-purpose digital I/O Input terminal for crystal oscillator XT1

General-purpose digital I/O with port interrupt and mappable secondary function Default mapping: SVM output

Output of reference voltage to the ADC Input for an external reference voltage to the ADC

General-purpose digital I/O with port interrupt and mappable secondary function Default mapping: RTCCLK output

Negative terminal for the ADC's reference voltage for both sources, the internal reference voltage, or an external applied reference voltage

General-purpose digital I/O with port interrupt and mappable secondary function Default mapping: TA1 CCR2 compare output or capture input Comparator_B input CB3 Analog input A3 – 12-bit ADC

Ground supply

the ground connection for the chip.

DESCRIPTION

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BIAS

RBIAS RF_XIN RF_XOUT

XOSC

LNA

FREQ

SYNTH

ADC

DEMODULATOR

PACKET HANDLER

RXFIFOTXFIFO

INTERFACE TO MCU

RADIOCONTROL

RF_P

RF_N

RCOSC

ADC

MODULATOR

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Short-Form Description

Sub-1-GHz Radio

The implemented sub-1-GHz radio module is based on the industry-leading CC1101, requiring very few external components. Figure 1 shows a high-level block diagram of the implemented radio.

SLAS554H –MAY 2009–REVISED SEPTEMBER 2013

Figure 1. Sub-1-GHz Radio Block Diagram

The radio features a low-IF receiver. The received RF signal is amplified by a low-noise amplifier (LNA) and down-converted in quadrature to the intermediate frequency (IF). At IF, the I/Q signals are digitized. Automatic gain control (AGC), fine channel filtering, demodulation bit and packet synchronization are performed digitally.

The transmitter part is based on direct synthesis of the RF frequency. The frequency synthesizer includes a completely on-chip LC VCO and a 90° phase shifter for generating the I and Q LO signals to the downconversion mixers in receive mode.

The 26-MHz crystal oscillator generates the reference frequency for the synthesizer, as well as clocks for the ADC and the digital part.

A memory mapped register interface is used for data access, configuration, and status request by the CPU. The digital baseband includes support for channel configuration, packet handling, and data buffering. For complete module descriptions, see the CC430 Family User's Guide (SLAU259).

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CPU

The MSP430 CPU has a 16-bit RISC architecture that is highly transparent to the application. All operations, other than program-flow instructions, are performed as register operations in conjunction with seven addressing modes for source operand and four addressing modes for destination operand.

The CPU is integrated with 16 registers that provide reduced instruction execution time. The register-to-register operation execution time is one cycle of the CPU clock.

Four of the registers, R0 to R3, are dedicated as program counter, stack pointer, status register, and constant generator, respectively. The remaining registers are general-purpose registers.

Peripherals are connected to the CPU using data, address, and control buses and can be handled with all instructions.

The instruction set consists of the original 51 instructions with three formats and seven address modes and additional instructions for the expanded address range. Each instruction can operate on word and byte data.

Operating Modes

The CC430 has one active mode and five software-selectable low-power modes of operation. An interrupt event can wake up the device from any of the low-power modes, service the request, and restore back to the lowpower mode on return from the interrupt program.

The following six operating modes can be configured by software:

• Active mode (AM) – All clocks are active

• Low-power mode 0 (LPM0) – CPU is disabled – ACLK and SMCLK remain active, MCLK is disabled – FLL loop control remains active

• Low-power mode 1 (LPM1) – CPU is disabled – FLL loop control is disabled – ACLK and SMCLK remain active, MCLK is disabled

• Low-power mode 2 (LPM2) – CPU is disabled – MCLK and FLL loop control and DCOCLK are disabled – DCO's dc-generator remains enabled – ACLK remains active

• Low-power mode 3 (LPM3) – CPU is disabled – MCLK, FLL loop control, and DCOCLK are disabled – DCO's dc-generator is disabled – ACLK remains active

• Low-power mode 4 (LPM4) – CPU is disabled – ACLK is disabled – MCLK, FLL loop control, and DCOCLK are disabled – DCO's dc-generator is disabled – Crystal oscillator is stopped – Complete data retention

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Interrupt Vector Addresses

The interrupt vectors and the power-up start address are located in the address range 0FFFFh to 0FF80h. The vector contains the 16-bit address of the appropriate interrupt-handler instruction sequence.

Table 4. Interrupt Sources, Flags, and Vectors

INTERRUPT SOURCE INTERRUPT FLAG PRIORITY

System Reset

Power-Up

External Reset

Watchdog Timeout, Password

WDTIFG, KEYV (SYSRSTIV)

Violation

Flash Memory Password Violation

System NMI

PMM

Vacant Memory Access

JTAG Mailbox

SVMLIFG, SVMHIFG, DLYLIFG, DLYHIFG,

VLRLIFG, VLRHIFG, VMAIFG, JMBNIFG, (Non)maskable 0FFFCh 62

JMBOUTIFG (SYSSNIV)

User NMI

NMI

Oscillator Fault

NMIIFG, OFIFG, ACCVIFG (SYSUNIV)

Flash Memory Access Violation

Comparator_B Comparator_B Interrupt Flags (CBIV) Watchdog Interval Timer Mode WDTIFG Maskable 0FFF6h 59 USCI_A0 Receive or Transmit UCA0RXIFG, UCA0TXIFG (UCA0IV)

USCI_B0 Receive or Transmit Maskable 0FFF2h 57

ADC12_A

(Reserved on CC430F612x)

UCB0RXIFG, UCB0TXIFG, I2C Status Interrupt

Flags (UCB0IV)

ADC12IFG0 ... ADC12IFG15 (ADC12IV) TA0 TA0CCR0 CCIFG0 Maskable 0FFEEh 55 TA0 Maskable 0FFECh 54

RF1A CC1101-based Radio Maskable 0FFEAh 53

TA0CCR1 CCIFG1 ... TA0CCR4 CCIFG4,

TA0IFG (TA0IV)

Radio Interface Interrupt Flags (RF1AIFIV)

Radio Core Interrupt Flags (RF1AIV)

DMA DMA0IFG, DMA1IFG, DMA2IFG (DMAIV)

TA1 TA1CCR0 CCIFG0 Maskable 0FFE6h 51 TA1 Maskable 0FFE4h 50

TA1CCR1 CCIFG1 ... TA1CCR2 CCIFG2,

TA1IFG (TA1IV) I/O Port P1 P1IFG.0 to P1IFG.7 (P1IV) I/O Port P2 P2IFG.0 to P2IFG.7 (P2IV)

(Reserved on CC430F513x)

LCD_B

RTC_A Maskable 0FFDCh 46

LCD_B Interrupt Flags (LCDBIV)

RTCRDYIFG, RTCTEVIFG, RTCAIFG,

RT0PSIFG, RT1PSIFG (RTCIV)

AES AESRDYIFG Maskable 0FFDAh 45

Reserved Reserved

(4)

(1) Multiple source flags (2) A reset is generated if the CPU tries to fetch instructions from within peripheral space. (3) (Non)maskable: the individual interrupt-enable bit can disable an interrupt event, but the general-interrupt enable cannot disable it. (4) Reserved interrupt vectors at addresses are not used in this device and can be used for regular program code if necessary. To maintain

compatibility with other devices, it is recommended to reserve these locations.

(1)(2)

(1)(3)

(1)

(1) (1)

(1)

SLAS554H –MAY 2009–REVISED SEPTEMBER 2013

SYSTEM WORD

INTERRUPT ADDRESS

Reset 0FFFEh 63, highest

(Non)maskable 0FFFAh 61

Maskable 0FFF8h 60

Maskable 0FFF4h 58

Maskable 0FFF0h 56

Maskable 0FFE8h 52

Maskable 0FFE2h 49 Maskable 0FFE0h 48

Maskable 0FFDEh 47

0FFD8h 44

⋮ ⋮

0FF80h 0, lowest

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Memory Organization

Table 5. Memory Organization

CC430F6137 CC430F6135 CC430F6127 CC430F6126

CC430F5137

Main Memory Total 32kB 32kB 16kB 8kB (flash) Size

Main: Interrupt 00FFFFh to 00FF80h 00FFFFh to 00FF80h 00FFFFh to 00FF80h 00FFFFh to 00FF80h vector

Main: code Bank 0 32kB 32kB 16kB 8kB memory 00FFFFh to 008000h 00FFFFh to 008000h 00FFFFh to 00C000h 00FFFFh to 00E000h

RAM

Device Descriptor

Information memory (flash)

Bootstrap loader (BSL) memory (flash)

Peripherals

(1) All memory regions not specified here are vacant memory, and any access to them causes a Vacant Memory Interrupt.

Total 4kB 2kB 2kB 2kB

Size

Sect 1 2kB not available not available not available

002BFFh to 002400h

Sect 0 2kB 2kB 2kB 2kB

0023FFh to 001C00h 0023FFh to 001C00h 0023FFh to 001C00h 0023FFh to 001C00h

128 B 128 B 128 B 128 B

001AFFh to 001A80h 001AFFh to 001A80h 001AFFh to 001A80h 001AFFh to 001A80h

128 B 128 B 128 B 128 B

001A7Fh to 001A00h 001A7Fh to 001A00h 001A7Fh to 001A00h 001A7Fh to 001A00h

Info A 128 B 128 B 128 B 128 B

0019FFh to 001980h 0019FFh to 001980h 0019FFh to 001980h 0019FFh to 001980h

Info B 128 B 128 B 128 B 128 B

00197Fh to 001900h 00197Fh to 001900h 00197Fh to 001900h 00197Fh to 001900h

Info C 128 B 128 B 128 B 128 B

0018FFh to 001880h 0018FFh to 001880h 0018FFh to 001880h 0018FFh to 001880h

Info D 128 B 128 B 128 B 128 B

00187Fh to 001800h 00187Fh to 001800h 00187Fh to 001800h 00187Fh to 001800h

BSL 3 512 B 512 B 512 B 512 B

0017FFh to 001600h 0017FFh to 001600h 0017FFh to 001600h 0017FFh to 001600h

BSL 2 512 B 512 B 512 B 512 B

0015FFh to 001400h 0015FFh to 001400h 0015FFh to 001400h 0015FFh to 001400h

BSL 1 512 B 512 B 512 B 512 B

0013FFh to 001200h 0013FFh to 001200h 0013FFh to 001200h 0013FFh to 001200h

BSL 0 512 B 512 B 512 B 512 B

0011FFh to 001000h 0011FFh to 001000h 0011FFh to 001000h 0011FFh to 001000h

000FFFh to 0h 000FFFh to 0h 000FFFh to 0h 000FFFh to 0h

(1)

4 KB 4 KB 4 KB 4 KB

(1)

CC430F6125 CC430F5133

CC430F5135

(1)

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(1)

Bootstrap Loader (BSL)

The BSL enables users to program the flash memory or RAM using various serial interfaces. Access to the device memory via the BSL is protected by an user-defined password. BSL entry requires a specific entry sequence on the RST/NMI/SBWTDIO and TEST/SBWTCK pins. For a complete description of the features of the BSL and its implementation, see the MSP430 Programming Via the Bootstrap Loader User's Guide (SLAU319).

Table 6. UART BSL Pin Requirements and Functions

RST/NMI/SBWTDIO Entry sequence signal

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DEVICE SIGNAL BSL FUNCTION

TEST/SBWTCK Entry sequence signal

P1.6 Data transmit P1.5 Data receive VCC Power supply VSS Ground supply

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JTAG Operation

JTAG Standard Interface

The CC430 family supports the standard JTAG interface which requires four signals for sending and receiving data. The JTAG signals are shared with general-purpose I/O. The TEST/SBWTCK pin is used to enable the JTAG signals. In addition to these signals, the RST/NMI/SBWTDIO is required to interface with MSP430 development tools and device programmers. The JTAG pin requirements are shown in Table 7. For further details on interfacing to development tools and device programmers, see the MSP430 Hardware Tools User's

Guide (SLAU278). For a complete description of the features of the JTAG interface and its implementation, see MSP430 Programming Via the JTAG Interface (SLAU320).

Table 7. JTAG Pin Requirements and Functions

DEVICE SIGNAL DIRECTION FUNCTION

PJ.3/TCK IN JTAG clock input PJ.2/TMS IN JTAG state control

PJ.1/TDI/TCLK IN JTAG data input, TCLK input

PJ.0/TDO OUT JTAG data output

TEST/SBWTCK IN Enable JTAG pins

RST/NMI/SBWTDIO IN External reset

VCC Power supply VSS Ground supply

SLAS554H –MAY 2009–REVISED SEPTEMBER 2013

Spy-Bi-Wire Interface

In addition to the standard JTAG interface, the CC430 family supports the two wire Spy-Bi-Wire interface. Spy-BiWire can be used to interface with MSP430 development tools and device programmers. The Spy-Bi-Wire interface pin requirements are shown in Table 8. For further details on interfacing to development tools and device programmers, see the MSP430 Hardware Tools User's Guide (SLAU278). For a complete description of the features of the JTAG interface and its implementation, see MSP430 Programming Via the JTAG Interface (SLAU320).

Table 8. Spy-Bi-Wire Pin Requirements and Functions

DEVICE SIGNAL DIRECTION FUNCTION

TEST/SBWTCK IN Spy-Bi-Wire clock input

RST/NMI/SBWTDIO IN, OUT Spy-Bi-Wire data input/output

VCC Power supply VSS Ground supply

Flash Memory

The flash memory can be programmed via the JTAG port, Spy-Bi-Wire (SBW), or in-system by the CPU. The CPU can perform single-byte, single-word, and long-word writes to the flash memory. Features of the flash memory include:

• Flash memory has n segments of main memory and four segments of information memory (Info A to Info D) of 128 bytes each. Each segment in main memory is 512 bytes in size.

• Segments 0 to n may be erased in one step, or each segment may be individually erased.

• Segments Info A to Info D can be erased individually, or as a group with the main memory segments. Segments Info A to Info D are also called information memory.

• Segment A can be locked separately.

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RAM Memory

The RAM memory is made up of n sectors. Each sector can be completely powered down to save leakage, however, all data is lost. Features of the RAM memory include:

• RAM memory has n sectors of 2k bytes each.

• Each sector 0 to n can be complete disabled, however data retention is lost.

• Each sector 0 to n automatically enters low power retention mode when possible.

Peripherals

Peripherals are connected to the CPU through data, address, and control busses and can be handled using all instructions. For complete module descriptions, see the CC430 Family User's Guide (SLAU259).

Oscillator and System Clock

The Unified Clock System (UCS) module includes support for a 32768-Hz watch crystal oscillator, an internal very-low-power low-frequency oscillator (VLO), an internal trimmed low-frequency oscillator (REFO), an integrated internal digitally-controlled oscillator (DCO), and a high-frequency crystal oscillator. The UCS module is designed to meet the requirements of both low system cost and low-power consumption. The UCS module features digital frequency locked loop (FLL) hardware that, in conjunction with a digital modulator, stabilizes the DCO frequency to a programmable multiple of the watch crystal frequency. The internal DCO provides a fast turn-on clock source and stabilizes in less than 5 µs. The UCS module provides the following clock signals:

• Auxiliary clock (ACLK), sourced from a 32768-Hz watch crystal, a high-frequency crystal, the internal lowfrequency oscillator (VLO), or the trimmed low-frequency oscillator (REFO).

• Main clock (MCLK), the system clock used by the CPU. MCLK can be sourced by same sources made available to ACLK.

• Sub-Main clock (SMCLK), the subsystem clock used by the peripheral modules. SMCLK can be sourced by same sources made available to ACLK.

• ACLK/n, the buffered output of ACLK, ACLK/2, ACLK/4, ACLK/8, ACLK/16, ACLK/32.

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Power Management Module (PMM)

The PMM includes an integrated voltage regulator that supplies the core voltage to the device and contains programmable output levels to provide for power optimization. The PMM also includes supply voltage supervisor (SVS) and supply voltage monitoring (SVM) circuitry, as well as brownout protection. The brownout circuit is implemented to provide the proper internal reset signal to the device during power-on and power-off. The SVS/SVM circuitry detects if the supply voltage drops below a user-selectable level and supports both supply voltage supervision (the device is automatically reset) and supply voltage monitoring (SVM, the device is not automatically reset). SVS and SVM circuitry is available on the primary supply and core supply.

Digital I/O

There are up to five 8-bit I/O ports implemented: ports P1 through P5.

• All individual I/O bits are independently programmable.

• Any combination of input, output, and interrupt conditions is possible.

• Programmable pullup or pulldown on all ports.

• Programmable drive strength on all ports.

• Edge-selectable interrupt input capability for all the eight bits of ports P1 and P2.

• Read/write access to port-control registers is supported by all instructions.

• Ports can be accessed byte-wise (P1 through P5) or word-wise in pairs (PA and PB).

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Port Mapping Controller

The port mapping controller allows the flexible and re-configurable mapping of digital functions to port pins of ports P1 through P3.

Table 9. Port Mapping, Mnemonics and Functions

VALUE PxMAPy MNEMONIC INPUT PIN FUNCTION (PxDIR.y = 0)

0 PM_NONE None DVSS

(1)

3 PM_ACLK None ACLK output 4 PM_MCLK None MCLK output 5 PM_SMCLK None SMCLK output 6 PM_RTCCLK None RTCCLK output

(1)

8 PM_SVMOUT None SVM output

9 PM_TA0CCR0A TA0 CCR0 capture input CCI0A TA0 CCR0 compare output Out0 10 PM_TA0CCR1A TA0 CCR1 capture input CCI1A TA0 CCR1 compare output Out1 11 PM_TA0CCR2A TA0 CCR2 capture input CCI2A TA0 CCR2 compare output Out2 12 PM_TA0CCR3A TA0 CCR3 capture input CCI3A TA0 CCR3 compare output Out3 13 PM_TA0CCR4A TA0 CCR4 capture input CCI4A TA0 CCR4 compare output Out4 14 PM_TA1CCR0A TA1 CCR0 capture input CCI0A TA1 CCR0 compare output Out0 15 PM_TA1CCR1A TA1 CCR1 capture input CCI1A TA1 CCR1 compare output Out1 16 PM_TA1CCR2A TA1 CCR2 capture input CCI2A TA1 CCR2 compare output Out2

(2)

(3)

(4)

(5)

23 PM_RFGDO0 Radio GDO0 (direction controlled by Radio) 24 PM_RFGDO1 Radio GDO1 (direction controlled by Radio) 25 PM_RFGDO2 Radio GDO2 (direction controlled by Radio) 26 Reserved None DVSS

PM_CBOUT0

PM_TA0CLK TA0 clock input -

PM_CBOUT1 -

PM_TA1CLK TA1 clock input -

PM_ADC12CLK - ADC12CLK output

PM_DMAE0 DMA external trigger input -

PM_UCA0RXD USCI_A0 UART RXD (Direction controlled by USCI - input)

PM_UCA0SOMI USCI_A0 SPI slave out master in (direction controlled by USCI)

PM_UCA0TXD USCI_A0 UART TXD (Direction controlled by USCI - output)

PM_UCA0SIMO USCI_A0 SPI slave in master out (direction controlled by USCI)

PM_UCA0CLK USCI_A0 clock input/output (direction controlled by USCI) PM_UCB0STE USCI_B0 SPI slave transmit enable (direction controlled by USCI - input)

PM_UCB0SOMI USCI_B0 SPI slave out master in (direction controlled by USCI)

PM_UCB0SCL USCI_B0 I2C clock (open drain and direction controlled by USCI)

PM_UCB0SIMO USCI_B0 SPI slave in master out (direction controlled by USCI)

PM_UCB0SDA USCI_B0 I2C data (open drain and direction controlled by USCI)

PM_UCB0CLK USCI_B0 clock input/output (direction controlled by USCI) PM_UCA0STE USCI_A0 SPI slave transmit enable (direction controlled by USCI - input)

SLAS554H –MAY 2009–REVISED SEPTEMBER 2013

OUTPUT PIN FUNCTION

(PxDIR.y = 1)

Comparator_B output (on TA0 clock

input)

Comparator_B output (on TA1 clock

input)

(1) Input or output function is selected by the corresponding setting in the port direction register PxDIR. (2) UART or SPI functionality is determined by the selected USCI mode. (3) UCA0CLK function takes precedence over UCB0STE function. If the mapped pin is required as UCA0CLK input or output USCI_B0 will

be forced to 3-wire SPI mode even if 4-wire mode is selected.

(4) SPI or I2C functionality is determined by the selected USCI mode. In case the I2C functionality is selected the output of the mapped pin

drives only the logical 0 to VSSlevel.

(5) UCB0CLK function takes precedence over UCA0STE function. If the mapped pin is required as UCB0CLK input or output USCI_A0 will

be forced to 3-wire SPI mode even if 4-wire mode is selected.

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Table 9. Port Mapping, Mnemonics and Functions (continued)

VALUE PxMAPy MNEMONIC INPUT PIN FUNCTION (PxDIR.y = 0)

27 Reserved None DVSS 28 Reserved None DVSS 29 Reserved None DVSS 30 Reserved None DVSS

31 (0FFh)

(6) The value of the PM_ANALOG mnemonic is set to 0FFh. The port mapping registers are only 5 bits wide and the upper bits are ignored

resulting in a read out value of 31.

(6)

PM_ANALOG

Disables the output driver as well as the input Schmitt-trigger to prevent

parasitic cross currents when applying analog signals.

OUTPUT PIN FUNCTION

(PxDIR.y = 1)

Table 10. Default Mapping

PIN PxMAPy MNEMONIC

P1.0/P1MAP0 PM_RFGDO0 None Radio GDO0 P1.1/P1MAP1 PM_RFGDO2 None Radio GDO2

P1.2/P1MAP2 PM_UCB0SOMI/PM_UCB0SCL

P1.3/P1MAP3 PM_UCB0SIMO/PM_UCB0SDA

P1.4/P1MAP4 PM_UCB0CLK/PM_UCA0STE

P1.5/P1MAP5 PM_UCA0RXD/PM_UCA0SOMI

P1.6/P1MAP6 PM_UCA0TXD/PM_UCA0SIMO

P1.7/P1MAP7 PM_UCA0CLK/PM_UCB0STE P2.0/P2MAP0 PM_CBOUT1/PM_TA1CLK TA1 clock input Comparator_B output

P2.1/P2MAP1 PM_TA1CCR0A TA1 CCR0 capture input CCI0A TA1 CCR0 compare output Out0 P2.2/P2MAP2 PM_TA1CCR1A TA1 CCR1 capture input CCI1A TA1 CCR1 compare output Out1 P2.3/P2MAP3 PM_TA1CCR2A TA1 CCR2 capture input CCI2A TA1 CCR2 compare output Out2 P2.4/P2MAP4 PM_RTCCLK None RTCCLK output P2.5/P2MAP5 PM_SVMOUT None SVM output P2.6/P2MAP6 PM_ACLK None ACLK output P2.7/P2MAP7 PM_ADC12CLK/PM_DMAE0 DMA external trigger input ADC12CLK output P3.0/P3MAP0 PM_CBOUT0/PM_TA0CLK TA0 clock input Comparator_B output P3.1/P3MAP1 PM_TA0CCR0A TA0 CCR0 capture input CCI0A TA0 CCR0 compare output Out0 P3.2/P3MAP2 PM_TA0CCR1A TA0 CCR1 capture input CCI1A TA0 CCR1 compare output Out1 P3.3/P3MAP3 PM_TA0CCR2A TA0 CCR2 capture input CCI2A TA0 CCR2 compare output Out2 P3.4/P3MAP4 PM_TA0CCR3A TA0 CCR3 capture input CCI3A TA0 CCR3 compare output Out3 P3.5/P3MAP5 PM_TA0CCR4A TA0 CCR4 capture input CCI4A TA0 CCR4 compare output Out4 P3.6/P3MAP6 PM_RFGDO1 None Radio GDO1 P3.7/P3MAP7 PM_SMCLK None SMCLK output

INPUT PIN FUNCTION OUTPUT PIN FUNCTION

(PxDIR.y = 0) (PxDIR.y = 1)

USCI_B0 SPI slave out master in (direction controlled by USCI),

USCI_B0 I2C clock (open drain and direction controlled by USCI)

USCI_B0 SPI slave in master out (direction controlled by USCI),

USCI_B0 I2C data (open drain and direction controlled by USCI)

USCI_B0 clock input/output (direction controlled by USCI),

USCI_A0 SPI slave transmit enable (direction controlled by USCI - input)

USCI_A0 UART RXD (Direction controlled by USCI - input),

USCI_A0 SPI slave out master in (direction controlled by USCI)

USCI_A0 UART TXD (Direction controlled by USCI - output),

USCI_A0 SPI slave in master out (direction controlled by USCI)

USCI_A0 clock input/output (direction controlled by USCI),

USCI_B0 SPI slave transmit enable (direction controlled by USCI - input)

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System Module (SYS)

The SYS module handles many of the system functions within the device. These include power on reset and power up clear handling, NMI source selection and management, reset interrupt vector generators, boot strap loader entry mechanisms, as well as, configuration management (device descriptors). It also includes a data exchange mechanism via JTAG called a JTAG mailbox that can be used in the application.

Table 11. System Module Interrupt Vector Registers

INTERRUPT VECTOR REGISTER ADDRESS INTERRUPT EVENT VALUE PRIORITY

SYSRSTIV, System Reset 019Eh No interrupt pending 00h

Brownout (BOR) 02h Highest RST/NMI (POR) 04h

DoBOR (BOR) 06h

Reserved 08h

Security violation (BOR) 0Ah

SVSL (POR) 0Ch

SVSH (POR) 0Eh SVML_OVP (POR) 10h SVMH_OVP (POR) 12h

DoPOR (POR) 14h

WDT timeout (PUC) 16h

WDT password violation (PUC) 18h

KEYV flash password violation (PUC) 1Ah

Reserved 1Ch

Peripheral area fetch (PUC) 1Eh

PMM password violation (PUC) 20h

Reserved 22h to 3Eh Lowest

SYSSNIV, System NMI 019Ch No interrupt pending 00h

SVMLIFG 02h Highest

SVMHIFG 04h

DLYLIFG 06h

DLYHIFG 08h

VMAIFG 0Ah

JMBINIFG 0Ch

JMBOUTIFG 0Eh

VLRLIFG 10h

VLRHIFG 12h

Reserved 14h to 1Eh Lowest

SYSUNIV, User NMI 019Ah No interrupt pending 00h

NMIFG 02h Highest OFIFG 04h

ACCVIFG 06h

Reserved 08h to 1Eh Lowest

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DMA Controller

The DMA controller allows movement of data from one memory address to another without CPU intervention. Using the DMA controller can increase the throughput of peripheral modules. The DMA controller reduces system power consumption by allowing the CPU to remain in sleep mode, without having to awaken to move data to or from a peripheral.

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Table 12. DMA Trigger Assignments

TRIGGER

0 DMAREQ DMAREQ DMAREQ 1 TA0CCR0 CCIFG TA0CCR0 CCIFG TA0CCR0 CCIFG 2 TA0CCR2 CCIFG TA0CCR2 CCIFG TA0CCR2 CCIFG 3 TA1CCR0 CCIFG TA1CCR0 CCIFG TA1CCR0 CCIFG 4 TA1CCR2 CCIFG TA1CCR2 CCIFG TA1CCR2 CCIFG 5 Reserved Reserved Reserved 6 Reserved Reserved Reserved 7 Reserved Reserved Reserved 8 Reserved Reserved Reserved

9 Reserved Reserved Reserved 10 Reserved Reserved Reserved 11 Reserved Reserved Reserved 12 Reserved Reserved Reserved 13 Reserved Reserved Reserved 14 Reserved Reserved Reserved 15 Reserved Reserved Reserved 16 UCA0RXIFG UCA0RXIFG UCA0RXIFG 17 UCA0TXIFG UCA0TXIFG UCA0TXIFG 18 UCB0RXIFG UCB0RXIFG UCB0RXIFG 19 UCB0TXIFG UCB0TXIFG UCB0TXIFG 20 Reserved Reserved Reserved 21 Reserved Reserved Reserved 22 Reserved Reserved Reserved 23 Reserved Reserved Reserved 24 ADC12IFGx 25 Reserved Reserved Reserved 26 Reserved Reserved Reserved 27 Reserved Reserved Reserved 28 Reserved Reserved Reserved 29 MPY ready MPY ready MPY ready 30 DMA2IFG DMA0IFG DMA1IFG 31 DMAE0 DMAE0 DMAE0

(1) Reserved DMA triggers may be used by other devices in the family. Reserved DMA triggers will not

cause any DMA trigger event when selected.

(2) Only on CC430F613x and CC430F513x. Reserved on CC430F612x.

0 1 2

(2)

CHANNEL

ADC12IFGx

(1)

(2)

ADC12IFGx

(2)

Watchdog Timer (WDT_A)

The primary function of the watchdog timer is to perform a controlled system restart after a software problem occurs. If the selected time interval expires, a system reset is generated. If the watchdog function is not needed in an application, the timer can be configured as an interval timer and can generate interrupts at selected time intervals.

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CRC16

The CRC16 module produces a signature based on a sequence of entered data values and can be used for data checking purposes. The CRC16 module signature is based on the CRC-CCITT standard.

Hardware Multiplier

The multiplication operation is supported by a dedicated peripheral module. The module performs operations with 32-bit, 24-bit, 16-bit, and 8-bit operands. The module is capable of supporting signed and unsigned multiplication as well as signed and unsigned multiply and accumulate operations.

AES128 Accelerator

The AES accelerator module performs encryption and decryption of 128-bit data with 128-bit keys according to the Advanced Encryption Standard (AES) (FIPS PUB 197) in hardware.

Universal Serial Communication Interface (USCI)

The USCI module is used for serial data communication. The USCI module supports synchronous communication protocols such as SPI (3 or 4 pin) and I2C, and asynchronous communication protocols such as UART, enhanced UART with automatic baudrate detection, and IrDA.

The USCI_An module provides support for SPI (3 or 4 pin), UART, enhanced UART, and IrDA. The USCI_Bn module provides support for SPI (3 or 4 pin) and I2C. A USCI_A0 and USCI_B0 module are implemented.

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TA0

TA0 is a 16-bit timer/counter (Timer_A type) with five capture/compare registers. TA0 can support multiple capture/compares, PWM outputs, and interval timing. TA0 also has extensive interrupt capabilities. Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare registers.

Table 13. TA0 Signal Connections

DEVICE INPUT SIGNAL MODULE INPUT NAME MODULE BLOCK

PM_TA0CLK TACLK

ACLK (internal) ACLK

SMCLK (internal) SMCLK

RFCLK/192

(1)

INCLK

Timer NA

PM_TA0CCR0A CCI0A PM_TA0CCR0A

DV DV DV

SS SS CC

CCI0B

GND

CCR0 TA0

PM_TA0CCR1A CCI1A PM_TA0CCR1A

CBOUT (internal) CCI1B

DV DV

SS CC

GND

CCR1 TA1

PM_TA0CCR2A CCI2A PM_TA0CCR2A

ACLK (internal) CCI2B

DV DV

SS CC

GND

CCR2 TA2

PM_TA0CCR3A CCI3A PM_TA0CCR3A

GDO1 from Radio

(internal)

CCI3B

GND

CCR3 TA3

PM_TA0CCR4A CCI4A PM_TA0CCR4A

GDO2 from Radio

(internal)

CCI4B

GND

CCR4 TA4

(1) If a different RFCLK divider setting is selected for a radio GDO output, this divider setting is also used for the Timer_A INCLK. (2) Only on CC430F613x and CC430F513x

MODULE OUTPUT DEVICE OUTPUT

SIGNAL SIGNAL

ADC12 (internal)

ADC12SHSx = {1}

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(2)

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TA1

TA1 is a 16-bit timer/counter (Timer_A type) with three capture/compare registers. TA1 can support multiple capture/compares, PWM outputs, and interval timing. TA1 also has extensive interrupt capabilities. Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare registers.

Table 14. TA1 Signal Connections

DEVICE INPUT SIGNAL MODULE INPUT NAME MODULE BLOCK

PM_TA1CLK TACLK

ACLK (internal) ACLK

SMCLK (internal) SMCLK

DV DV

SS CC

(1)

INCLK

CCI0B RF Async. Input (internal)

GND

RFCLK/192

PM_TA1CCR0A CCI0A PM_TA1CCR0A

RF Async. Output

(internal)

PM_TA1CCR1A CCI1A PM_TA1CCR1A

CBOUT (internal) CCI1B

PM_TA1CCR2A CCI2A PM_TA1CCR2A

ACLK (internal) CCI2B

(1) If a different RFCLK divider setting is selected for a radio GDO output, this divider setting is also used for the Timer_A INCLK.

Timer NA

CCR0 TA0

CCR1 TA1

CCR2 TA2

SLAS554H –MAY 2009–REVISED SEPTEMBER 2013

MODULE OUTPUT

SIGNAL

DEVICE OUTPUT

SIGNAL

Real-Time Clock (RTC_A)

The RTC_A module can be used as a general-purpose 32-bit counter (counter mode) or as an integrated realtime clock (RTC) (calendar mode). In counter mode, the RTC_A also includes two independent 8-bit timers that can be cascaded to form a 16-bit timer/counter. Both timers can be read and written by software. Calendar mode integrates an internal calendar which compensates for months with less than 31 days and includes leap year correction. The RTC_A also supports flexible alarm functions and offset-calibration hardware.

REF Voltage Reference

The reference module (REF) is responsible for generation of all critical reference voltages that can be used by the various analog peripherals in the device. These include the ADC12_A, LCD_B, and COMP_B modules.

LCD_B (Only CC430F613x and CC430F612x)

The LCD_B driver generates the segment and common signals required to drive a liquid crystal display (LCD). The LCD_B controller has dedicated data memories to hold segment drive information. Common and segment signals are generated as defined by the mode. Static, 2-mux, 3-mux, and 4-mux LCDs are supported. The module can provide a LCD voltage independent of the supply voltage with its integrated charge pump. It is possible to control the level of the LCD voltage and thus contrast by software. The module also provides an automatic blinking capability for individual segments.

Comparator_B

The primary function of the Comparator_B module is to support precision slope analog-to-digital conversions, battery voltage supervision, and monitoring of external analog signals.

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ADC12_A (Only CC430F613x and CC430F513x)

The ADC12_A module supports fast, 12-bit analog-to-digital conversions. The module implements a 12-bit SAR core, sample select control, reference generator and a 16 word conversion-and-control buffer. The conversionand-control buffer allows up to 16 independent ADC samples to be converted and stored without any CPU intervention.

Embedded Emulation Module (EEM) (S Version)

The Embedded Emulation Module (EEM) supports real-time in-system debugging. The S version of the EEM implemented on all devices has the following features:

• Three hardware triggers or breakpoints on memory access

• One hardware trigger or breakpoint on CPU register write access

• Up to four hardware triggers can be combined to form complex triggers or breakpoints

• One cycle counter

• Clock control on module level

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Peripheral File Map

32-Bit Hardware Multiplier (see Table 36) 04C0h 000h-02Fh

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Table 15. Peripherals

MODULE NAME BASE ADDRESS

Special Functions (see Table 16) 0100h 000h-01Fh

PMM (see Table 17) 0120h 000h-00Fh

Flash Control (see Table 18) 0140h 000h-00Fh

CRC16 (see Table 19) 0150h 000h-007h

RAM Control (see Table 20) 0158h 000h-001h

Watchdog (see Table 21) 015Ch 000h-001h

UCS (see Table 22) 0160h 000h-01Fh

SYS (see Table 23) 0180h 000h-01Fh

Shared Reference (see Table 24) 01B0h 000h-001h

Port Mapping Control (see Table 25) 01C0h 000h-007h Port Mapping Port P1 (see Table 26) 01C8h 000h-007h Port Mapping Port P2 (see Table 27) 01D0h 000h-007h Port Mapping Port P3 (see Table 28) 01D8h 000h-007h

Port P1, P2 (see Table 29) 0200h 000h-01Fh Port P3, P4 (see Table 30)

(P4 not available on CC430F513x)

Port P5 (see Table 31) 0240h 000h-01Fh Port PJ (see Table 32) 0320h 000h-01Fh

TA0 (see Table 33) 0340h 000h-03Fh TA1 (see Table 34) 0380h 000h-03Fh

RTC_A (see Table 35) 04A0h 000h-01Fh

DMA Module Control (see Table 37) 0500h 000h-00Fh

DMA Channel 0 (see Table 38) 0510h 000h-00Fh DMA Channel 1 (see Table 39) 0520h 000h-00Fh DMA Channel 2 (see Table 40) 0530h 000h-00Fh

USCI_A0 (see Table 41) 05C0h 000h-01Fh USCI_B0 (see Table 42) 05E0h 000h-01Fh

ADC12 (see Table 43)

(only CC430F613x and CC430F513x)

Comparator_B (see Table 44) 08C0h 000h-00Fh

AES Accelerator (see Table 45) 09C0h 000h-00Fh

LCD_B (see Table 46)

(only CC430F613x and CC430F612x)

Radio Interface (see Table 47) 0F00h 000h-03Fh

0220h 000h-01Fh

0700h 000h-03Fh

0A00h 000h-05Fh

OFFSET ADDRESS

RANGE

Product Folder Links: CC430F6137 CC430F6135 CC430F6127 CC430F6126 CC430F6125 CC430F5137

CC430F5135 CC430F5133

ECCN 5E002 TSPA - Technology / Software Publicly Available

CC430F6137, CC430F6135, CC430F6127, CC430F6126, CC430F6125 CC430F5137, CC430F5135, CC430F5133

SLAS554H –MAY 2009–REVISED SEPTEMBER 2013

Table 16. Special Function Registers (Base Address: 0100h)

SFR interrupt enable SFRIE1 00h SFR interrupt flag SFRIFG1 02h SFR reset pin control SFRRPCR 04h

Table 17. PMM Registers (Base Address: 0120h)

PMM Control 0 PMMCTL0 00h PMM control 1 PMMCTL1 02h SVS high side control SVSMHCTL 04h SVS low side control SVSMLCTL 06h PMM interrupt flags PMMIFG 0Ch PMM interrupt enable PMMIE 0Eh PMM power mode 5 control PM5CTL0 10h

Table 18. Flash Control Registers (Base Address: 0140h)

Flash control 1 FCTL1 00h Flash control 3 FCTL3 04h Flash control 4 FCTL4 06h

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Table 19. CRC16 Registers (Base Address: 0150h)

CRC data input CRC16DI 00h CRC initialization and result CRCINIRES 04h

Table 20. RAM Control Registers (Base Address: 0158h)

RAM control 0 RCCTL0 00h

Table 21. Watchdog Registers (Base Address: 015Ch)

Watchdog timer control WDTCTL 00h

Table 22. UCS Registers (Base Address: 0160h)

UCS control 0 UCSCTL0 00h UCS control 1 UCSCTL1 02h UCS control 2 UCSCTL2 04h UCS control 3 UCSCTL3 06h UCS control 4 UCSCTL4 08h UCS control 5 UCSCTL5 0Ah UCS control 6 UCSCTL6 0Ch UCS control 7 UCSCTL7 0Eh UCS control 8 UCSCTL8 10h

Product Folder Links: CC430F6137 CC430F6135 CC430F6127 CC430F6126 CC430F6125 CC430F5137

CC430F5135 CC430F5133

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Texas Instruments CC430F6137, CC430F6135, CC430F6126, CC430F6125, CC430F5137 User Manual

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