Texas Instruments CC3200 Technical Reference Manual
CC3200 SimpleLink Wi-Fi and Internet-ofThings Solution, a Single Chip Wireless MCU
Technical Reference Manual
Literature Number: SWRU367D
June 2014–Revised May 2018
Contents
1 Architecture Overview......................................................................................................... 22
1.1 Introduction.................................................................................................................. 23
1.1.1 Related Documentation........................................................................................... 23
1.1.2 Register Bit Conventions ......................................................................................... 23
1.2 Architecture Overview ..................................................................................................... 24
1.3 Functional Overview ....................................................................................................... 25
1.3.1 Processor Core.................................................................................................... 25
1.3.2 Memory............................................................................................................. 26
1.3.3 Micro Direct Memory Access Controller (µDMA).............................................................. 27
1.3.4 General Purpose Timer (GPT) .................................................................................. 27
1.3.5 Watch Dog Timer (WDT)......................................................................................... 28
1.3.6 Multi-Channel Audio Serial Port (McASP) ..................................................................... 28
1.3.7 Serial Peripheral Interface (SPI)................................................................................. 28
1.3.8 Inter-Integrated Circuit Interface (I2C).......................................................................... 29
1.3.9 Universal Asynchronous Receiver/Transmitter (UART)...................................................... 29
1.3.10 General Purpose Input / Output (GPIO)....................................................................... 30
1.3.11 Analog to Digital Converter (ADC)............................................................................. 30
1.3.12 SD Card Host..................................................................................................... 30
1.3.13 Parallel Camera Interface....................................................................................... 30
1.3.14 Debug Interface .................................................................................................. 30
1.3.15 Hardware Cryptography Accelerator........................................................................... 31
1.3.16 Clock, Reset, and Power Management ....................................................................... 31
1.3.17 SimpleLink Subsystem .......................................................................................... 32
1.3.18 I/O Pads and Pin Multiplexing .................................................................................. 32
2 Cortex-M4 Processor .......................................................................................................... 33
2.1 Overview..................................................................................................................... 34
2.1.1 Block Diagram ..................................................................................................... 34
2.1.2 System-Level Interface ........................................................................................... 35
2.1.3 Integrated Configurable Debug.................................................................................. 35
2.1.4 Trace Port Interface Unit (TPIU) ................................................................................ 36
2.1.5 Cortex-M4 System Component Details......................................................................... 36
2.2 Functional Description ..................................................................................................... 36
2.2.1 Programming Model .............................................................................................. 36
2.2.2 Register Description .............................................................................................. 37
2.2.3 Memory Model..................................................................................................... 41
2.2.4 Exception Model................................................................................................... 44
2.2.5 Fault Handling ..................................................................................................... 50
2.2.6 Power Management............................................................................................... 52
2.2.7 Instruction Set Summary ......................................................................................... 54
3 Cortex-M4 Peripherals......................................................................................................... 59
3.1 Overview..................................................................................................................... 60
3.2 Functional Description ..................................................................................................... 60
3.2.1 System Timer (SysTick) .......................................................................................... 60
3.2.2 Nested Vectored Interrupt Controller (NVIC) .................................................................. 61
3.2.3 System Control Block (SCB)..................................................................................... 62
2
Contents
Copyright © 2014–2018, Texas Instruments Incorporated
SWRU367D–June 2014–Revised May 2018
Submit Documentation Feedback
www.ti.com
3.3 Register Map................................................................................................................ 62
3.3.1 PERIPHERAL Registers ......................................................................................... 66
4 Direct Memory Access (DMA) .............................................................................................. 97
4.1 Overview..................................................................................................................... 98
4.2 Functional Description ..................................................................................................... 98
4.2.1 Channel Assignment.............................................................................................. 99
4.2.2 Priority............................................................................................................. 100
4.2.3 Arbitration Size................................................................................................... 100
4.2.4 Channel Configuration .......................................................................................... 100
4.2.5 Transfer Mode.................................................................................................... 101
4.2.6 Transfer Size and Increment................................................................................... 106
4.2.7 Peripheral Interface.............................................................................................. 107
4.2.8 Interrupts and Errors ............................................................................................ 107
4.3 Register Description...................................................................................................... 108
4.3.1 DMA Register Map .............................................................................................. 108
4.3.2 µDMA Channel Control Structure.............................................................................. 109
4.3.3 DMA Registers ................................................................................................... 110
4.3.4 DMA_(OFFSET_FROM_DMA_BASE_ADDRESS) Registers............................................. 115
5 General-Purpose Input/Outputs (GPIOs).............................................................................. 139
5.1 Overview................................................................................................................... 140
5.2 Functional Description.................................................................................................... 140
5.2.1 Data Control ...................................................................................................... 141
5.3 Interrupt Control........................................................................................................... 142
5.3.1 μDMA Trigger Source ........................................................................................... 142
5.4 Initialization and Configuration .......................................................................................... 142
5.5 GPIO_REGISTER_MAP Registers..................................................................................... 144
5.5.1 GPIO Register Description ..................................................................................... 144
6 Universal Asynchronous Receivers/Transmitters (UARTs) .................................................... 156
6.1 Overview................................................................................................................... 157
6.1.1 Block Diagram.................................................................................................... 158
6.2 Functional Description.................................................................................................... 158
6.2.1 Transmit/Receive Logic ......................................................................................... 158
6.2.2 Baud-Rate Generation .......................................................................................... 159
6.2.3 Data Transmission............................................................................................... 159
6.2.4 Initialization and Configuration ................................................................................. 162
6.3 Register Description...................................................................................................... 163
6.3.1 UART Registers.................................................................................................. 164
7 Inter-Integrated Circuit (I2C) Interface ................................................................................. 186
7.1 Overview................................................................................................................... 187
7.1.1 Block Diagram.................................................................................................... 188
7.1.2 Signal Description ............................................................................................... 188
7.2 Functional Description.................................................................................................... 189
7.2.1 I2C Bus Functional Overview .................................................................................. 189
7.2.2 Supported Speed Modes ....................................................................................... 193
7.2.3 Interrupts.......................................................................................................... 194
7.2.4 Loopback Operation............................................................................................. 194
7.2.5 FIFO and µDMA Operation..................................................................................... 194
7.2.6 Command Sequence Flow Charts............................................................................. 196
7.2.7 Initialization and Configuration ................................................................................. 203
7.3 Register Map .............................................................................................................. 204
7.3.1 I2C Registers..................................................................................................... 205
8 SPI (Serial Peripheral Interface).......................................................................................... 244
SWRU367D–June 2014–Revised May 2018
Submit Documentation Feedback
Copyright © 2014–2018, Texas Instruments Incorporated
Contents
3
www.ti.com
8.1 Overview................................................................................................................... 245
8.1.1 Features........................................................................................................... 246
8.2 Functional Description.................................................................................................... 246
8.2.1 SPI interface...................................................................................................... 246
8.2.2 SPI Transmission ................................................................................................ 246
8.2.3 Master Mode ..................................................................................................... 250
8.2.4 Slave Mode....................................................................................................... 258
8.2.5 Interrupts.......................................................................................................... 260
8.2.6 DMA Requests ................................................................................................... 260
8.2.7 Reset .............................................................................................................. 261
8.3 Initialization and Configuration .......................................................................................... 261
8.3.1 Basic Initialization................................................................................................ 261
8.3.2 Master Mode Operation Without Interrupt (Polling) ......................................................... 261
8.3.3 Slave Mode Operation With Interrupt ......................................................................... 262
8.3.4 Generic Interrupt Handler Implementation ................................................................... 262
8.4 Access to Data Registers................................................................................................ 262
8.5 Module Initialization....................................................................................................... 263
8.5.1 Common Transfer Sequence................................................................................... 263
8.5.2 End of Transfer Sequences .................................................................................... 264
8.5.3 FIFO Mode........................................................................................................ 265
8.6 SPI Registers.............................................................................................................. 269
8.6.1 SPI Register Description........................................................................................ 270
9 General-Purpose Timers.................................................................................................... 285
9.1 Overview................................................................................................................... 286
9.2 Block Diagram............................................................................................................. 286
9.3 Functional Description.................................................................................................... 287
9.3.1 GPTM Reset Conditions ........................................................................................ 287
9.3.2 Timer Modes ..................................................................................................... 288
9.3.3 DMA Operation................................................................................................... 294
9.3.4 Accessing Concatenated 16/32-Bit GPTM Register Values ............................................... 294
9.4 Initialization and Configuration .......................................................................................... 294
9.4.1 One-Shot and Periodic Timer Mode........................................................................... 294
9.4.2 Input Edge-Count Mode......................................................................................... 295
9.4.3 Input Edge-Time Mode.......................................................................................... 295
9.4.4 PWM Mode ....................................................................................................... 296
9.5 TIMER Registers.......................................................................................................... 297
9.5.1 GPT Register Description....................................................................................... 297
10 Watchdog Timer ............................................................................................................... 327
10.1 Overview................................................................................................................... 328
10.1.1 Block Diagram................................................................................................... 328
10.2 Functional Description.................................................................................................... 329
10.2.1 Initialization and Configuration................................................................................ 329
10.3 Register Map .............................................................................................................. 329
10.3.1 Register Description............................................................................................ 330
10.4 MCU Watch Dog Controller Usage Caveats .......................................................................... 338
10.4.1 System WatchDog.............................................................................................. 338
10.4.2 System WatchDog Recovery Sequence..................................................................... 339
11 SD Host Controller Interface .............................................................................................. 341
11.1 Overview................................................................................................................... 342
11.2 SD Host Features......................................................................................................... 342
11.3 1-Bit SD Interface......................................................................................................... 343
11.3.1 Clock and Reset Management................................................................................ 343
11.4 Initialization and Configuration Using Peripheral APIs............................................................... 343
4
Contents
Copyright © 2014–2018, Texas Instruments Incorporated
SWRU367D–June 2014–Revised May 2018
Submit Documentation Feedback
www.ti.com
11.4.1 Basic Initialization and Configuration......................................................................... 344
11.4.2 Sending Command ............................................................................................. 344
11.4.3 Card Detection and Initialization.............................................................................. 345
11.4.4 Block Read ...................................................................................................... 347
11.4.5 Block Write ...................................................................................................... 348
11.5 Performance and Testing................................................................................................ 348
11.6 Peripheral Library APIs .................................................................................................. 349
11.7 Register Description...................................................................................................... 353
11.7.1 SD-HOST Registers............................................................................................ 354
12 Inter-Integrated Sound (I2S) Multi-Channel Audio Serial Port................................................. 380
12.1 Overview................................................................................................................... 381
12.1.1 I2S Format....................................................................................................... 381
12.2 Functional Description.................................................................................................... 382
12.3 Programming Model...................................................................................................... 382
12.3.1 Clock and Reset Management................................................................................ 382
12.3.2 I2S Data Port Interface......................................................................................... 383
12.3.3 Initialization and Configuration................................................................................ 383
12.4 Peripheral Library APIs for I2S Configuration......................................................................... 385
12.4.1 Basic APIs for Enabling and Configuring the Interface .................................................... 385
12.4.2 APIs for Data Access if DMA is Not Used................................................................... 388
12.4.3 APIs for Setting Up, Handling Interrupts, or Getting Status from I2S Peripheral....................... 390
12.4.4 APIs to Control FIFO Structures Associated with I2S Peripheral ........................................ 394
13 Analog-to-Digital Converter [ADC] ...................................................................................... 396
13.1 Overview................................................................................................................... 397
13.2 Key Features .............................................................................................................. 397
13.3 ADC Register Mapping................................................................................................... 398
13.4 ADC_MODULE Registers ............................................................................................... 399
13.4.1 ADC Register Description ..................................................................................... 399
13.5 Initialization and Configuration ......................................................................................... 420
13.6 Peripheral Library APIs for ADC Operation ........................................................................... 421
13.6.1 Overview......................................................................................................... 421
13.6.2 Configuring the ADC Channels ............................................................................... 421
13.6.3 Basic APIs for Enabling and Configuring the Interface .................................................... 421
13.6.4 APIs for Data Transfer [Direct Access to FIFO and DMA Setup] ........................................ 422
13.6.5 APIs for Interrupt Usage ....................................................................................... 424
13.6.6 APIs for Setting Up ADC Timer for Time Stamping the Samples ........................................ 426
14 Parallel Camera Interface Module ....................................................................................... 428
14.1 Overview................................................................................................................... 429
14.2 Image Sensor Interface .................................................................................................. 429
14.3 Functional Description.................................................................................................... 430
14.3.1 Modes of Operation ............................................................................................ 430
14.3.2 FIFO Buffer ...................................................................................................... 432
14.3.3 Reset ............................................................................................................. 432
14.3.4 Clock Generation ............................................................................................... 433
14.3.5 Interrupt Generation ............................................................................................ 433
14.3.6 DMA Interface................................................................................................... 433
14.4 Programming Model...................................................................................................... 434
14.4.1 Camera Core Reset............................................................................................ 434
14.4.2 Enable the Picture Acquisition ................................................................................ 434
14.4.3 Disable the Picture Acquisition................................................................................ 435
14.5 Interrupt Handling......................................................................................................... 435
14.5.1 FIFO_OF_IRQ (FIFO overflow)............................................................................... 435
SWRU367D–June 2014–Revised May 2018
Submit Documentation Feedback
Copyright © 2014–2018, Texas Instruments Incorporated
Contents
5
www.ti.com
14.5.2 FIFO_UF_IRQ (FIFO underflow) ............................................................................. 435
14.6 Camera Interface Module Functional Registers ...................................................................... 436
14.6.1 Functional Register Description............................................................................... 436
14.6.2 Peripheral Library APIs ........................................................................................ 447
14.7 Developer’s Guide ........................................................................................................ 450
14.7.1 Using Peripheral Driver APIs for Capturing an Image ..................................................... 450
14.7.2 Using Peripheral Driver APIs for Communicating with Image Sensors.................................. 452
15 Power, Reset and Clock Management ................................................................................. 454
15.1 Trademarks...................................................................................................................... 455
15.2 Overview................................................................................................................... 455
15.2.1 VBAT Wide-Voltage Connection.............................................................................. 455
15.2.2 Pre-Regulated 1.85 V.......................................................................................... 455
15.2.3 Supply Brownout and Blackout ............................................................................... 457
15.2.4 Application Processor Power Modes......................................................................... 457
15.3 Power Management Control Architecture ............................................................................. 459
15.3.1 Global Power-Reset-Clock Manager (GPRCM) ............................................................ 461
15.3.2 Application Reset-Clock Manager (ARCM) ................................................................. 462
15.4 PRCM APIs................................................................................................................ 462
15.4.1 MCU Initialization ............................................................................................... 462
15.4.2 Reset Control.................................................................................................... 462
15.4.3 Peripheral Reset ................................................................................................ 462
15.4.4 Reset Cause..................................................................................................... 462
15.4.5 Clock Control.................................................................................................... 463
15.4.6 Low Power Modes.............................................................................................. 463
15.4.7 Sleep (SLEEP) .................................................................................................. 464
15.4.8 Deep Sleep (DEEPSLEEP) ................................................................................... 464
15.4.9 Low-Power Deep Sleep (LPDS) .............................................................................. 464
15.4.10 Hibernate (HIB)................................................................................................ 466
15.4.11 Slow Clock Counter........................................................................................... 468
15.5 Peripheral Macros ........................................................................................................ 468
15.6 Power Management Framework........................................................................................ 469
15.7 PRCM Registers .......................................................................................................... 470
15.7.1 PRCM Register Description................................................................................... 471
16 I/O Pads and Pin Multiplexing............................................................................................. 522
16.1 Overview................................................................................................................... 523
16.2 I/O Pad Electrical Specifications........................................................................................ 523
16.3 Analog-Digital Pin Multiplexing.......................................................................................... 525
16.4 Special Ana/DIG Pins .................................................................................................... 526
16.4.1 Pin 45 and 52 ................................................................................................... 526
16.4.2 Pin 29 and 30 ................................................................................................... 528
16.4.3 Pin 57, 58, 59, 60............................................................................................... 528
16.5 Analog Mux Control Registers .......................................................................................... 528
16.6 Pins Available for Applications.......................................................................................... 530
16.7 Functional Pin Mux Configurations..................................................................................... 532
16.8 Pin Mapping Recommendations........................................................................................ 546
16.8.1 Pad Configuration Registers for Application Pins .......................................................... 547
16.8.2 PAD Behavior During Reset and Hibernate................................................................. 549
16.8.3 Control Architecture ............................................................................................ 549
16.8.4 CC3200 Pin-mux Examples................................................................................... 550
16.8.5 Wake on Pad.................................................................................................... 553
16.8.6 Sense on Power ................................................................................................ 553
A Software Development Kit Examples................................................................................... 556
6
Contents
Copyright © 2014–2018, Texas Instruments Incorporated
SWRU367D–June 2014–Revised May 2018
Submit Documentation Feedback
www.ti.com
A.1 Software Development Kit Examples .................................................................................. 556
B CC3200 Miscellaneous Registers........................................................................................ 557
B.1 Miscellaneous Register Summary ...................................................................................... 557
B.1.1 DMA_IMR Register (offset = 8Ch) [reset = FF0Fh] ......................................................... 558
B.1.2 DMA_IMS Register (offset = 90h) [reset = 0h]............................................................... 560
B.1.3 DMA_IMC Register (offset = 94h) [reset = 0h]............................................................... 562
B.1.4 DMA_ICR Register (offset = 9Ch) [reset = 0h] .............................................................. 564
B.1.5 DMA_MIS Register (offset = A0h) [reset = 0h] .............................................................. 566
B.1.6 DMA_RIS Register (offset = A4h) [reset = 0h]............................................................... 568
B.1.7 GPTTRIGSEL Register (offset = B0h) [reset = 0h].......................................................... 570
Revision History ........................................................................................................................ 571
SWRU367D–June 2014–Revised May 2018
Submit Documentation Feedback
Copyright © 2014–2018, Texas Instruments Incorporated
Contents
7
www.ti.com
List of Figures
1-1. CC3200 MCU and WIFI System-on-Chip............................................................................... 24
2-1. Application CPU Block Diagram.......................................................................................... 35
2-2. TPIU Block Diagram ....................................................................................................... 36
2-3. Cortex-M4 Register Set ................................................................................................... 38
2-4. Data Storage................................................................................................................ 43
2-5. Vector Table ................................................................................................................ 48
2-6. Exception Stack Frame.................................................................................................... 50
2-7. Power Management Architecture in CC3200 SoC..................................................................... 53
3-1. ACTLR Register ............................................................................................................ 67
3-2. STCTRL Register .......................................................................................................... 68
3-3. STRELOAD Register ...................................................................................................... 69
3-4. STCURRENT Register .................................................................................................... 70
3-5. EN_0 to EN_6 Register.................................................................................................... 71
3-6. DIS_0 to DIS_6 Register.................................................................................................. 72
3-7. PEND_0 to PEND_6 Register............................................................................................ 73
3-8. UNPEND_0 to UNPEND_6 Register .................................................................................... 74
3-9. ACTIVE_0 to ACTIVE_6 Register........................................................................................ 75
3-10. PRI_0 to PRI_49 Register................................................................................................. 76
3-11. CPUID Register............................................................................................................. 77
3-12. INTCTRL Register.......................................................................................................... 78
3-13. VTABLE Register........................................................................................................... 80
3-14. APINT Register ............................................................................................................. 81
3-15. SYSCTRL Register ........................................................................................................ 82
3-16. CFGCTRL Register ........................................................................................................ 83
3-17. SYSPRI1 Register.......................................................................................................... 85
3-18. SYSPRI2 Register.......................................................................................................... 86
3-19. SYSPRI3 Register.......................................................................................................... 87
3-20. SYSHNDCTRL Register................................................................................................... 88
3-21. FAULTSTAT Register ..................................................................................................... 90
3-22. HFAULTSTAT Register.................................................................................................... 94
3-23. FAULTDDR Register....................................................................................................... 95
3-24. SWTRIG Register .......................................................................................................... 96
4-1. DMA Channel Assignment ................................................................................................ 99
4-2. Ping-Pong Mode .......................................................................................................... 103
4-3. Memory Scatter-Gather Mode .......................................................................................... 105
4-4. Peripheral Scatter-Gather Mode........................................................................................ 106
4-5. DMA_SRCENDP Register............................................................................................... 111
4-6. DMA_DSTENDP Register ............................................................................................... 112
4-7. DMA_CHCTL Register................................................................................................... 113
4-8. DMA_STAT Register ..................................................................................................... 116
4-9. DMA_CFG Register ...................................................................................................... 117
4-10. DMA_CTLBASE Register................................................................................................ 118
4-11. DMA_ALTBASE Register................................................................................................ 119
4-12. DMA_WAITSTAT Register .............................................................................................. 120
4-13. DMA_SWREQ Register.................................................................................................. 121
4-14. DMA_USEBURSTSET Register ........................................................................................ 122
4-15. DMA_USEBURSTCLR Register........................................................................................ 123
8
List of Figures
Copyright © 2014–2018, Texas Instruments Incorporated
SWRU367D–June 2014–Revised May 2018
Submit Documentation Feedback
www.ti.com
4-16. DMA_REQMASKSET Register ......................................................................................... 124
4-17. DMA_REQMASKCLR Register ......................................................................................... 125
4-18. DMA_ENASET Register ................................................................................................. 126
4-19. DMA_ENACLR Register ................................................................................................. 127
4-20. DMA_ALTSET Register.................................................................................................. 128
4-21. DMA_ALTCLR Register.................................................................................................. 129
4-22. DMA_PRIOSET Register ................................................................................................ 130
4-23. DMA_PRIOCLR Register................................................................................................ 131
4-24. DMA_ERRCLR Register................................................................................................. 132
4-25. DMA_CHASGN Register ................................................................................................ 133
4-26. DMA_CHMAP0 Register................................................................................................. 134
4-27. DMA_CHMAP1 Register................................................................................................. 135
4-28. DMA_CHMAP2 Register................................................................................................. 136
4-29. DMA_CHMAP3 Register................................................................................................. 137
4-30. DMA_PV Register ........................................................................................................ 138
5-1. Digital I/O Pads ........................................................................................................... 140
5-2. GPIODATA Write Example.............................................................................................. 141
5-3. GPIODATA Read Example.............................................................................................. 141
5-4. GPIODATA Register ..................................................................................................... 145
5-5. GPIODIR Register ........................................................................................................ 146
5-6. GPIOIS Register .......................................................................................................... 147
5-7. GPIOIBE Register ........................................................................................................ 148
5-8. GPIOIEV Register ........................................................................................................ 149
5-9. GPIOIM Register.......................................................................................................... 150
5-10. GPIORIS Register ........................................................................................................ 151
5-11. GPIOMIS Register........................................................................................................ 152
5-12. GPIOICR Register ........................................................................................................ 153
6-1. UART Module Block Diagram........................................................................................... 158
6-2. UART Character Frame.................................................................................................. 159
6-3. UARTDR Register ........................................................................................................ 165
6-4. UARTRSR_UARTECR Register........................................................................................ 166
6-5. UARTFR Register ........................................................................................................ 168
6-6. UARTFBRD Register..................................................................................................... 171
6-7. UARTLCRH Register..................................................................................................... 172
6-8. UARTCTL Register....................................................................................................... 174
6-9. UARTIFLS Register ...................................................................................................... 176
6-10. UARTIM Register ......................................................................................................... 177
6-11. UARTRIS Register........................................................................................................ 179
6-12. UARTMIS Register ....................................................................................................... 181
6-13. UARTICR Register ....................................................................................................... 183
6-14. UARTDMACTL Register ................................................................................................. 185
7-1. I2C Block Diagram........................................................................................................ 188
7-2. I2C Bus Configuration.................................................................................................... 189
7-3. START and STOP Conditions .......................................................................................... 190
7-4. Complete Data Transfer with a 7-Bit Address ........................................................................ 190
7-5. R/S Bit in First Byte....................................................................................................... 190
7-6. Data Validity During Bit Transfer on the I2C Bus..................................................................... 191
7-7. Master Single TRANSMIT ............................................................................................... 197
7-8. Master Single RECEIVE ................................................................................................. 198
SWRU367D–June 2014–Revised May 2018
Submit Documentation Feedback
Copyright © 2014–2018, Texas Instruments Incorporated
List of Figures
9
www.ti.com
7-9. Master TRANSMIT of Multiple Data Bytes ............................................................................ 199
7-10. Master RECEIVE of Multiple Data Bytes .............................................................................. 200
7-11. Master RECEIVE with Repeated START after Master TRANSMIT................................................ 201
7-12. Master TRANSMIT with Repeated START after Master RECEIVE................................................ 202
7-13. Slave Command Sequence ............................................................................................. 203
7-14. I2CMSA Register ......................................................................................................... 206
7-15. I2CMCS Register ......................................................................................................... 207
7-16. I2CMDR Register ......................................................................................................... 209
7-17. I2CMTPR Register........................................................................................................ 210
7-18. I2CMIMR Register ........................................................................................................ 211
7-19. I2CMRIS Register ........................................................................................................ 213
7-20. I2CMMIS Register ........................................................................................................ 215
7-21. I2CMICR Register ........................................................................................................ 217
7-22. I2CMCR Register ......................................................................................................... 219
7-23. I2CMCLKOCNT Register ................................................................................................ 220
7-24. I2CMBMON Register..................................................................................................... 221
7-25. I2CMBLEN Register...................................................................................................... 222
7-26. I2CMBCNT Register...................................................................................................... 223
7-27. I2CSOAR Register........................................................................................................ 224
7-28. I2CSCSR Register........................................................................................................ 225
7-29. I2CSDR Register.......................................................................................................... 227
7-30. I2CSIMR Register ........................................................................................................ 228
7-31. I2CSRIS Register......................................................................................................... 230
7-32. I2CSMIS Register......................................................................................................... 232
7-33. I2CSICR Register......................................................................................................... 234
7-34. I2CSOAR2 Register ...................................................................................................... 236
7-35. I2CSACKCTL Register................................................................................................... 237
7-36. I2CFIFODATA Register.................................................................................................. 238
7-37. I2CFIFOCTL Register .................................................................................................... 239
7-38. I2CFIFOSTATUS Register .............................................................................................. 241
7-39. I2CPP Register............................................................................................................ 242
7-40. I2CPC Register ........................................................................................................... 243
8-1. SPI Block Diagram........................................................................................................ 245
8-2. SPI Full Duplex Transmission (Example).............................................................................. 247
8-3. Full Duplex Single Transfer Format with PHA = 0.................................................................... 249
8-4. Full Duplex Single Transfer Format with PHA = 1.................................................................... 250
8-5. Contiguous Transfers with SPIEN Kept Active (2 Data Pins Interface Mode).................................... 252
8-6. Transmit/Receive Mode With no FIFO Used.......................................................................... 254
8-7. Transmit/Receive Mode With Only Receive FIFO Enabled......................................................... 254
8-8. Transmit/Receive Mode With Only Transmit FIFO Used............................................................ 255
8-9. Transmit/Receive Mode With Both FIFO Directions Used .......................................................... 255
8-10. Buffer Almost Full Level (AFL) .......................................................................................... 256
8-11. Buffer Almost Empty Level (AEL)....................................................................................... 256
8-12. 3-Pin Mode System Overview........................................................................................... 257
8-13. Flow Chart - Module Initialization....................................................................................... 263
8-14. Flow Chart - Common Transfer Sequence............................................................................ 264
8-15. Flow Chart - Transmit and Receive (Master and Slave)............................................................. 265
8-16. Flow Chart - FIFO Mode Common Sequence (Master) ............................................................. 267
8-17. Flow Chart - FIFO Mode Transmit and Receive with Word Count (Master)...................................... 268
10
List of Figures
Copyright © 2014–2018, Texas Instruments Incorporated
SWRU367D–June 2014–Revised May 2018
Submit Documentation Feedback
www.ti.com
8-18. Flow Chart - FIFO Mode Transmit and Receive without Word Count (Master) .................................. 269
8-19. SPI_SYSCONFIG Register.............................................................................................. 271
8-20. SPI_SYSSTATUS Register.............................................................................................. 272
8-21. SPI_IRQSTATUS Register .............................................................................................. 273
8-22. SPI_IRQENABLE Register .............................................................................................. 275
8-23. SPI_MODULCTRL Register............................................................................................. 276
8-24. SPI_CHCONF Register .................................................................................................. 277
8-25. SPI_CHSTAT Register................................................................................................... 280
8-26. SPI_CHCTRL Register................................................................................................... 281
8-27. SPI_TX Register .......................................................................................................... 282
8-28. SPI_RX Register.......................................................................................................... 283
8-29. SPI_XFERLEVEL Register .............................................................................................. 284
9-1. GPTM Module Block Diagram .......................................................................................... 286
9-2. Input Edge-Count Mode Example, Counting Down .................................................................. 291
9-3. 16-Bit Input Edge-Time Mode Example................................................................................ 292
9-4. 16-Bit PWM Mode Example............................................................................................. 293
9-5. GPTMCFG Register...................................................................................................... 298
9-6. GPTMTAMR Register.................................................................................................... 299
9-7. GPTMTBMR Register.................................................................................................... 301
9-8. GPTMCTL Register....................................................................................................... 303
9-9. GPTMIMR Register....................................................................................................... 305
9-10. GPTMRIS Register ....................................................................................................... 307
9-11. GPTMMIS Register....................................................................................................... 309
9-12. GPTMICR Register ....................................................................................................... 311
9-13. GPTMTAILR Register .................................................................................................... 313
9-14. GPTMTBILR Register .................................................................................................... 314
9-15. GPTMTAMATCHR Register............................................................................................. 315
9-16. GPTMTBMATCHR Register............................................................................................. 316
9-17. GPTMTAPR Register .................................................................................................... 317
9-18. GPTMTBPR Register .................................................................................................... 318
9-19. GPTMTAPMR Register .................................................................................................. 319
9-20. GPTMTBPMR Register .................................................................................................. 320
9-21. GPTMTAR Register ...................................................................................................... 321
9-22. GPTMTBR Register ...................................................................................................... 322
9-23. GPTMTAV Register ...................................................................................................... 323
9-24. GPTMTBV Register ...................................................................................................... 324
9-25. GPTMDMAEV Register .................................................................................................. 325
10-1. WDT Module Block Diagram ............................................................................................ 328
10-2. WDTLOAD Register...................................................................................................... 332
10-3. WDTVALUE Register .................................................................................................... 333
10-4. WDTCTL Register ........................................................................................................ 334
10-5. WDTICR Register......................................................................................................... 335
10-6. WDTRIS Register......................................................................................................... 336
10-7. WDTTEST Register ...................................................................................................... 337
10-8. WDTLOCK Register...................................................................................................... 338
10-9. WatchDog Flow Chart.................................................................................................... 339
10-10. System WatchDog Recovery Sequence............................................................................... 340
11-1. SDHost Controller Interface Block Diagram........................................................................... 343
11-2. MMCHS_CSRE Register ................................................................................................ 355
SWRU367D–June 2014–Revised May 2018
Submit Documentation Feedback
Copyright © 2014–2018, Texas Instruments Incorporated
List of Figures
11
www.ti.com
11-3. MMCHS_CON Register.................................................................................................. 356
11-4. MMCHS_BLK Register................................................................................................... 358
11-5. MMCHS_ARG Register.................................................................................................. 359
11-6. MMCHS_CMD Register.................................................................................................. 360
11-7. MMCHS_RSP10 Register ............................................................................................... 362
11-8. MMCHS_RSP32 Register ............................................................................................... 363
11-9. MMCHS_RSP54 Register ............................................................................................... 364
11-10. MMCHS_RSP76 Register ............................................................................................... 365
11-11. MMCHS_DATA Register................................................................................................. 366
11-12. MMCHS_PSTATE Register ............................................................................................. 367
11-13. MMCHS_HCTL Register................................................................................................. 369
11-14. MMCHS_SYSCTL Register ............................................................................................. 370
11-15. MMCHS_STAT Register................................................................................................. 372
11-16. MMCHS_IE Register ..................................................................................................... 376
11-17. MMCHS_ISE Register ................................................................................................... 378
12-1. I2S Protocol................................................................................................................ 381
12-2. MCASP Module ........................................................................................................... 382
12-3. Logical Clock Path........................................................................................................ 383
13-1. Architecture of the ADC Module in CC3200 .......................................................................... 397
13-2. Operation of the ADC .................................................................................................... 398
13-3. ADC_CTRL Register ..................................................................................................... 400
13-4. ADC_CH0_IRQ_EN Register ........................................................................................... 401
13-5. ADC_CH2_IRQ_EN Register ........................................................................................... 402
13-6. ADC_CH4_IRQ_EN Register ........................................................................................... 403
13-7. ADC_CH6_IRQ_EN Register ........................................................................................... 404
13-8. ADC_CH0_IRQ_STATUS Register .................................................................................... 405
13-9. ADC_CH2_IRQ_STATUS Register .................................................................................... 406
13-10. ADC_CH4_IRQ_STATUS Register .................................................................................... 407
13-11. ADC_CH6_IRQ_STATUS Register .................................................................................... 408
13-12. ADC_DMA_MODE_EN Register ....................................................................................... 409
13-13. ADC_TIMER_CONFIGURATION Register............................................................................ 410
13-14. ADC_TIMER_CURRENT_COUNT Register .......................................................................... 411
13-15. CHANNEL0FIFODATA Register........................................................................................ 412
13-16. CHANNEL2FIFODATA Register........................................................................................ 413
13-17. CHANNEL4FIFODATA Register........................................................................................ 414
13-18. CHANNEL6FIFODATA Register........................................................................................ 415
13-19. ADC_CH0_FIFO_LVL Register......................................................................................... 416
13-20. ADC_CH2_FIFO_LVL Register......................................................................................... 417
13-21. ADC_CH4_FIFO_LVL Register......................................................................................... 418
13-22. ADC_CH6_FIFO_LVL Register......................................................................................... 419
13-23. ADC_CH_ENABLE Register ............................................................................................ 420
14-1. The Camera Module Interfaces......................................................................................... 429
14-2. Synchronization Signals and Frame Timing........................................................................... 430
14-3. Synchronization Signals and Data Timing............................................................................. 430
14-4. Different Scenarios of CAM_P_HS and CAM_P_VS ................................................................ 431
14-5. CAM_P_HS Toggles Between Pixels in Decimation................................................................. 431
14-6. Parallel Camera I/F State Machine..................................................................................... 431
14-7. FIFO Image Data Format................................................................................................ 432
14-8. Assertion and De-Assertion of the DMA Request Signal............................................................ 434
12
List of Figures
Copyright © 2014–2018, Texas Instruments Incorporated
SWRU367D–June 2014–Revised May 2018
Submit Documentation Feedback
www.ti.com
14-9. CC_SYSCONFIG Register .............................................................................................. 437
14-10. CC_SYSSTATUS Register.............................................................................................. 438
14-11. CC_IRQSTATUS Register............................................................................................... 439
14-12. CC_IRQENABLE Register............................................................................................... 441
14-13. CC_CTRL Register....................................................................................................... 443
14-14. CC_CTRL_DMA Register ............................................................................................... 445
14-15. CC_CTRL_XCLK Register .............................................................................................. 446
14-16. CC_FIFODATA Register................................................................................................. 447
15-1. Power Management Unit Supports Two Supply Configurations.................................................... 456
15-2. Sleep Modes .............................................................................................................. 459
15-3. Power Management Control Architecture in CC3200................................................................ 461
15-4. CAMCLKCFG Register .................................................................................................. 472
15-5. CAMCLKEN Register .................................................................................................... 473
15-6. CAMSWRST Register.................................................................................................... 474
15-7. MCASPCLKEN Register................................................................................................. 475
15-8. MCASPSWRST Register ................................................................................................ 476
15-9. SDIOMCLKCFG Register................................................................................................ 477
15-10. SDIOMCLKEN Register.................................................................................................. 478
15-11. SDIOMSWRST Register................................................................................................. 479
15-12. APSPICLKCFG Register................................................................................................. 480
15-13. APSPICLKEN Register .................................................................................................. 481
15-14. APSPISWRST Register.................................................................................................. 482
15-15. DMACLKEN Register .................................................................................................... 483
15-16. DMASWRST Register.................................................................................................... 484
15-17. GPIO0CLKEN Register .................................................................................................. 485
15-18. GPIO0SWRST Register ................................................................................................. 486
15-19. GPIO1CLKEN Register .................................................................................................. 487
15-20. GPIO1SWRST Register ................................................................................................. 488
15-21. GPIO2CLKEN Register .................................................................................................. 489
15-22. GPIO2SWRST Register ................................................................................................. 490
15-23. GPIO3CLKEN Register .................................................................................................. 491
15-24. GPIO3SWRST Register ................................................................................................. 492
15-25. GPIO4CLKEN Register .................................................................................................. 493
15-26. GPIO4SWRST Register ................................................................................................. 494
15-27. WDTCLKEN Register .................................................................................................... 495
15-28. WDTSWRST Register.................................................................................................... 496
15-29. UART0CLKEN Register.................................................................................................. 497
15-30. UART0SWRST Register................................................................................................. 498
15-31. UART1CLKEN Register.................................................................................................. 499
15-32. UART1SWRST Register................................................................................................. 500
15-33. GPT0CLKCFG Register ................................................................................................. 501
15-34. GPT0SWRST Register................................................................................................... 502
15-35. GPT1CLKEN Register ................................................................................................... 503
15-36. GPT1SWRST Register................................................................................................... 504
15-37. GPT2CLKEN Register ................................................................................................... 505
15-38. GPT2SWRST Register................................................................................................... 506
15-39. GPT3CLKEN Register ................................................................................................... 507
15-40. GPT3SWRST Register................................................................................................... 508
15-41. MCASPCLKCFG0 Register ............................................................................................. 509
SWRU367D–June 2014–Revised May 2018
Submit Documentation Feedback
Copyright © 2014–2018, Texas Instruments Incorporated
List of Figures
13
www.ti.com
15-42. MCASPCLKCFG1 Register ............................................................................................. 510
15-43. I2CLCKEN Register ...................................................................................................... 511
15-44. I2CSWRST Register ..................................................................................................... 512
15-45. LPDSREQ Register....................................................................................................... 513
15-46. TURBOREQ Register .................................................................................................... 514
15-47. DSLPWAKECFG Register............................................................................................... 515
15-48. DSLPTIMRCFG Register ................................................................................................ 516
15-49. SLPWAKEEN Register................................................................................................... 517
15-50. SLPTMRCFG Register................................................................................................... 518
15-51. WAKENWP Register ..................................................................................................... 519
15-52. RCM_IS Register ......................................................................................................... 520
15-53. RCM_IEN Register ....................................................................................................... 521
16-1. Board Configuration to Use Pins 45 and 52 as Digital Signals..................................................... 526
16-2. Board Configuration to Use Pins 45 and 52 as Digital Signals..................................................... 527
16-3. I/O Pad Data and Control Path Architecture in CC3200............................................................. 550
16-4. Wake on Pad for Hibernate Mode...................................................................................... 553
B-1. DMA_IMR Register....................................................................................................... 558
B-2. DMA_IMS Register ....................................................................................................... 560
B-3. DMA_IMC Register....................................................................................................... 562
B-4. DMA_ICR Register ....................................................................................................... 564
B-5. DMA_MIS Register ....................................................................................................... 566
B-6. DMA_RIS Register ....................................................................................................... 568
B-7. GPTTRIGSEL Register .................................................................................................. 570
14
List of Figures
Copyright © 2014–2018, Texas Instruments Incorporated
SWRU367D–June 2014–Revised May 2018
Submit Documentation Feedback
www.ti.com
1-1. Register Bit Accessibility and Initial Condition ......................................................................... 23
2-1. Summary of Processor Mode, Privilege Level, and Stack Use ...................................................... 37
2-2. Processor Register Map................................................................................................... 38
2-3. PSR Register Combinations .............................................................................................. 40
2-4. Memory Map................................................................................................................ 41
2-5. SRAM Memory Bit-Banding Regions.................................................................................... 42
2-6. Exception Types............................................................................................................ 46
2-7. CC3200 Application Processor Interrupts............................................................................... 46
2-8. Faults ........................................................................................................................ 50
2-9. Fault Status and Fault Address Registers .............................................................................. 52
2-10. Cortex-M4 Instruction Summary.......................................................................................... 54
3-1. Core Peripheral Register Regions ....................................................................................... 60
3-2. Peripherals Register Map ................................................................................................. 62
3-3. PERIPHERAL REGISTERS .............................................................................................. 66
3-4. ACTLR Register Field Descriptions...................................................................................... 67
3-5. STCTRL Register Field Descriptions .................................................................................... 68
3-6. STRELOAD Register Field Descriptions................................................................................ 69
3-7. STCURRENT Register Field Descriptions.............................................................................. 70
3-8. EN_0 to EN_6 Register Field Descriptions ............................................................................. 71
3-9. DIS_0 to DIS_6 Register Field Descriptions............................................................................ 72
3-10. PEND_0 to PEND_6 Register Field Descriptions...................................................................... 73
3-11. UNPEND_0 to UNPEND_6 Register Field Descriptions.............................................................. 74
3-12. ACTIVE_0 to ACTIVE_6 Register Field Descriptions ................................................................. 75
3-13. PRI_0 to PRI_49 Register Field Descriptions .......................................................................... 76
3-14. CPUID Register Field Descriptions ...................................................................................... 77
3-15. INTCTRL Register Field Descriptions ................................................................................... 78
3-16. VTABLE Register Field Descriptions .................................................................................... 80
3-17. APINT Register Field Descriptions....................................................................................... 81
3-18. SYSCTRL Register Field Descriptions .................................................................................. 82
3-19. CFGCTRL Register Field Descriptions.................................................................................. 83
3-20. SYSPRI1 Register Field Descriptions ................................................................................... 85
3-21. SYSPRI2 Register Field Descriptions ................................................................................... 86
3-22. SYSPRI3 Register Field Descriptions ................................................................................... 87
3-23. SYSHNDCTRL Register Field Descriptions ............................................................................ 88
3-24. FAULTSTAT Register Field Descriptions ............................................................................... 90
3-25. HFAULTSTAT Register Field Descriptions ............................................................................. 94
3-26. FAULTDDR Register Field Descriptions ................................................................................ 95
3-27. SWTRIG Register Field Descriptions.................................................................................... 96
4-1. Channel Control Memory ................................................................................................ 100
4-2. Individual Control Structure.............................................................................................. 101
4-3. 8-bit Data Peripheral Configuration..................................................................................... 106
4-4. µDMA Register Map...................................................................................................... 108
4-5. DMA Registers ............................................................................................................ 110
4-6. DMA_SRCENDP Register Field Descriptions ........................................................................ 111
4-7. DMA_DSTENDP Register Field Descriptions......................................................................... 112
4-8. DMA_CHCTL Register Field Descriptions............................................................................. 113
4-9. DMA_(OFFSET_FROM_DMA_BASE_ADDRESS) Registers...................................................... 115
List of Tables
SWRU367D–June 2014–Revised May 2018
Submit Documentation Feedback
Copyright © 2014–2018, Texas Instruments Incorporated
List of Tables
15
www.ti.com
4-10. DMA_STAT Register Field Descriptions............................................................................... 116
4-11. DMA_CFG Register Field Descriptions................................................................................ 117
4-12. DMA_CTLBASE Register Field Descriptions ......................................................................... 118
4-13. DMA_ALTBASE Register Field Descriptions ......................................................................... 119
4-14. DMA_WAITSTAT Register Field Descriptions........................................................................ 120
4-15. DMA_SWREQ Register Field Descriptions ........................................................................... 121
4-16. DMA_USEBURSTSET Register Field Descriptions.................................................................. 122
4-17. DMA_USEBURSTCLR Register Field Descriptions.................................................................. 123
4-18. DMA_REQMASKSET Register Field Descriptions................................................................... 124
4-19. DMA_REQMASKCLR Register Field Descriptions................................................................... 125
4-20. DMA_ENASET Register Field Descriptions........................................................................... 126
4-21. DMA_ENACLR Register Field Descriptions........................................................................... 127
4-22. DMA_ALTSET Register Field Descriptions ........................................................................... 128
4-23. DMA_ALTCLR Register Field Descriptions ........................................................................... 129
4-24. DMA_PRIOSET Register Field Descriptions.......................................................................... 130
4-25. DMA_PRIOCLR Register Field Descriptions.......................................................................... 131
4-26. DMA_ERRCLR Register Field Descriptions........................................................................... 132
4-27. DMA_CHASGN Register Field Descriptions .......................................................................... 133
4-28. DMA_CHMAP0 Register Field Descriptions .......................................................................... 134
4-29. DMA_CHMAP1 Register Field Descriptions .......................................................................... 135
4-30. DMA_CHMAP2 Register Field Descriptions .......................................................................... 136
4-31. DMA_CHMAP3 Register Field Descriptions .......................................................................... 137
4-32. DMA_PV Register Field Descriptions.................................................................................. 138
5-1. GPIO Pad Configuration Examples .................................................................................... 142
5-2. GPIO Interrupt Configuration Example................................................................................. 143
5-3. GPIO_REGISTER_MAP Registers..................................................................................... 144
5-4. GPIODATA Register Field Descriptions ............................................................................... 145
5-5. GPIODIR Register Field Descriptions.................................................................................. 146
5-6. GPIOIS Register Field Descriptions.................................................................................... 147
5-7. GPIOIBE Register Field Descriptions.................................................................................. 148
5-8. GPIOIEV Register Field Descriptions.................................................................................. 149
5-9. GPIOIM Register Field Descriptions ................................................................................... 150
5-10. GPIORIS Register Field Descriptions.................................................................................. 151
5-11. GPIOMIS Register Field Descriptions.................................................................................. 152
5-12. GPIOICR Register Field Descriptions.................................................................................. 153
5-13. GPIO_TRIG_EN Register Field Descriptions ......................................................................... 154
5-14. GPIO Mapping ............................................................................................................ 154
6-1. Flow Control Mode........................................................................................................ 160
6-2. UART Register Map ...................................................................................................... 163
6-3. UART REGISTERS....................................................................................................... 164
6-4. UARTDR Register Field Descriptions.................................................................................. 165
6-5. UARTRSR_UARTECR Register Field Descriptions.................................................................. 166
6-6. UARTFR Register Field Descriptions .................................................................................. 168
6-7. UARTIBRD Register Field Descriptions ............................................................................... 170
6-8. UARTFBRD Register Field Descriptions .............................................................................. 171
6-9. UARTLCRH Register Field Descriptions .............................................................................. 172
6-10. UARTCTL Register Field Descriptions................................................................................. 174
6-11. UARTIFLS Register Field Descriptions ................................................................................ 176
6-12. UARTIM Register Field Descriptions................................................................................... 177
16
List of Tables
Copyright © 2014–2018, Texas Instruments Incorporated
SWRU367D–June 2014–Revised May 2018
Submit Documentation Feedback
www.ti.com
6-13. UARTRIS Register Field Descriptions ................................................................................. 179
6-14. UARTMIS Register Field Descriptions................................................................................. 181
6-15. UARTICR Register Field Descriptions ................................................................................. 183
6-16. UARTDMACTL Register Field Descriptions........................................................................... 185
7-1. I2C Signals (64QFN) ..................................................................................................... 189
7-2. Timer Periods ............................................................................................................. 193
7-3. I2C REGISTERS.......................................................................................................... 205
7-4. I2CMSA Register Field Descriptions................................................................................... 206
7-5. I2CMCS Register Field Descriptions................................................................................... 207
7-6. I2CMDR Register Field Descriptions................................................................................... 209
7-7. I2CMTPR Register Field Descriptions ................................................................................. 210
7-8. I2CMIMR Register Field Descriptions.................................................................................. 211
7-9. I2CMRIS Register Field Descriptions .................................................................................. 213
7-10. I2CMMIS Register Field Descriptions.................................................................................. 215
7-11. I2CMICR Register Field Descriptions.................................................................................. 217
7-12. I2CMCR Register Field Descriptions................................................................................... 219
7-13. I2CMCLKOCNT Register Field Descriptions.......................................................................... 220
7-14. I2CMBMON Register Field Descriptions............................................................................... 221
7-15. I2CMBLEN Register Field Descriptions................................................................................ 222
7-16. I2CMBCNT Register Field Descriptions ............................................................................... 223
7-17. I2CSOAR Register Field Descriptions ................................................................................. 224
7-18. I2CSCSR Register Field Descriptions ................................................................................. 225
7-19. I2CSDR Register Field Descriptions ................................................................................... 227
7-20. I2CSIMR Register Field Descriptions .................................................................................. 228
7-21. I2CSRIS Register Field Descriptions................................................................................... 230
7-22. I2CSMIS Register Field Descriptions .................................................................................. 232
7-23. I2CSICR Register Field Descriptions .................................................................................. 234
7-24. I2CSOAR2 Register Field Descriptions................................................................................ 236
7-25. I2CSACKCTL Register Field Descriptions ............................................................................ 237
7-26. I2CFIFODATA Register Field Descriptions............................................................................ 238
7-27. I2CFIFOCTL Register Field Descriptions.............................................................................. 239
7-28. I2CFIFOSTATUS Register Field Descriptions ........................................................................ 241
7-29. I2CPP Register Field Descriptions ..................................................................................... 242
7-30. I2CPC Register Field Descriptions ..................................................................................... 243
8-1. SPI Interface .............................................................................................................. 246
8-2. Phase and Polarity Combinations ...................................................................................... 248
8-3. Clock Ratio Granularity .................................................................................................. 253
8-4. Granularity Examples .................................................................................................... 253
8-5. SPI Word Length WL..................................................................................................... 253
8-6. SPI Registers.............................................................................................................. 270
8-7. SPI_SYSCONFIG Register Field Descriptions ....................................................................... 271
8-8. SPI_SYSSTATUS Register Field Descriptions ....................................................................... 272
8-9. SPI_IRQSTATUS Register Field Descriptions........................................................................ 273
8-10. SPI_IRQENABLE Register Field Descriptions........................................................................ 275
8-11. SPI_MODULCTRL Register Field Descriptions ...................................................................... 276
8-12. SPI_CHCONF Register Field Descriptions............................................................................ 277
8-13. SPI_CHSTAT Register Field Descriptions ............................................................................ 280
8-14. SPI_CHCTRL Register Field Descriptions ............................................................................ 281
8-15. SPI_TX Register Field Descriptions.................................................................................... 282
SWRU367D–June 2014–Revised May 2018
Submit Documentation Feedback
Copyright © 2014–2018, Texas Instruments Incorporated
List of Tables
17
www.ti.com
8-16. SPI_RX Register Field Descriptions.................................................................................... 283
8-17. SPI_XFERLEVEL Register Field Descriptions........................................................................ 284
9-1. Available CCP Pins and PWM Outputs/Signals Pins ................................................................ 286
9-2. General-Purpose Timer Capabilities ................................................................................... 287
9-3. Counter Values When the Timer is Enabled in Periodic or One-Shot Modes .................................... 288
9-4. 16-Bit Timer With Prescaler Configurations........................................................................... 289
9-5. Counter Values When the Timer is Enabled in Input Edge-Count Mode.......................................... 290
9-6. Counter Values When the Timer is Enabled in Input Event-Count Mode......................................... 291
9-7. Counter Values When the Timer is Enabled in PWM Mode ........................................................ 292
9-8. TIMER Registers.......................................................................................................... 297
9-9. GPTMCFG Register Field Descriptions................................................................................ 298
9-10. GPTMTAMR Register Field Descriptions.............................................................................. 299
9-11. GPTMTBMR Register Field Descriptions.............................................................................. 301
9-12. GPTMCTL Register Field Descriptions ................................................................................ 303
9-13. GPTMIMR Register Field Descriptions ................................................................................ 305
9-14. GPTMRIS Register Field Descriptions................................................................................. 307
9-15. GPTMMIS Register Field Descriptions................................................................................. 309
9-16. GPTMICR Register Field Descriptions................................................................................. 311
9-17. GPTMTAILR Register Field Descriptions.............................................................................. 313
9-18. GPTMTBILR Register Field Descriptions.............................................................................. 314
9-19. GPTMTAMATCHR Register Field Descriptions ...................................................................... 315
9-20. GPTMTBMATCHR Register Field Descriptions ...................................................................... 316
9-21. GPTMTAPR Register Field Descriptions .............................................................................. 317
9-22. GPTMTBPR Register Field Descriptions .............................................................................. 318
9-23. GPTMTAPMR Register Field Descriptions............................................................................ 319
9-24. GPTMTBPMR Register Field Descriptions............................................................................ 320
9-25. GPTMTAR Register Field Descriptions................................................................................ 321
9-26. GPTMTBR Register Field Descriptions................................................................................ 322
9-27. GPTMTAV Register Field Descriptions ................................................................................ 323
9-28. GPTMTBV Register Field Descriptions ................................................................................ 324
9-29. GPTMDMAEV Register Field Descriptions............................................................................ 325
10-1. Watchdog Timers Register Map ........................................................................................ 330
10-2. WATCHDOG Registers .................................................................................................. 331
10-3. WDTLOAD Register Field Descriptions................................................................................ 332
10-4. WDTVALUE Register Field Descriptions .............................................................................. 333
10-5. WDTCTL Register Field Descriptions.................................................................................. 334
10-6. WDTICR Register Field Descriptions .................................................................................. 335
10-7. WDTRIS Register Field Descriptions .................................................................................. 336
10-8. WDTTEST Register Field Descriptions ................................................................................ 337
10-9. WDTLOCK Register Field Descriptions................................................................................ 338
11-1. Card Types ................................................................................................................ 349
11-2. Throughput Data .......................................................................................................... 349
11-3. Base Address of SD-Host (also referred as MMCHS)............................................................... 354
11-4. SD-HOST Registers...................................................................................................... 354
11-5. MMCHS_CSRE Register Field Descriptions.......................................................................... 355
11-6. MMCHS_CON Register Field Descriptions ........................................................................... 356
11-7. MMCHS_BLK Register Field Descriptions ............................................................................ 358
11-8. MMCHS_ARG Register Field Descriptions............................................................................ 359
11-9. MMCHS_CMD Register Field Descriptions ........................................................................... 360
18
List of Tables
Copyright © 2014–2018, Texas Instruments Incorporated
SWRU367D–June 2014–Revised May 2018
Submit Documentation Feedback
www.ti.com
11-10. MMCHS_RSP10 Register Field Descriptions......................................................................... 362
11-11. MMCHS_RSP32 Register Field Descriptions......................................................................... 363
11-12. MMCHS_RSP54 Register Field Descriptions......................................................................... 364
11-13. MMCHS_RSP76 Register Field Descriptions......................................................................... 365
11-14. MMCHS_DATA Register Field Descriptions .......................................................................... 366
11-15. MMCHS_PSTATE Register Field Descriptions....................................................................... 367
11-16. MMCHS_HCTL Register Field Descriptions .......................................................................... 369
11-17. MMCHS_SYSCTL Register Field Descriptions....................................................................... 370
11-18. MMCHS_STAT Register Field Descriptions........................................................................... 372
11-19. MMCHS_IE Register Field Descriptions............................................................................... 376
11-20. MMCHS_ISE Register Field Descriptions............................................................................. 378
12-1. ulIntFlags Parameter ..................................................................................................... 392
12-2. ulStatFlags Parameter ................................................................................................... 392
13-1. ADC Registers ............................................................................................................ 398
13-2. ADC_MODULE Registers ............................................................................................... 399
13-3. ADC_CTRL Register Field Descriptions............................................................................... 400
13-4. ADC_CH0_IRQ_EN Register Field Descriptions..................................................................... 401
13-5. ADC_CH2_IRQ_EN Register Field Descriptions..................................................................... 402
13-6. ADC_CH4_IRQ_EN Register Field Descriptions..................................................................... 403
13-7. ADC_CH6_IRQ_EN Register Field Descriptions..................................................................... 404
13-8. ADC_CH0_IRQ_STATUS Register Field Descriptions .............................................................. 405
13-9. ADC_CH2_IRQ_STATUS Register Field Descriptions .............................................................. 406
13-10. ADC_CH4_IRQ_STATUS Register Field Descriptions.............................................................. 407
13-11. ADC_CH6_IRQ_STATUS Register Field Descriptions.............................................................. 408
13-12. ADC_DMA_MODE_EN Register Field Descriptions................................................................. 409
13-13. ADC_TIMER_CONFIGURATION Register Field Descriptions ..................................................... 410
13-14. ADC_TIMER_CURRENT_COUNT Register Field Descriptions.................................................... 411
13-15. CHANNEL0FIFODATA Register Field Descriptions ................................................................. 412
13-16. CHANNEL2FIFODATA Register Field Descriptions ................................................................. 413
13-17. CHANNEL4FIFODATA Register Field Descriptions ................................................................. 414
13-18. CHANNEL6FIFODATA Register Field Descriptions ................................................................. 415
13-19. ADC_CH0_FIFO_LVL Register Field Descriptions................................................................... 416
13-20. ADC_CH2_FIFO_LVL Register Field Descriptions................................................................... 417
13-21. ADC_CH4_FIFO_LVL Register Field Descriptions................................................................... 418
13-22. ADC_CH6_FIFO_LVL Register Field Descriptions................................................................... 419
13-23. ADC_CH_ENABLE Register Field Descriptions...................................................................... 420
13-24. ulChannel Tags ........................................................................................................... 421
13-25. ulIntFlags Tags............................................................................................................ 421
14-1. Image Sensor Interface Signals ........................................................................................ 429
14-2. Ratio of the XCLK Frequency Generator.............................................................................. 433
14-3. CAMERA REGISTERS .................................................................................................. 436
14-4. CC_SYSCONFIG Register Field Descriptions........................................................................ 437
14-5. CC_SYSSTATUS Register Field Descriptions........................................................................ 438
14-6. CC_IRQSTATUS Register Field Descriptions ........................................................................ 439
14-7. CC_IRQENABLE Register Field Descriptions ........................................................................ 441
14-8. CC_CTRL Register Field Descriptions................................................................................. 443
14-9. CC_CTRL_DMA Register Field Descriptions ......................................................................... 445
14-10. CC_CTRL_XCLK Register Field Descriptions ........................................................................ 446
14-11. CC_FIFODATA Register Field Descriptions .......................................................................... 447
SWRU367D–June 2014–Revised May 2018
Submit Documentation Feedback
Copyright © 2014–2018, Texas Instruments Incorporated
List of Tables
19
www.ti.com
15-1. Possible PM State Combinations of Application Processor and Network Subsystem (NWP+WLAN) ........ 460
15-2. Peripheral Macro Table.................................................................................................. 468
15-3. PRCM Registers .......................................................................................................... 470
15-4. CAMCLKCFG Register Field Descriptions ............................................................................ 472
15-5. CAMCLKEN Register Field Descriptions .............................................................................. 473
15-6. CAMSWRST Register Field Descriptions ............................................................................. 474
15-7. MCASPCLKEN Register Field Descriptions........................................................................... 475
15-8. MCASPSWRST Register Field Descriptions.......................................................................... 476
15-9. SDIOMCLKCFG Register Field Descriptions ......................................................................... 477
15-10. SDIOMCLKEN Register Field Descriptions ........................................................................... 478
15-11. SDIOMSWRST Register Field Descriptions........................................................................... 479
15-12. APSPICLKCFG Register Field Descriptions .......................................................................... 480
15-13. APSPICLKEN Register Field Descriptions ............................................................................ 481
15-14. APSPISWRST Register Field Descriptions ........................................................................... 482
15-15. DMACLKEN Register Field Descriptions .............................................................................. 483
15-16. DMASWRST Register Field Descriptions ............................................................................. 484
15-17. GPIO0CLKEN Register Field Descriptions............................................................................ 485
15-18. GPIO0SWRST Register Field Descriptions ........................................................................... 486
15-19. GPIO1CLKEN Register Field Descriptions............................................................................ 487
15-20. GPIO1SWRST Register Field Descriptions ........................................................................... 488
15-21. GPIO2CLKEN Register Field Descriptions............................................................................ 489
15-22. GPIO2SWRST Register Field Descriptions ........................................................................... 490
15-23. GPIO3CLKEN Register Field Descriptions............................................................................ 491
15-24. GPIO3SWRST Register Field Descriptions ........................................................................... 492
15-25. GPIO4CLKEN Register Field Descriptions............................................................................ 493
15-26. GPIO4SWRST Register Field Descriptions ........................................................................... 494
15-27. WDTCLKEN Register Field Descriptions.............................................................................. 495
15-28. WDTSWRST Register Field Descriptions ............................................................................. 496
15-29. UART0CLKEN Register Field Descriptions ........................................................................... 497
15-30. UART0SWRST Register Field Descriptions........................................................................... 498
15-31. UART1CLKEN Register Field Descriptions ........................................................................... 499
15-32. UART1SWRST Register Field Descriptions........................................................................... 500
15-33. GPT0CLKCFG Register Field Descriptions ........................................................................... 501
15-34. GPT0SWRST Register Field Descriptions ............................................................................ 502
15-35. GPT1CLKEN Register Field Descriptions............................................................................. 503
15-36. GPT1SWRST Register Field Descriptions ............................................................................ 504
15-37. GPT2CLKEN Register Field Descriptions............................................................................. 505
15-38. GPT2SWRST Register Field Descriptions ............................................................................ 506
15-39. GPT3CLKEN Register Field Descriptions............................................................................. 507
15-40. GPT3SWRST Register Field Descriptions ............................................................................ 508
15-41. MCASPCLKCFG0 Register Field Descriptions....................................................................... 509
15-42. MCASPCLKCFG1 Register Field Descriptions....................................................................... 510
15-43. I2CLCKEN Register Field Descriptions................................................................................ 511
15-44. I2CSWRST Register Field Descriptions ............................................................................... 512
15-45. LPDSREQ Register Field Descriptions ................................................................................ 513
15-46. TURBOREQ Register Field Descriptions.............................................................................. 514
15-47. DSLPWAKECFG Register Field Descriptions ........................................................................ 515
15-48. DSLPTIMRCFG Register Field Descriptions.......................................................................... 516
15-49. SLPWAKEEN Register Field Descriptions ............................................................................ 517
20
List of Tables
Copyright © 2014–2018, Texas Instruments Incorporated
SWRU367D–June 2014–Revised May 2018
Submit Documentation Feedback
www.ti.com
15-50. SLPTMRCFG Register Field Descriptions ............................................................................ 518
15-51. WAKENWP Register Field Descriptions............................................................................... 519
15-52. RCM_IS Register Field Descriptions................................................................................... 520
15-53. RCM_IEN Register Field Descriptions................................................................................. 521
16-1. GPIO Pin Electrical Specifications (25 C)(Except Pin 29, 30, 45, 50, 52 , 53) ................................... 523
16-2. GPIO Pin Electrical Specifications (25 C) For Pins 29, 30, 45, 50, 52 , 53....................................... 524
16-3. Pin Internal Pullup and Pulldown Electrical Specifications (25 C).................................................. 525
16-4. Analog Mux Control Registers and Bits................................................................................ 528
16-5. Board Level Behavior .................................................................................................... 529
16-6. GPIO/Pins Available for Application.................................................................................... 530
16-7. Pin Multiplexing ........................................................................................................... 533
16-8. Pin Groups for I2S........................................................................................................ 547
16-9. Pin Groups for SPI........................................................................................................ 547
16-10. Pin Groups for SD-Card I/F ............................................................................................. 547
16-11. Pad Configuration Registers ............................................................................................ 547
16-12. GPIO_PAD_CONFIG_0 to GPIO_PAD_CONFIG_32 Register Description ...................................... 548
16-13. Recommended Pin Multiplexing Configurations...................................................................... 551
16-14. Sense-on-Power Configurations........................................................................................ 555
A-1. Peripheral Samples....................................................................................................... 556
B-1. Miscellaneous Register Summary ...................................................................................... 557
B-2. DMA_IMR Register Field Descriptions................................................................................. 558
B-3. DMA_IMS Register Field Descriptions................................................................................. 560
B-4. DMA_IMC Register Field Descriptions................................................................................. 562
B-5. DMA_ICR Register Field Descriptions................................................................................. 564
B-6. DMA_MIS Register Field Descriptions................................................................................. 566
B-7. DMA_RIS Register Field Descriptions ................................................................................. 568
B-8. GPTTRIGSEL Register Field Descriptions............................................................................ 570
SWRU367D–June 2014–Revised May 2018
Submit Documentation Feedback
Copyright © 2014–2018, Texas Instruments Incorporated
List of Tables
21
Chapter 1
SWRU367D–June 2014–Revised May 2018
Architecture Overview
Topic ........................................................................................................................... Page
1.1 Introduction....................................................................................................... 23
1.2 Architecture Overview ........................................................................................ 24
1.3 Functional Overview........................................................................................... 25
22
Architecture Overview
Copyright © 2014–2018, Texas Instruments Incorporated
SWRU367D–June 2014–Revised May 2018
Submit Documentation Feedback
www.ti.com
1.1 Introduction
Created for the Internet of Things (IoT), the SimpleLink CC3200 device is a wireless MCU that integrates
a high-performance ARM Cortex-M4 MCU, allowing customers to develop an entire application with a
single IC. With on-chip Wi-Fi, Internet, and robust security protocols, no prior Wi-Fi experience is required
for faster development.
The applications MCU subsystem contains an industry-standard ARM Cortex-M4 core running at 80 MHz.
The device includes a wide variety of peripherals, including a fast parallel camera interface, I2S, SD,
UART, SPI, I2C, and four-channel ADC. The CC3200 family includes flexible embedded RAM for code
and data and ROM with external serial flash bootloader and peripheral drivers.
The Wi-Fi network processor subsystem features a Wi-Fi Internet-on-a-chip, and contains an additional
dedicated ARM MCU that completely offloads the applications MCU. This subsystem includes an 802.11
b/g/n radio, baseband, and MAC with a powerful crypto engine for fast, secure Internet connections with
256-bit encryption. The CC3200 device supports Station, Access Point, and Wi-Fi Direct modes. The
device also supports WPA2 personal and enterprise security and WPS 2.0. The Wi-Fi Internet-on-a-chip
includes embedded TCP/IP and TLS/SSL stacks, HTTP server, and multiple Internet protocols.
About This Manual
This manual describes the modules and peripherals of the SimpleLink CC3200 wireless MCU. Each
description presents the module or peripheral in a general sense. Not all features and functions of all
modules or peripherals may be present on all devices. Pin functions, internal signal connections, and
operational parameters differ from device to device. The user should consult the device-specific data
sheet for these details.
Introduction
1.1.1 Related Documentation
Additional documentation about the device can be accessed from these links from Texas Instruments
http://www.ti.com/simplelinkwifi and http://www.ti.com/simplelinkwifi-wiki
1.1.2 Register Bit Conventions
Each register is shown with a key indicating the accessibility of the individual bit, and the initial condition:
Table 1-1. Register Bit Accessibility and Initial Condition
Key Bit Accessibility
rw Read/write
r Read only
r0 Read as 0
r1 Read as 1
w Write only
w0 Write as 0
w1 Write as 1
(w)
h0 Cleared by hardware
h1 Set by hardware
-0, -1 Condition after PUC
-(0), -(1) Condition after POR
-[0], -[1] Condition after BOR
-{0},-{1} Condition after Brownout
No register bit implemented; writing a 1 results in a pulse. The register bit is always read
as 0.
SWRU367D–June 2014–Revised May 2018
Submit Documentation Feedback
Copyright © 2014–2018, Texas Instruments Incorporated
Architecture Overview
23
Architecture Overview
1.2 Architecture Overview
The building blocks of CC3200 system-on-chip are shown in Figure 1-1
Figure 1-1. CC3200 MCU and WIFI System-on-Chip
www.ti.com
24
Architecture Overview
Copyright © 2014–2018, Texas Instruments Incorporated
SWRU367D–June 2014–Revised May 2018
Submit Documentation Feedback
www.ti.com
1.3 Functional Overview
The following sections provide an overview of the main components of the CC3200 system on chip (SoC)
from a microcontroller point of view.
1.3.1 Processor Core
1.3.1.1 ARM CortexTMM4 Processor Core
The CC3200 application MCU subsystem is built around an ARM Cortex-M4 processor core, which
provides outstanding computational performance and exceptional system response to interrupts at low
power consumption while optimizing memory footprint – making it an ideal fit for embedded applications.
Key features of ARM Cortex-M4 processor core are:
• Thumb-2 mixed 16- and 32-bit instruction set delivers the high performance expected of a 32-bit ARM
core in a compact memory size – enabling richer applications within a given device memory size.
• Single-cycle multiply instruction and hardware divide
• Atomic bit manipulation (bit-banding), delivering maximum memory use and streamlined peripheral
control
• Unaligned data access, enabling data to be efficiently packed into memory
• Fast code execution, permitting slower processor clock or increased sleep mode time.
• Hardware division and fast multiplier
• Deterministic, high-performance interrupt handling for time-critical applications
• Bit-band support for memory and select peripherals that includes atomic bit-band write and read
operations
• Configurable 4-pin JTAG and 2-pin (SWJ-DP) debug access
• Flash patch and breakpoint (FPB) unit to implement breakpoints and code patches
• Ultra-low power sleep modes
• Low active power consumption
• 80-MHz operation
Functional Overview
1.3.1.2 System Timer (SysTick)
The ARM Cortex-M4 processor core includes an integrated system timer, SysTick. SysTick provides a
simple, 24-bit, clear-on-write, decrementing, wrap-on-zero counter with a flexible control mechanism. The
counter is clocked on the system clock.
SysTick makes OS porting between Cortex-M4 devices much easier because there is no need to change
the OS system timer code. The SysTick timer integrates with the NVIC and can generate a SysTick
exception (exception type 15). In many OSes, a hardware timer generates interrupts so that the OS can
perform task management (for example, to allow multiple tasks to run at different time slots and to ensure
that no single task can lock up the entire system). To perform this function, the timer must be able to
generate interrupts and, if possible, be protected from user tasks so that user applications cannot change
the timer behavior.
The counter can be used in several different ways; for example:
• An RTOS tick timer that fires at a programmable rate (for example, 100 Hz) and invokes a SysTick
routine
• A high-speed alarm timer using the system clock
• A simple counter used to measure time to completion and time used
• An internal clock-source control based on missing or meeting durations
SWRU367D–June 2014–Revised May 2018
Submit Documentation Feedback
Copyright © 2014–2018, Texas Instruments Incorporated
Architecture Overview
25
Functional Overview
1.3.1.3 Nested Vector Interrupt Controller (NVIC)
CC3200 includes the ARM NVIC. The NVIC and Cortex-M3 prioritize and handle all exceptions in handler
mode. The processor state is automatically stored to the stack on an exception and automatically restored
from the stack at the end of the interrupt service routine (ISR). The interrupt vector is fetched in parallel to
the state saving, thus enabling efficient interrupt entry. The processor supports tail-chaining, meaning that
back-to-back interrupts can be performed without the overhead of state saving and restoration. The NVIC
and Cortex-M4 processor prioritize and handle all exceptions in handler mode. The NVIC and the
processor core interface are closely coupled to enable low-latency interrupt processing and efficient
processing of late-arriving interrupts. The NVIC maintains knowledge of the stacked, or nested, interrupts
to enable tail-chaining of interrupts.
Key features are:
• Exceptional interrupt handling through hardware implementation of required register manipulations
• Deterministic, fast interrupt processing: always 12 cycles, or just 6 cycles with tail-chaining
• Programmable priority level for each interrupt
• Low-latency interrupt and exception handling
• Level and pulse detection of interrupt signals
• Grouping of interrupts into group priority and sub-priority interrupts
• Tail chaining of interrupts
1.3.1.4 System Control Block
The system control block (SCB) provides system implementation information and system control, including
configuration, control, and reporting of system exceptions.
www.ti.com
1.3.2 Memory
1.3.2.1 On-Chip SRAM
To enable low-cost applications, the CC3200 device family follows a flash-less approach. CC3200 has up
to 256KB of zero wait state, on-chip SRAM, to which application programs are downloaded and executed.
The SRAM is used for both code and data, and is connected to the Multi-Layer-AHB bus-matrix of the
chip. There is no restriction on relative size or partitioning of code and data.
The micro direct memory access (μDMA) controller can transfer data to and from SRAM and various
peripherals. The SRAM banks implement an advanced 4-way interleaved architecture which almost
eliminates the performance penalty when DMA and processor simultaneously access the SRAM.
Internal RAM has selective retention capability during low-power deep-sleep (LPDS) mode. Based on
need, during LPDS mode the application can choose to retain 256KB, 192KB, 128KB or 64KB. Retaining
the memory during low power mode provides a faster wakeup. TI provides an easy to use power
management framework for processor and peripheral context save and restore mechanism based on
SRAM retention. For more information, refer to the Power Management Framework User Guide in
Section 15.6.
1.3.2.2 ROM
CC3200 comes with factory programmed zero-wait-state ROM with the following firmware components:
• Device initialization
• Bootloader
• Peripheral driver library (DriverLib) release for product-specific peripherals and interfaces
When CC3200 powers up, or chip reset is released or returns from hibernate mode, the device
initialization procedure is executed first. After the chip hardware has been correctly configured, the
bootloader is executed, which loads the application code from non-volatile memory into on-chip SRAM
and makes a jump to the application code entry point.
26
Architecture Overview
Copyright © 2014–2018, Texas Instruments Incorporated
SWRU367D–June 2014–Revised May 2018
Submit Documentation Feedback
www.ti.com
The CC3200 DriverLib is a software library that controls on-chip peripherals. The library performs both
peripheral initialization and control functions, with a choice of polled or interrupt-driven peripheral support.
The ROM DriverLib provides a rich set of drivers for peripheral and chip. It is aimed at reducing
application development time and improving solution robustness. TI recommends that applications make
extensive use of the DriverLib APIs to optimize memory and MIPS requirement of end applications.
1.3.3 Micro Direct Memory Access Controller (µDMA)
The CC3200 microcontroller includes a multichannel DMA controller, or μDMA. The μDMA controller
provides a way to offload data-transfer tasks from the Cortex-M4 processor, allowing more efficient use of
the processor and the available bus bandwidth. The μDMA controller can perform transfers between
memory and peripherals; it has dedicated channels for each supported on-chip module. The μDMA
controller can be programmed to automatically perform transfers between peripherals and memory as the
peripheral is ready to transfer more data.
The μDMA controller provides the following features:
• 32 configurable channels
• 80-MHz operation
• Support for memory to memory, memory to peripheral, and peripheral to memory in multiple transfer
modes
– Basic and simple transfer scenarios
– Ping-Pong for continuous data flow
– Scatter-gather for a programmable list of arbitrary transfers initiated from a single request
• Highly flexible and configurable channel operation
– Independently configured and operated channels
– Dedicated channels for supported on-chip modules
– One channel each for receive and transmit path for bidirectional modules
– Dedicated channel for software-initiated transfers
– Per-channel configurable bus arbitration scheme
– Software-initiated requests for any channel
• Two levels of priority
• Design optimizations for improved bus access performance between the µDMA controller and the
processor core
– µDMA controller access subordinate to core access
– Simultaneous concurrent access
• Data sizes of 8, 16, and 32 bits
• Transfer size is programmable in binary steps from 1 to 1024
• Source and destination address increment size of byte, half-word, word, or no increment
• Maskable peripheral requests
• Interrupt on transfer completion, with a separate interrupt per channel
Functional Overview
1.3.4 General Purpose Timer (GPT)
The CC3200 includes 4 instances of 32-bit user-programmable general purpose timers. GPTs count or
time external events that drive the timer input pins. Each GPT module (GPTM) block provides two 16-bit
timers or counters that can be configured to operate independently as timers or event counters, or
configured to operate as one 32-bit timer. The GPTM contains GPTM blocks with the following functional
options:
• Operating modes:
– 16- or 32-bit programmable one-shot timer
– 16- or 32-bit programmable periodic timer
SWRU367D–June 2014–Revised May 2018
Submit Documentation Feedback
Copyright © 2014–2018, Texas Instruments Incorporated
Architecture Overview
27
Functional Overview
– 16-bit general-purpose timer with an 8-bit prescaler
– 16-bit input-edge count or time-capture modes
– 16-bit pulse-width modulation (PWM) mode with software-programmable output inversion of the
PWM signal
• Count up or down
• Ability to determine the elapsed time between the assertion of the timer interrupt and entry into the ISR
• Can trigger efficient transfers using the µDMA.
– Dedicated channel for each timer
– Burst request generated on timer interrupt
1.3.5 Watch Dog Timer (WDT)
The watchdog timer in the CC3200 restarts the system when it gets stuck due to an error and does not
respond as expected. The watchdog timer can be configured to generate an interrupt to the
microcontroller on its first time-out, and to generate a reset signal on its second time-out. Once the
watchdog timer is configured, the lock register can be written to prevent the timer configuration from being
inadvertently altered.
The watchdog timer provides the following features:
• 32-bit down-counter with a programmable load register
• Programmable interrupt generation logic with interrupt masking
• Lock register protection from runaway software
• Reset generation logic
www.ti.com
1.3.6 Multi-Channel Audio Serial Port (McASP)
CC3200 includes a configurable multichannel audio serial port for glue-less interfacing to audio CODEC
and DAC (speaker drivers). The audio port has two serializer / deserializers that can be individually
enabled to either transmit or receive and operate synchronously. Key features are:
• Two stereo I2S channels
– One stereo receive and one stereo transmit lines
– Two stereo transmit lines
• Programmable clock and frame-sync polarity (rising or falling edge)
• Programmable word length (bits per word): 16 and 24 bits
• Programmable fractional divider for bit-clock generation, up to 9 MHz.
1.3.7 Serial Peripheral Interface (SPI)
The serial peripheral interface (SPI) is a four-wire bidirectional communications interface that converts
data between parallel and serial. The SPI module performs serial-to-parallel conversion on data received
from a peripheral device, and parallel-to-serial conversion on data transmitted to a peripheral device. The
SPI allows a duplex serial communication between a local host and SPI-compliant external devices.
The CC3200 includes one SPI port dedicated to the application. Key features are
• Programmable interface operation for Freescale SPI, MICROWIRE, or TI synchronous serial interfaces
master and slave modes
• 3-pin and 4-pin mode
• Full duplex and half duplex
• Serial clock with programmable frequency, polarity, and phase
• Up to 20-MHz operation
• Programmable chip select polarity
• Programmable delay before the first SPI word is transmitted
• Programmable timing control between chip select and external clock generation
28
Architecture Overview
Copyright © 2014–2018, Texas Instruments Incorporated
SWRU367D–June 2014–Revised May 2018
Submit Documentation Feedback
www.ti.com
• No dead cycle between two successive words in slave mode
• SPI word lengths of 8, 16, and 32 bits
• Efficient transfers using the μDMA controller
• Programmable interface operation for Freescale SPI, MICROWIRE, or TI-SSI
1.3.8 Inter-Integrated Circuit Interface (I2C)
The inter-integrated circuit (I2C) bus provides bidirectional data transfer through a two-wire design (a
serial data line SDA and a serial clock line SCL). The I2C bus interfaces to a wide variety of external I2C
devices such as sensors, serial memory, control ports of image sensors, and audio codecs. Multiple slave
devices can be connected to the same I2C bus. The CC3200 microcontroller includes one I2C module
with the following features:
• Master and slave modes of operation
• Master with arbitration and clock synchronization
• Multi-master support
• 7-bit addressing mode
• Standard (100 Kbps) and fast (400 Kbps) modes
1.3.9 Universal Asynchronous Receiver/Transmitter (UART)
A universal asynchronous receivers/transmitter (UART) is an integrated circuit used for RS-232 serial
communications. UARTs contain a transmitter (parallel-to-serial converter) and a receiver (serial-toparallel converter), each clocked separately.
The CC3200 device includes two fully programmable UARTs. The UART can generate individuallymasked interrupts from the RX, TX, modem status, and error conditions. The module generates a single
combined interrupt when any of the interrupts are asserted and unmasked.
The UARTs include the following features:
• Programmable baud-rate generator, allowing speeds up to 3 Mbps
• Separate 16 × 8 transmit (TX) and receive (RX) FIFOs to reduce CPU interrupt service loading
• Programmable FIFO length, including 1-byte deep operation providing conventional double-buffered
interface
• FIFO trigger levels of 1/8, 1/4, 1/2, 3/4, and 7/8
• Standard asynchronous communication bits for start, stop, and parity
• Line-break generation and detection
• Fully programmable serial interface characteristics:
– 5, 6, 7, or 8 data bits
– Even, odd, stick, or no-parity bit generation and detection
– 1 or 2 stop-bit generation
• RTS and CTS modem handshake support
• Standard FIFO-level and end-of-transmission interrupts
• Efficient transfers using µDMA
– Separate channels for transmit and receive
– Receive single request asserted when data is in the FIFO; burst request asserted at programmed
FIFO level
– Transmit single request asserted when there is space in the FIFO; burst request asserted at
programmed FIFO level
Functional Overview
SWRU367D–June 2014–Revised May 2018
Submit Documentation Feedback
Copyright © 2014–2018, Texas Instruments Incorporated
Architecture Overview
29
Functional Overview
1.3.10 General Purpose Input / Output (GPIO)
All digital pins of the CC3200 device and some of the analog pins can be used as a general-purpose
input/output (GPIO). The GPIOs are grouped as 4 instance GPIO modules, each 8-bit. Supported features
include:
• Up to 24 GPIOs, depending on the functional pin configuration
• Interrupt capability for all GPIO pins
– Level or edge sensitive
– Rising or falling edge
– Selective interrupt masking
• Can trigger DMA operation
• Selectable wakeup source (one out of 6 pins)
• Programmable pad configuration
– Internal 5 µA pull-up and pull-down
– Configurable drive strength of 2, 4, 6, 8, 10, 12, and 14 mA
– Open-drain mode
• GPIO register readable through the high-speed internal bus matrix
1.3.11 Analog to Digital Converter (ADC)
The ADC peripheral converts a continuous analog voltage into a discrete digital number. The CC3200
device includes ADC modules with four input channels. Each ADC module features 12-bit conversion
resolution for the four input channels. Features include:
• Number of bits: 12-bit
• Effective nominal accuracy: 10 bits
• Four analog input channels
• Automatic round-robin sampling
• Fixed sampling interval of 16 µs per channel
• Automatic 16-bit time-stamping of every ADC samples based on the system clock
• Dedicated DMA channel to transfer ADC channel data to the application RAM.
www.ti.com
1.3.12 SD Card Host
The CC3200 includes an SD-Host interface for applications that require mass storage. The SD-Host
interface support is limited to 1-bit mode due to chip pin constraints.
1.3.13 Parallel Camera Interface
The CC3200 includes an 8-bit parallel camera port to enable image sensor-based applications.
1.3.14 Debug Interface
The CC3200 supports both IEEE Standard 1149.1 JTAG (4-wire) and the low-pin-count ARM SWD (2wire) debug interfaces. Depending on the board level configuration of the sense-on-power pull resistors,
by default the chip powers up with either the 4-wire JTAG or the 2-wire SWD interface.
As shown in Figure 1-1, the 4-wire JTAG signals from the chip pins are routed through an IcePick module.
TAPs other than the application MCU are reserved for TI production testing. A TAP select sequence must
be sent to the device to connect to the ARM Cortex M4 JTAG TAP. The 2-wire mode, however, directly
routes the ARM SWD-TMS and SWD-TCK pins directly to the respective chip pins.
30
Architecture Overview
Copyright © 2014–2018, Texas Instruments Incorporated
SWRU367D–June 2014–Revised May 2018
Submit Documentation Feedback
Loading...