TEXAS INSTRUMENTS CC2550 Technical data

CC2550

Single Chip Low Cost Low Power RF Transmitter

Applications

CC2550

• 2400-2483.5 MHz ISM/SRD band systems

• Consumer Electronics

• Wireless game controllers

• Wireless audio

Product Description

The

CC2550

GHz transmitter designed for very low power wireless applications. The circuit is intended for the ISM (Industrial, Scientific and Medical) and SRD (Short Range Device) frequency band at 2400-2483.5 MHz.

The RF transmitter is integrated with a highly configurable baseband modulator which has a configurable data rate up to 500 kbps. Performance can be increased by enabling a Forward Error Correction option, which is integrated in the modulator.

The

CC2550

support for packet handling, data buffering and burst transmissions.

This data sheet contains preliminary data, and supplementary data will be published at a later date. Chipcon reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. The product is not fully qualified at this point.

is a low cost true single chip 2.4

provides extensive hardware

The main operating parameters and the 64byte transmit FIFO of via an SPI interface. In a typical system, the

CC2550

controller and a few passive components.

CC2550

technology platform based on 0.18 µm CMOS technology.

will be used together with a micro-

is part of Chipcon’s 4th generation

CC2550

can be controlled

Key Features

• Small size (QLP 4x4 mm package, 16

pins)

• True single chip 2.4 GHz RF transmitter

• Frequency range: 2400-2483.5 MHz

• Programmable data rate up to 500 kbps

• Low current consumption

• Programmable output power up to +1 dBm

• Very few external components: Totally on-

chip frequency synthesizer, no external filters needed

• Programmable baseband modulator

• Ideal for multi-channel operation

• Configurable packet handling hardware

• Suitable for frequency hopping systems

due to a fast settling frequency synthesizer

• Optional Forward Error Correction with

interleaving

• 64-byte TX data FIFO

• Suited for systems compliant with EN 300

328 and EN 300 440 class 2 (Europe),

PRELIMINARY Data Sheet (Rev.1.2) SWRS039A Page 1 of 54

FCC CFR47 Part 15 (US), and ARIB STDT66 (Japan)

• Many powerful digital features allow a

high-performance RF system to be made using an inexpensive microcontroller

• Efficient SPI interface: All registers can be

programmed with one “burst” transfer

• Integrated analog temperature sensor

• Lead-free “green“ package

• Flexible support for packet oriented

systems: On chip support for sync word insertion, flexible packet length and automatic CRC handling

• OOK supported

• FSK, GFSK and MSK supported.

• Optional automatic whitening of data

• Support for asynchronous transparent

transmit mode for backwards compatibility with existing radio communication protocols

Table of Contents

CC2550

APPLICATIONS...........................................................................................................................................1

PRODUCT DESCRIPTION.........................................................................................................................1

KEY FEATURES..........................................................................................................................................1

TABLE OF CONTENTS..............................................................................................................................2

ABBREVIATIONS........................................................................................................................................4

ABSOLUTE MAXIMUM RATINGS..............................................................................................4

OPERATING CONDITIONS ..........................................................................................................5

GENERAL CHARACTERISTICS..................................................................................................5

ELECTRICAL SPECIFICATIONS................................................................................................5

4.1 C

4.2 RF T

4.3 C

4.4 F

4.5 A

4.6 DC C

4.7 P

5 6 7 8 9

10 4-WIRE SERIAL CONFIGURATION AND DATA INTERFACE...........................................13

10.1 C

10.2 R

10.3 SPI R

10.4 C

10.5 FIFO A

10.6 PATABLE A

11 MICROCONTROLLER INTERFACE AND PIN CONFIGURATION...................................17

11.1 C

11.2 G

12 DATA RATE PROGRAMMING...................................................................................................18

13 PACKET HANDLING HARDWARE SUPPORT.......................................................................18

13.1 D

13.2 P

13.3 P

14 MODULATION FORMATS..........................................................................................................21

14.1 F

14.2 M

14.3 A

15 FORWARD ERROR CORRECTION WITH INTERLEAVING..............................................22

15.1 F

15.2 I

16 RADIO CONTROL.........................................................................................................................23

16.1 P

16.2 C

16.3 V

16.4 A

16.5 T

17 DATA FIFO.....................................................................................................................................25

18 FREQUENCY PROGRAMMING.................................................................................................26

URRENT CONSUMPTION

RANSMIT SECTION

RYSTAL OSCILLATOR

REQUENCY SYNTHESIZER CHARACTERISTICS

NALOG TEMPERATURE SENSOR

HARACTERISTICS

OWER ON RESET

PIN CONFIGURATION...................................................................................................................8

CIRCUIT DESCRIPTION...............................................................................................................9

APPLICATION CIRCUIT.............................................................................................................10

CONFIGURATION OVERVIEW.................................................................................................12

CONFIGURATION SOFTWARE.................................................................................................13

HIP STATUS BYTE EGISTERS ACCESS

EAD

...........................................................................................................................................16

OMMAND STROBES

CCESS

ONFIGURATION INTERFACE ENERAL CONTROL AND STATUS PINS

ATA WHITENING ACKET FORMAT ACKET HANDLING IN TRANSMIT MODE

REQUENCY SHIFT KEYING

INIMUM SHIFT KEYING

MPLITUDE MODULATION

ORWARD ERROR CORRECTION

NTERLEAVING

OWER-ON START-UP SEQUENCE

RYSTAL CONTROL

OLTAGE REGULATOR CONTROL

CTIVE MODE IMING

...............................................................................................................................................25

.................................................................................................................................8

.....................................................................................................................................16

CCESS

...............................................................................................................................18

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(FEC)...............................................................................................22

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PRELIMINARY Data Sheet (Rev.1.2) SWRS039A Page 2 of 54

CC2550

19 VCO..................................................................................................................................................27

19.1 VCO

20 VOLTAGE REGULATORS ..........................................................................................................27

21 OUTPUT POWER PROGRAMMING.........................................................................................28

22 CRYSTAL OSCILLATOR.............................................................................................................29

22.1 R

23 EXTERNAL RF MATCH ..............................................................................................................30

24 GENERAL PURPOSE / TEST OUTPUT CONTROL PINS......................................................30

25 ASYNCHRONOUS AND SYNCHRONOUS SERIAL OPERATION.......................................32

25.1 A

25.2 S

26 SYSTEM CONSIDERATIONS AND GUIDELINES..................................................................32

26.1 SRD R

26.2 F

26.3 W

26.4 D

26.5 C

26.6 S

26.7 L

26.8 B

26.9 I

27 CONFIGURATION REGISTERS.................................................................................................34

27.1 C

27.2 S

28 PACKAGE DESCRIPTION (QLP 16).......................................................................................... 49

28.1 R

28.2 P

28.3 S

28.4 T

28.5 C

29 ORDERING INFORMATION.......................................................................................................51

30 GENERAL INFORMATION.........................................................................................................51

30.1 D

30.2 P

31 ADDRESS INFORMATION..........................................................................................................53

32 TI WORLDWIDE TECHNICAL SUPPORT...............................................................................53

AND

PLL S

ELF-CALIBRATION

EFERENCE SIGNAL

SYNCHRONOUS OPERATION YNCHRONOUS SERIAL OPERATION

EGULATIONS

REQUENCY HOPPING AND MULTI-CHANNEL SYSTEMS

IDEBAND MODULATION NOT USING SPREAD SPECTRUM ATA BURST TRANSMISSIONS ONTINUOUS TRANSMISSIONS

PECTRUM EFFICIENT MODULATION OW COST SYSTEMS

ATTERY OPERATED SYSTEMS

NCREASING OUTPUT POWER

ONFIGURATION REGISTER DETAILS

TATUS REGISTER DETAILS

ECOMMENDED

ACKAGE THERMAL PROPERTIES OLDERING INFORMATION RAY SPECIFICATION

ARRIER TAPE AND REEL SPECIFICATION

OCUMENT HISTORY

RODUCT STATUS DEFINITIONS

...........................................................................................................................30

............................................................................................................................32

..........................................................................................................................34

.................................................................................................................46

PCB

LAYOUT FOR PACKAGE

..................................................................................................................50

..........................................................................................................................51

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..............................................................................................................32

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(QLP 16).....................................................................50

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PRELIMINARY Data Sheet (Rev.1.2) SWRS039A Page 3 of 54

CC2550

Abbreviations

Abbreviations used in this data sheet are described below.

ACP Adjacent Channel Power MSK Minimum Shift Keying

ADC Analog to Digital Converter NA Not Applicable

AGC Automatic Gain Control LO Local Oscillator

AMR Automatic Meter Reading OOK On Off Keying

ARIB Association of Radio Industries and Businesses PA Power Amplifier

ASK Amplitude Shift Keying PCB Printed Circuit Board

BER Bit Error Rate PD Power Down

BT Bandwidth-Time product PER Packet Error Rate

CFR Code of Federal Regulations PLL Phase Locked Loop

CRC Cyclic Redundancy Check QPSK Quadrature Phase Shift Keying

DC Direct Current QLP Quad Leadless Package

ESR Equivalent Series Resistance RF Radio Frequency

FCC Federal Communications Commission RX Receive, Receive Mode

FEC Forward Error Correction SMD Surface Mount Device

FHSS Frequency Hopping Spread Spectrum SNR Signal to Noise Ratio

FIFO First-In-First-Out SPI Serial Peripheral Interface

FSK Frequency Shift Keying SRD Short Range Device

GFSK Gaussian shaped Frequency Shift Keying TX Transmit, Transmit Mode

I/Q In-Phase/Quadrature VCO Voltage Controlled Oscillator

ISM Industrial, Scientific and Medical WLAN Wireless Local Area Networks

LC Inductor-Capacitor XOSC Crystal Oscillator

LO Local Oscillator XTAL Crystal

MCU Microcontroller Unit

1 Absolute Maximum Ratings

Under no circumstances must the absolute maximum ratings given in Table 1 be violated. Stress exceeding one or more of the limiting values may cause permanent damage to the device.

Caution! ESD sensitive device. Precaution should be used when handling the device in order to prevent permanent damage.

Parameter Min Max Units Condition

Supply voltage –0.3 3.6 V All supply pins must have the same voltage

Voltage on any digital pin –0.3 VDD+0.3,

Voltage on the pins RF_P, RF_N and DCOUPL

Storage temperature range –50 150

Solder reflow temperature 260

ESD <500 V According to JEDEC STD 22, method A114,

max 3.6

–0.3 2.0 V

°C

According to IPC/JEDEC J-STD-020C

°C

Human Body Model

Table 1: Absolute maximum r atings

PRELIMINARY Data Sheet (Rev.1.2) SWRS039A Page 4 of 54

2 Operating Conditions

CC2550

The operating conditions for

Parameter Min Max Unit Condition

Operating temperature –40 85

Operating supply voltage 1.8 3.6 V All supply pins must have the same voltage

CC2550

are listed Table 2 in below.

°C

Table 2: Operating conditions

3 General Characteristics

Parameter Min Typ Max Unit Condition/Note

Frequency range 2400 2483.5 MHz There will be spurious signals at n/2·crystal oscillator

Data rate 1.2

1.2

500

250

500

kbps

frequency (n is an integer number). RF frequencies at n/2·crystal oscillator frequency should therefore not be used (e.g. 2405, 2418, 2444, 2457, 2470 and 2483 MHz when using a 26 MHz crystal). Please refer to the Errata Note for more details.

FSK

GFSK and OOK

(Shaped) MSK (also known as differential offset QPSK)

Optional Manchester encoding (halves the data rate).

CC2550

Table 3: General characteristics

4 Electrical Specifications

4.1 Current Consumption

Tc = 25°C, VDD = 3.0 V if nothing else stated. All measurement results obtained using the CC2550EM reference design.

Parameter Min Typ Max Unit Condition

down modes

Current consumption

Current consumption, TX states

200 nA Voltage regulator to digital part off (SLEEP state) Current consumption in power

160

1.4 mA Only voltage regulator to digital part and crystal oscillator running

7.3 mA Only the frequency synthesizer running (after going from IDLE

11.2 mA Transmit mode, –12 dBm output power (TX state)

14.7 mA Transmit mode, -6 dBm output power (TX state)

19.4 mA Transmit mode, 0 dBm output power (TX state)

21.3 mA Transmit mode, +1 dBm output power (TX state)

Voltage regulator to digital part on, all other modules in power

µA

down (XOFF state)

(IDLE state)

until reaching TX state, and frequency calibration states)

Table 4: Current consumption

PRELIMINARY Data Sheet (Rev.1.2) SWRS039A Page 5 of 54

CC2550

4.2 RF Transmit Section

Tc = 25°C, VDD = 3.0 V, 0 dBm if nothing else stated. All measurement results obtained using the CC2550EM reference design.

Parameter Min Typ Max Unit Condition/Note

Differential load impedance

Output power, highest setting

Output power, lowest setting

Adjacent channel power

Alternate channel power

Spurious emissions

25 MHz – 1 GHz

47-74, 87.5-118, 174230, 470-862 MHz

1800-1900 MHz

At 2·RF and 3·RF

Otherwise above 1 GHz

80 + j74

+1 dBm Output power is programmable and is available across the

–30 dBm Output power is programmable and is available across the

–19 dBc 1 MHz channel spacing (±1 MHz from carrier) and 500

–39 dBc 1 MHz channel spacing (±2 MHz from carrier) and 500

–36

–54

–47

dBm

–41

–30

Differential impedance as seen from the RF-port (RF_P

Ω

and RF_N) towards the antenna. Follow the CC2550EM reference design available from the TI and Chipcon websites.

entire frequency band.

Delivered to 50 Ω single-ended load via CC2550EM reference RF matching network.

entire frequency band.

Delivered to 50 Ω single-ended load via CC2550EM reference RF matching network.

kbps MSK.

dBm

Restricted band in Europe

dBm

Restricted bands in USA

dBm

Table 5: RF transmit parameters

4.3 Crystal Oscillator

Tc = 25°C, VDD = 3.0 V if nothing else stated.

Parameter Min Typ Max Unit Condition/Note

Crystal frequency 26 26 27 MHz

Tolerance ±40 ppm This is the total tolerance including a) initial tolerance, b) crystal

ESR 100

Start-up time 300 µs Measured on CC2550 EM reference design.

loading, c) aging and d) temperature dependence.

The acceptable crystal tolerance depends on RF frequency and channel spacing / bandwidth.

Ω

Table 6: Crystal oscillator parameters

PRELIMINARY Data Sheet (Rev.1.2) SWRS039A Page 6 of 54

CC2550

4.4 Frequency Synthesizer Characteristics

Tc = 25°C, VDD = 3.0 V if nothing else stated. All measurement results obtained using the CC2550EM reference design.

Parameter Min Typ Max Unit Condition/Note

Programmed frequency resolution

Synthesizer frequency tolerance

RF carrier phase noise

PLL turn-on / hop time 88.4

PLL calibration time

397 F

±40 ppm Given by crystal used. Required accuracy (including

–74 dBc/Hz @ 50 kHz offset from carrier

–74 dBc/Hz @ 100 kHz offset from carrier

–77 dBc/Hz @ 200 kHz offset from carrier

–97 dBc/Hz @ 1 MHz offset from carrier

–106 dBc/Hz @ 2 MHz offset from carrier

–114 dBc/Hz @ 5 MHz offset from carrier

–117 dBc/Hz @ 10 MHz offset from carrier

0.69

XOSC

18739

0.72

Table 7: Frequency synthesizer pa rameters

4.5 Analog Temperature Sensor

427 Hz 26-27 MHz crystal.

temperature and aging) depends on frequency band and channel bandwidth / spacing.

Time from leaving the IDLE state until arriving in the FSTXON or TX state, when not performing calibration. Crystal oscillator running.

Calibration can be initiated manually or automatically before entering or after leaving RX/TX.

Min/typ/max time is for 27/26/26 MHz crystal frequency.

0.72

µs

XOSC cycles

The characteristics of the analog temperature sensor are listed in Table 8 below. Note that it is necessary to write 0xBF to the PTEST register to use the analog temperature sensor in the IDLE state.

Parameter Min Typ Max Unit Condition/Note

Output voltage at –40°C

Output voltage at 0°C

Output voltage at +40°C

Output voltage at +80°C

Temperature coefficient 2.54

Error in calculated temperature, calibrated

Current consumption increase when enabled

0.660 V

0.755 V

0.859 V

0.958 V

mV/°C Fitted from –20°C to +80°C

-2

0 2

0.3 mA

°C From –20°C to +80°C when using 2.54 mV / °C,

after 1-point calibration at room temperature

The indicated minimum and maximum error with 1point calibration is based on simulated values for typical process parameters

Table 8: Analog temperature sensor parameters

PRELIMINARY Data Sheet (Rev.1.2) SWRS039A Page 7 of 54

CC2550

4.6 DC Characteristics

Tc = 25°C if nothing else stated.

Digital Inputs/Outputs Min Max Unit Condition

Logic "0" input voltage 0 0.7 V

Logic "1" input voltage VDD-0.7 VDD V

Logic "0" output voltage 0 0.5 V For up to 4 mA output current

Logic "1" output voltage VDD-0.3 VDD V For up to 4 mA output current

Logic "0" input current NA -50 nA Input equals 0 V

Logic "1" input current NA 50 nA Input equals VDD

Table 9: DC characteristics

4.7 Power On Reset

When the power supply complies with the requirements in Table 10 below, proper Power-OnReset functionality is guaranteed. Otherwise, the chip should be assumed to have unknown state until transmitting an SRES strobe over the SPI interface. See Section 16.1 on page 23 for further details.

Parameter Min Typ Max Unit Condition/Note

Power-up ramp-up time. 5 ms From 0 V until reaching 1.8 V

Power off time 1 ms Minimum time between power off and power-on.

Table 10: Power-on reset requirements

5 Pin Configuration

AVDD

RBIAS

DGUARD

1SCLK

2SO (GDO1)

3DVDD

4DCOUPL

XOSC_Q16AVDD7XOSC_Q28GDO0 (ATEST)

12 AVDD

11 RF_N

10 RF_P

9CSn

GND Exposed die attach pad

Figure 1: Pinout top view

Note: The exposed die attach pad must be connected to a solid ground plane as this is the main

ground connection for the chip.

PRELIMINARY Data Sheet (Rev.1.2) SWRS039A Page 8 of 54

CC2550

Pin # Pin name Pin type Description

1 SCLK Digital Input Serial configuration interface, clock input

2 SO (GDO1) Digital Output Serial configuration interface, data output.

Optional general output pin when

3 DVDD Power (Digital) 1.8 - 3.6 V digital power supply for digital I/O’s and for the digital core

4 DCOUPL Power (Digital) 1.6 - 2.0 V digital power supply output for decoupling.

5 XOSC_Q1 Analog I/O Crystal oscillator pin 1, or external clock input

6 AVDD Power (Analog) 1.8 - 3.6 V analog power supply connection

7 XOSC_Q2 Analog I/O Crystal oscillator pin 2

8 GDO0

(ATEST)

9 CSn Digital Input Serial configuration interface, chip select

10 RF_P RF Output Positive RF output signal from PA

11 RF_N RF Output Negative RF output signal from PA

12 AVDD Power (Analog) 1.8 - 3.6 V analog power supply connection

13 AVDD Power (Analog) 1.8 - 3.6 V analog power supply connection

14 RBIAS Analog I/O External bias resistor for reference current

15 DGUARD Power (Digital) Power supply connection for digital noise isolation

16 SI Digital Input Serial configuration interface, data input

Digital I/O

voltage regulator

NOTE: This pin is intended for use with the used to provide supply voltage to other devices.

Digital output pin for general use:

• Test signals

• FIFO status signals

• Clock output, down-divided from XOSC

• Serial input TX data

Also used as analog test I/O for prototype/production testing

CSn

is high

CC2550

only. It can not be

Table 11: Pinout overview

6 Circuit Description

RADIO CONTROL

RF_P RF_N

BIAS

RBIAS

FREQ

SYNTH

XOSC

XOSC_Q1 XOSC_Q2

Figure 2:

CC2550

FEC /

MODULATOR

PACKET

HANDLER

INTERLEAVER

simplified block diagram

TX FIFO

SCLK SO (GDO1) SI

DIGITAL

INTERFACE

CSn

TO MCU

GDO0 (ATEST)

PRELIMINARY Data Sheet (Rev.1.2) SWRS039A Page 9 of 54

CC2550

A simplified block diagram of in Figure 2.

CC2550

The synthesis of the RF frequency.

The frequency synthesizer includes a completely on-chip LC VCO.

A crystal is to be connected to XOSC_Q1 and

transmitter is based on direct

CC2550

is shown

7 Application Circuit

Only a few external components are required for using the application circuit is shown in Figure 3. The external components are described in Table 12, and typical values are given in Table 13.

Bias resistor

The bias resistor R141 is used to set an accurate bias current.

Balun and RF matching

C102, C112, L101 and L111 form a balun that converts the differential RF signal on to a single-ended RF signal. C101 and C111 are needed for DC blocking. Together with an appropriate LC network, the balun components also transform the impedance to match a 50 Ω antenna (or cable). Component values for the RF balun and LC network are easily found using the SmartRF software. Suggested values are listed in Table

CC2550

. The recommended

CC2550

Studio

XOSC_Q2. The crystal oscillator generates the reference frequency for the synthesizer, as well as clocks for the digital part.

A 4-wire SPI serial interface is used for configuration and data buffer access.

The digital baseband includes support for channel configuration, packet handling and data buffering.

13. The balun and LC filter component values and their placement are important to keep the performance optimized. It is highly recommended to follow the CC2550EM reference design.

Crystal

The crystal oscillator uses an external crystal with two loading capacitors (C51 and C71). See Section 22 on page 29 for details.

Power supply decoupling

The power supply must be properly decoupled close to the supply pins. Note that decoupling capacitors are not shown in the application circuit. The placement and the size of the decoupling capacitors are very important to achieve the optimum performance. The CC2550EM reference design should be followed closely.

Component Description

C41 100 nF decoupling capacitor for on-chip voltage regulator to digital part

C51/C71 Crystal loading capacitors, see Section 22 on page 29 for details

C101/C111 RF balun DC blocking capacitors

C102/C112 RF balun/matching capacitors

C103/C104 RF LC filter/matching capacitors

L101/L111 RF balun/matching inductors (inexpensive multi-layer type)

L102 RF LC filter inductor (inexpensive multi-layer type)

R141 Resistor for internal bias current reference

XTAL 26-27 MHz crystal, see Section 22 on page 29 for details

Table 12: Overview of external components (excluding supply decoupling capacitors)

PRELIMINARY Data Sheet (Rev.1.2) SWRS039A Page 10 of 54

CC2550

1.8V-3.6V power supply

SCLK

SO (GDO1)

Digital Inteface

C41

GDO0 (optional) CSn

1 SCLK

2 SO (GDO1)

3 DVDD

DCOUPL 4

C51 C71

DIE ATTACH PAD:

SI 16

DGUARD 15

CC2550

6 AVDD

XOSC_Q1

XTAL

R141

RBIAS 14

7 XOSC_Q2

AVDD

AVDD 12

RF_N 11

RF_P 10

CSn 9

8 GDO0

L111

C111

C101

L101

C102

Alternative: Folded dipole PCB antenna (no external components needed)

Antenna

(50 Ohm)

C112

L102

C103 C104

Figure 3: Typical application and evaluation circuit (excluding supply decoupling capacitors)

Component Value Manufacturer

C41 100 nF±10%, 0402 X5R Murata GRM15 series

C51 27 pF±5%, 0402 NP0 Murata GRM15 series

C71 27 pF±5%, 0402 NP0 Murata GRM15 series

C101 100 pF±5%, 0402 NP0 Murata GRM15 series

C102 1.0 pF±0.25pF, 0402 NP0 Murata GRM15 series

C103 1.8 pF±0.25pF, 0402 NP0 Murata GRM15 series

C104 1.5 pF±0.25pF, 0402 NP0 Murata GRM15 series

C111

C112

L101

L102

L111

R141

XTAL

100 pF±5%, 0402 NP0

1.0 pF±0.25pF, 0402 NP0

1.2 nH±0.3nH, 0402 monolithic

56 kΩ±1%, 0402

26.0 MHz surface mount crystal

Murata GRM15 series

Murata LQG15 series

Koa RK73 series

NDK, AT-41CD2

Table 13: Bill of Materials for the application circuit

In the CC2550EM reference design, LQG15 series inductors from Murata have been used. Measurements have been performed with multi-layer inductors from other manufacturers (e.g. Würth) and the measurement results were the same as when using the Murata part.

PRELIMINARY Data Sheet (Rev.1.2) SWRS039A Page 11 of 54

The Gerber files for the CC2550EM reference design are available from the TI and Chipcon websites.

8 Configuration Overview

CC2550

performance for many different applications. Configuration is done using the SPI interface. The following key parameters can be programmed:

• Power-down / power up mode

• Crystal oscillator power-up / power – down

• Transmit mode

• RF channel selection

• Data rate

• Modulation format

• RF output power

• Data buffering with 64-byte transmit FIFO

• Packet radio hardware support

can be configured to achieve optimum

• Forward Error Correction with interleaving

• Data Whitening

Details of each configuration register can be found in Section 27, starting on page 34.

Figure 4 shows a simplified state diagram that explains the main typical usage and current consumption. For detailed information on controlling the state machine, and a complete state diagram, see Section 16, starting on page 23.

CC2550

states, together with

CC2550

Figure 4: Simplified state diagram, with typical usage and current consumption

PRELIMINARY Data Sheet (Rev.1.2) SWRS039A Page 12 of 54

9 Configuration Software

CC2550

Studio software, available for download from http://www.ti.com. The SmartRF software is highly recommended for obtaining

can be configured using the SmartRF®

Studio

optimum register settings, and for evaluating performance and functionality. A screenshot of the SmartRF is shown in Figure 5.

Studio user interface for

CC2550

Figure 5: SmartRF

Studio user interface

10 4-wire Serial Configuration and Data Interface

CC2550

compatible interface (SI, SO, SCLK and CSn) where

also used to read and write buffered data. All address and data transfer on the SPI interface is done most significant bit first.

All transactions on the SPI interface start with a header byte containing a read/write bit, a burst access bit and a 6-bit address.

During address and data transfer, the CSn pin (Chip Select, active low) must be kept low. If CSn goes high during the access, the transfer will be cancelled. The timing for the address

is configured via a simple 4-wire SPI-

CC2550

is the slave. This interface is

PRELIMINARY Data Sheet (Rev.1.2) SWRS039A Page 13 of 54

and data transfer on the SPI interface is shown in Figure 6 with reference to Table 14.

When CSn goes low, the MCU must wait until the

CC2550

transfer the header byte. This indicates that the voltage regulator has stabilized and the crystal is running. Unless the chip is in the SLEEP or XOFF states or an SRES command strobe is issued, the SO pin will always go low immediately after taking CSn low.

Figure 7 gives a brief overview of different register access types possible.

SO pin goes low before starting to

CC2550

SCLK:

CSn:

Hi-Z

Write to register :

S7 S 6 S 5 S4 S 3 S 2 S 1 S0 S7 S6 S5 S4 S3 S2 S1 S0 S7

Read from register:

S7 S 6 S 5 S4 S 3 S 2 S 1 S0

A6 A5 A4 A3 A2

A0A1

DW7 DW6 DW5 DW4 DW3 DW2 DW1 DW0

A0A1

DR7 DR6 DR5 DR4 DR3 DR2 DR1 D

Hi-Z

Figure 6: Configuration registers write and read operations

Parameter Description Min Max Units

SCLK

sp,pd

tsp

tch Clock high 50 - ns

tcl Clock low 50 - ns

Clock rise time - 5 ns

rise

Clock fall time - 5 ns

fall

thd

tns

SCLK

frequency

100 ns delay inserted between address byte and data byte (single access), or between address and data, and between each data byte (burst access).

SCLK

frequency, single access

No delay between address and data byte

SCLK

frequency, burst access

No delay between address and data byte, or between data bytes

CSn

low to positive edge on

CSn

low to positive edge on

SCLK

Setup data (negative positive edge on

(tsd applies between address and data bytes, and between data bytes)

Hold data after positive edge on

Negative edge on

CSn

SCLK

, in power-down mode

SCLK

, in active mode

edge) to

SCLK

high

Single access 55 - ns tsd

Burst access 76 - ns

- 10 MHz

9 MHz

6.5 MHz

200 -

20 - ns

µs

Table 14: SPI interface timing requirements

Figure 7: Register access types

PRELIMINARY Data Sheet (Rev.1.2) SWRS039A Page 14 of 54

CC2550

10.1 Chip Status Byte

When the header byte, data byte or command strobe is sent on the SPI interface, the chip

status byte is sent by the

CC2550

on the SO

pin. The status byte contains key status signals, useful for the MCU. The first bit, s7, is the CHIP_RDYn signal; this signal must go low before the first positive edge of SCLK. The CHIP_RDYn signal indicates that the crystal is running and the regulated digital supply voltage is stable.

should only be updated when the chip is in this state. The TX state will be active when the chip is transmitting.

The last four bits (3:0) in the status byte contains FIFO_BYTES_AVAILABLE. This field contains the number of bytes free for writing into the TX FIFO. When FIFO_BYTES_AVAILABLE=15, 15 or more bytes are free.

Table 15 gives a status byte summary.

Bits 6, 5 and 4 comprise the STATE value. This value reflects the state of the chip. The XOSC and power to the digital core is on in the IDLE state, but all other modules are in power down. The frequency and channel configuration

Bits Name Description

7 CHIP_RDYn Stays high until power and crystal have stabilized. Should always be low when using

6:4 STATE[2:0] Indicates the current main state machine mode

3:0 FIFO_BYTES_AVAILABLE[3:0] The number of free bytes in the TX FIFO. If FIFO_BYTES_AVAILABLE=15, it

the SPI interface.

Value State Description

000 Idle IDLE state

001 Not used

(RX)

010 TX Transmit mode

011 FSTXON Fast TX ready

100 CALIBRATE Frequency synthesizer calibration is running

101 SETTLING PLL is settling

110 Not used

(RXFIFO_OVERFLOW)

111 TXFIFO_UNDERFLOW TX FIFO has underflowed. Acknowledge with

indicates that 15 or more bytes are free.

(Also reported for some transitional states instead of SETTLING or CALIBRATE)

Not used, included for software compatibility with

CC2500

transceiver

Not used, included for software compatibility with

CC2500

transceiver

SFTX

Table 15: Status byte summary

10.2 Registers Access

The configuration registers on the

CC2550

are

located on SPI addresses from 0x00 to 0x2F. Table 24 on page 36 lists all configuration registers. The detailed description of each register is found in Section 27.1, starting on page 38. All configuration registers can be both written and read. The read/write bit controls if the register should be written or read. When writing to registers, the status byte

PRELIMINARY Data Sheet (Rev.1.2) SWRS039A Page 15 of 54

is sent on the SO pin each time a header byte or data byte is transmitted on the SI pin. When reading from registers, the status byte is sent on the SO pin each time a header byte is transmitted on the SI pin.

Registers with consecutive addresses can be accessed in an efficient way by setting the burst bit in the address header. The address sets the start address in an internal address counter. This counter is incremented by one

each new byte (every 8 clock pulses). The burst access is either a read or a write access and must be terminated by setting CSn high.

For register addresses in the range 0x300x3D, the “burst” bit is used to select between status registers and command strobes (see below). The status registers can only be read. Burst read is not available for status registers, so they must be read one at a time.

10.3 SPI Read

When reading register fields over the SPI interface while the register fields are updated by the radio hardware (e.g. MARCSTATE or TXBYTES), there is a small, but finite, probability that a single read from the register is being corrupt. As an example, the probability of any single read from TXBYTES being corrupt, assuming the maximum data rate is used, is approximately 80 ppm. Refer to the

CC2550

10.4 Command Strobes

Command strobes may be viewed as single byte instructions to command strobe register, internal sequences will be started. These commands are used to disable the crystal oscillator, enable transmit mode, flush the TX FIFO etc. The 9 command strobes are listed in Table 23 on page 35.

The command strobe registers are accessed in the same way as for a register write operation, but no data is transferred. That is, only the R/W bit (set to 0), burst access (set to

0) and the six address bits (in the range 0x30 through 0x3D) are written.

When writing command strobes, the status byte is sent on the SO pin.

A command strobe may be followed by any other SPI access without pulling CSn high. After issuing an SRES command strobe the next command strobe can be issued when the SO pin goes low as shown in Figure 8. The command strobes are executed immediately, with the exception of the SPWD and the SXOFF strobes that are executed when CSn goes high.

Errata Note for more details.

CC2550

. By addressing a

CC2550

Figure 8: SRES command strobe

10.5 FIFO Access

The 64-byte TX FIFO is accessed through the 0x3F address. When the read/write bit is zero, the TX FIFO is accessed. The TX FIFO is write-only.

The burst bit is used to determine if FIFO access is single byte or a burst access. The single byte access method expects address with burst bit set to zero and one data byte. After the data byte a new address is expected; hence, CSn can remain low. The burst access method expects one address byte and then consecutive data bytes until terminating the access by setting CSn high.

The following header bytes access the FIFO:

• 0x3F: Single byte access to TX FIFO

• 0x7F: Burst access to TX FIFO

When writing to the TX FIFO, the status byte (see Section 10.1) is output for each new data byte on SO, as shown in Figure 6. This status byte can be used to detect TX FIFO underflow while writing data to the TX FIFO. Note that the status byte contains the number of bytes

free before writing the byte in progress to the

TX FIFO. When the last byte that fits in the TX FIFO is transmitted to the SI pin, the status byte received concurrently on the SO pin will indicate that one byte is free in the TX FIFO.

The transmit FIFO may be flushed by issuing a SFTX command strobe. The FIFO is cleared when going to the SLEEP state.

10.6 PATABLE Access

The 0x3E address is used to access the PATABLE, which is used for selecting PA power control settings. The SPI expects up to eight data bytes after receiving the address. By programming the PATABLE, controlled PA power ramp-up and ramp-down can be achieved. See Section 21 on page 28 for output power programming details.

PRELIMINARY Data Sheet (Rev.1.2) SWRS039A Page 16 of 54

CC2550

The PATABLE is an 8-byte table that defines the PA control settings to use for each of the eight PA power values (selected by the 3-bit value FREND0.PA_POWER). The table is written and read from the lowest setting (0) to the highest (7), one byte at a time. An index counter is used to control the access to the table. This counter is incremented each time a byte is read or written to the table, and set to the lowest index when CSn is high. When the highest value is reached the counter restarts at

0. The access to the PATABLE is either single

byte or burst access depending on the burst bit. When using burst access the index counter will count up; when reaching 7 the counter will restart at 0. The read/write bit controls whether the access is a write access (R/W=0) or a read access (R/W=1).

If one byte is written to the PATABLE and this value is to be read out then CSn must be set high before the read access in order to set the index counter back to zero.

Note that the content of the PATABLE is lost when entering the SLEEP state.

11 Microcontroller Interface and Pin Configuration

In a typical system, microcontroller. This microcontroller must be able to:

• Program

• Write buffered data

• Read back status information via the 4-wire

SPI-bus configuration interface (SI, SO, SCLK and CSn)

CC2550

into different modes

will interface to a

pin is the SO pin in the SPI interface. The default setting for GDO1/SO is 3-state output. By selecting any other of the programming options the GDO1/SO pin will become a generic pin. When CSn is low, the pin will always function as a normal SO pin.

In the synchronous and asynchronous serial modes, the GDO0 pin is used as a serial TX data input pin while in transmit mode.

11.1 Configuration Interface

The microcontroller uses four I/O pins for the SPI configuration interface (SI, SO, SCLK and CSn). The SPI is described in 13 on page 13.

11.2 General Control and Status Pins

The

CC2550

pin and one shared pin that can output internal status information useful for control software. These pins can be used to generate interrupts on the MCU. See Section 24 page 30 for more details of the signals that can be programmed. The dedicated pin is called GDO0. The shared

has one dedicated configurable

PRELIMINARY Data Sheet (Rev.1.2) SWRS039A Page 17 of 54

The GDO0 pin can also be used for an on-chip analog temperature sensor. By measuring the voltage on the GDO0 pin with an external ADC, the temperature can be calculated. Specifications for the temperature sensor are found in Section 4.5 on page 7.

With default PTEST register setting (0x7F) the temperature sensor output is only available when the frequency synthesizer is enabled (e.g. the MANCAL, FSTXON and TX states). It is necessary to write 0xBF to the PTEST register to use the analog temperature sensor in the IDLE state. Before leaving the IDLE state, the PTEST register should be restored to its default value (0x7F).

+ 38 hidden pages

TEXAS INSTRUMENTS CC2550 Technical data

Specifications and Main Features

Frequently Asked Questions

User Manual

Abbreviations

Current consumption

4.2 RF Transmit Section

4.4 Frequency Synthesizer Characteristics

4.5 Analog Temperature Sensor

4.7 Power On Reset

10 4-wire Serial Configuration and Data Interface

11 Microcontroller Interface and Pin Configuration