TEXAS INSTRUMENTS CC2550 Technical data

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CC2550

Single Chip Low Cost Low Power RF Transmitter

Applications

CC2550

• 2400-2483.5 MHz ISM/SRD band systems

• Consumer Electronics

• Wireless game controllers

• Wireless audio

Product Description

The

CC2550

GHz transmitter designed for very low power wireless applications. The circuit is intended for the ISM (Industrial, Scientific and Medical) and SRD (Short Range Device) frequency band at 2400-2483.5 MHz.

The RF transmitter is integrated with a highly configurable baseband modulator which has a configurable data rate up to 500 kbps. Performance can be increased by enabling a Forward Error Correction option, which is integrated in the modulator.

The

CC2550

support for packet handling, data buffering and burst transmissions.

This data sheet contains preliminary data, and supplementary data will be published at a later date. Chipcon reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. The product is not fully qualified at this point.

is a low cost true single chip 2.4

provides extensive hardware

The main operating parameters and the 64byte transmit FIFO of via an SPI interface. In a typical system, the

CC2550

controller and a few passive components.

CC2550

technology platform based on 0.18 µm CMOS technology.

will be used together with a micro-

is part of Chipcon’s 4th generation

CC2550

can be controlled

Key Features

• Small size (QLP 4x4 mm package, 16

pins)

• True single chip 2.4 GHz RF transmitter

• Frequency range: 2400-2483.5 MHz

• Programmable data rate up to 500 kbps

• Low current consumption

• Programmable output power up to +1 dBm

• Very few external components: Totally on-

chip frequency synthesizer, no external filters needed

• Programmable baseband modulator

• Ideal for multi-channel operation

• Configurable packet handling hardware

• Suitable for frequency hopping systems

due to a fast settling frequency synthesizer

• Optional Forward Error Correction with

interleaving

• 64-byte TX data FIFO

• Suited for systems compliant with EN 300

328 and EN 300 440 class 2 (Europe),

PRELIMINARY Data Sheet (Rev.1.2) SWRS039A Page 1 of 54

FCC CFR47 Part 15 (US), and ARIB STDT66 (Japan)

• Many powerful digital features allow a

high-performance RF system to be made using an inexpensive microcontroller

• Efficient SPI interface: All registers can be

programmed with one “burst” transfer

• Integrated analog temperature sensor

• Lead-free “green“ package

• Flexible support for packet oriented

systems: On chip support for sync word insertion, flexible packet length and automatic CRC handling

• OOK supported

• FSK, GFSK and MSK supported.

• Optional automatic whitening of data

• Support for asynchronous transparent

transmit mode for backwards compatibility with existing radio communication protocols

Table of Contents

CC2550

APPLICATIONS...........................................................................................................................................1

PRODUCT DESCRIPTION.........................................................................................................................1

KEY FEATURES..........................................................................................................................................1

TABLE OF CONTENTS..............................................................................................................................2

ABBREVIATIONS........................................................................................................................................4

ABSOLUTE MAXIMUM RATINGS..............................................................................................4

OPERATING CONDITIONS ..........................................................................................................5

GENERAL CHARACTERISTICS..................................................................................................5

ELECTRICAL SPECIFICATIONS................................................................................................5

4.1 C

4.2 RF T

4.3 C

4.4 F

4.5 A

4.6 DC C

4.7 P

5 6 7 8 9

10 4-WIRE SERIAL CONFIGURATION AND DATA INTERFACE...........................................13

10.1 C

10.2 R

10.3 SPI R

10.4 C

10.5 FIFO A

10.6 PATABLE A

11 MICROCONTROLLER INTERFACE AND PIN CONFIGURATION...................................17

11.1 C

11.2 G

12 DATA RATE PROGRAMMING...................................................................................................18

13 PACKET HANDLING HARDWARE SUPPORT.......................................................................18

13.1 D

13.2 P

13.3 P

14 MODULATION FORMATS..........................................................................................................21

14.1 F

14.2 M

14.3 A

15 FORWARD ERROR CORRECTION WITH INTERLEAVING..............................................22

15.1 F

15.2 I

16 RADIO CONTROL.........................................................................................................................23

16.1 P

16.2 C

16.3 V

16.4 A

16.5 T

17 DATA FIFO.....................................................................................................................................25

18 FREQUENCY PROGRAMMING.................................................................................................26

URRENT CONSUMPTION

RANSMIT SECTION

RYSTAL OSCILLATOR

REQUENCY SYNTHESIZER CHARACTERISTICS

NALOG TEMPERATURE SENSOR

HARACTERISTICS

OWER ON RESET

PIN CONFIGURATION...................................................................................................................8

CIRCUIT DESCRIPTION...............................................................................................................9

APPLICATION CIRCUIT.............................................................................................................10

CONFIGURATION OVERVIEW.................................................................................................12

CONFIGURATION SOFTWARE.................................................................................................13

HIP STATUS BYTE EGISTERS ACCESS

EAD

...........................................................................................................................................16

OMMAND STROBES

CCESS

ONFIGURATION INTERFACE ENERAL CONTROL AND STATUS PINS

ATA WHITENING ACKET FORMAT ACKET HANDLING IN TRANSMIT MODE

REQUENCY SHIFT KEYING

INIMUM SHIFT KEYING

MPLITUDE MODULATION

ORWARD ERROR CORRECTION

NTERLEAVING

OWER-ON START-UP SEQUENCE

RYSTAL CONTROL

OLTAGE REGULATOR CONTROL

CTIVE MODE IMING

...............................................................................................................................................25

.................................................................................................................................8

.....................................................................................................................................16

CCESS

...............................................................................................................................18

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(FEC)...............................................................................................22

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PRELIMINARY Data Sheet (Rev.1.2) SWRS039A Page 2 of 54

CC2550

19 VCO..................................................................................................................................................27

19.1 VCO

20 VOLTAGE REGULATORS ..........................................................................................................27

21 OUTPUT POWER PROGRAMMING.........................................................................................28

22 CRYSTAL OSCILLATOR.............................................................................................................29

22.1 R

23 EXTERNAL RF MATCH ..............................................................................................................30

24 GENERAL PURPOSE / TEST OUTPUT CONTROL PINS......................................................30

25 ASYNCHRONOUS AND SYNCHRONOUS SERIAL OPERATION.......................................32

25.1 A

25.2 S

26 SYSTEM CONSIDERATIONS AND GUIDELINES..................................................................32

26.1 SRD R

26.2 F

26.3 W

26.4 D

26.5 C

26.6 S

26.7 L

26.8 B

26.9 I

27 CONFIGURATION REGISTERS.................................................................................................34

27.1 C

27.2 S

28 PACKAGE DESCRIPTION (QLP 16).......................................................................................... 49

28.1 R

28.2 P

28.3 S

28.4 T

28.5 C

29 ORDERING INFORMATION.......................................................................................................51

30 GENERAL INFORMATION.........................................................................................................51

30.1 D

30.2 P

31 ADDRESS INFORMATION..........................................................................................................53

32 TI WORLDWIDE TECHNICAL SUPPORT...............................................................................53

AND

PLL S

ELF-CALIBRATION

EFERENCE SIGNAL

SYNCHRONOUS OPERATION YNCHRONOUS SERIAL OPERATION

EGULATIONS

REQUENCY HOPPING AND MULTI-CHANNEL SYSTEMS

IDEBAND MODULATION NOT USING SPREAD SPECTRUM ATA BURST TRANSMISSIONS ONTINUOUS TRANSMISSIONS

PECTRUM EFFICIENT MODULATION OW COST SYSTEMS

ATTERY OPERATED SYSTEMS

NCREASING OUTPUT POWER

ONFIGURATION REGISTER DETAILS

TATUS REGISTER DETAILS

ECOMMENDED

ACKAGE THERMAL PROPERTIES OLDERING INFORMATION RAY SPECIFICATION

ARRIER TAPE AND REEL SPECIFICATION

OCUMENT HISTORY

RODUCT STATUS DEFINITIONS

...........................................................................................................................30

............................................................................................................................32

..........................................................................................................................34

.................................................................................................................46

PCB

LAYOUT FOR PACKAGE

..................................................................................................................50

..........................................................................................................................51

.........................................................................................................................51

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(QLP 16).....................................................................50

........................................................................................................50

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PRELIMINARY Data Sheet (Rev.1.2) SWRS039A Page 3 of 54

CC2550

Abbreviations

Abbreviations used in this data sheet are described below.

ACP Adjacent Channel Power MSK Minimum Shift Keying

ADC Analog to Digital Converter NA Not Applicable

AGC Automatic Gain Control LO Local Oscillator

AMR Automatic Meter Reading OOK On Off Keying

ARIB Association of Radio Industries and Businesses PA Power Amplifier

ASK Amplitude Shift Keying PCB Printed Circuit Board

BER Bit Error Rate PD Power Down

BT Bandwidth-Time product PER Packet Error Rate

CFR Code of Federal Regulations PLL Phase Locked Loop

CRC Cyclic Redundancy Check QPSK Quadrature Phase Shift Keying

DC Direct Current QLP Quad Leadless Package

ESR Equivalent Series Resistance RF Radio Frequency

FCC Federal Communications Commission RX Receive, Receive Mode

FEC Forward Error Correction SMD Surface Mount Device

FHSS Frequency Hopping Spread Spectrum SNR Signal to Noise Ratio

FIFO First-In-First-Out SPI Serial Peripheral Interface

FSK Frequency Shift Keying SRD Short Range Device

GFSK Gaussian shaped Frequency Shift Keying TX Transmit, Transmit Mode

I/Q In-Phase/Quadrature VCO Voltage Controlled Oscillator

ISM Industrial, Scientific and Medical WLAN Wireless Local Area Networks

LC Inductor-Capacitor XOSC Crystal Oscillator

LO Local Oscillator XTAL Crystal

MCU Microcontroller Unit

1 Absolute Maximum Ratings

Under no circumstances must the absolute maximum ratings given in Table 1 be violated. Stress exceeding one or more of the limiting values may cause permanent damage to the device.

Caution! ESD sensitive device. Precaution should be used when handling the device in order to prevent permanent damage.

Parameter Min Max Units Condition

Supply voltage –0.3 3.6 V All supply pins must have the same voltage

Voltage on any digital pin –0.3 VDD+0.3,

Voltage on the pins RF_P, RF_N and DCOUPL

Storage temperature range –50 150

Solder reflow temperature 260

ESD <500 V According to JEDEC STD 22, method A114,

max 3.6

–0.3 2.0 V

°C

According to IPC/JEDEC J-STD-020C

°C

Human Body Model

Table 1: Absolute maximum r atings

PRELIMINARY Data Sheet (Rev.1.2) SWRS039A Page 4 of 54

2 Operating Conditions

CC2550

The operating conditions for

Parameter Min Max Unit Condition

Operating temperature –40 85

Operating supply voltage 1.8 3.6 V All supply pins must have the same voltage

CC2550

are listed Table 2 in below.

°C

Table 2: Operating conditions

3 General Characteristics

Parameter Min Typ Max Unit Condition/Note

Frequency range 2400 2483.5 MHz There will be spurious signals at n/2·crystal oscillator

Data rate 1.2

1.2

500

250

500

kbps

frequency (n is an integer number). RF frequencies at n/2·crystal oscillator frequency should therefore not be used (e.g. 2405, 2418, 2444, 2457, 2470 and 2483 MHz when using a 26 MHz crystal). Please refer to the Errata Note for more details.

FSK

GFSK and OOK

(Shaped) MSK (also known as differential offset QPSK)

Optional Manchester encoding (halves the data rate).

CC2550

Table 3: General characteristics

4 Electrical Specifications

4.1 Current Consumption

Tc = 25°C, VDD = 3.0 V if nothing else stated. All measurement results obtained using the CC2550EM reference design.

Parameter Min Typ Max Unit Condition

down modes

Current consumption

Current consumption, TX states

200 nA Voltage regulator to digital part off (SLEEP state) Current consumption in power

160

1.4 mA Only voltage regulator to digital part and crystal oscillator running

7.3 mA Only the frequency synthesizer running (after going from IDLE

11.2 mA Transmit mode, –12 dBm output power (TX state)

14.7 mA Transmit mode, -6 dBm output power (TX state)

19.4 mA Transmit mode, 0 dBm output power (TX state)

21.3 mA Transmit mode, +1 dBm output power (TX state)

Voltage regulator to digital part on, all other modules in power

µA

down (XOFF state)

(IDLE state)

until reaching TX state, and frequency calibration states)

Table 4: Current consumption

PRELIMINARY Data Sheet (Rev.1.2) SWRS039A Page 5 of 54

CC2550

4.2 RF Transmit Section

Tc = 25°C, VDD = 3.0 V, 0 dBm if nothing else stated. All measurement results obtained using the CC2550EM reference design.

Parameter Min Typ Max Unit Condition/Note

Differential load impedance

Output power, highest setting

Output power, lowest setting

Adjacent channel power

Alternate channel power

Spurious emissions

25 MHz – 1 GHz

47-74, 87.5-118, 174230, 470-862 MHz

1800-1900 MHz

At 2·RF and 3·RF

Otherwise above 1 GHz

80 + j74

+1 dBm Output power is programmable and is available across the

–30 dBm Output power is programmable and is available across the

–19 dBc 1 MHz channel spacing (±1 MHz from carrier) and 500

–39 dBc 1 MHz channel spacing (±2 MHz from carrier) and 500

–36

–54

–47

dBm

–41

–30

Differential impedance as seen from the RF-port (RF_P

Ω

and RF_N) towards the antenna. Follow the CC2550EM reference design available from the TI and Chipcon websites.

entire frequency band.

Delivered to 50 Ω single-ended load via CC2550EM reference RF matching network.

entire frequency band.

Delivered to 50 Ω single-ended load via CC2550EM reference RF matching network.

kbps MSK.

dBm

Restricted band in Europe

dBm

Restricted bands in USA

dBm

Table 5: RF transmit parameters

4.3 Crystal Oscillator

Tc = 25°C, VDD = 3.0 V if nothing else stated.

Parameter Min Typ Max Unit Condition/Note

Crystal frequency 26 26 27 MHz

Tolerance ±40 ppm This is the total tolerance including a) initial tolerance, b) crystal

ESR 100

Start-up time 300 µs Measured on CC2550 EM reference design.

loading, c) aging and d) temperature dependence.

The acceptable crystal tolerance depends on RF frequency and channel spacing / bandwidth.

Ω

Table 6: Crystal oscillator parameters

PRELIMINARY Data Sheet (Rev.1.2) SWRS039A Page 6 of 54

CC2550

4.4 Frequency Synthesizer Characteristics

Tc = 25°C, VDD = 3.0 V if nothing else stated. All measurement results obtained using the CC2550EM reference design.

Parameter Min Typ Max Unit Condition/Note

Programmed frequency resolution

Synthesizer frequency tolerance

RF carrier phase noise

PLL turn-on / hop time 88.4

PLL calibration time

397 F

±40 ppm Given by crystal used. Required accuracy (including

–74 dBc/Hz @ 50 kHz offset from carrier

–74 dBc/Hz @ 100 kHz offset from carrier

–77 dBc/Hz @ 200 kHz offset from carrier

–97 dBc/Hz @ 1 MHz offset from carrier

–106 dBc/Hz @ 2 MHz offset from carrier

–114 dBc/Hz @ 5 MHz offset from carrier

–117 dBc/Hz @ 10 MHz offset from carrier

0.69

XOSC

18739

0.72

Table 7: Frequency synthesizer pa rameters

4.5 Analog Temperature Sensor

427 Hz 26-27 MHz crystal.

temperature and aging) depends on frequency band and channel bandwidth / spacing.

Time from leaving the IDLE state until arriving in the FSTXON or TX state, when not performing calibration. Crystal oscillator running.

Calibration can be initiated manually or automatically before entering or after leaving RX/TX.

Min/typ/max time is for 27/26/26 MHz crystal frequency.

0.72

µs

XOSC cycles

The characteristics of the analog temperature sensor are listed in Table 8 below. Note that it is necessary to write 0xBF to the PTEST register to use the analog temperature sensor in the IDLE state.

Parameter Min Typ Max Unit Condition/Note

Output voltage at –40°C

Output voltage at 0°C

Output voltage at +40°C

Output voltage at +80°C

Temperature coefficient 2.54

Error in calculated temperature, calibrated

Current consumption increase when enabled

0.660 V

0.755 V

0.859 V

0.958 V

mV/°C Fitted from –20°C to +80°C

-2

0 2

0.3 mA

°C From –20°C to +80°C when using 2.54 mV / °C,

after 1-point calibration at room temperature

The indicated minimum and maximum error with 1point calibration is based on simulated values for typical process parameters

Table 8: Analog temperature sensor parameters

PRELIMINARY Data Sheet (Rev.1.2) SWRS039A Page 7 of 54

CC2550

4.6 DC Characteristics

Tc = 25°C if nothing else stated.

Digital Inputs/Outputs Min Max Unit Condition

Logic "0" input voltage 0 0.7 V

Logic "1" input voltage VDD-0.7 VDD V

Logic "0" output voltage 0 0.5 V For up to 4 mA output current

Logic "1" output voltage VDD-0.3 VDD V For up to 4 mA output current

Logic "0" input current NA -50 nA Input equals 0 V

Logic "1" input current NA 50 nA Input equals VDD

Table 9: DC characteristics

4.7 Power On Reset

When the power supply complies with the requirements in Table 10 below, proper Power-OnReset functionality is guaranteed. Otherwise, the chip should be assumed to have unknown state until transmitting an SRES strobe over the SPI interface. See Section 16.1 on page 23 for further details.

Parameter Min Typ Max Unit Condition/Note

Power-up ramp-up time. 5 ms From 0 V until reaching 1.8 V

Power off time 1 ms Minimum time between power off and power-on.

Table 10: Power-on reset requirements

5 Pin Configuration

AVDD

RBIAS

DGUARD

1SCLK

2SO (GDO1)

3DVDD

4DCOUPL

XOSC_Q16AVDD7XOSC_Q28GDO0 (ATEST)

12 AVDD

11 RF_N

10 RF_P

9CSn

GND Exposed die attach pad

Figure 1: Pinout top view

Note: The exposed die attach pad must be connected to a solid ground plane as this is the main

ground connection for the chip.

PRELIMINARY Data Sheet (Rev.1.2) SWRS039A Page 8 of 54

CC2550

Pin # Pin name Pin type Description

1 SCLK Digital Input Serial configuration interface, clock input

2 SO (GDO1) Digital Output Serial configuration interface, data output.

Optional general output pin when

3 DVDD Power (Digital) 1.8 - 3.6 V digital power supply for digital I/O’s and for the digital core

4 DCOUPL Power (Digital) 1.6 - 2.0 V digital power supply output for decoupling.

5 XOSC_Q1 Analog I/O Crystal oscillator pin 1, or external clock input

6 AVDD Power (Analog) 1.8 - 3.6 V analog power supply connection

7 XOSC_Q2 Analog I/O Crystal oscillator pin 2

8 GDO0

(ATEST)

9 CSn Digital Input Serial configuration interface, chip select

10 RF_P RF Output Positive RF output signal from PA

11 RF_N RF Output Negative RF output signal from PA

12 AVDD Power (Analog) 1.8 - 3.6 V analog power supply connection

13 AVDD Power (Analog) 1.8 - 3.6 V analog power supply connection

14 RBIAS Analog I/O External bias resistor for reference current

15 DGUARD Power (Digital) Power supply connection for digital noise isolation

16 SI Digital Input Serial configuration interface, data input

Digital I/O

voltage regulator

NOTE: This pin is intended for use with the used to provide supply voltage to other devices.

Digital output pin for general use:

• Test signals

• FIFO status signals

• Clock output, down-divided from XOSC

• Serial input TX data

Also used as analog test I/O for prototype/production testing

CSn

is high

CC2550

only. It can not be

Table 11: Pinout overview

6 Circuit Description

RADIO CONTROL

RF_P RF_N

BIAS

RBIAS

FREQ

SYNTH

XOSC

XOSC_Q1 XOSC_Q2

Figure 2:

CC2550

FEC /

MODULATOR

PACKET

HANDLER

INTERLEAVER

simplified block diagram

TX FIFO

SCLK SO (GDO1) SI

DIGITAL

INTERFACE

CSn

TO MCU

GDO0 (ATEST)

PRELIMINARY Data Sheet (Rev.1.2) SWRS039A Page 9 of 54

CC2550

A simplified block diagram of in Figure 2.

CC2550

The synthesis of the RF frequency.

The frequency synthesizer includes a completely on-chip LC VCO.

A crystal is to be connected to XOSC_Q1 and

transmitter is based on direct

CC2550

is shown

7 Application Circuit

Only a few external components are required for using the application circuit is shown in Figure 3. The external components are described in Table 12, and typical values are given in Table 13.

Bias resistor

The bias resistor R141 is used to set an accurate bias current.

Balun and RF matching

C102, C112, L101 and L111 form a balun that converts the differential RF signal on to a single-ended RF signal. C101 and C111 are needed for DC blocking. Together with an appropriate LC network, the balun components also transform the impedance to match a 50 Ω antenna (or cable). Component values for the RF balun and LC network are easily found using the SmartRF software. Suggested values are listed in Table

CC2550

. The recommended

CC2550

Studio

XOSC_Q2. The crystal oscillator generates the reference frequency for the synthesizer, as well as clocks for the digital part.

A 4-wire SPI serial interface is used for configuration and data buffer access.

The digital baseband includes support for channel configuration, packet handling and data buffering.

13. The balun and LC filter component values and their placement are important to keep the performance optimized. It is highly recommended to follow the CC2550EM reference design.

Crystal

The crystal oscillator uses an external crystal with two loading capacitors (C51 and C71). See Section 22 on page 29 for details.

Power supply decoupling

The power supply must be properly decoupled close to the supply pins. Note that decoupling capacitors are not shown in the application circuit. The placement and the size of the decoupling capacitors are very important to achieve the optimum performance. The CC2550EM reference design should be followed closely.

Component Description

C41 100 nF decoupling capacitor for on-chip voltage regulator to digital part

C51/C71 Crystal loading capacitors, see Section 22 on page 29 for details

C101/C111 RF balun DC blocking capacitors

C102/C112 RF balun/matching capacitors

C103/C104 RF LC filter/matching capacitors

L101/L111 RF balun/matching inductors (inexpensive multi-layer type)

L102 RF LC filter inductor (inexpensive multi-layer type)

R141 Resistor for internal bias current reference

XTAL 26-27 MHz crystal, see Section 22 on page 29 for details

Table 12: Overview of external components (excluding supply decoupling capacitors)

PRELIMINARY Data Sheet (Rev.1.2) SWRS039A Page 10 of 54

CC2550

1.8V-3.6V power supply

SCLK

SO (GDO1)

Digital Inteface

C41

GDO0 (optional) CSn

1 SCLK

2 SO (GDO1)

3 DVDD

DCOUPL 4

C51 C71

DIE ATTACH PAD:

SI 16

DGUARD 15

CC2550

6 AVDD

XOSC_Q1

XTAL

R141

RBIAS 14

7 XOSC_Q2

AVDD

AVDD 12

RF_N 11

RF_P 10

CSn 9

8 GDO0

L111

C111

C101

L101

C102

Alternative: Folded dipole PCB antenna (no external components needed)

Antenna

(50 Ohm)

C112

L102

C103 C104

Figure 3: Typical application and evaluation circuit (excluding supply decoupling capacitors)

Component Value Manufacturer

C41 100 nF±10%, 0402 X5R Murata GRM15 series

C51 27 pF±5%, 0402 NP0 Murata GRM15 series

C71 27 pF±5%, 0402 NP0 Murata GRM15 series

C101 100 pF±5%, 0402 NP0 Murata GRM15 series

C102 1.0 pF±0.25pF, 0402 NP0 Murata GRM15 series

C103 1.8 pF±0.25pF, 0402 NP0 Murata GRM15 series

C104 1.5 pF±0.25pF, 0402 NP0 Murata GRM15 series

C111

C112

L101

L102

L111

R141

XTAL

100 pF±5%, 0402 NP0

1.0 pF±0.25pF, 0402 NP0

1.2 nH±0.3nH, 0402 monolithic

56 kΩ±1%, 0402

26.0 MHz surface mount crystal

Murata GRM15 series

Murata LQG15 series

Koa RK73 series

NDK, AT-41CD2

Table 13: Bill of Materials for the application circuit

In the CC2550EM reference design, LQG15 series inductors from Murata have been used. Measurements have been performed with multi-layer inductors from other manufacturers (e.g. Würth) and the measurement results were the same as when using the Murata part.

PRELIMINARY Data Sheet (Rev.1.2) SWRS039A Page 11 of 54

The Gerber files for the CC2550EM reference design are available from the TI and Chipcon websites.

8 Configuration Overview

CC2550

performance for many different applications. Configuration is done using the SPI interface. The following key parameters can be programmed:

• Power-down / power up mode

• Crystal oscillator power-up / power – down

• Transmit mode

• RF channel selection

• Data rate

• Modulation format

• RF output power

• Data buffering with 64-byte transmit FIFO

• Packet radio hardware support

can be configured to achieve optimum

• Forward Error Correction with interleaving

• Data Whitening

Details of each configuration register can be found in Section 27, starting on page 34.

Figure 4 shows a simplified state diagram that explains the main typical usage and current consumption. For detailed information on controlling the state machine, and a complete state diagram, see Section 16, starting on page 23.

CC2550

states, together with

CC2550

Figure 4: Simplified state diagram, with typical usage and current consumption

PRELIMINARY Data Sheet (Rev.1.2) SWRS039A Page 12 of 54

9 Configuration Software

CC2550

Studio software, available for download from http://www.ti.com. The SmartRF software is highly recommended for obtaining

can be configured using the SmartRF®

Studio

optimum register settings, and for evaluating performance and functionality. A screenshot of the SmartRF is shown in Figure 5.

Studio user interface for

CC2550

Figure 5: SmartRF

Studio user interface

10 4-wire Serial Configuration and Data Interface

CC2550

compatible interface (SI, SO, SCLK and CSn) where

also used to read and write buffered data. All address and data transfer on the SPI interface is done most significant bit first.

All transactions on the SPI interface start with a header byte containing a read/write bit, a burst access bit and a 6-bit address.

During address and data transfer, the CSn pin (Chip Select, active low) must be kept low. If CSn goes high during the access, the transfer will be cancelled. The timing for the address

is configured via a simple 4-wire SPI-

CC2550

is the slave. This interface is

PRELIMINARY Data Sheet (Rev.1.2) SWRS039A Page 13 of 54

and data transfer on the SPI interface is shown in Figure 6 with reference to Table 14.

When CSn goes low, the MCU must wait until the

CC2550

transfer the header byte. This indicates that the voltage regulator has stabilized and the crystal is running. Unless the chip is in the SLEEP or XOFF states or an SRES command strobe is issued, the SO pin will always go low immediately after taking CSn low.

Figure 7 gives a brief overview of different register access types possible.

SO pin goes low before starting to

CC2550

SCLK:

CSn:

Hi-Z

Write to register :

S7 S 6 S 5 S4 S 3 S 2 S 1 S0 S7 S6 S5 S4 S3 S2 S1 S0 S7

Read from register:

S7 S 6 S 5 S4 S 3 S 2 S 1 S0

A6 A5 A4 A3 A2

A0A1

DW7 DW6 DW5 DW4 DW3 DW2 DW1 DW0

A0A1

DR7 DR6 DR5 DR4 DR3 DR2 DR1 D

Hi-Z

Figure 6: Configuration registers write and read operations

Parameter Description Min Max Units

SCLK

sp,pd

tsp

tch Clock high 50 - ns

tcl Clock low 50 - ns

Clock rise time - 5 ns

rise

Clock fall time - 5 ns

fall

thd

tns

SCLK

frequency

100 ns delay inserted between address byte and data byte (single access), or between address and data, and between each data byte (burst access).

SCLK

frequency, single access

No delay between address and data byte

SCLK

frequency, burst access

No delay between address and data byte, or between data bytes

CSn

low to positive edge on

CSn

low to positive edge on

SCLK

Setup data (negative positive edge on

(tsd applies between address and data bytes, and between data bytes)

Hold data after positive edge on

Negative edge on

CSn

SCLK

, in power-down mode

SCLK

, in active mode

edge) to

SCLK

high

Single access 55 - ns tsd

Burst access 76 - ns

- 10 MHz

9 MHz

6.5 MHz

200 -

20 - ns

µs

Table 14: SPI interface timing requirements

Figure 7: Register access types

PRELIMINARY Data Sheet (Rev.1.2) SWRS039A Page 14 of 54

CC2550

10.1 Chip Status Byte

When the header byte, data byte or command strobe is sent on the SPI interface, the chip

status byte is sent by the

CC2550

on the SO

pin. The status byte contains key status signals, useful for the MCU. The first bit, s7, is the CHIP_RDYn signal; this signal must go low before the first positive edge of SCLK. The CHIP_RDYn signal indicates that the crystal is running and the regulated digital supply voltage is stable.

should only be updated when the chip is in this state. The TX state will be active when the chip is transmitting.

The last four bits (3:0) in the status byte contains FIFO_BYTES_AVAILABLE. This field contains the number of bytes free for writing into the TX FIFO. When FIFO_BYTES_AVAILABLE=15, 15 or more bytes are free.

Table 15 gives a status byte summary.

Bits 6, 5 and 4 comprise the STATE value. This value reflects the state of the chip. The XOSC and power to the digital core is on in the IDLE state, but all other modules are in power down. The frequency and channel configuration

Bits Name Description

7 CHIP_RDYn Stays high until power and crystal have stabilized. Should always be low when using

6:4 STATE[2:0] Indicates the current main state machine mode

3:0 FIFO_BYTES_AVAILABLE[3:0] The number of free bytes in the TX FIFO. If FIFO_BYTES_AVAILABLE=15, it

the SPI interface.

Value State Description

000 Idle IDLE state

001 Not used

(RX)

010 TX Transmit mode

011 FSTXON Fast TX ready

100 CALIBRATE Frequency synthesizer calibration is running

101 SETTLING PLL is settling

110 Not used

(RXFIFO_OVERFLOW)

111 TXFIFO_UNDERFLOW TX FIFO has underflowed. Acknowledge with

indicates that 15 or more bytes are free.

(Also reported for some transitional states instead of SETTLING or CALIBRATE)

Not used, included for software compatibility with

CC2500

transceiver

Not used, included for software compatibility with

CC2500

transceiver

SFTX

Table 15: Status byte summary

10.2 Registers Access

The configuration registers on the

CC2550

are

located on SPI addresses from 0x00 to 0x2F. Table 24 on page 36 lists all configuration registers. The detailed description of each register is found in Section 27.1, starting on page 38. All configuration registers can be both written and read. The read/write bit controls if the register should be written or read. When writing to registers, the status byte

PRELIMINARY Data Sheet (Rev.1.2) SWRS039A Page 15 of 54

is sent on the SO pin each time a header byte or data byte is transmitted on the SI pin. When reading from registers, the status byte is sent on the SO pin each time a header byte is transmitted on the SI pin.

Registers with consecutive addresses can be accessed in an efficient way by setting the burst bit in the address header. The address sets the start address in an internal address counter. This counter is incremented by one

each new byte (every 8 clock pulses). The burst access is either a read or a write access and must be terminated by setting CSn high.

For register addresses in the range 0x300x3D, the “burst” bit is used to select between status registers and command strobes (see below). The status registers can only be read. Burst read is not available for status registers, so they must be read one at a time.

10.3 SPI Read

When reading register fields over the SPI interface while the register fields are updated by the radio hardware (e.g. MARCSTATE or TXBYTES), there is a small, but finite, probability that a single read from the register is being corrupt. As an example, the probability of any single read from TXBYTES being corrupt, assuming the maximum data rate is used, is approximately 80 ppm. Refer to the

CC2550

10.4 Command Strobes

Command strobes may be viewed as single byte instructions to command strobe register, internal sequences will be started. These commands are used to disable the crystal oscillator, enable transmit mode, flush the TX FIFO etc. The 9 command strobes are listed in Table 23 on page 35.

The command strobe registers are accessed in the same way as for a register write operation, but no data is transferred. That is, only the R/W bit (set to 0), burst access (set to

0) and the six address bits (in the range 0x30 through 0x3D) are written.

When writing command strobes, the status byte is sent on the SO pin.

A command strobe may be followed by any other SPI access without pulling CSn high. After issuing an SRES command strobe the next command strobe can be issued when the SO pin goes low as shown in Figure 8. The command strobes are executed immediately, with the exception of the SPWD and the SXOFF strobes that are executed when CSn goes high.

Errata Note for more details.

CC2550

. By addressing a

CC2550

Figure 8: SRES command strobe

10.5 FIFO Access

The 64-byte TX FIFO is accessed through the 0x3F address. When the read/write bit is zero, the TX FIFO is accessed. The TX FIFO is write-only.

The burst bit is used to determine if FIFO access is single byte or a burst access. The single byte access method expects address with burst bit set to zero and one data byte. After the data byte a new address is expected; hence, CSn can remain low. The burst access method expects one address byte and then consecutive data bytes until terminating the access by setting CSn high.

The following header bytes access the FIFO:

• 0x3F: Single byte access to TX FIFO

• 0x7F: Burst access to TX FIFO

When writing to the TX FIFO, the status byte (see Section 10.1) is output for each new data byte on SO, as shown in Figure 6. This status byte can be used to detect TX FIFO underflow while writing data to the TX FIFO. Note that the status byte contains the number of bytes

free before writing the byte in progress to the

TX FIFO. When the last byte that fits in the TX FIFO is transmitted to the SI pin, the status byte received concurrently on the SO pin will indicate that one byte is free in the TX FIFO.

The transmit FIFO may be flushed by issuing a SFTX command strobe. The FIFO is cleared when going to the SLEEP state.

10.6 PATABLE Access

The 0x3E address is used to access the PATABLE, which is used for selecting PA power control settings. The SPI expects up to eight data bytes after receiving the address. By programming the PATABLE, controlled PA power ramp-up and ramp-down can be achieved. See Section 21 on page 28 for output power programming details.

PRELIMINARY Data Sheet (Rev.1.2) SWRS039A Page 16 of 54

CC2550

The PATABLE is an 8-byte table that defines the PA control settings to use for each of the eight PA power values (selected by the 3-bit value FREND0.PA_POWER). The table is written and read from the lowest setting (0) to the highest (7), one byte at a time. An index counter is used to control the access to the table. This counter is incremented each time a byte is read or written to the table, and set to the lowest index when CSn is high. When the highest value is reached the counter restarts at

0. The access to the PATABLE is either single

byte or burst access depending on the burst bit. When using burst access the index counter will count up; when reaching 7 the counter will restart at 0. The read/write bit controls whether the access is a write access (R/W=0) or a read access (R/W=1).

If one byte is written to the PATABLE and this value is to be read out then CSn must be set high before the read access in order to set the index counter back to zero.

Note that the content of the PATABLE is lost when entering the SLEEP state.

11 Microcontroller Interface and Pin Configuration

In a typical system, microcontroller. This microcontroller must be able to:

• Program

• Write buffered data

• Read back status information via the 4-wire

SPI-bus configuration interface (SI, SO, SCLK and CSn)

CC2550

into different modes

will interface to a

pin is the SO pin in the SPI interface. The default setting for GDO1/SO is 3-state output. By selecting any other of the programming options the GDO1/SO pin will become a generic pin. When CSn is low, the pin will always function as a normal SO pin.

In the synchronous and asynchronous serial modes, the GDO0 pin is used as a serial TX data input pin while in transmit mode.

11.1 Configuration Interface

The microcontroller uses four I/O pins for the SPI configuration interface (SI, SO, SCLK and CSn). The SPI is described in 13 on page 13.

11.2 General Control and Status Pins

The

CC2550

pin and one shared pin that can output internal status information useful for control software. These pins can be used to generate interrupts on the MCU. See Section 24 page 30 for more details of the signals that can be programmed. The dedicated pin is called GDO0. The shared

has one dedicated configurable

PRELIMINARY Data Sheet (Rev.1.2) SWRS039A Page 17 of 54

The GDO0 pin can also be used for an on-chip analog temperature sensor. By measuring the voltage on the GDO0 pin with an external ADC, the temperature can be calculated. Specifications for the temperature sensor are found in Section 4.5 on page 7.

With default PTEST register setting (0x7F) the temperature sensor output is only available when the frequency synthesizer is enabled (e.g. the MANCAL, FSTXON and TX states). It is necessary to write 0xBF to the PTEST register to use the analog temperature sensor in the IDLE state. Before leaving the IDLE state, the PTEST register should be restored to its default value (0x7F).

12 Data Rate Programming

CC2550

The data rate used when transmitting is programmed by the MDMCFG3.DRATE_M and the MDMCFG4.DRATE_E configuration registers. The data rate is given by the formula below. As the formula shows, the programmed data rate depends on the crystal frequency.

R ⋅

The following approach can be used to find suitable values for a given data rate:

()

DATA

⎢

log_

EDRATE

⎢ ⎢

⎣

MDRATE

XOSC

⎛ ⎜

⎜ ⎝

DATA

⋅

MDRATE

DATA

⋅

⋅+

2_256

XOSC

EDRATE

XOSC

⎥

⎞

⋅

⎟

⎥

⎟

⎥

⎠

⎦

−

256

EDRATE

If DRATE_M is rounded to the nearest integer and becomes 256, increment DRATE_E and use DRATE_M=0.

The data rate can programmed from 1.2 kbps to 500 kbps with a minimum step size of:

Data rate

start

[kbps]

0.8 1.2/2.4 3.17 0.0062

3.17 4.8 6.35 0.0124

6.35 9.6 12.7 0.0248

12.7 19.6 25.4 0.0496

25.4 38.4 50.8 0.0992

50.8 76.8 101.6 0.1984

101.6 153.6 203.1 0.3967

203.1 250 406.3 0.7935

406.3 500 500 1.5869

Typical

data rate

[kbps]

Table 16: Data rate step size

Data rate

stop [kbps]

Data rate step size

[kbps]

13 Packet Handling Hardware Support

The

CC2550

packet oriented radio protocols.

In transmit mode, the packet handler will add the following elements to the packet stored in the TX FIFO:

• A programmable number of preamble

bytes.

• A two byte synchronization (sync) word.

Can be duplicated to give a 4-byte sync word.

• Optionally whiten the data with a PN9

sequence.

• Optionally Interleave and Forward Error

Code the data.

• Optionally compute and add a CRC

checksum over the data field.

In a system where transmitter and recommended setting is 4-byte preamble and 4-byte sync word except for 500 kbps data rate where the recommended preamble length is 8 bytes.

has built-in hardware support for

CC2550

CC2500

is used as the

as the receiver the

13.1 Data whitening

From a radio perspective, the ideal over the air data are random and DC free. This results in the smoothest power distribution over the occupied bandwidth. This also gives the regulation loops in the receiver uniform operation conditions (no data dependencies).

Real world data often contain long sequences of zeros and ones. Performance can then be improved by whitening the data before transmitting, and de-whitening in the receiver. With

CC2550

the receiver end, this can be done automatically by setting PKTCTRL0 .WHITE_DATA=1. All data, except the preamble and the sync word, are then XOR-ed with a 9-bit pseudo-random (PN9) sequence before being transmitted as shown in Figure 9. At the receiver end, the data are XOR-ed with the same pseudo-random sequence. This way, the whitening is reversed, and the original data appear in the receiver.

Data whitening can only be used when PKTCTRL0.CC2400_EN = 0 (default).

, in combination with a

CC2500

PRELIMINARY Data Sheet (Rev.1.2) SWRS039A Page 18 of 54

CC2550

Figure 9: Data whitening in TX mode

13.2 Packet format

The format of the data packet can be configured and consists of the following items (see Figure 10):

• Preamble

• Synchronization word

Optional data whitening

Optionally FEC encoded/decoded

Optional CRC-16 calculation

Preamble bits

(1010...1010)

8 x n bits 16/32 bits

Sync word

Length field

Address field

bits8bits

Data field

8 x n bits 16 bits

Figure 10: Packet format

The preamble pattern is an alternating sequence of ones and zeros (01010101…). The minimum length of the preamble is programmable. When enabling TX, the modulator will start transmitting the preamble. When the programmed number of preamble bytes has been transmitted, the modulator will send the sync word and then data from the TX FIFO if data is available. If the TX FIFO is empty, the modulator will continue to send preamble bytes until the first byte is written to the TX FIFO. The modulator will then send the sync word and then the data bytes. The

• Length byte or constant programmable

packet length

• Optional Address byte

• Payload

• Optional 2 byte CRC

Legend:

Inserted automatically in TX, processed and removed in RX.

Optional user-provided fields processed in TX,

CRC-16

processed but not removed in RX.

Unprocessed user data (apart from FEC and/or whitening)

number of preamble bytes is programmed with the MDMCFG1.NUM_PREAMBLE value.

The synchronization word is a two-byte value set in the SYNC1 and SYNC0 registers. The sync word provides byte synchronization of the incoming packet. A one-byte synch word can be emulated by setting the SYNC1 value to the preamble pattern. It is also possible to emulate a 32 bit sync word by using MDMCFG2.SYNC_MODE=3 or 7. The sync word will then be repeated twice.

PRELIMINARY Data Sheet (Rev.1.2) SWRS039A Page 19 of 54

CC2550

protocols and variable packet length protocols. Variable or fixed packet length mode can be used for packets up to 255 bytes. For longer packets, infinite packet length mode must be used.

Fixed packet length mode is selected by setting PKTCTRL0.LENGTH_CONFIG=0. The

desired packet length is set by the PKTLEN

In variable packet length mode, PKTCTRL0.LENGTH_CONFIG=1, the packet length is configured by the first byte after the sync word. The packet length is defined as the payload data, excluding the length byte and the optional automatic CRC.

With PKTCTRL0.LENGTH_CONFIG=2, the packet length is set to infinite and transmission will continue until turned off manually. The infinite mode can be turned off while a packet is being transmitted. As described in the next section, this can be used to support packet formats with different length configuration than natively supported by

supports both fixed packet length

CC2550

13.2.1 Arbitrary length field configuration

By utilizing the infinite packet length option, arbitrary packet length is available. At the start of the packet, the infinite mode must be active. On the TX side, the PKTLEN register is set to mod(length, 256). When less than 256 bytes remains of the packet the MCU disables infinite packet length and activates fixed length packets. When the internal byte counter reaches the PKTLEN value, the transmission ends. Automatic CRC appending/checking can be used (by setting PKTCTRL0.CRC_EN to 1).

When for example a 600-byte packet is to be transmitted, the MCU should do the following (see also Figure 11):

• Set PKTCTRL0.LENGTH_CONFIG=2 (10).

• Pre-program the PKTLEN register to

mod(600,256)=88.

• Transmit at least 345 bytes, for example

by filling the 64-byte TX FIFO six times (384 bytes transmitted).

• Set PKTCTRL0.LENGTH_CONFIG=0 (00).

• The transmission ends when the packet

counter reaches 88. A total of 600 bytes are transmitted.

Figure 11: Arbitrary length field configuration

PRELIMINARY Data Sheet (Rev.1.2) SWRS039A Page 20 of 54

CC2550

13.3 Packet Handling in Transmit Mode

The payload that is to be transmitted must be written into the TX FIFO. The first byte written must be the length byte when variable packet length is enabled. The length byte has a value equal to the payload of the packet (including the optional address byte). If fixed packet length is enabled, then the first byte written to the TX FIFO is interpreted as the destination address, if this feature is enabled in the device that receives the packet.

The modulator will first send the programmed number of preamble bytes. If data is available in the TX FIFO, the modulator will send the two-byte (optionally 4-byte) sync word and then the payload in the TX FIFO. If CRC is

14 Modulation Formats

CC2550

phase shift modulation formats. The desired modulation format is set in the MDMCFG2.MOD_FORMAT register.

supports amplitude, frequency and

enabled, the checksum is calculated over all the data pulled from the TX FIFO and the result is sent as two extra bytes at the end of the payload data.

If whitening is enabled, the length byte, payload data and the two CRC bytes will be whitened. This is done before the optional FEC/Interleaver stage. Whitening is enabled by setting PKTCTRL0.WHITE_DATA=1.

If FEC/Interleaving is enabled, the length byte, payload data and the two CRC bytes will be scrambled by the interleaver, and FEC encoded before being modulated.

Format Symbol Coding

FSK\GFSK ‘0’ – Deviation

‘1’ + Deviation

Optionally, the data stream can be Manchester coded by the modulator. This option is enabled by setting MDMCFG2.MANCHESTER_EN=1. Manchester encoding is not supported at the same time as using the FEC/Interleaver option.

14.1 Frequency Shift Keying

FSK can optionally be shaped by a Gaussian filter with BT=1, producing a GFSK modulated signal.

The frequency deviation is programmed with the DEVIATION_M and DEVIATION_E values in the DEVIATN register. The value has an exponent/mantissa form, and the resultant deviation is given by:

dev

xosc

The symbol encoding is shown in Table 17.

MDEVIATION

2)_8(

⋅+⋅=

EDEVIATION

Table 17: Symbol enc oding for FSK

modulation

14.2 Minimum Shift Keying

When using MSK (preamble, sync word and payload) will be MSK modulated.

Phase shifts are performed with a constant transition time.

The fraction of a symbol period used to change the phase can be modified with the DEVIATN.DEVIATION_M setting. This is equivalent to changing the shaping of the symbol.

The MSK modulation format implemented in

CC2550

compared to e.g. signal generators.

14.3 Amplitude Modulation

The supported amplitude modulation On-Off Keying (OOK) simply turns on or off the PA to modulate 1 and 0 respectively.

inverts the sync word and data

, the complete transmission

Identical to offset QPSK with half-sine

shaping (data coding may differ)

PRELIMINARY Data Sheet (Rev.1.2) SWRS039A Page 21 of 54

15 Forward Error Correction with Interleaving

CC2550

15.1 Forward Error Correction (FEC)

CC2550

Correction (FEC) that can be used with

has built in support for Forward Error

CC2500

at the receiver end. To enable this option, set MDMCFG1.FEC_EN to 1. FEC is employed on the data field and CRC word in order to reduce the gross bit error rate when operating near the sensitivity limit. Redundancy is added to the transmitted data in such a way that the receiver can restore the original data in the presence of some bit errors.

The use of FEC allows correct reception at a lower SNR, thus extending communication range. Alternatively, for a given SNR, using FEC decreases the bit error rate (BER). As the packet error rate (PER) is related to BER by:

lengthpacket

BERPER

)1(1 −−=

a lower BER can be used to allow longer packets, or a higher percentage of packets of a given length, to be transmitted successfully. Finally, in realistic ISM radio environments, transient and time-varying phenomena will produce occasional errors even in otherwise good reception conditions. FEC will mask such errors and, combined with interleaving of the coded data, even correct relatively long periods of faulty reception (burst errors).

The FEC scheme adopted for

CC2550

convolutional coding, in which n bits are generated based on k input bits and the m

most recent input bits, forming a code stream able to withstand a certain number of bit errors

between each coding state (the m-bit window).

The convolutional coder is a rate 1/2 code with a constraint length of m=4. The coder codes one input bit and produces two output bits; hence, the effective data rate is halved.

15.2 Interleaving

Data received through real radio channels will often experience burst errors due to interference and time-varying signal strengths. In order to increase the robustness to errors spanning multiple bits, interleaving is used when FEC is enabled. After de-interleaving, a continuous span of errors in the received stream will become single errors spread apart.

CC2550

employs matrix interleaving, which is illustrated in Figure 12. The on-chip interleaving and de-interleaving buffers are 4 x 4 matrices. In the transmitter, the data bits are written into the rows of the matrix, whereas the bit sequence to be transmitted is read from the columns of the matrix and fed to the rate ½ convolutional coder. Conversely, in a

CC2500

receiver, the received symbols are written into the columns of the matrix, whereas the data passed onto the convolutional decoder is read from the rows of the matrix.

When FEC and interleaving is used at least one extra byte is required for trellis termination. In addition, the amount of data transmitted over the air must be a multiple of the size of the interleaver buffer (two bytes). The packet control hardware therefore automatically inserts one or two extra bytes at the end of the packet, so that the total length of the data to be interleaved is an even number. Note that these extra bytes are invisible to the user, as they are removed before the received packet enters the RX FIFO in a

CC2500

When FEC and interleaving is used the minimum data payload is 2 bytes in fixed and variable packet length mode.

Note that for the

CC2500

transceiver FEC is

only supported in fixed packet length mode (PKTCTRL0.LENGTH_CONFIG=0).

Data

1) Storing coded

Encoder

data

2) Transmitting interleaved data

3) Receiving interleaved data

Modulator

Demodulator

4) Passing on data

ReceiverTransmitter

to decoder

Data

Decoder

Figure 12: General principle of matrix interleaving

PRELIMINARY Data Sheet (Rev.1.2) SWRS039A Page 22 of 54

16 Radio Control

MANCAL

3,4,5

SIDLE

CALIBRATE

SLEEP

XOFF

CAL_COMPLETE

SCAL

FS_AUTOCAL = 00 | 10 | 11

IDLE

STX | SFSTXON

FS_WAKEUP

STX | SFSTXON

SPWD

6,7

CSn = 0

SXOFF

CSn = 0

FS_AUTOCAL = 01

STX | SFSTXON

CC2550

TXOFF_MODE = 01

TXOFF_MODE = 10

TXFIFO_UNDERFLOW

TX_UNDERFLOW

FSTXON

SFSTXON

SFTX

SETTLING

9,10,11

STX

19,20

TXOFF_MODE = 00

FS_AUTOCAL = 00 | 01

CAL_COMPLETE

TXOFF_MODE = 00

FS_AUTOCAL = 10 | 11

IDLE

CALIBRATE

Figure 13: Radio control state diagram

CC2550

has a built-in state machine that is used to switch between different operation states (modes). The change of state is done either by using command strobes or by internal events such as TX FIFO underflow.

A simplified state diagram, together with typical usage and current consumption, is shown in Figure 4 on page 12. The complete radio control state diagram is shown in Figure

PRELIMINARY Data Sheet (Rev.1.2) SWRS039A Page 23 of 54

13. The numbers refer to the state number readable in the MARCSTATE status register. This functionality is primarily for test purposes.

16.1 Power-On Start-Up Sequence

When the power supply is turned on, the system must be reset. One of the following two

CC2550

sequences must be followed: Automatic power-on reset (POR) or manual reset.

16.1.1 Automatic POR

A power-on reset circuit is included in the

CC2550

Section 4.7 must be followed for the power-on reset to function properly. The internal powerup sequence is completed when CHIP_RDYn goes low. CHIP_RDYn is observed on the SO pin after CSn is pulled low. See Section 10.1 for more details on CHIP_RDYn.

When the will be in the IDLE state and the crystal oscillator running. If the chip has had sufficient time for the crystal oscillator and voltage regulator to stabilize after the power-on-reset, the SO pin will go low immediately after taking CSn low. If CSn is taken low before reset is completed the SO pin will first go high, indicating that the crystal oscillator and voltage regulator is not stabilized, before going low as shown in Figure 14.

16.1.2 Manual Reset

The other global reset possibility on the SRES command strobe. By issuing this strobe, all internal registers and states are set to the default, IDLE state. The manual powerup sequence is as follows (see Figure 15):

. The minimum requirements stated in

CC2550

CSn

Figure 14: Power-on reset

reset is completed the chip

XOSC and voltage regulator stabilized

CC2550

XOSC and voltage regulator switched on

40 us

CSn

XOSC and voltage regulator stabilized

Figure 15: Power-on reset with SRES

Note that the above reset procedure is only required just after the power supply is first turned on. If the user wants to reset the

CC2550

an SRES command strobe.

16.2 Crystal Control

The crystal oscillator is automatically turned on when CSn goes low. It will be turned off if the SXOFF or SPWD command strobes are issued; the state machine then goes to XOFF or SLEEP respectively. This can be done from any state. The XOSC will be turned off when CSn is released (goes high). The XOSC will be automatically turned on again when CSn goes low. The state machine will then go to the IDLE state. The SO pin on the SPI interface must be zero before the SPI interface is ready to be used; as described in Section 10.1 on page 15.

Crystal oscillator start-up time depends on crystal ESR and load capacitances. The electrical specification for the crystal oscillator can be found in Section 4.3 on page 6.

after this, it is only necessary to issue

SRES

• Set SCLK=1 and SI=0, to avoid potential

problems with pin control mode (see Section 11.2 on page 17).

• Strobe CSn low / high.

• Hold CSn high for at least 40 µs relative to

pulling CSn low

• Pull CSn low and wait for SO to go low

(CHIP_RDYn).

• Issue the SRES strobe on the SI line.

• When SO goes low again, reset is

complete and the chip is in the IDLE state.

PRELIMINARY Data Sheet (Rev.1.2) SWRS039A Page 24 of 54

16.3 Voltage Regulator Control

The voltage regulator to the digital core is controlled by the radio controller. When the chip enters the SLEEP state, which is the state with the lowest current consumption, the voltage regulator is disabled. This occurs after CSn is released when a SPWD command strobe has been sent on the SPI interface. The chip is now in the SLEEP state. Setting CSn low again will turn on the regulator and crystal oscillator and make the chip enter the IDLE state.

All

CC2550

of the MCSM0.PO_TIMEOUT field) are lost in

CC2550

the SLEEP state. After the chip gets back to the IDLE state, the registers will have default (reset) contents and must be reprogrammed over the SPI interface.

16.4 Active Mode

The active transmit mode is activated by the MCU by using the STX command strobe.

The frequency synthesizer must be calibrated regularly. option (using the SCAL strobe), and three automatic calibration options, controlled by the MCSM0.FS_AUTOCAL setting:

The calibration takes a constant number of XOSC cycles (see Table 18 for timing details).

When TX is active, the chip will remain in the TX state until the current packet has been successfully transmitted. Then the state will change as indicated by the MCSM1.TXOFF_MODE setting. The possible destinations are:

CC2550

• Calibrate when going from IDLE to TX

(or FSTXON)

• Calibrate when going from TX to IDLE

• Calibrate every fourth time when going

from TX to IDLE

has one manual calibration

The SIDLE command strobe can always be used to force the radio controller to go to the IDLE state.

16.5 Timing

The radio controller controls most timing in

CC2550

PLL lock. Timing from IDLE to TX is constant, dependent on the auto calibration setting. The calibration time is constant 18739 clock periods. Table 18 shows timing in crystal clock cycles for key state transitions.

Power on time and XOSC start-up times are variable, but within the limits stated in Table 6.

Note that in a frequency hopping spread spectrum or a multi-channel protocol the calibration time can be reduced from 721 µs to approximately 150 µs. This is explained in Section 26.2.

Description XOSC

Idle to TX/FSTXON, no calibration 2298 88.4 µs

Idle to TX/FSTXON, with calibration ~21037 809 µs

TX to IDLE, no calibration 2 0.1 µs

TX to IDLE, including calibration ~18739 721 µs

Manual calibration ~18739 721 µs

, such as synthesizer calibration and

periods

26 MHz crystal

• IDLE

• FSTXON: Frequency synthesizer on

and ready at the TX frequency. Activate TX with STX.

• TX: Start sending preambles

17 Data FIFO

The

CC2550

to be transmitted. The SPI interface is used for writing to the TX FIFO. Section 10.5 contains details on the SPI FIFO access. The FIFO controller will detect underflow in the TX FIFO.

When writing to the TX FIFO it is the responsibility of the MCU to avoid TX FIFO overflow. A TX FIFO overflow will result in an error in the TX FIFO content.

The chip status byte that is available on the SO pin while transferring the SPI address contains the fill grade of the TX FIFO. Section 10.1 on page 15 contains more details on this.

contains a 64 byte FIFO for data

Table 18: State transitio n timing

The number of bytes in the TX FIFO can also be read from the TXBYTES.NUM_TXBYTES status register.

The 4-bit FIFOTHR.FIFO_THR setting is used to program the FIFO threshold point. Table 19 lists the 16 FIFO_THR settings and the corresponding thresholds for the TX FIFO.

A flag will assert when the number of bytes in the FIFO is equal to or higher than the programmed threshold. The flag is used to generate the FIFO status signals that can be viewed on the GDO pins (see Section 24 on page 30).

PRELIMINARY Data Sheet (Rev.1.2) SWRS039A Page 25 of 54

(

CC2550

Figure 17 shows the number of bytes in the TX FIFO when the threshold flag toggles, in the case of FIFO_THR=13. Figure 16 shows the flag as the FIFO is filled above the threshold, and then drained below.

FIFO_THR

0 (0000) 61

1 (0001) 57

2 (0010) 53

3 (0011) 49

4 (0100) 45

5 (0101) 41

6 (0110) 37

7 (0111) 33

8 (1000) 29

9 (1001) 25

10 (1010) 21

11 (1011) 17

12 (1100) 13

13 (1101) 9

14 (1110) 5

15 (1111) 1

Bytes in TX FIFO

NUM_TXBYTES

6 7 8 9 678910

GDO

Figure 16: FIFO_THR=13 vs. number of bytes

in FIFO (GDOx_CFG=0x02)

Underflow

margin

8 bytes

TXFIFO

Figure 17: Example of FIFO at threshold

Table 19: FIFO_THR settings and the

corresponding FIFO thresholds

18 Frequency Programming

The frequency programming in designed to minimize the programming needed in a channel-oriented system.

To set up a system with channel numbers, the desired channel spacing is programmed with the MDMCFG0.CHANSPC_M and MDMCFG1.CHANSPC_E registers. The channel spacing registers are mantissa and exponent respectively.

carrier

XOSC

With a 26 MHz crystal the maximum channel spacing is 405 kHz. To get e.g. 1 MHz channel spacing one solution is to use 333 kHz

CC2550

()

The base or start frequency is set by the 24 bit frequency word located in the FREQ2, FREQ1 and FREQ0 registers. This word will typically be set to the centre of the lowest channel frequency that is to be used.

The desired channel number is programmed with the 8-bit channel number register, CHANNR.CHAN, which is multiplied by the channel offset. The resultant carrier frequency is given by:

−

ECHANSPC

2_256

⋅+⋅+⋅=

MCHANSPCCHANFREQ

)()

channel spacing and select each third channel in CHANNR.CHAN.

PRELIMINARY Data Sheet (Rev.1.2) SWRS039A Page 26 of 54

CC2550

If any frequency programming register is altered when the frequency synthesizer is running, the synthesizer may give an

19 VCO

The VCO is completely integrated on-chip.

19.1 VCO and PLL Self-Calibration

The VCO characteristics will vary with temperature and supply voltage changes, as well as the desired operating frequency. In order to ensure reliable operation, includes frequency synthesizer self-calibration circuitry. This calibration should be done regularly, and must be performed after turning on power and before using a new frequency (or channel). The number of XOSC cycles for completing the PLL calibration is given in Table 18 on page 25.

The calibration can be initiated automatically or manually. The synthesizer can be automatically calibrated each time the synthesizer is turned on, or each time the synthesizer is turned off. This is configured with the MCSM0.FS_AUTOCAL register setting.

CC2550

undesired response. Hence, the frequency programming should only be updated when the radio is in the IDLE state.

In manual mode, the calibration is initiated when the SCAL command strobe is activated in the IDLE mode.

The calibration values are not maintained in sleep mode. Therefore, the recalibrated after reprogramming the configuration registers when the chip has been in the SLEEP state.

To check that the PLL is in lock the user can program register IOCFGx.GDOx_CFG to 0x0A and use the lock detector output available on the GDOx pin as an interrupt for the MCU (x = 0,1 or 2). A positive transition on the GDOx pin means that the PLL is in lock. As an alternative the user can read register FSCAL1. The PLL is in lock if the register content is different from 0x3F. For more robust operation the source code could include a check so that the PLL is re-calibrated until PLL lock is achieved if the PLL does not lock the first time.

CC2550

must be

20 Voltage Regulators

CC2550

regulators, which generate the supply voltage needed by low-voltage modules. These voltage regulators are invisible to the user, and can be viewed as integral parts of the various modules. The user must however make sure that the absolute maximum ratings and required pin voltages in Table 1 and Table 11 are not exceeded. The voltage regulator for the digital core requires one external decoupling capacitor.

Setting the CSn pin low turns on the voltage regulator to the digital core and starts the crystal oscillator. The SO pin on the SPI interface must go low before using the serial interface (setup time is given in Table 14).

contains several on-chip linear voltage

If the chip is programmed to enter power-down mode, (SPWD strobe issued), the power will be turned off after CSn goes high. The power and crystal oscillator will be turned on again when CSn goes low.

The voltage regulator output should only be used for driving the

CC2550

PRELIMINARY Data Sheet (Rev.1.2) SWRS039A Page 27 of 54

21 Output Power Programming

CC2550

The RF output power level from the device has two levels of programmability, as illustrated in Figure 18. Firstly, the special PATABLE register can hold up to eight user selected output power settings. Secondly, the 3-bit

FREND0.PA_POWER value selects the PATABLE entry to use. This two-level

functionality provides flexible PA power ramp up and ramp down at the start and end of transmission. All the PA power settings in the

PATABLE from index 0 up to the FREND0.PA_POWER value are used.

PATABLE(7)[7:0]

PATABLE(6)[7:0]

PATABLE(5)[7:0]

PATABLE(4)[7:0]

PATABLE(3)[7:0]

PATABLE(2)[7:0]

PATABLE(1)[7:0]

The power ramping at the start and at the end of a packet can be turned off by setting FREND0.PA_POWER to 0 and then programming the desired output power to index 0 in the PATABLE.

Table 20 contains recommended PATABLE settings for various output levels and frequency bands. See Section 10.6 on page 16 for PATABLE programming details.

PATABLE must be programmed in burst mode if you want to write to other entries than

PATABLE[0].

The PA uses this setting.

Settings 0 to PA_POWER are used during ramp-up at start of transmission and ramp -down at end of transmission, and for OOK modulation.

PATABLE(0)[7:0]

Index into PATABLE(7:0)

e.g 6

PA_POWER[2:0] in FREND0 register

Figure 18: PA_POWER and PATABLE

The SmartRF® Studio software should be used to obtain optimum PATABLE settings for various output powers.

PRELIMINARY Data Sheet (Rev.1.2) SWRS039A Page 28 of 54

CC2550

Output power, typical,

+25oC, 3.0 V [dBm]

(–55 or less) 0x00 8.0

–30 0x44 9.3

–28 0x41 9.2

–26 0x43 9.7

–24 0x84 9.8

–22 0x82 9.7

–20 0x47 10.0

–18 0xC8 11.6

–16 0x85 10.2

–14 0x59 11.6

–12 0xC6 11.2

–10 0x97 12.0

–8 0xD6 12.9

–6 0x7F 14.7

–4 0xA9 16.2

–2 0xBF 18.1

0 0xEE 19.4

1 0xFF 21.3

PATABLE

value

Current consumption,

typical [mA]

Table 20: Optimum PATABLE settings for various output power levels

22 Crystal Oscillator

A crystal in the frequency range 26-27 MHz must be connected between the XOSC_Q1 and XOSC_Q2 pins. The oscillator is designed for parallel mode operation of the crystal. In addition, loading capacitors (C51 and C71) for the crystal are required. The loading capacitor values depend on the total load capacitance, C

, specified for the crystal. The total load

capacitance seen between the crystal terminals should equal C oscillate at the specified frequency.

C +

The parasitic capacitance is constituted by pin input capacitance and PCB stray capacitance. Total parasitic capacitance is typically 2.5 pF.

for the crystal to

7151

parasiticL

The crystal oscillator circuit is shown in Figure

19. Typical component values for different values of C

are given in Table 21.

The crystal oscillator is amplitude regulated. This means that a high current is used to start up the oscillations. When the amplitude builds up, the current is reduced to what is necessary to maintain approximately 0.4 Vpp signal swing. This ensures a fast start-up, and keeps the drive level to a minimum. The ESR of the crystal should be within the specification in order to ensure a reliable start-up (see Section

4.3 on page 6).

XOSC_Q1 XOSC_Q2

XTAL

C51 C71

Figure 19: Crystal oscillator circuit

PRELIMINARY Data Sheet (Rev.1.2) SWRS039A Page 29 of 54

CC2550

Component CL= 10pF CL=13pF CL=16pF

C51 15 pF 22 pF 27 pF

C71 15 pF 22 pF 27 pF

Table 21: Crystal oscillator component values

22.1 Reference Signal

The chip can alternatively be operated with a reference signal from 26 to 27 MHz instead of a crystal. This input clock can either be a fullswing digital signal (0 V to VDD) or a sine wave of maximum 1 V peak-peak amplitude.

23 External RF Match

The balanced RF output of for a simple, low-cost matching and balun network on the printed circuit board. A few passive external components ensure proper matching.

Although the chip can be connected to a single-ended antenna with few external low cost capacitors and inductors.

The passive matching/filtering network connected to

CC2550

has a balanced RF output,

CC2550

should have the following

is designed

The reference signal must be connected to the XOSC_Q1 input. The sine wave must be connected to XOSC_Q1 using a serial capacitor. The XOSC_Q2 line must be left unconnected. C51 and C71 can be omitted when using a reference signal

differential impedance as seen from the RFport (RF_P and RF_N) towards the antenna:

= 80 + j74 Ω

out

To ensure optimal matching of the differential output it is highly recommended to follow the CC2550EM reference designs as closely as possible. Gerber files for the reference designs are available for download from the TI and Chipcon websites.

CC2550

24 General Purpose / Test Output Control Pins

The two digital output pins GDO0 and GDO1 are general control pins. Their functions are programmed by IOCFG0.GDO0_CFG and IOCFG1.GDO1_CFG respectively. Table 22 shows the different signals that can be monitored on the GDO pins. These signals can be used as an interrupt to the MCU. GDO1 is the same pin as the SO pin on the SPI interface, thus the output programmed on this pin will only be valid when CSn is high. The default value for GDO1 is 3-stated, which is useful when the SPI interface is shared with other devices.

The default value for GDO0 is a 135-141 kHz clock output (XOSC frequency divided by 192). Since the XOSC is turned on at power-onreset, this can be used to clock the MCU in systems with only one crystal. When the MCU is up and running, it can change the clock frequency by writing to IOCFG0.GDO0_CFG.

An on-chip analog temperature sensor is enabled by writing the value 128 (0x80h) to the IOCFG0.GDO0_CFG register. The voltage on the GDO0 pin is then proportional to temperature. See Section 4.5 on page 7 for temperature sensor specifications.

PRELIMINARY Data Sheet (Rev.1.2) SWRS039A Page 30 of 54

GDOx

_CFG[5:0] Description

0 (0x00) 1 (0x01)

2 (0x02)

3 (0x03)

4 (0x04) 5 (0x05)

6 (0x06)

7 (0x07) 8 (0x08) 9 (0x09)

10 (0x0A)

11 (0x0B)

12 (0x0C) 13 (0x0D) 14 (0x0E) 15 (0x0F) 16 (0x10) 17 (0x11) 18 (0x12) 19 (0x13) 20 (0x14) 21 (0x15) 22 (0x16) 23 (0x17) 24 (0x18) 25 (0x19) 26 (0x1A)

27 (0x1B)

28 (0x1C) 29 (0x1D) 30 (0x1E) 31 (0x1F) 32 (0x20) 33 (0x21) 34 (0x22) 35 (0x23) 36 (0x24) 37 (0x25) 38 (0x26) 39 (0x27) 40 (0x28) 41 (0x29) 42 (0x2A) 43 (0x2B) 44 (0x2C) 45 (0x2D) 46 (0x2E) 47 (0x2F) 48 (0x30) 49 (0x31) 50 (0x32) 51 (0x33) 52 (0x34) 53 (0x35) 54 (0x36) 55 (0x37) 56 (0x38) 57 (0x39) 58 (0x3A) 59 (0x3B) 60 (0x3C) 61 (0x3D) 62 (0x3E) 63 (0x3F)

Reserved – defined on the transceiver version. Reserved – defined on the transceiver version. Associated with the TX FIFO: Asserts when the TX FIFO is filled at or above TXFIFO_THR. De-asserts when the TX

FIFO is below TXFIFO_THR. Associated to the TX FIFO: Asserts when TX FIFO is full. De-asserts when the TX FIFO is drained below

TXFIFO_THR. Reserved – defined on the transceiver version. Asserts when the TX FIFO has underflowed. De-asserts when the FIFO is flushed. Asserts when sync word has been sent, and de-asserts at the end of the packet. The pin will also de-assert if the TX

FIFO underflows. Reserved – defined on the transceiver version. Reserved – defined on the transceiver version. Reserved – defined on the transceiver version. Lock detector output. The PLL is in lock if the lock detector output has a positive transition or is constantly logic high. To

check for PLL lock the lock detector output should be used as an interrupt for the MCU. Serial Clock. Synchronous to the data in synchronous serial mode. Data is set up on the falling edge and is read on the rising edge of SERIAL_CLK when Reserved – defined on the transceiver version. Reserved – defined on the transceiver version. Reserved – defined on the transceiver version. Reserved – defined on the transceiver version. Reserved – used for test. Reserved – used for test. Reserved – used for test. Reserved – used for test. Reserved – used for test. Reserved – used for test. Reserved – defined on the transceiver version. Reserved – defined on the transceiver version. Reserved – used for test. Reserved – used for test. Reserved – used for test. PA_PD. Note: PA_PD will have the same signal level in SLEEP and TX states. To control an external PA in applications

where the SLEEP state is used it is recommended to use address 47 (0x2F). Reserved – defined on the transceiver version. Reserved – defined on the transceiver version. Reserved – used for test. Reserved – used for test. Reserved – used for test. Reserved – used for test. Reserved – used for test. Reserved – used for test. Reserved – used for test. Reserved – used for test. Reserved – used for test. Reserved – used for test. Reserved – used for test. CHIP_RDY Reserved – used for test. XOSC_STABLE Reserved – used for test.

GDO0

High impedance (3-state) HW to 0 (HW1 achieved with _INV signal). Can be used to control an external PA CLK_XOSC/1 CLK_XOSC/1.5 CLK_XOSC/2 CLK_XOSC/3 CLK_XOSC/4 CLK_XOSC/6 CLK_XOSC/8 CLK_XOSC/12 CLK_XOSC/16 CLK_XOSC/24 CLK_XOSC/32 CLK_XOSC/48 CLK_XOSC/64 CLK_XOSC/96 CLK_XOSC/128 CLK_XOSC/192

GDOx_INV

_Z_EN_N. When this output is 0, GDO0 is configured as input (for serial TX data).

Note: There are 2 GDO pins, but only one CLK_XOSC/n can be selected as an output at any time. If CLK_XOSC/n is to be monitored on one of the GDO pins, the other GDO pin must be configured to a value less than 0x30. The GDO0 default value is CLK_XOSC/192.

CC2550

=0.

Table 22: GDOx signal selection (x = 0 or 1)

PRELIMINARY Data Sheet (Rev.1.2) SWRS039A Page 31 of 54

25 Asynchronous and Synchronous Serial Operation

CC2550

Several features and modes of operation have been included in the backward compatibility with previous Chipcon products and other existing RF communication systems. For new systems, it is recommended to use the built-in packet handling features, as they can give more robust communication, significantly offload the microcontroller and simplify software development.

25.1 Asynchronous operation

For backward compatibility with systems already using the asynchronous data transfer from other Chipcon products, asynchronous transfer is also included in asynchronous transfer is enabled, several of the support mechanisms for the MCU that are included in packet handling hardware, buffering in the FIFO and so on. The asynchronous transfer mode does not allow the use of the data whitener, interleaver and FEC.

Only FSK, GFSK and OOK are supported for asynchronous transfer.

Setting PKTCTRL0.PKT_FORMAT to 3 enables asynchronous transparent (serial) mode.

In TX, the GDO0 pin is used for data input (TX data).

The MCU must control start and stop of transmit with the STX and SIDLE strobes.

CC2550

will be disabled, such as

to provide

CC2550

. When

The

CC2550

asynchronous input 8 times faster than the programmed data rate. The timing requirement for the asynchronous stream is that the error in the bit period must be less than one eighth of the programmed data rate.

25.2 Synchronous serial operation

Setting PKTCTRL0.PKT_FORMAT to 1 enables synchronous serial operation mode. In this operational mode the data must be NRZ encoded (MDMCFG2.MANCHESTER_EN=0). In synchronous serial operation mode, data is transferred on a two wire serial interface. The

CC2550

new data on the data input line. Data input (TX data) is the GDO0 pin. This pin will automatically be configured as an input when TX is active.

Preamble and sync word insertion may or may not be active, dependent on the sync mode set by the MDMCFG3.SYNC_MODE. If preamble and sync word is disabled, all other packet handler features and FEC should also be disabled. The MCU must then handle preamble and sync word insertion in software. If preamble and sync word insertion is left on, all packet handling features and FEC can be used. The

CC2550

and the MCU will only provide the data payload. This is equivalent to the recommended FIFO operation mode.

modulator samples the level of the

provides a clock that is used to set up

will insert the preamble and sync word

26 System considerations and Guidelines

26.1 SRD Regulations

International regulations and national laws regulate the use of radio receivers and transmitters. Short Range Devices (SRDs) for license free operation are allowed to operate in the 2.45 GHz bands worldwide. The most important regulations are EN 300 440 and EN 300 328 (Europe), FCC CFR47 part 15.247 and 15.249 (USA), and ARIB STD-T66 (Japan). A summary of the most important aspects of these regulations can be found in

Application Note AN032 SRD regulations for

license-free transceiver operation in the 2.4 GHz band, available from the TI and Chipcon

websites.

PRELIMINARY Data Sheet (Rev.1.2) SWRS039A Page 32 of 54

Please note that compliance with regulations is dependent on complete system performance. It is the customer’s responsibility to ensure that the system complies with regulations.

26.2 Frequency Hopping and MultiChannel Systems

The 2.400 – 2.4835 GHz band is shared by many systems both in industrial, office and home environments. It is therefore recommended to use frequency hopping spread spectrum (FHSS) or a multi-channel protocol because the frequency diversity makes the system more robust with respect to

CC2550

interference from other systems operating in the same frequency band. FHSS also combats multipath fading.

CC2550

channel systems due to its agile frequency synthesizer and effective communication interface. Using the packet handling support and data buffering is also beneficial in such systems as these features will significantly offload the host controller.

Charge pump current, VCO current and VCO capacitance array calibration data is required for each frequency when implementing frequency hopping for ways of obtaining the calibration data from the chip:

1) Frequency hopping with calibration for each hop. The PLL calibration time is approximately 720 µs.

2) Fast frequency hopping without calibration for each hop can be done by calibrating each frequency at startup and saving the resulting FSCAL3, FSCAL2 and FSCAL1 register values in MCU memory. Between each frequency hop, the calibration process can then be replaced by writing the FSCAL3, FSCAL2 and FSCAL1 register values corresponding to the next RF frequency. The PLL turn on time is approximately 90 µs.

3) Run calibration on a single frequency at startup. Next write 0 to FSCAL3[5:4] to disable the charge pump calibration. After writing to FSCAL3[5:4] strobe SRX (or STX) with MCSM0.FS_AUTOCAL = 1 for each new frequency hop. That is, VCO current and VCO capacitance calibration is done but not charge pump current calibration. When charge pump current calibration is disabled the calibration time is reduced from approximately 720 µs to approximately 150 µs.

There is a trade off between blanking time and memory space needed for storing calibration data in non-volatile memory. Solution 2) above gives the shortest blanking interval, but requires more memory space to store calibration values. Solution 3) gives approximately 570 µs smaller blanking interval than solution 1).

26.3 Wideband Modulation not Using

is highly suited for FHSS or multi-

CC2550

Spread Spectrum

. There are 3

A maximum peak output power of 1 W (+30 dBm) is allowed if the 6 dB bandwidth of the modulated signal exceeds 500 kHz. In addition, the peak power spectral density conducted to the antenna shall not be greater than +8 dBm in any 3 kHz band.

Operating at high data rates and high frequency separation, the systems targeting compliance with digital modulation systems as defined by FCC part

15.247. An external power amplifier is needed

to increase the output above +1 dBm.

26.4 Data Burst Transmissions

The high maximum data rate of up for burst transmissions. A low average data rate link (e.g. 10 kbps), can be realized using a higher over-the-air data rate. Buffering the data and transmitting in bursts at high data rate (e.g. 500 kbps) will reduce the time in active mode, and hence also reduce the average current consumption significantly. Reducing the time in active mode will reduce the likelihood of collisions with other 2.4 GHz systems, e.g. WLAN.

26.5 Continuous Transmissions

In data streaming applications the opens up for continuous transmissions at 500 kbps effective data rate. As the modulation is done with an I/Q up-converter with LO I/Qsignals coming from a closed loop PLL, there is no limitation in the length of a transmission. (Open loop modulation used in some transceivers often prevents this kind of continuous data streaming and reduces the effective data rate.)

26.6 Spectrum Efficient Modulation

CC2500

Gaussian shaped FSK (GFSK). This spectrum-shaping feature improves adjacent channel power (ACP) and occupied bandwidth. In ‘true’ FSK systems with abrupt frequency shifting, the spectrum is inherently broad. By making the frequency shift ‘softer’, the spectrum can be made significantly narrower. Thus, higher data rates can be transmitted in the same bandwidth using GFSK.

also has the possibility to use

CC2550

is suited for

CC2550

opens

CC2550

Digital modulation systems under FCC part

15.247 includes FSK and GFSK modulation.

PRELIMINARY Data Sheet (Rev.1.2) SWRS039A Page 33 of 54

CC2550

26.7 Low Cost Systems

As the channel performance without any external filters, a very low cost system can be made.

A differential antenna will eliminate the need for a balun, and the DC biasing can be achieved in the antenna topology, see Figure

A HC-49 type SMD crystal is used in the CC2550EM reference design. Note that the crystal package strongly influences the price. In a size constrained PCB design a smaller, but more expensive, crystal may be used.

CC2550

provides 500 kbps multi-

26.8 Battery Operated Systems

In low power applications, the SLEEP state should be used when the

26.9 Increasing Output Power

In some applications it may be necessary to extend the link range by adding an external power amplifier.

The power amplifier should be inserted between the antenna and the balun as shown in Figure 20.

CC2550

is not active.

Figure 20. Block diagram of

CC2550

27 Configuration Registers

The configuration of programming 8-bit registers. The configuration data based on selected system parameters are most easily found by using the SmartRF Studio software. Complete descriptions of the registers are given in the following tables. After chip reset, all the registers have default values as shown in the tables.

There are 9 Command Strobe Registers, listed in Table 23. Accessing these registers will initiate the change of an internal state or mode. There are 29 normal 8-bit Configuration Registers, listed in Table 24. Many of these registers are for test purposes only, and need not be written for normal operation of

There are also 6 Status registers, which are listed in Table 25. These registers, which are read-only, contain information about the status

CC2550

is done by

CC2550

usage with external power amplifier

The TX FIFO is accessed through one 8-bit register. Only write operations are allowed to the TX FIFO.

During the address transfer and while writing to a register or the TX FIFO, a status byte is returned. This status byte is described in Table 15 on page 15.

Table 26 summarizes the SPI address space. Registers that are only defined on the transceiver are also listed. are register compatible, but registers and fields only implemented in the transceiver always contain 0 in

The address to use is given by adding the base address to the left and the burst and read/write bits on the top. Note that the burst bit has different meaning for base addresses above and below 0x2F.

CC2550

CC2500

and

CC2500 CC2550

PRELIMINARY Data Sheet (Rev.1.2) SWRS039A Page 34 of 54

CC2550

Address Strobe Name Description

0x30 SRES Reset chip.

0x31 SFSTXON

0x32 SXOFF Turn off crystal oscillator.

0x33 SCAL Calibrate frequency synthesizer and turn it off (enables quick start). SCAL can be strobed

0x35 STX

0x36 SIDLE Exit TX and turn off frequency synthesizer.

0x39 SPWD

0x3B SFTX Flush the TX FIFO buffer.

0x3D SNOP No operation. May be used to pad strobe commands to two bytes for simpler software.

Enable and calibrate frequency synthesizer (if

in IDLE state without setting manual calibration mode (

Enable TX. Perform calibration first if

Enter power down mode when

MCSM0.FS_AUTOCAL

CSn

goes high.

Table 23: Command strobes

MCSM0.FS_AUTOCAL

=1.

=1).

=0).

PRELIMINARY Data Sheet (Rev.1.2) SWRS039A Page 35 of 54

CC2550

Address Register Description Details on page number

GDO1

0x01 IOCFG1

0x02 IOCFG0

0x03 FIFOTHR FIFO threshold 38

0x04 SYNC1 Sync word, high byte 39

0x05 SYNC0 Sync word, low byte 39

0x06 PKTLEN Packet length 39

0x08 PKTCTRL0 Packet automation control 39

0x0A CHANNR Channel number 40

0x0D FREQ2 Frequency control word, high byte 40

0x0E FREQ1 Frequency control word, middle byte 40

0x0F FREQ0 Frequency control word, low byte 40

0x10 MDMCFG4 Modulator configuration 40

0x11 MDMCFG3 Modulator configuration 41

0x12 MDMCFG2 Modulator configuration 41

0x13 MDMCFG1 Modulator configuration 42

0x14 MDMCFG0 Modulator configuration 42

0x15 DEVIATN Modulator deviation setting 43

0x17 MCSM1 Main Radio Control State Machine configuration 43

0x18 MCSM0 Main Radio Control State Machine configuration 44

0x22 FREND0 Front end TX configuration 44

0x23 FSCAL3 Frequency synthesizer calibration 45

0x24 FSCAL2 Frequency synthesizer calibration 45

0x25 FSCAL1 Frequency synthesizer calibration 45

0x26 FSCAL0 Frequency synthesizer calibration 45

0x29 FSTEST Frequency synthesizer calibration control 45

0x2A PTEST Production test 46

0x2C TEST2 Various test settings 46

0x2D TEST1 Various test settings 46

0x2E TEST0 Various test settings 46

output pin configuration

GDO0

output pin configuration

Table 24: Configuration registers overview

Address Register Description Details on page number

0x30 (0xF0) PARTNUM

0x31 (0xF1) VERSION Current version number 46

0x35 (0xF5) MARCSTATE Control state machine state 47

0x38 (0xF8) PKTSTATUS Current GDOx status and packet status 47

0x39 (0xF9) VCO_VC_DAC Current setting from PLL calibration module 48

0x3A (0xFA) TXBYTES Underflow and number of bytes in the TX FIFO 48

CC2550

part number

Table 25: Status regist ers overv ie w

PRELIMINARY Data Sheet (Rev.1.2) SWRS039A Page 36 of 54

CC2550

Write Read Single byte Burst Single byte Burst +0x00 +0x40 +0x80 +0xC0

0x00 IOCFG2 0x01 IOCFG1 0x02 IOCFG0 0x03 FIFOTHR 0x04 SYNC1 0x05 SYNC0 0x06 PKTLEN 0x07 PKTCTRL1 0x08 PKTCTRL0 0x09 ADDR 0x0A CHANNR 0x0B FSCTRL1 0x0C FSCTRL0 0x0D FREQ2 0x0E FREQ1 0x0F FREQ0 0x10 MDMCFG4 0x11 MDMCFG3 0x12 MDMCFG2 0x13 MDMCFG1 0x14 MDMCFG0 0x15 DEVIATN 0x16 MCSM2 0x17 MCSM1 0x18 MCSM0 0x19 FOCCFG 0x1A BSCFG 0x1B AGCCTRL2 0x1C AGCCTRL1 0x1D AGCCTRL0 0x1E WOREVT1 0x1F WOREVT0 0x20 WORCTRL 0x21 FREND1 0x22 FREND0 0x23 FSCAL3 0x24 FSCAL2 0x25 FSCAL1 0x26 FSCAL0 0x27 RCCTRL1 0x28 RCCTRL0 0x29 FSTEST 0x2A PTEST 0x2B AGCTEST 0x2C TEST2 0x2D TEST1 0x2E TEST0 0x2F 0x30 SRES SRES PARTNUM 0x31 SFSTXON SFSTXON VERSION 0x32 SXOFF SXOFF FREQEST 0x33 SCAL SCAL LQI 0x34 SRX SRX RSSI 0x35 STX STX MARCSTATE 0x36 SIDLE SIDLE WORTIME1 0x37 SAFC SAFC WORTIME0 0x38 SWOR SWOR PKTSTATUS 0x39 SPWD SPWD VCO_VC_DAC 0x3A SFRX SFRX TXBYTES 0x3B SFTX SFTX RXBYTES 0x3C SWORRST SWORRST 0x3D SNOP SNOP 0x3E PATABLE PATABLE PATABLE PATABLE 0x3F TX FIFO TX FIFO RX FIFO RX FIFO

R/W configuration registers, burst access possible

Command Strobes, Status registers

(read only) and multi byte registers

Table 26: SPI address space (greyed text: for reference only; not implemented on

PRELIMINARY Data Sheet (Rev.1.2) SWRS039A Page 37 of 54

CC2550

)

27.1 Configuration Register Details

0x01: IOCFG1 – GDO1 output pin configuration

Bit Field Name Reset R/W Description

CC2550

7 GDO_DS 0 R/W Set high (1) or low (0) output drive strength on the

5:0

GDO1 GDO1

_INV

_CFG[5:0]

0 R/W Invert output, i.e. select active low / high

46 (0x2E) R/W Default is 3-state (see Table 22 on page 31)

GDO pins.

0x02: IOCFG0 – GDO0 output pin configuration

Bit Field Name Reset R/W Description

7 TEMP_SENSOR_ENABLE 0 R/W Enable analog temperature sensor. Write 0 in all

5:0

GDO0 GDO0

_INV

_CFG[5:0]

0 R/W Invert output, i.e. select active low / high

63 (0x3F) R/W Default is CLK_XOSC/192 (see Table 22 on page

other register bits when using temperature sensor.

31)

0x03: FIFOTHR – FIFO threshold

Bit Field Name Reset R/W Description

7:4 Reserved 0 (0000) R/W Write 0 (0000) for compatibility with possible future

3:0 FIFO_THR[3:0] 7 (0111) R/W Set the threshold for the TX FIFO. The threshold is

extensions.

exceeded when the number of bytes in the FIFO is equal to or higher than the threshold value.

Setting Bytes in TX FIFO

0 (0000) 61

1 (0001) 57

2 (0010) 53

3 (0011) 49

4 (0100) 45

5 (0101) 41

6 (0110) 37

7 (0111) 33

8 (1000) 29

9 (1001) 25

10 (1010) 21

11 (1011) 17

12 (1100) 13

13 (1101) 9

14 (1110) 5

15 (1111) 1

PRELIMINARY Data Sheet (Rev.1.2) SWRS039A Page 38 of 54

0x04: SYNC1– Sync word, high byte

Bit Field Name Reset R/W Description

7:0 SYNC[15:8] 211 (0xD3) R/W 8 MSB of 16-bit sync word

0x05: SYNC0 – Sync word, low byte

Bit Field Name Reset R/W Description

7:0 SYNC[7:0] 145 (0x91) R/W 8 LSB of 16-bit sync word

0x06: PKTLEN – Packet length

Bit Field Name Reset R/W Description

CC2550

7:0 PACKET_LENGTH 255 (0xFF) R/W Indicates the packet length when fixed length

packets are enabled.

0x08: PKTCTRL0 – Packet automation control

Bit Field Name Reset R/W Description

7 Reserved R0

6 WHITE_DATA 1 R/W Turn data whitening on / off

0: Whitening off 1: Whitening on

Data whitening can only be used when

KTCTRL0.CC2400_EN

5:4 PKT_FORMAT[1:0] 0 (00) R/W Format of RX and TX data

Setting Packet format

0 (00) Normal mode, use TX FIFO

1 (01)

2 (10)

3 (11)

3 CC2400_EN 0 R/W Enable CC2400 support. Use same CRC implementation as

CC2400.

Serial Synchronous mode, used for backwards compatibility

Random TX mode; sends random data using PN9 generator. Used for test.

Asynchronous transparent mode. Data in on and Data out on either of the GDO pins

PKTCTRL0.WHITE_DATA PKTCTRL0.CC2400_EN

2 CRC_EN 1 R/W 1: CRC calculation enabled

0: CRC disabled

1:0 LENGTH_CONFIG[1:0] 1 (01) R/W Configure the packet length

Setting Packet length configuration

0 (00) Fixed length packets, length configured in

1 (01) Variable length packets, packet length configured

2 (10) Enable infinite length packets

3 (11) Reserved

PKTLEN register

by the first byte after sync word

= 0 (default).

GDO0

must be 0 if

= 1.

PRELIMINARY Data Sheet (Rev.1.2) SWRS039A Page 39 of 54

0x0A: CHANNR – Channel number

Bit Field Name Reset R/W Description

CC2550

7:0 CHAN[7:0] 0 (0x00) R/W The 8-bit unsigned channel number, which is multiplied by

the channel spacing setting and added to the base frequency.

0x0D: FREQ2 – Frequency control word, high byte

Bit Field Name Reset R/W Description

7:6 FREQ[23:22] 1 (01) R FREQ[23:22] is always binary 01 (the FREQ2 register is in the range

5:0 FREQ[21:16] 30

(0x1E)

85 to 95 with 26 - 27 MHz crystal)

R/W FREQ[23:0] is the base frequency for the frequency synthesiser in

increments of F

carrier

The default frequency word gives a base frequency of 2464 MHz, assuming a 26.0 MHz crystal. With the default channel spacing settings, the following FREQ2 values and channel numbers can be used:

FREQ2 Base frequency Frequency range (CHAN

91 (0x5B) 2386 MHz 2400.2-2437 MHz (71-255)

92 (0x5C) 2412 MHz 2412-2463 MHz (0-255)

93 (0x5D) 2438 MHz 2431-2483.4 MHz (0-227)

94 (0x5E) 2464 MHz 2464-2483.4 MHz (0-97)

XOSC

/216.

FREQ

⋅=

[]

0:23

numbers)

0x0E: FREQ1 – Frequency control word, middle byte

Bit Field Name Reset R/W Description

7:0 FREQ[15:8] 196 (0xC4) R/W Ref. FREQ2 register

0x0F: FREQ0 – Frequency control word, low byte

Bit Field Name Reset R/W Description

7:0 FREQ[7:0] 236 (0xEC) R/W Ref. FREQ2 register

0x10: MDMCFG4 – Modulator configuration

Bit Field Name Reset R/W Description

7:4 Reserved R0 Defined on the transceiver version

3:0 DRATE_E[3:0] 12 (1100) R/W The exponent of the user specified symbol rate

PRELIMINARY Data Sheet (Rev.1.2) SWRS039A Page 40 of 54

(

0x11: MDMCFG3 – Modulator configuration

Bit Field Name Reset R/W Description

CC2550

7:0 DRATE_M[7:0] 34 (0x22) R/W The mantissa of the user specified symbol rate. The symbol

rate is configured using an unsigned, floating-point number with 9-bit mantissa and 4-bit exponent. The 9 hidden ‘1’. The resulting data rate is:

)

MDRATE

R ⋅

DATA

The default values give a data rate of 115.051 kbps (closest setting to 115.2 kbps), assuming a 26.0 MHz crystal.

⋅+

bit is a

EDRATE

2_256

XOSC

0x12: MDMCFG2 – Modulator configuration

Bit Field Name Reset R/W Description

7 Reserved R0

6:4 MOD_FORMAT[2:0] 1 (001) R/W The modulation format of the radio signal

Setting Modulation format

0 (000) FSK

1 (001) GFSK

2 (010) -

3 (011) OOK

4 (100) -

5 (101) -

6 (110) -

7 (111) MSK

3 MANCHESTER_EN 0 R/W Enables Manchester encoding/decoding

0 = Disable

1 = Enable

2:0 SYNC_MODE[2:0] 2 (010) R/W Combined sync-word qualifier mode.

The values 0 (000) and 4 (100) disables preamble and sync word transmission. The values 1 (001), 2 (001), 5 (101) and 6 (110) enables 16-bit sync word transmission. The values 3 (011) and 7 (111) enables repeated sync word transmission. The table below lists the meaning of each mode (for compatibility with the

Setting Sync-word qualifier mode

0 (000) No preamble/sync word

1 (001) 15/16 sync word bits detected

2 (010) 16/16 sync word bits detected

3 (011) 30/32 sync word bits detected

4 (100) No preamble/sync, carrier-sense

5 (101) 15/16 + carrier-sense above threshold

6 (110) 16/16 + carrier-sense above threshold

7 (111) 30/32 + carrier-sense above threshold

above threshold

CC2500

transceiver):

PRELIMINARY Data Sheet (Rev.1.2) SWRS039A Page 41 of 54

0x13: MDMCFG1 – Modulator configuration

Bit Field Name Reset R/W Description

CC2550

7 FEC_EN 0 R/W Enable Forward Error Correction (FEC) with interleaving for

6:4 NUM_PREAMBLE[2:0] 2 (010) R/W Sets the minimum number of preamble bytes to be

3:2 Reserved R0

1:0 CHANSPC_E[1:0] 2 (10) R/W 2 bit exponent of channel spacing

packet payload

0 = Disable

1 = Enable

transmitted

Setting Number of preamble bytes

0 (000) 2

1 (001) 3

2 (010) 4

3 (011) 6

4 (100) 8

5 (101) 12

6 (110) 16

7 (111) 24

0x14: MDMCFG0 – Modulator configuration

Bit Field Name Reset R/W Description

7:0 CHANSPC_M[7:0] 248 (0xF8) R/W 8-bit mantissa of channel spacing (initial 1 assumed). The

channel spacing is multiplied by the channel number CHAN and added to the base frequency. It is unsigned and has the format:

XOSC

CHANNEL

The default values give 199.951 kHz channel spacing (the closest setting to 200 kHz), assuming 26.0 MHz crystal frequency.

()

2_256

ECHANSPC

⋅⋅+⋅=∆

CHANMCHANSPC

PRELIMINARY Data Sheet (Rev.1.2) SWRS039A Page 42 of 54

0x15: DEVIATN – Modulator deviation setting

Bit Field Name Reset R/W Description

7 Reserved R0

6:4 DEVIATION_E[2:0] 4 (100) R/W Deviation exponent

3 Reserved R0

2:0 DEVIATION_M[2:0] 7 (111) R/W When MSK modulation is enabled:

Sets fraction of symbol period used for phase change.

When FSK modulation is enabled:

Deviation mantissa, interpreted as a 4-bit value with MSB implicit 1. The resulting FSK deviation is given by:

CC2550

dev

xosc

The default values give ±47.607 kHz deviation, assuming

26.0 MHz crystal frequency.

MDEVIATION

2)_8(

⋅+⋅=

EDEVIATION

0x17: MCSM1 – Main Radio Control State Machine configuration

Bit Field Name Reset R/W Description

7:6 Reserved R0

5:2 Reserved R0 Defined on the transceiver version

1:0 TXOFF_MODE[1:0] 0 (00) R/W Select what should happen when a packet has been sent

(TX)

Setting Next state after finishing packet transmission

0 (00) IDLE

1 (01) FSTXON

2 (10) Stay in TX (start sending preamble)

3 (11)

Do not use, not implemented on (Go to RX)

CC2550

PRELIMINARY Data Sheet (Rev.1.2) SWRS039A Page 43 of 54

CC2550

0x18: MCSM0 – Main Radio Control State Machine configuration

Bit Field Name Reset R/W Description

7:6 Reserved R0

5:4 FS_AUTOCAL[1:0] 0 (00) R/W Automatically calibrate when going to TX or back to IDLE

Setting When to perform automatic calibration

0 (00)

1 (01) When going from IDLE to TX (or FSTXON)

2 (10) When going from TX back to IDLE

3 (11) Every 4th time when going from TX to IDLE

3:2 PO_TIMEOUT 2 (10) R/W Programs the number of times the six-bit ripple counter must expire

1:0 Reserved R0 Defined on the transceiver version

after XOSC has stabilized before CHP_RDYn goes low.

The XOSC is off during power-down so the regulated digital supply voltage has time to stabilize while waiting for the crystal to be stable even with PO_TIMEOUT to 0.

Setting Expire count Timeout after XOSC start

0 (00) 1 Approx. 2.3 – 2.4 µs

1 (01) 16 Approx. 37 – 39 µs

2 (10) 64 Approx. 149 – 155 µs

3 (11) 256 Approx. 597 – 620 µs

Exact timeout depends on crystal frequency.

In order to reduce start up time from the SLEEP state, this field is preserved in powerdown (SLEEP state).

Never (manually calibrate using

SCAL

strobe)

0x22: FREND0 – Front end TX configuration

Bit Field Name Reset R/W Description

7:6 Reserved R0

5:4 LODIV_BUF_CURRENT_TX[1:0] 1 (01) R/W Adjusts current TX LO buffer (input to PA). The

value to use in this field is given by the SmartRF Studio software.

3 Reserved R0

2:0 PA_POWER[2:0] 0 (000) R/W Selects PA power setting. This value is an index to

the PATABLE, which can be programmed with up to 8 different PA settings. The PATABLE settings from index ‘0’ to the PA_POWER value are used for power ramp-up/ramp-down at the start/end of transmission in all TX modulation formats.

PRELIMINARY Data Sheet (Rev.1.2) SWRS039A Page 44 of 54

0x23: FSCAL3 – Frequency synthesizer calibration

Bit Field Name Reset R/W Description

CC2550

7:6 FSCAL3[7:6] 2 (10) R/W Frequency synthesizer calibration configuration. The value to write

5:4 CHP_CURR_CAL_EN[1:0] 2 (10) R/W Disable charge pump calibration stage when 0

3:0 FSCAL3[3:0] 9

(1001)

in this register before calibration is given by the SmartRF software.

R/W Frequency synthesizer calibration result register.

Fast frequency hopping without calibration for each hop can be done by calibrating upfront for each frequency and saving the resulting FSCAL3, FSCAL2 and FSCAL1 register values. Between each frequency hop, calibration can be replaced by writing the FSCAL3, FSCAL2 and FSCAL1 register values corresponding to the next RF frequency.

Studio

0x24: FSCAL2 – Frequency synthesizer calibration

Bit Field Name Reset R/W Description

7:6 Reserved R0

5:0 FSCAL2[5:0] 10

(0x0A)

R/W Frequency synthesizer calibration result register.

0x25: FSCAL1 – Frequency synthesizer calibration

Bit Field Name Reset R/W Description

7:6 Reserved R0

5:0 FSCAL1[5:0] 32

(0x20)

R/W Frequency synthesizer calibration result register.

0x26: FSCAL0 – Frequency synthesizer calibration

Bit Field Name Reset R/W Description

7 Reserved R0

6:5 Reserved 0 (00) R0 Defined on the transceiver version

4:0 FSCAL0[4:0] 13

(0x0D)

R/W Frequency synthesizer calibration control. The value to use in

0x29: FSTEST – Frequency synthesizer calibration control

Bit Field Name Reset R/W Description

Studio software.

7:0 FSTEST[7:0] 87

(0x57)

PRELIMINARY Data Sheet (Rev.1.2) SWRS039A Page 45 of 54

R/W For test only. Do not write to this register.

0x2A: PTEST – Production test

Bit Field Name Reset R/W Description

CC2550

7 PTEST[7:0] 127

(0x7F)

R/W Writing 0xBF to this register makes the on-chip temperature sensor

available in the IDLE state. The default 0x7F value should then be written back before leaving the IDLE state. Other use of this register is for test only.

0x2C: TEST2 – Various test settings

Bit Field Name Reset R/W Description

7:0 TEST2[7:0] 152

(0x98)

R/W

The value to use in this register is given by the SmartRF software.

0x2D: TEST1 – Various test settings

Bit Field Name Reset R/W Description

7:0 TEST1[7:0] 49 (0x31) R/W

The value to use in this register is given by the SmartRF Studio software.

0x2E: TEST0 – Various test settings

Bit Field Name Reset R/W Description

7:0 TEST0[7:0] 11 (0x0B) R/W

The value to use in this register is given by the SmartRF Studio software.

Studio

27.2 Status register details 0x30 (0xF0): PARTNUM – Chip ID

Bit Field Name Reset R/W Description

7:0 PARTNUM[7:0] 130 (0x82) R Chip part number

0x31 (0xF1): VERSION – Chip ID

Bit Field Name Reset R/W Description

7:0 VERSION[7:0] 2 (0x02) R Chip version number.

PRELIMINARY Data Sheet (Rev.1.2) SWRS039A Page 46 of 54

0x35 (0xF5): MARCSTATE – Main Radio Control State Machine state

Bit Field Name Reset R/W Description

7:5 Reserved R0

4:0 MARC_STATE[4:0] R Main Radio Control FSM State

Value State name State (Figure 13, page 23)

0 (0x00) SLEEP SLEEP

1 (0x01) IDLE IDLE

2 (0x02) XOFF XOFF

3 (0x03) VCOON_MC MANCAL

4 (0x04) REGON_MC MANCAL

5 (0x05) MANCAL MANCAL

6 (0x06) VCOON FS_WAKEUP

7 (0x07) REGON FS_WAKEUP

8 (0x08) STARTCAL CALIBRATE

9 (0x09) BWBOOST SETTLING

10 (0x0A) FS_LOCK SETTLING

11 (0x0B) IFADCON SETTLING

12 (0x0C) ENDCAL CALIBRATE

13 (0x0D) NA NA

14 (0x0E) NA NA

15 (0x0F) NA NA

16 (0x10) NA NA

17 (0x11) NA NA

18 (0x12) FSTXON FSTXON

19 (0x13) TX TX

20 (0x14) TX_END TX

21 (0x15) NA NA

22 (0x16) TX_UNDERFLOW TX_UNDERFLOW

CC2550

0x38 (0xF8): PKTSTATUS – Current GDOx status

Bit Field Name Reset R/W Description

7:2 Reserved R0 Defined on the transceiver version

1 Reserved R0

GDO0

Current inverted value irrespective what

programmed to.

It is not recommended to check for PLL lock by reading

PKTSTATUS[0]

GDO0

value. Note: the reading gives the non-

IOCFG0.GDO0_INV

with

GDO0_CFG

PRELIMINARY Data Sheet (Rev.1.2) SWRS039A Page 47 of 54

= 0x0A.

0x39 (0xF9): VCO_VC_DAC – Current setting from PLL calibration module

Bit Field Name Reset R/W Description

7:0 VCO_VC_DAC[7:0] R Status register for test only.

0x3A (0xFA): TXBYTES – Underflow and number of bytes

Bit Field Name Reset R/W Description

7 TXFIFO_UNDERFLOW R

6:0 NUM_TXBYTES R Number of bytes in TX FIFO

CC2550

PRELIMINARY Data Sheet (Rev.1.2) SWRS039A Page 48 of 54

28 Package Description (QLP 16)

CC2550

All dimensions are in millimetres, angles in degrees. NOTE: The lead-free package only.

CC2550

is available in RoHS

Figure 21: Package dimensions drawing (the actual package has 16 pins)

Package

type

Min 0.75 0.005 0.55 3.90 3.65 3.90 3.65 0.45 0.190 0.23

QLP 16 (4x4) Typ. 0.85 0.025 0.65 4.00 3.75 2.30 4.00 3.75 2.30 0.55 0.28 0.65

Max 0.95 0.045 0.75 4.10 3.85 4.10 3.85 0.65 0.245 0.35

A A1 A2 D D1 D2 E E1 E2 L T b e

Table 27: Package dimensions

PRELIMINARY Data Sheet (Rev.1.2) SWRS039A Page 49 of 54

28.1 Recommended PCB layout for package (QLP 16)

CC2550

Figure 22: Recommended PCB layout for QLP 16 package

Note: The figure is an illustration only and not to scale. There are five 10 mil diameter via holes distributed symmetrically in the ground pad under the package. See also the CC2550EM reference design.

28.2 Package thermal properties

Thermal resistance

Air velocity [m/s] 0

Rth,j-a [K/W] 40.1

Table 28: Thermal properties of QLP 16 package

28.3 Soldering information

The recommendations for lead-free reflow in IPC/JEDEC J-STD-020C should be followed.

PRELIMINARY Data Sheet (Rev.1.2) SWRS039A Page 50 of 54

28.4 Tray specification

CC2550

can be delivered in standard QLP 4x4 mm shipping trays.

Tray Specification

Package Tray Width Tray Height Tray Length Units per Tray

QLP 16 125.9 mm 7.62 mm 322.6 mm 490

Table 29: Tray specification

28.5 Carrier tape and reel specification

Carrier tape and reel is in accordance with EIA Specification 481.

Tape and Reel Specification

Package Tape Width Component

Pitch

QLP 16 12 mm 8 mm 4 mm 13 inches 2500

Hole

Pitch

Diameter

Table 30: Carrier tape and reel specification

29 Ordering Information

Chipcon Part Number

CC2550-RTY1 CC2550RTK

CC2550-RTR1 CC2550RTKR

CC2500-CC2550DK CC2500-CC2550DK

CC2550EMK CC2550EMK

TI Part Number Description Minimum Order Quantity

CC2550

QLP16 RoHS Pb-free 490/tray

CC2550

QLP16 RoHS Pb-free 2500/T&R

CC2500_CC2550 CC2500

Evaluation Module Kit

Development Kit

Reel

Units per Reel

(MOQ)

490 (tray)

2500 (tape and reel)

Table 31: Ordering information

30 General Information

30.1 Document History

Revision Date Description/Changes

1.2 2006-06-28

1.1 2005-06-27 Updated TEST1 register default value. 26-27 MHz crystal range. Added matching

1.0 2005-01-24 First preliminary data sheet release.

Added figures to table on SPI interface timing requirements. Added information about SPI read. Updates to text and included new figure in section on arbitrary length configuration. Added information that RF frequencies at n/2·crystal frequency (n is an integer number) should not be used due to spurious signals at these frequencies . Updates to text and included new figures in section on power-on start-up sequence. Added information about how to check for PLL lock in section on VCO. Better explanation of some of the signals in table of GDO signal selection. Added section on wideband modulation not using spread spectrum under section on system considerations and guidelines. Added more detailed information on PO_TIMEOUT in register MCSM0. Changes to ordering information.

information. Added information about using a reference signal instead of a crystal.

Table 32: Document history

PRELIMINARY Data Sheet (Rev.1.2) SWRS039A Page 51 of 54

CC2550

30.2 Product Status Definitions

Data Sheet Identification Product Status Definition

Advance Information Planned or Under

Development

Preliminary Engineering Samples

and Pre-Production Prototypes

No Identification Noted Full Production This data sheet contains the final specifications.

Obsolete Not In Production This data sheet contains specifications on a product

Table 33: Product statu s definiti ons

This data sheet contains the design specifications for product development. Specifications may change in any manner without notice.

Chipcon reserves the right to make changes at any time without notice in order to improve design and supply the best possible product.

that has been discontinued by Chipcon. The data sheet is printed for reference information only.

PRELIMINARY Data Sheet (Rev.1.2) SWRS039A Page 52 of 54

CC2550

31 Address Information

Texas Instruments Norway AS Gaustadalléen 21 N-0349 Oslo NORWAY Tel: +47 22 95 85 44 Fax: +47 22 95 85 46 Web site: http://www.ti.com/lpw

32 TI Worldwide Technical Support Internet

TI Semiconductor Product Information Center Home Page: support.ti.com

TI Semiconductor KnowledgeBase Home Page: support.ti.com/sc/knowledgebase

Product Information Centers

Americas Phone: +1(972) 644-5580

Fax: +1(972) 927-6377 Internet/Email: support.ti.com/sc/pic/americas.htm

Europe, Middle East and Africa Phone:

Belgium (English) +32 (0) 27 45 54 32

Finland (English) +358 (0) 9 25173948

France +33 (0) 1 30 70 11 64

Germany +49 (0) 8161 80 33 11

Israel (English) 180 949 0107

Italy 800 79 11 37

Netherlands (English) +31 (0) 546 87 95 45

Russia +7 (4) 95 98 10 701

Spain +34 902 35 40 28

Sweden (English) +46 (0) 8587 555 22

United Kingdom +44 (0) 1604 66 33 99

Fax: +49 (0) 8161 80 2045 Internet: support.ti.com/sc/pic/euro.htm

Japan Fax International +81-3-3344-5317

Domestic 0120-81-0036 Internet/Email International support.ti.com/sc/pic/japan.htm

Domestic www.tij.co.jp/pic

PRELIMINARY Data Sheet (Rev.1.2) SWRS039A Page 53 of 54

Asia Phone International +886-2-23786800

Domestic Toll-Free Number

Australia 1-800-999-084

China 800-820-8682

Hong Kong 800-96-5941

India +91-80-51381665 (Toll)

Indonesia 001-803-8861-1006

Korea 080-551-2804

Malaysia 1-800-80-3973

New Zealand 0800-446-934

Philippines 1-800-765-7404

Singapore 800-886-1028

Taiwan 0800-006800

Thailand 001-800-886-0010

Fax +886-2-2378-6808 Email tiasia@ti.com or ti-china@ti.com Internet support.ti.com/sc/pic/asia.htm

CC2550

PRELIMINARY Data Sheet (Rev.1.2) SWRS039A Page 54 of 54

IMPORTANT NOTICE

Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment.

TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty . Except where mandated by government requirements, testing of all parameters of each product is not necessarily performed.

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TEXAS INSTRUMENTS CC2550 Technical data

Specifications and Main Features

Frequently Asked Questions

User Manual

Abbreviations

Current consumption

4.2 RF Transmit Section

4.4 Frequency Synthesizer Characteristics

4.5 Analog Temperature Sensor

4.7 Power On Reset

10 4-wire Serial Configuration and Data Interface

11 Microcontroller Interface and Pin Configuration

13 Packet Handling Hardware Support

15 Forward Error Correction with Interleaving

21 Output Power Programming

23 External RF Match

24 General Purpose / Test Output Control Pins

25 Asynchronous and Synchronous Serial Operation

28 Package Description (QLP 16)

Tray Specification