Texas Instruments CC253x, CC2540, CC2541 User Manual
CC253x System-on-Chip Solution for 2.4-GHz
IEEE 802.15.4 and ZigBee®Applications
A
CC2540/41 System-on-Chip Solution for 2.4GHz Bluetooth®low energy Applications
User's Guide
Literature Number: SWRU191F
April 2009–Revised April 2014
Contents
Preface....................................................................................................................................... 14
1 Introduction....................................................................................................................... 17
1.1 Overview..................................................................................................................... 18
1.1.1 CPU and Memory ................................................................................................. 21
1.1.2 Clocks and Power Management ................................................................................ 21
1.1.3 Peripherals ......................................................................................................... 21
1.1.4 Radio................................................................................................................ 23
1.2 Applications ................................................................................................................. 23
2 8051 CPU........................................................................................................................... 24
2.1 8051 CPU Introduction .................................................................................................... 25
2.2 Memory...................................................................................................................... 25
2.2.1 Memory Map....................................................................................................... 25
2.2.2 CPU Memory Space .............................................................................................. 27
2.2.3 Physical Memory .................................................................................................. 28
2.2.4 XDATA Memory Access.......................................................................................... 33
2.2.5 Memory Arbiter .................................................................................................... 33
2.3 CPU Registers.............................................................................................................. 34
2.3.1 Data Pointers ...................................................................................................... 34
2.3.2 Registers R0–R7 .................................................................................................. 35
2.3.3 Program Status Word............................................................................................. 35
2.3.4 Accumulator........................................................................................................ 36
2.3.5 B Register .......................................................................................................... 36
2.3.6 Stack Pointer....................................................................................................... 36
2.4 Instruction Set Summary .................................................................................................. 36
2.5 Interrupts .................................................................................................................... 40
2.5.1 Interrupt Masking.................................................................................................. 41
2.5.2 Interrupt Processing............................................................................................... 45
2.5.3 Interrupt Priority.................................................................................................... 47
3 Debug Interface.................................................................................................................. 50
3.1 Debug Mode ................................................................................................................ 51
3.2 Debug Communication .................................................................................................... 51
3.3 Debug Commands ......................................................................................................... 53
3.3.1 Debug Configuration.............................................................................................. 55
3.3.2 Debug Status ...................................................................................................... 55
3.3.3 Hardware Breakpoints ............................................................................................ 56
3.4 Flash Programming ........................................................................................................ 57
3.4.1 Lock Bits............................................................................................................ 57
3.5 Debug Interface and Power Modes...................................................................................... 57
3.6 Registers .................................................................................................................... 59
4 Power Management and Clocks ........................................................................................... 60
4.1 Power Management Introduction......................................................................................... 61
4.1.1 Active and Idle Modes............................................................................................ 62
4.1.2 PM1 ................................................................................................................. 62
4.1.3 PM2 ................................................................................................................. 62
2
Contents SWRU191F–April 2009–Revised April 2014
Copyright © 2009–2014, Texas Instruments Incorporated
Submit Documentation Feedback
www.ti.com
4.1.4 PM3 ................................................................................................................. 62
4.2 Power-Management Control.............................................................................................. 62
4.3 Power-Management Registers ........................................................................................... 63
4.4 Oscillators and Clocks ..................................................................................................... 66
4.4.1 Oscillators .......................................................................................................... 66
4.4.2 System Clock ...................................................................................................... 66
4.4.3 32-kHz Oscillators................................................................................................. 67
4.4.4 Oscillator and Clock Registers .................................................................................. 67
4.5 Timer Tick Generation ..................................................................................................... 69
4.6 Data Retention.............................................................................................................. 69
5 Reset ................................................................................................................................ 70
5.1 Power-On Reset and Brownout Detector ............................................................................... 71
5.2 Clock-Loss Detector ....................................................................................................... 71
6 Flash Controller ................................................................................................................. 72
6.1 Flash Memory Organization............................................................................................... 73
6.2 Flash Write .................................................................................................................. 73
6.2.1 Flash-Write Procedure............................................................................................ 73
6.2.2 Writing Multiple Times to a Word ............................................................................... 74
6.2.3 DMA Flash Write .................................................................................................. 74
6.2.4 CPU Flash Write................................................................................................... 75
6.3 Flash Page Erase .......................................................................................................... 75
6.3.1 Performing Flash Erase From Flash Memory ................................................................. 76
6.3.2 Different Flash Page Size on CC2533 ......................................................................... 76
6.4 Flash DMA Trigger ......................................................................................................... 76
6.5 Flash Controller Registers ................................................................................................ 76
7 I/O Ports............................................................................................................................ 78
7.1 Unused I/O Pins ............................................................................................................ 79
7.2 Low I/O Supply Voltage ................................................................................................... 79
7.3 General-Purpose I/O....................................................................................................... 79
7.4 General-Purpose I/O Interrupts........................................................................................... 79
7.5 General-Purpose I/O DMA ................................................................................................ 80
7.6 Peripheral I/O ............................................................................................................... 80
7.6.1 Timer 1.............................................................................................................. 81
7.6.2 Timer 3.............................................................................................................. 81
7.6.3 Timer 4.............................................................................................................. 82
7.6.4 USART 0 ........................................................................................................... 82
7.6.5 USART 1 ........................................................................................................... 82
7.6.6 ADC................................................................................................................. 83
7.6.7 Operational Amplifier and Analog Comparator................................................................ 83
7.7 Debug Interface............................................................................................................. 83
7.8 32-kHz XOSC Input ........................................................................................................ 83
7.9 Radio Test Output Signals................................................................................................ 84
7.10 Power-Down Signal MUX (PMUX)....................................................................................... 84
7.11 I/O Registers................................................................................................................ 84
8 DMA Controller .................................................................................................................. 92
8.1 DMA Operation ............................................................................................................. 93
8.2 DMA Configuration Parameters .......................................................................................... 95
8.2.1 Source Address.................................................................................................... 95
8.2.2 Destination Address............................................................................................... 95
8.2.3 Transfer Count..................................................................................................... 95
8.2.4 VLEN Setting....................................................................................................... 96
8.2.5 Trigger Event....................................................................................................... 96
SWRU191F–April 2009–Revised April 2014 Contents
Submit Documentation Feedback
Copyright © 2009–2014, Texas Instruments Incorporated
3
www.ti.com
8.2.6 Source and Destination Increment.............................................................................. 96
8.2.7 DMA Transfer Mode .............................................................................................. 97
8.2.8 DMA Priority........................................................................................................ 97
8.2.9 Byte or Word Transfers........................................................................................... 97
8.2.10 Interrupt Mask .................................................................................................... 97
8.2.11 Mode 8 Setting ................................................................................................... 97
8.3 DMA Configuration Setup ................................................................................................. 97
8.4 Stopping DMA Transfers .................................................................................................. 98
8.5 DMA Interrupts.............................................................................................................. 98
8.6 DMA Configuration-Data Structure....................................................................................... 98
8.7 DMA Memory Access...................................................................................................... 98
8.8 DMA Registers ............................................................................................................ 101
9 Timer 1 (16-Bit Timer)........................................................................................................ 103
9.1 16-Bit Counter............................................................................................................. 104
9.2 Timer 1 Operation ........................................................................................................ 104
9.3 Free-Running Mode ...................................................................................................... 104
9.4 Modulo Mode.............................................................................................................. 105
9.5 Up-and-Down Mode ...................................................................................................... 105
9.6 Channel-Mode Control ................................................................................................... 105
9.7 Input Capture Mode ...................................................................................................... 106
9.8 Output Compare Mode................................................................................................... 106
9.9 IR Signal Generation and Learning .................................................................................... 111
9.9.1 Introduction ....................................................................................................... 111
9.9.2 Modulated Codes ................................................................................................ 111
9.9.3 Non-Modulated Codes .......................................................................................... 112
9.9.4 Learning........................................................................................................... 113
9.9.5 Other Considerations............................................................................................ 113
9.10 Timer 1 Interrupts......................................................................................................... 113
9.11 Timer 1 DMA Triggers.................................................................................................... 113
9.12 Timer 1 Registers......................................................................................................... 114
9.13 Accessing Timer 1 Registers as Array ................................................................................ 119
10 Timer 3 and Timer 4 (8-Bit Timers)...................................................................................... 120
10.1 8-Bit Timer Counter....................................................................................................... 121
10.2 Timer 3 and Timer 4 Mode Control..................................................................................... 121
10.2.1 Free-Running Mode ............................................................................................ 121
10.2.2 Down Mode...................................................................................................... 121
10.2.3 Modulo Mode.................................................................................................... 121
10.2.4 Up-and-Down Mode ............................................................................................ 121
10.3 Channel Mode Control ................................................................................................... 121
10.4 Input Capture Mode ...................................................................................................... 122
10.5 Output Compare Mode................................................................................................... 122
10.6 Timer 3 and Timer 4 Interrupts.......................................................................................... 122
10.7 Timer 3 and Timer 4 DMA Triggers .................................................................................... 123
10.8 Timer 3 and Timer 4 Registers.......................................................................................... 123
11 Sleep Timer...................................................................................................................... 128
11.1 General..................................................................................................................... 129
11.2 Timer Compare ........................................................................................................... 129
11.3 Timer Capture............................................................................................................. 129
11.4 Sleep Timer Registers ................................................................................................... 130
12 ADC ................................................................................................................................ 132
12.1 ADC Introduction.......................................................................................................... 133
12.2 ADC Operation............................................................................................................ 133
4
Contents SWRU191F–April 2009–Revised April 2014
Copyright © 2009–2014, Texas Instruments Incorporated
Submit Documentation Feedback
www.ti.com
12.2.1 ADC Inputs ...................................................................................................... 133
12.2.2 ADC Conversion Sequences.................................................................................. 134
12.2.3 Single ADC Conversion........................................................................................ 134
12.2.4 ADC Operating Modes......................................................................................... 134
12.2.5 ADC Conversion Results ...................................................................................... 135
12.2.6 ADC Reference Voltage ....................................................................................... 135
12.2.7 ADC Conversion Timing ....................................................................................... 135
12.2.8 ADC Interrupts .................................................................................................. 135
12.2.9 ADC DMA Triggers............................................................................................. 135
12.2.10 ADC Registers................................................................................................. 136
13 Battery Monitor ................................................................................................................ 139
13.1 Functionality and Usage of the Battery Monitor ...................................................................... 140
13.2 Using the Battery Monitor for Temperature Monitoring.............................................................. 140
13.3 Battery Monitor Registers ............................................................................................... 141
14 Random-Number Generator ............................................................................................... 143
14.1 Introduction ................................................................................................................ 144
14.2 Random-Number-Generator Operation................................................................................ 144
14.2.1 Pseudorandom Sequence Generation....................................................................... 144
14.2.2 Seeding .......................................................................................................... 144
14.2.3 CRC16 ........................................................................................................... 144
14.3 Random-Number-Generator Registers ................................................................................ 145
15 AES Coprocessor ............................................................................................................. 146
15.1 AES Operation ............................................................................................................ 147
15.2 Key and IV ................................................................................................................. 147
15.3 Padding of Input Data.................................................................................................... 147
15.4 Interface to CPU .......................................................................................................... 147
15.5 Modes of Operation ...................................................................................................... 147
15.6 CBC-MAC.................................................................................................................. 147
15.7 CCM Mode................................................................................................................. 148
15.8 AES Interrupts............................................................................................................. 150
15.9 AES DMA Triggers ....................................................................................................... 150
15.10 AES Registers ............................................................................................................ 150
16 Watchdog Timer ............................................................................................................... 152
16.1 Watchdog Mode........................................................................................................... 153
16.2 Timer Mode................................................................................................................ 153
16.3 Watchdog Timer Register................................................................................................ 153
17 USART ............................................................................................................................ 155
17.1 UART Mode ............................................................................................................... 156
17.1.1 UART Transmit.................................................................................................. 156
17.1.2 UART Receive .................................................................................................. 156
17.1.3 UART Hardware Flow Control ................................................................................ 156
17.1.4 UART Character Format....................................................................................... 157
17.2 SPI Mode .................................................................................................................. 157
17.2.1 SPI Master Operation .......................................................................................... 157
17.2.2 SPI Slave Operation............................................................................................ 158
17.3 SSN Slave-Select Pin .................................................................................................... 158
17.4 Baud-Rate Generation ................................................................................................... 158
17.5 USART Flushing .......................................................................................................... 159
17.6 USART Interrupts......................................................................................................... 159
17.7 USART DMA Triggers.................................................................................................... 159
17.8 USART Registers......................................................................................................... 159
18 Operational Amplifier ........................................................................................................ 164
SWRU191F–April 2009–Revised April 2014 Contents
Submit Documentation Feedback
Copyright © 2009–2014, Texas Instruments Incorporated
5
www.ti.com
18.1 Description................................................................................................................. 165
18.2 Calibration ................................................................................................................. 165
18.3 Clock Source .............................................................................................................. 165
18.4 Registers................................................................................................................... 165
19 Analog Comparator........................................................................................................... 166
19.1 Description................................................................................................................. 167
19.2 Register .................................................................................................................... 167
20 I
2
C................................................................................................................................... 168
20.1 Operation .................................................................................................................. 169
20.1.1 I
20.1.2 I
20.1.3 I
20.1.4 I
20.1.5 I
2
C Initialization and Reset..................................................................................... 170
2
C Serial Data .................................................................................................. 170
2
C Addressing Modes ......................................................................................... 171
2
C Module Operating Modes ................................................................................. 171
2
C Clock Generation and Synchronization.................................................................. 177
20.1.6 Bus Error......................................................................................................... 178
2
C Interrupt...................................................................................................... 178
2
C Pins........................................................................................................... 178
20.2 I
20.1.7 I
20.1.8 I
2
C Registers............................................................................................................... 178
21 USB Controller ................................................................................................................. 181
21.1 USB Introduction.......................................................................................................... 182
21.2 USB Enable................................................................................................................ 182
21.3 48-MHz USB PLL......................................................................................................... 182
21.4 USB Interrupts............................................................................................................. 183
21.5 Endpoint 0 ................................................................................................................. 183
21.6 Endpoint-0 Interrupts ..................................................................................................... 183
21.6.1 Error Conditions................................................................................................. 184
21.6.2 SETUP Transactions (IDLE State) ........................................................................... 184
21.6.3 IN Transactions (TX State) .................................................................................... 184
21.6.4 OUT Transactions (RX State)................................................................................. 185
21.7 Endpoints 1–5............................................................................................................. 185
21.7.1 FIFO Management ............................................................................................. 185
21.7.2 Double Buffering ................................................................................................ 186
21.7.3 FIFO Access..................................................................................................... 187
21.7.4 Endpoint 1–5 Interrupts ........................................................................................ 187
21.7.5 Bulk or Interrupt IN Endpoint.................................................................................. 188
21.7.6 Isochronous IN Endpoint....................................................................................... 188
21.7.7 Bulk or Interrupt OUT Endpoint............................................................................... 188
21.7.8 Isochronous OUT Endpoint.................................................................................... 188
21.8 DMA ........................................................................................................................ 189
21.9 USB Reset................................................................................................................. 189
21.10 Suspend and Resume ................................................................................................... 189
21.11 Remote Wake-Up ........................................................................................................ 189
21.12 USB Registers ............................................................................................................ 190
22 Timer 2 (MAC Timer) ......................................................................................................... 197
22.1 Timer Operation........................................................................................................... 198
22.1.1 General........................................................................................................... 198
22.1.2 Up Counter ...................................................................................................... 198
22.1.3 Timer Overflow.................................................................................................. 198
22.1.4 Timer Delta Increment ......................................................................................... 198
22.1.5 Timer Compare ................................................................................................. 198
22.1.6 Overflow Count.................................................................................................. 198
22.1.7 Overflow-Count Update........................................................................................ 199
6
Contents SWRU191F–April 2009–Revised April 2014
Copyright © 2009–2014, Texas Instruments Incorporated
Submit Documentation Feedback
www.ti.com
22.1.8 Overflow-Count Overflow ...................................................................................... 199
22.1.9 Overflow-Count Compare...................................................................................... 199
22.1.10 Capture Input .................................................................................................. 199
22.1.11 Long Compare (CC2541 Only).............................................................................. 199
22.2 Interrupts................................................................................................................... 199
22.3 Event Outputs (DMA Trigger and Radio Events)..................................................................... 200
22.4 Timer Start-and-Stop Synchronization ................................................................................. 200
22.4.1 General........................................................................................................... 200
22.4.2 Timer Synchronous Stop ...................................................................................... 200
22.4.3 Timer Synchronous Start ...................................................................................... 201
22.5 Timer 2 Registers......................................................................................................... 202
23 CC253x Radio................................................................................................................... 208
23.1 RF Core .................................................................................................................... 209
23.1.1 Interrupts......................................................................................................... 209
23.1.2 Interrupt Registers.............................................................................................. 209
23.2 FIFO Access............................................................................................................... 213
23.3 DMA ........................................................................................................................ 213
23.4 Memory Map .............................................................................................................. 213
23.4.1 RXFIFO .......................................................................................................... 214
23.4.2 TXFIFO........................................................................................................... 214
23.4.3 Frame-Filtering and Source-Matching Memory Map....................................................... 214
23.5 Frequency and Channel Programming ................................................................................ 215
23.6 IEEE 802.15.4-2006 Modulation Format............................................................................... 215
23.7 IEEE 802.15.4-2006 Frame Format.................................................................................... 217
23.7.1 PHY Layer ....................................................................................................... 217
23.7.2 MAC Layer....................................................................................................... 217
23.8 Transmit Mode ............................................................................................................ 218
23.8.1 TX Control ....................................................................................................... 218
23.8.2 TX State Timing................................................................................................. 218
23.8.3 TXFIFO Access ................................................................................................. 218
23.8.4 Retransmission.................................................................................................. 219
23.8.5 Error Conditions................................................................................................. 219
23.8.6 TX Flow Diagram ............................................................................................... 219
23.8.7 Transmitted Frame Processing ............................................................................... 221
23.8.8 Synchronization Header ....................................................................................... 221
23.8.9 Frame-Length Field............................................................................................. 221
23.8.10 Frame Check Sequence ..................................................................................... 221
23.8.11 Interrupts ....................................................................................................... 222
23.8.12 Clear-Channel Assessment.................................................................................. 222
23.8.13 Output Power Programming................................................................................. 222
23.8.14 Tips and Tricks ................................................................................................ 222
23.9 Receive Mode ............................................................................................................ 222
23.9.1 RX Control....................................................................................................... 222
23.9.2 RX State Timing ................................................................................................ 223
23.9.3 Received-Frame Processing .................................................................................. 223
23.9.4 Synchronization Header and Frame-Length Fields ........................................................ 224
23.9.5 Frame Filtering .................................................................................................. 224
23.9.6 Source Address Matching ..................................................................................... 227
23.9.7 Frame-Check Sequence....................................................................................... 230
23.9.8 Acknowledgement Transmission ............................................................................. 230
23.10 RXFIFO Access........................................................................................................... 232
23.10.1 Using the FIFO and FIFOP .................................................................................. 232
23.10.2 Error Conditions ............................................................................................... 233
SWRU191F–April 2009–Revised April 2014 Contents
Submit Documentation Feedback
Copyright © 2009–2014, Texas Instruments Incorporated
7
www.ti.com
23.10.3 RSSI ............................................................................................................ 233
23.10.4 Link Quality Indication ........................................................................................ 234
23.11 Radio-Control State Machine ........................................................................................... 234
23.12 Random-Number Generation ........................................................................................... 236
23.13 Packet Sniffing and Radio Test Output Signals...................................................................... 237
23.14 Command Strobe Processor............................................................................................ 238
23.14.1 Instruction Memory............................................................................................ 238
23.14.2 Data Registers................................................................................................. 239
23.14.3 Program Execution............................................................................................ 239
23.14.4 Interrupt Requests ............................................................................................ 239
23.14.5 Random Number Instruction................................................................................. 239
23.14.6 Running CSP Programs...................................................................................... 239
23.14.7 Registers ....................................................................................................... 240
23.14.8 Instruction Set Summary..................................................................................... 241
23.14.9 Instruction Set Definition ..................................................................................... 243
23.15 Registers................................................................................................................... 255
23.15.1 Register Settings Update..................................................................................... 256
23.15.2 Register Access Modes ...................................................................................... 256
23.15.3 Register Descriptions ......................................................................................... 257
24 CC2540 and CC2541 Bluetooth low energy Radio .................................................................. 275
24.1 Registers................................................................................................................... 276
25 CC2541 Proprietary Mode Radio......................................................................................... 278
25.1 RF Core .................................................................................................................... 279
25.2 Interrupts................................................................................................................... 279
25.2.1 Interrupt Registers.............................................................................................. 279
25.3 RF Core Data Memory................................................................................................... 280
25.3.1 FIFOs............................................................................................................. 281
25.3.2 DMA .............................................................................................................. 284
25.3.3 RAM-Based Registers ......................................................................................... 285
25.3.4 Variables in RAM Page 5...................................................................................... 291
25.4 Bit-Stream Processor..................................................................................................... 291
25.4.1 Whitening ........................................................................................................ 291
25.4.2 CC2500-Compatible PN9 Whitening......................................................................... 292
25.4.3 CRC .............................................................................................................. 293
25.4.4 Coprocessor Mode ............................................................................................. 295
25.5 Frequency and Channel Programming ................................................................................ 296
25.6 Modulation Formats ...................................................................................................... 296
25.7 Receiver.................................................................................................................... 296
25.8 Packet Format............................................................................................................. 297
25.8.1 RX FIFO Packet Organization ................................................................................ 299
25.8.2 TX FIFO Packet Organization................................................................................. 300
25.8.3 TX Buffers for ACK Payload................................................................................... 300
25.9 Link Layer Engine......................................................................................................... 301
25.9.1 Command Register............................................................................................. 302
25.9.2 Radio Tasks ..................................................................................................... 302
25.9.3 RF Test Commands............................................................................................ 317
25.10 Random Number Generation ........................................................................................... 318
25.11 Packet Sniffing............................................................................................................ 319
25.12 Registers................................................................................................................... 320
25.12.1 Register Overview............................................................................................. 320
25.12.2 Register Settings Update..................................................................................... 321
25.12.3 SFR Register Descriptions................................................................................... 322
26 Voltage Regulator ............................................................................................................. 342
8
Contents SWRU191F–April 2009–Revised April 2014
Copyright © 2009–2014, Texas Instruments Incorporated
Submit Documentation Feedback
www.ti.com
27 Available Software ............................................................................................................ 343
27.1 SmartRF™ Software for Evaluation (www.ti.com/smartrfstudio) ................................................... 344
27.2 RemoTI™ Network Protocol (www.ti.com/remoti).................................................................... 344
27.3 SimpliciTI™ Network Protocol (www.ti.com/simpliciti) ............................................................... 345
27.4 TIMAC Software (www.ti.com/timac)................................................................................... 345
27.5 Z-Stack™ Software (www.ti.com/z-stack) ............................................................................. 346
27.6 BLE Stack Software ...................................................................................................... 346
A Abbreviations................................................................................................................... 347
B Additional Information....................................................................................................... 350
B.1 Texas Instruments Low-Power RF Web Site ......................................................................... 351
B.2 Low-Power RF Online Community ..................................................................................... 351
B.3 Texas Instruments Low-Power RF Developer Network.............................................................. 351
B.4 Low-Power RF eNewsletter ............................................................................................. 351
C References....................................................................................................................... 352
Revision History ........................................................................................................................ 353
SWRU191F–April 2009–Revised April 2014 Contents
Submit Documentation Feedback
Copyright © 2009–2014, Texas Instruments Incorporated
9
www.ti.com
List of Figures
1-1. CC253x Block Diagram.................................................................................................... 18
1-2. CC2540 Block Diagram ................................................................................................... 19
1-3. CC2541 Block Diagram ................................................................................................... 20
2-1. XDATA Memory Space (Showing SFR and DATA Mapping) ........................................................ 26
2-2. CODE Memory Space ..................................................................................................... 26
2-3. CODE Memory Space for Running Code From SRAM ............................................................... 26
2-4. Interrupt Overview.......................................................................................................... 43
3-1. External Debug Interface Timing......................................................................................... 51
3-2. Transmission of One Byte................................................................................................. 51
3-3. Typical Command Sequence—No Extra Wait for Response......................................................... 52
3-4. Typical Command Sequence. Wait for Response ..................................................................... 53
3-5. Burst Write Command (First 2 Bytes) ................................................................................... 55
4-1. Clock System Overview ................................................................................................... 65
6-1. Flash Write Using DMA.................................................................................................... 75
8-1. DMA Operation ............................................................................................................. 94
8-2. Variable Length (VLEN) Transfer Options .............................................................................. 96
9-1. Free-Running Mode ...................................................................................................... 104
9-2. Modulo Mode.............................................................................................................. 105
9-3. Up-and-Down Mode ...................................................................................................... 105
9-4. Output Compare Modes, Timer Free-Running Mode ................................................................ 108
9-5. Output Compare Modes, Timer Modulo Mode........................................................................ 109
9-6. Output Compare Modes, Timer Up-and-Down Mode................................................................ 110
9-7. Block Diagram of Timers in IR-Generation Mode .................................................................... 112
9-8. Modulated Waveform Example ......................................................................................... 112
9-9. IR Learning Board Diagram ............................................................................................. 113
11-1. Sleep Timer Capture (Example Using Rising Edge on P0_0)...................................................... 130
12-1. ADC Block Diagram ...................................................................................................... 133
14-1. Basic Structure of the Random-Number Generator.................................................................. 144
15-1. Message Authentication Phase Block B0 ............................................................................. 148
15-2. Authentication Flag Byte................................................................................................. 148
15-3. Message Encryption Phase Block...................................................................................... 149
15-4. Encryption Flag Byte ..................................................................................................... 149
19-1. Analog Comparator....................................................................................................... 167
20-1. Block Diagram of the I
20-2. I
20-3. I
2
C Bus Connection Diagram............................................................................................ 170
2
C Module Data Transfer................................................................................................ 170
20-4. Bit Transfer on I
20-5. I
20-6. I
2
C Module 7-Bit Addressing Format ................................................................................... 171
2
C Module Addressing Format With Repeated START Condition................................................. 171
20-7. Arbitration Procedure Between Two Master Transmitters........................................................... 177
20-8. Synchronization of Two I
21-1. USB Controller Block Diagram.......................................................................................... 182
21-2. IN and OUT FIFOs ....................................................................................................... 186
23-1. Modulation................................................................................................................. 216
23-2. I/Q Phases When Transmitting a Zero-Symbol Chip Sequence, t
23-3. Schematic View of the IEEE 802.15.4 Frame Format [1] ........................................................... 217
23-4. Format of the Frame Control Field (FCF) ............................................................................. 217
2
C Module ....................................................................................... 169
2
C Bus................................................................................................... 171
2
C Clock Generators During Arbitration .................................................. 177
= 0.5 μs ..................................... 216
C
10
List of Figures SWRU191F–April 2009–Revised April 2014
Copyright © 2009–2014, Texas Instruments Incorporated
Submit Documentation Feedback
www.ti.com
23-5. Frame Data Written to the TXFIFO..................................................................................... 219
23-6. TX Flow .................................................................................................................... 220
23-7. Single Transmitted Frame............................................................................................... 221
23-8. Transmitted Synchronization Header .................................................................................. 221
23-9. FCS Hardware Implementation......................................................................................... 222
23-10. Single Received Frame and Transmitted Acknowledgment Frame................................................ 223
23-11. SFD Signal Timing........................................................................................................ 224
23-12. Filtering Scenarios (Exceptions Generated During Reception)..................................................... 226
23-13. Matching Algorithm for Short and Extended Addresses............................................................. 228
23-14. Interrupts Generated by Source Address Matching.................................................................. 229
23-15. Data in RXFIFO for Different Settings ................................................................................. 230
23-16. Acknowledge Frame Format ............................................................................................ 230
23-17. Acknowledgment Timing................................................................................................. 231
23-18. Command Strobe Timing ................................................................................................ 231
23-19. Behavior of FIFO and FIFOP Signals.................................................................................. 233
23-20. Main FSM.................................................................................................................. 235
23-21. FFT of the Random Bytes ............................................................................................... 236
23-22. Histogram of 20 Million Bytes Generated With the RANDOM Instruction......................................... 236
23-23. Running a CSP Program ................................................................................................ 240
23-24. Example Hardware Structure for the R* Register Access Mode ................................................... 256
25-1. Mapping of Radio Memory to MCU XDATA Memory Space........................................................ 281
25-2. FIFO Pointers ............................................................................................................. 281
25-3. PN7 Whitening ............................................................................................................ 292
25-4. CC2500-Compatible Whitening ......................................................................................... 293
25-5. CRC Module............................................................................................................... 294
25-6. Air Interface Packet Format for Basic Mode .......................................................................... 297
25-7. Air Interface Packet Format for Auto Mode ........................................................................... 298
25-8. Bits of 9-Bit Header....................................................................................................... 298
25-9. Bits of 10-Bit Header ..................................................................................................... 298
25-10. Structure of Packets in the RX FIFO................................................................................... 299
25-11. Structure of Packets in the TX FIFO ................................................................................... 300
25-12. Timing of Packets in RX Tasks ......................................................................................... 316
25-13. Timing of Packets in TX Tasks.......................................................................................... 317
25-14. Complete Appended Packet............................................................................................. 319
SWRU191F–April 2009–Revised April 2014 List of Figures
Submit Documentation Feedback
Copyright © 2009–2014, Texas Instruments Incorporated
11
www.ti.com
List of Tables
0-1. CC253x Family Overview ................................................................................................. 15
0-2. Register Bit Conventions .................................................................................................. 16
2-1. SFR Overview .............................................................................................................. 29
2-2. Overview of XREG Registers............................................................................................. 32
2-3. Instruction Set Summary .................................................................................................. 37
2-4. Instructions That Affect Flag Settings ................................................................................... 40
2-5. Interrupts Overview ........................................................................................................ 41
2-6. Priority Level Setting....................................................................................................... 48
2-7. Interrupt Priority Groups................................................................................................... 48
2-8. Interrupt Polling Sequence................................................................................................ 49
3-1. Debug Commands ......................................................................................................... 53
3-2. Debug Configuration....................................................................................................... 55
3-3. Debug Status ............................................................................................................... 55
3-4. Relation Between PCON_IDLE and PM_ACTIVE.......................................................................... 56
3-5. Flash Lock-Protection Bit Structure Definition.......................................................................... 57
4-1. Power Modes ............................................................................................................... 61
6-1. Example Write Sequence ................................................................................................. 74
7-1. Peripheral I/O Pin Mapping ............................................................................................... 81
8-1. DMA Trigger Sources...................................................................................................... 98
8-2. DMA Configuration-Data Structure....................................................................................... 99
9-1. Initial Compare Output Values (Compare Mode)..................................................................... 107
9-2. Frequency Error Calculation for 38-kHz Carrier ...................................................................... 111
10-1. Initial Compare Output Values (Compare Mode)..................................................................... 122
13-1. Values Showing How Different Temperatures Relate to BATTMON_VOLTAGE for a Typical Device........ 140
13-2. Values for A and B (for a Typical Device) When Using the Battery monitor for Temperature Monitoring .... 141
17-1. Commonly Used Baud-Rate Settings for 32 MHz System Clock................................................... 158
20-1. Slave Transmitter Mode.................................................................................................. 172
20-2. Slave Receiver Mode..................................................................................................... 173
20-3. Master Transmitter Mode................................................................................................ 175
20-4. Master Receiver Mode................................................................................................... 176
20-5. Miscellaneous States..................................................................................................... 178
20-6. Clock Rates Defined at 32 MHz ........................................................................................ 179
21-1. USB Interrupt Flags Interrupt-Enable Mask Registers............................................................... 183
21-2. FIFO Sizes for EP 1–5 ................................................................................................... 186
22-1. Internal Registers ......................................................................................................... 203
23-1. Frame Filtering and Source Matching Memory Map ................................................................. 214
23-2. IEEE 802.15.4-2006 Symbol-to-Chip Mapping ....................................................................... 216
23-3. FSM State Mapping ...................................................................................................... 236
23-4. Instruction Set Summary................................................................................................. 242
23-5. Register Overview ........................................................................................................ 255
23-6. Registers That Require Update From Their Default Value.......................................................... 256
23-7. Register-Bit Access Modes.............................................................................................. 256
25-1. Radio RAM Pages........................................................................................................ 280
25-2. Commands to FIFO via RFST Register ............................................................................... 283
25-3. Access to FIFO Registers ............................................................................................... 283
25-4. RAM-Based Registers.................................................................................................... 285
25-5. Address Structure for Auto Mode....................................................................................... 289
12
List of Tables SWRU191F–April 2009–Revised April 2014
Copyright © 2009–2014, Texas Instruments Incorporated
Submit Documentation Feedback
www.ti.com
25-6. Address Structure for Basic Mode...................................................................................... 290
25-7. RAM-Based Registers in RAM Page 5 ................................................................................ 291
25-8. Register Settings for Different CRCs................................................................................... 294
25-9. Register Settings for Some Commonly Used CRCs, Assuming Initialization With All 1s....................... 295
25-10. Supported Modulation Formats, Data Rates, and Deviations....................................................... 296
25-11. Segments for Holding ACK Payload for Each Address Entry....................................................... 300
25-12. Commands From MCU to LL Engine via RFST Register ........................................................... 302
25-13. Timer 2 Capture Settings ................................................................................................ 304
25-14. End-of-Task Causes...................................................................................................... 304
25-15. Recommended RAM Register Settings for Start Tone .............................................................. 306
25-16. Interrupt and Counter Operation for Received Messages........................................................... 307
25-17. Interrupt and Counter Operation for Received Messages........................................................... 308
25-18. End-of-Receive Tasks.................................................................................................... 310
25-19. Interrupt and Counter Operation for Received ACK Packets....................................................... 312
25-20. End-of-Transmit Tasks................................................................................................... 313
25-21. Additional Reasons for End-of-Transmit on Clear-Channel Tasks................................................. 315
25-22. Packet-Sniffer Modes of Operation..................................................................................... 319
25-23. XREG Register Overview................................................................................................ 320
25-24. Registers That Should Be Updated From Their Default Value, Bit Rates 1 Mbps and Lower ................. 321
25-25. Registers That Should Be Updated From Their Default Value, Bit Rate 2 Mbps ................................ 321
SWRU191F–April 2009–Revised April 2014 List of Tables
Submit Documentation Feedback
Copyright © 2009–2014, Texas Instruments Incorporated
13
About This Manual
The CC2540 and CC2541 are cost-effective, low-power, and true system-on-chip (SoC) solutions for
Bluetooth low energy applications. They enable robust BLE master or slave nodes to be built with very low
total bill-of-material costs. The CC2540 and CC2541 combine the excellent performance of a leading RF
transceiver with an industry-standard enhanced 8051 MCU, in-system programmable flash memory, 8-KB
RAM, and many other powerful supporting features and peripherals. The CC2540 and CC2541 are suited
for systems where very low power consumption is required. Very low-power sleep modes are available.
Short transition times between operating modes further enable low power consumption.
The CC2540 comes in two different versions: CC2540F128 and CC2540F256, with 128 KB and 256 KB of
flash memory, respectively.
The CC2541 comes in two different versions: CC2541F128 and CC2541F256, with 128 KB and 256 KB of
flash memory, respectively.
The CC2541F128/F256 comes in two different versions: CC2541F128/F256, with 128 and 256 KB of flash
memory, respectively.
Combined with the Bluetooth low-energy protocol stack from Texas Instruments, the
CC2540F128/CC2540F256 and CC2541F128/CC2541F256 constitute the market’s most comprehensive
single-mode Bluetooth low energy solution.
The CC253x System-on-Chip solution for 2.4 GHz is suitable for a wide range of applications. These can
easily be built on top of the IEEE 802.15.4 based standard protocols (RemoTI™ network protocol, TIMAC
software, and Z-Stack™ software for ZigBee®compliant solutions) or on top of the proprietary SimpliciTI™
network protocol. The usage is, however, not limited to these protocols alone. The CC253x family is, for
example, also suitable for 6LoWPAN and Wireless HART implementations.
Each chapter of this manual describes details of a module or peripheral; however, not all features are
present on all devices. To see the differences regarding features, see Table 0-1 in the Devices section.
For detailed technical numbers, such as power consumption and RF performance, see the device-specific
data sheet (Appendix C).
Preface
SWRU191F–April 2009–Revised April 2014
Read This First
Related Documentation and Software From Texas Instruments
Related documentation (for example, the CC2530 data sheet http://www-s.ti.com/sc/techlit/swrs081 and
CC2540 data sheet http://www-s.ti.com/sc/techlit/swrs084) can be found in Appendix C.
For more information regarding software that can be used with the CC253x, CC2540, or CC2541 Systemon-Chip solution (for example, SmartRF™ software for radio performance and functionality evaluation),
see Chapter 27, which also contains more information regarding the RemoTI network protocol, the
SimpliciTI network protocol, the TIMAC software, the Z-Stack software, and the BLE stack software.
SmartRF, RemoTI, SimpliciTI, Z-Stack are trademarks of Texas Instruments.
Bluetooth is a registered trademark of Bluetooth SIG, Inc.
Microsoft, Windows are trademarks of Microsoft Corporation.
ZigBee is a registered trademark of ZigBee Alliance.
14
Read This First SWRU191F–April 2009–Revised April 2014
Copyright © 2009–2014, Texas Instruments Incorporated
Submit Documentation Feedback
www.ti.com
FCC Warning
This equipment generates, uses, and can radiate radio frequency energy and has not been tested for
compliance with the limits of computing devices pursuant to subpart J of part 15 of FCC rules, which are
designed to provide reasonable protection against radio frequency interference. Operation of this
equipment in other environments may cause interference with radio communications, in which case the
user at his own expense will be required to take whatever measures may be required to correct this
interference.
If You Need Assistance
All technical support is channeled through the TI Product Information Centers (PIC) - www.ti.com/support.
To send an E-mail request, please enter your contact information, along with your request at the following
link – PIC request form.
Also visit the Low Power RF, ZigBee, and Bluetooth low energy sections of the TI E2E Community
(www.ti.com/lprf-forum), where you can easily get in touch with other CC253x, CC2540, and CC2541
users and find FAQs, Design Notes, Application Notes, Videos, and so forth.
Glossary
Abbreviations used in this user guide can be found in Appendix A.
Devices
The CC253x System-on-Chip solution family consists of several devices. The following table provides a
device overview and points out the differences regarding memory sizes and peripherals. For a complete
feature list of any of the devices, see the corresponding data sheet (Appendix C).
FCC Warning
Table 0-1. CC253x Family Overview
Feature
FLASH_SIZE 128 KB, 256 KB 32 KB, 64 KB, 96 KB 128 KB, 256 KB
SRAM_SIZE 8 KB, 8 KB 4 KB, 4 KB, 6 KB 8 KB 8 KB
USB Not included Included Not included Included Not included
ADC Included Included Not included Included Included
Battery monitor Not included Not included Included Not included Not included
I2C Not included Not included Included Not included Included
Operational
amplifier
Analog comparator Included Included Not included Included Included
CC2530F32, -F64, CC2531F128, CC2533F32, CC2540F128, CC2541F128,
-F128/, -F256 CC2531F256 -F64, -F96 -F256 -F256
32 KB, 64 KB, 128 KB,
128 KB, 256 KB 256 KB
8 KB, 8 KB, 8 KB,
8 KB
Included Included Not included Included Not included
Legend:
FLASH_SIZE – The size of the flash
SRAM_SIZE – The size of the SRAM
SWRU191F–April 2009–Revised April 2014 Read This First
Submit Documentation Feedback
Copyright © 2009–2014, Texas Instruments Incorporated
15
Register Conventions
Register Conventions
Each SFR and XREG register is described in a separate table, where each table title contains the
following information in the format indicated:
For SFR registers: REGISTER NAME (SFR address) – register description
For XREG registers: REGISTER NAME (XDATA address) – register description
Each table has five columns to describe the different register fields as described in the following:
Column 1 – Bit: Denotes which bits of the register are described and addressed in the specific row
Column 2 – Name: Specific name of the register field
Column 3 – Reset: Reset or initial value of the register field
Column 4 – R/W: Key indicating the accessibility of the bits in the field (see Table 0-2 for more details)
Column 5 – Description: More details about the register field, and often a description of the functions of
the different values
In the register descriptions, each register field is shown with a symbol (R/W) indicating the access mode of
the register field. The register values are always given in binary notation unless prefixed by 0x, which
indicates hexadecimal notation.
www.ti.com
Table 0-2. Register Bit Conventions
SYMBOL ACCESS MODE
R/W Read and write
R Read-only
R0 Read as 0
R1 Read as 1
W Write-only
W0 Write as 0
W1 Write as 1
H0 Hardware clear
H1 Hardware set
16
Read This First SWRU191F–April 2009–Revised April 2014
Copyright © 2009–2014, Texas Instruments Incorporated
Submit Documentation Feedback
Chapter 1
SWRU191F–April 2009–Revised April 2014
Introduction
As mentioned in the preface, the CC253x, CC2540, and CC2541 device family provides solutions for a
wide range of applications. In order to help the user to develop these applications, this user's guide
focuses on the usage of the different building blocks of the CC253x, CC2540, and CC2541 device family.
For detailed device descriptions, complete feature lists, and performance numbers, see the device-specific
data sheet (Appendix C).
In order to provide easy access to relevant information, the following subsections guide the reader to the
different chapters in this guide.
Topic ........................................................................................................................... Page
1.1 Overview........................................................................................................... 18
1.2 Applications ...................................................................................................... 23
SWRU191F–April 2009–Revised April 2014 Introduction
Submit Documentation Feedback
Copyright © 2009–2014, Texas Instruments Incorporated
17
RESET
WATCHDOG
TIMER
IRQ CTRL
CC2530/CC2531
FLASH CTRL
DEBUG
INTERFACE
CLOCK MUX
and
CALIBRATION
DMA
8051 CPU
CORE
32-MHz
CRYSTAL OSC
32.768-kHz
CRYSTAL OSC
HIGH-
SPEED
RC-OSC
USART 0
USART 1
TIMER 1 (16-Bit)
TIMER 3 (8-Bit)
TIMER 4 (8-Bit)
TIMER 2
(IEEE 802.15.4 MAC TIMER)
32/64/128/256-KB
FLASH
8-KB SRAM
RESET_N
XOSC_Q2
XOSC_Q1
P2_4
P1_7
P0_7
P2_3
P1_6
P0_6
P2_2
P1_5
P0_5
P1_2
P0_2
P2_1
P1_4
P0_4
P1_1
P0_1
P2_0
P1_3
P0_3
P1_0
P0_0
MODULATOR
DEMODULATOR
AND AGC
RECEIVE TRANSMIT
FREQUENCY
SYNTHESIZER
SYNTH
RF_P RF_N
B0301-03
RADIO DATA INTERFACE
COMMAND STROBE PROCESSOR
RADIO REGISTERS
FIFO and FRAME CONTROL
SFR Bus
SFR Bus
12-BIT -
ADC
D S
AES
ENCRYPTION
AND
DECRYPTION
MEMORY
ARBITER
SFR
IRAM
XRAM
PDATA
32-kHz
RC-OSC
I/O CONTROLLER
DIGITAL
ANALOG
MIXED
POWER MANAGEMENT CONTROLLER
ON-CHIP VOLTAGE
REGULATOR
POWER-ON RESET
BROWNOUT
VDD (2 V–3.6 V)
DCOUPL
SLEEP TIMER
BATTERY MONITOR (CC2533 ONLY)
USB
USB
PHY
1-KB
FIFO SRAM
DP
DM
CC2531
OP-AMP
ANALOG COMPARATOR
Overview
1.1 Overview
The block diagrams in Figure 1-1, Figure 1-2, and Figure 1-3 show the different building blocks of the
CC253x and, CC2540, and CC2541 devices. Not all features and functions of all modules or peripherals
are present on all devices of the CC253x, CC2540, and CC2541; hence, see the device-specific data
sheet for a device-specific block diagram.
www.ti.com
18
Introduction SWRU191F–April 2009–Revised April 2014
Figure 1-1. CC253x Block Diagram
Copyright © 2009–2014, Texas Instruments Incorporated
Submit Documentation Feedback
RESET
WATCHDOG
TIMER
IRQ CTRL
FLASH CTRL
DEBUG
INTERFACE
CLOCK MUX
and
CALIBRATION
DMA
8051 CPU
CORE
32-MHz
CRYSTAL OSC
OP-AMP
32.768-kHz
CRYSTAL OSC
HIGH-
SPEED
RC-OSC
POWER MANAGEMENT CONTROLLER
USART 0
USART 1
TIMER 1 (16-Bit)
TIMER 3 (8-Bit)
TIMER 4 (8-Bit)
TIMER 2
(BLE LL TIMER)
FLASH
FIFOCTRL
1 KB SRAM
ON-CHIP VOLTAGE
REGULATOR
POWER-ON RESET
BROWN OUT
VDD (2 V–3.6 V)
DCOUPL
RESET_N
XOSC_Q2
XOSC_Q1
P2_4
P1_7
P0_7
P2_3
P1_6
P0_6
P2_2
P1_5
P0_5
P1_2
P0_2
P2_1
P1_4
P0_4
P1_1
P0_1
P2_0
P1_3
P0_3
P1_0
P0_0
MODULATOR
DEMODULATOR
RECEIVE
TRANSMIT
FREQUENCY
SYNTHESIZER
SYNTH
RF_P
RF_N
B0301a-055
RADIO REGISTERS
SFR Bus
SFR Bus
DS
ADC
AUDIO/DC
AES
ENCRYPTION
AND
DECRYPTION
MEMORY
ARBITRATOR
FLASH
UNIFIED
SFR
IRAM
XRAM
PDATA
SLEEP TIMER
32-kHz
RC-OSC
I/O CONTROLLER
DIGITAL
ANALOG
MIXED
ANALOG COMPARATOR
Radio Arbiter
Link Layer Engine
USB
USB_N
USB_P
USB
PHY
www.ti.com
Overview
The modules can be roughly divided into one of three categories: CPU and memory related modules;
Figure 1-2. CC2540 Block Diagram
modules related to peripherals, clocks, and power management; and radio-related modules.
SWRU191F–April 2009–Revised April 2014 Introduction
Submit Documentation Feedback
Copyright © 2009–2014, Texas Instruments Incorporated
19
SFR bus SFR bus
MEMORY
ARBITRATOR
8051 CPU
CORE
DMA
FLASH
SRAM
FLASH CTRL
DEBUG
INTERFACE
RESET
RESET_N
P2_4
P2_3
P2_2
P2_1
P2_0
P1_4
P1_3
P1_2
P1_1
P1_0
P1_7
P1_6
P1_5
P0_4
P0_3
P0_2
P0_1
P0_0
P0_7
P0_6
P0_5
32.768-kHz
CRYSTAL OSC
32-MHZ
CRYSTAL OSC
HIGH SPEED
RC-OSC
32-kHz
RC-OSC
CLOCK MUX and
CALIBRATION
RAM
USART 0
USART 1
TIMER 1 (16-Bit)
TIMER 3 (8-bit)
TIMER 2
(BLE LL TIMER)
TIMER 4 (8-bit)
AES
ENCRYPTION
and
DECRYPTION
WATCHDOG TIMER
IRQ
CTRL
FLASH
UNIFIED
RF_P RF_N
SYNTH
MODULATOR
POWER-ON RESET
BROWN OUT
RADIO
REGISTERS
POWER MGT. CONTROLLER
SLEEP TIMER
PDATA
XRAM
IRAM
SFR
XOSC_Q2
XOSC_Q1
DS ADC
AUDIO / DC
DIGITAL
ANALOG
MIXED
VDD (2 V–3.6 V)
DCOUPL
ON-CHIP VOLTAGE
REGULATOR
Link Layer Engine
FREQUENCY
SYNTHESIZER
I2C
DEMODULATOR
RECEIVE TRANSMIT
OP-
ANALOG COMPARATOR
I/O CONTROLLER
1-KB SRAM
Radio Arbiter
FIFOCTRL
SDA
SCL
Overview
www.ti.com
20
Submit Documentation Feedback
Introduction SWRU191F–April 2009–Revised April 2014
Figure 1-3. CC2541 Block Diagram
Copyright © 2009–2014, Texas Instruments Incorporated
www.ti.com
1.1.1 CPU and Memory
The 8051 CPU core is a single-cycle 8051-compatible core. It has three different memory access buses
(SFR, DATA, and CODE/XDATA) with single-cycle access to SFR, DATA, and the main SRAM. It also
includes a debug interface and an 18-input extended interrupt unit. The detailed functionality of the CPU
and the memory is addressed in Chapter 2.
The interrupt controller services a total of 18 interrupt sources, divided into six interrupt groups, each of
which is associated with one of four interrupt priorities. Any interrupt service request is serviced also when
the device is in idle mode by going back to active mode. Some interrupts can also wake up the device
from sleep mode (when in sleep mode, the device is in one of the three low-power modes PM1, PM2, or
PM3); see Chapter 4 for more details.
The memory arbiter is at the heart of the system, as it connects the CPU and DMA controller with the
physical memories and all peripherals through the SFR bus. The memory arbiter has four memory access
points, access of which can map to one of three physical memories: SRAM, flash memory, and
XREG/SFR registers. The memory arbiter is responsible for performing arbitration and sequencing
between simultaneous memory accesses to the same physical memory.
The 4-, 6-, or 8-KB SRAM maps to the DATA memory space and to parts of the XDATA memory spaces.
The SRAM is an ultralow-power SRAM that retains its contents in all power modes. This is an important
feature for low-power applications.
The 32-, 64-, 96-, 128-, or 256-KB flash block provides in-circuit programmable non-volatile program
memory for the device, and maps into the CODE and XDATA memory spaces. In addition to holding
program code and constants, the non-volatile memory allows the application to save data that must be
preserved such that it is available after restarting the device. Using this feature one can, for example, use
saved network-specific data to avoid the need for a full start-up and network find-and-join process.
Overview
1.1.2 Clocks and Power Management
The digital core and peripherals are powered by a 1.8-V low-dropout voltage regulator (Chapter 26).
Additionally, the CC253x, CC2540, and CC2541 contain a power-management functionality that allows the
use of different low-power modes (PM1, PM2, and PM3) for low-power applications with a long battery life
(see Chapter 4 for more details). Five different reset sources exist to reset the device; see Chapter 5 for
more details.
1.1.3 Peripherals
The CC253x, CC2540, and CC2541 include many different peripherals that allow the application designer
to develop advanced applications. Not all peripherals are present on all devices. See Table 0-1 for a listing
of which peripherals are present on each device.
The debug interface (Chapter 3) implements a proprietary two-wire serial interface that is used for incircuit debugging. Through this debug interface, it is possible to perform an erasure of the entire flash
memory, control which oscillators are enabled, stop and start execution of the user program, execute
supplied instructions on the 8051 core, set code breakpoints, and single-step through instructions in the
code. Using these techniques, it is possible to perform in-circuit debugging and external flash
programming elegantly.
The device contains flash memory for storage of program code. The flash memory is programmable from
the user software and through the debug interface (as mentioned previously). The flash controller
(Chapter 6) handles writing and erasing the embedded flash memory. The flash controller allows pagewise erasure and 4-bytewise programming.
The I/O controller (Chapter 7) is responsible for all general-purpose I/O pins. The CPU can configure
whether peripheral modules control certain pins or whether they are under software control, and if so,
whether each pin is configured as an input or output and if a pullup or pulldown resistor in the pad is
connected. CPU interrupts can be enabled on each pin individually. Each peripheral that connects to the
I/O pins can choose between two different I/O pin locations to ensure flexibility in various applications.
SWRU191F–April 2009–Revised April 2014 Introduction
Submit Documentation Feedback
Copyright © 2009–2014, Texas Instruments Incorporated
21
Overview
www.ti.com
A versatile five-channel DMA controller (Chapter 8) is available in the system, accesses memory using
the XDATA memory space, and thus has access to all physical memories. Each channel (trigger, priority,
transfer mode, addressing mode, source and destination pointers, and transfer count) is configured with
DMA descriptors anywhere in memory. Many of the hardware peripherals (AES core, flash controller,
USARTs, timers, ADC interface) achieve highly efficient operation by using the DMA controller for data
transfers between SFR or XREG addresses and flash or SRAM.
Timer 1 (Chapter 9) is a 16-bit timer with timer, counter, and PWM functionality. Timer 1 has a
programmable prescaler, a 16-bit period value, and five individually programmable counter or capture
channels, each with a 16-bit compare value. Each of the counter or capture channels can be used as a
PWM output or to capture the timing of edges on input signals. Timer 1 can also be configured in IR
generation mode, where it counts Timer 3 periods and the output is ANDed with the output of Timer 3 to
generate modulated consumer IR signals with minimal CPU interaction (see Section 9.9).
Timer 2 (MAC Timer) (Chapter 22) is specially designed for supporting an IEEE 802.15.4 MAC or other
time-slotted protocol in software. The timer has a configurable timer period and a 24-bit overflow counter
that can be used to keep track of the number of periods that have transpired. A 40-bit capture register is
also used to record the exact time at which a start-of-frame delimiter is received or transmitted, or the
exact time at which transmission ends, as well as two 16-bit output compare registers and two 24-bit
overflow compare registers that can send various command strobes (start RX, start TX, etc.) at specific
times to the radio modules.
Timer 3 and Timer 4 (Chapter 10) are 8-bit timers with timer, counter, and PWM functionality. They have
a programmable prescaler, an 8-bit period value, and one programmable counter channel with an 8-bit
compare value. Each of the counter channels can be used as a PWM output.
The Sleep Timer (Chapter 11) is an ultralow-power timer that counts 32-kHz crystal oscillator or 32-kHz
RC oscillator periods. The Sleep Timer runs continuously in all operating modes except power mode 3
(PM3). Typical applications of this timer are as a real-time counter or as a wake-up timer for coming out of
power mode 1 (PM1) or power mode 2 (PM2).
The ADC (Chapter 12) supports 7 bits (30-kHz bandwidth) to 12 bits (4-kHz bandwidth) of resolution. DC
and audio conversions with up to eight input channels (Port 0) are possible. The inputs can be selected as
single-ended or differential. The reference voltage can be internal, AVDD, or a single-ended or differential
external signal. The ADC also has a temperature-sensor input channel. The ADC can automate the
process of periodic sampling or conversion over a sequence of channels.
The battery monitor (Chapter 13) (CC2533 only) enables simple voltage monitoring in devices that do
not include an ADC. It is designed such that it is accurate in the voltage areas around 2 V, with lower
resolution at higher voltages.
The random-number generator (Chapter 14) uses a 16-bit LFSR to generate pseudorandom numbers,
which can be read by the CPU or used directly by the command strobe processor. The random-number
generator can be seeded with random data from noise in the radio ADC.
The AES coprocessor (Chapter 15) allows the user to encrypt and decrypt data using the AES algorithm
with 128-bit keys. The core is able to support the security operations required by IEEE 802.15.4 MAC
security, the ZigBee network layer, and the application layer.
A built-in Watchdog Timer (Chapter 16) allows the device to reset itself in case the firmware hangs.
When enabled by software, the Watchdog Timer must be cleared periodically; otherwise, it resets the
device when it times out. It can alternatively be configured for use as a general 32-kHz timer.
USART 0 and USART 1 (Chapter 18) are each configurable as either a SPI master or slave or as a
UART. They provide double buffering on both RX and TX and hardware flow control, and are thus well
suited to high-throughput full-duplex applications. Each has its own high-precision baud-rate generator,
thus leaving the ordinary timers free for other uses.
The I2C module (Chapter 20) (CC2533 and CC2541) provides a digital peripheral connection with two pins
and supports both master and slave operation.
The USB 2.0 controller (Chapter 21) (CC2531 and CC2540) operates at Full-Speed, 12 Mbps transfer
rate. The controller has five bidirectional endpoints in addition to control endpoint 0. The endpoints support
bulk, Interrupt, and Isochronous operation for implementation of a wide range of applications. The 1024
bytes of dedicated, flexible FIFO memory combined with DMA access ensures that a minimum of CPU
involvement is needed for USB communication.
22
Introduction SWRU191F–April 2009–Revised April 2014
Copyright © 2009–2014, Texas Instruments Incorporated
Submit Documentation Feedback
www.ti.com
The operational amplifier (Chapter 18) (CC2530, CC2531, and CC2540) is intended to provide front-end
buffering and gain for the ADC. Both the inputs as well as the output are available on pins, so the
feedback network is fully customizable. A chopper-stabilized mode is available for applications that need
good accuracy with high gain.
The ultralow-power analog comparator (Chapter 19) (CC2530, CC2531, CC2540, and CC2541) enables
applications to wake up from PM2 or PM3 based on an analog signal. Both inputs are brought out to pins;
the reference voltage must be provided externally. The comparator output is mapped into the digital I/O
port and can be treated by the MCU as a regular digital input.
1.1.4 Radio
The CC2540 and CC2541 provide a Bluetooth low energy-compliant radio transceiver. The RF core which
controls the analog and digital radio modules is only indirectly accessible through API commands to the
BLE stack. More details about the CC2540 or CC2541 BLE radio can be found in Chapter 24. The
CC2541 can also be run in proprietary modes; more details can be found in Chapter 25.
The CC253x device family provides an IEEE 802.15.4-compliant radio transceiver. The RF core
controls the analog radio modules. In addition, it provides an interface between the MCU and the radio
which makes it possible to issue commands, read status, and automate and sequence radio events. The
radio also includes a packet-filtering and address-recognition module. More details about the CC253x
radio can be found in Chapter 23.
1.2 Applications
As shown in the overview (Section 1.1), this user's guide focuses on the functionality of the different
modules that are available to build different types of applications based on the CC253x,CC2540, and
CC2541 device family. When looking at the complete application development process, additional
information is useful. However, as this information and help is not device-specific (that is, not unique for
the CC253x, CC2540, and 41 device family), see the additional information sources in the following
paragraphs.
The first step is to set up the development environment (hardware, tools, and so forth) by purchasing a
development kit (see the device-specific product Web site to find links to the relevant development kits).
The development kits come with an out-of-the-box demonstration and information on how to set up the
development environment; install required drivers (done easily by installing the SmartRF software,
Section 27.1), set up the compiler tool chain, and so forth. As soon as one has installed the development
environment, one is ready to start the application development.
The easiest way to write the application software is to base the application on one of the available
standard protocols (RemoTI network protocol, Section 27.2; TIMAC software, Section 27.4; Z-Stack
software for ZigBee-compliant solutions, Section 27.5); BLE stack software for Bluetooth low energycompliant solutions Section 27.6; or the proprietary SimpliciTI network protocol, Section 27.3. They all
come with several sample applications.
For the hardware layout design of the user-specific hardware, the designer can find reference designs on
the different product pages (Section B.1). By copying these designs, the designer achieves optimal
performance. The developed hardware can then be tested easily using the SmartRF Studio software
(Section 27.1).
In case the final system should not have the expected performance, it is recommended to try out the
developed software on the development kit hardware and see how it works there. To check the userspecific hardware, it is a good first step to use SmartRF Studio software to compare the development kit
performance versus the user-specific hardware using the same settings.
The user can also find additional information and help by joining the Low-Power RF Online Community
(Section B.2) and by subscribing to the Low-Power RF eNewsletter (Section B.4).
To contact a third-party to help with development or to use modules, check out the Texas Instruments
Low-Power RF Developer Network (Section B.3).
Overview
SWRU191F–April 2009–Revised April 2014 Introduction
Submit Documentation Feedback
Copyright © 2009–2014, Texas Instruments Incorporated
23
Chapter 2
SWRU191F–April 2009–Revised April 2014
8051 CPU
The System-on-Chip solution is based on an enhanced 8051 core. More details regarding the core,
memory map, instruction set, and interrupts are described in the following subsections.
Topic ........................................................................................................................... Page
2.1 8051 CPU Introduction........................................................................................ 25
2.2 Memory............................................................................................................. 25
2.3 CPU Registers ................................................................................................... 34
2.4 Instruction Set Summary..................................................................................... 36
2.5 Interrupts .......................................................................................................... 40
24
8051 CPU SWRU191F–April 2009–Revised April 2014
Copyright © 2009–2014, Texas Instruments Incorporated
Submit Documentation Feedback
www.ti.com
2.1 8051 CPU Introduction
The enhanced 8051 core uses the standard 8051 instruction set. Instructions execute faster than the
standard 8051 due to the following:
• One clock per instruction cycle is used as opposed to 12 clocks per instruction cycle in the standard
8051.
• Wasted bus states are eliminated.
Because an instruction cycle is aligned with memory fetch when possible, most of the single-byte
instructions are performed in a single clock cycle. In addition to the speed improvement, the enhanced
8051 core also includes architectural enhancements:
• A second data pointer
• An extended 18-source interrupt unit
The 8051 core is object-code-compatible with the industry-standard 8051 microcontroller. That is, object
code compiled with an industry-standard 8051 compiler or assembler executes on the 8051 core and is
functionally equivalent. However, because the 8051 core uses a different instruction timing than many
other 8051 variants, existing code with timing loops may require modification. Also, because the peripheral
units such as timers and serial ports differ from those on other 8051 cores, code which includes
instructions using the peripheral-unit SFRs does not work correctly.
Flash prefetching is not enabled by default, but improves CPU performance by up to 33%. This is at the
expense of slightly increased power consumption, but in most cases improves energy consumption as it is
faster. Flash prefetching can be enabled in the FCTL register.
8051 CPU Introduction
2.2 Memory
The 8051 CPU architecture has four different memory spaces. The 8051 has separate memory spaces for
program memory and data memory. The 8051 memory spaces are the following (see Section 2.2.1 and
Section 2.2.2 for details):
CODE. A read-only memory space for program memory. This memory space addresses 64 KB.
DATA. A read-or-write data memory space that can be directly or indirectly accessed by a single-cycle
CPU instruction. This memory space addresses 256 bytes. The lower 128 bytes of the DATA memory
space can be addressed either directly or indirectly, the upper 128 bytes only indirectly.
XDATA. A read-and-write data memory space, access to which usually requires 4–5 CPU instruction
cycles. This memory space addresses 64 KB. Access to XDATA memory is also slower than DATA
access, as the CODE and XDATA memory spaces share a common bus on the CPU core, and instruction
prefetch from CODE thus cannot be performed in parallel with XDATA accesses.
SFR. A read-or-write register memory space which can be directly accessed by a single CPU instruction.
This memory space consists of 128 bytes. For SFR registers whose address is divisible by eight, each bit
is also individually addressable.
The four different memory spaces are distinct in the 8051 architecture, but are partly overlapping in the
device to ease DMA transfers and hardware debugger operation.
How the different memory spaces are mapped onto the three physical memories (flash program memory,
SRAM, and memory-mapped registers) is described in Section 2.2.1 and Section 2.2.2.
2.2.1 Memory Map
The memory map differs from the standard 8051 memory map in two important aspects, as described in
the following paragraphs.
First, in order to allow the DMA controller access to all physical memory and thus allow DMA transfers
between the different 8051 memory spaces, parts of SFR and the DATA memory space are mapped into
the XDATA memory space (see Figure 2-1).
Second, two alternative schemes for CODE memory space mapping can be used. The first scheme is the
standard 8051 mapping where only the program memory (that is, flash memory) is mapped to CODE
memory space. This mapping is the default after a device reset and is shown in Figure 2-2.
SWRU191F–April 2009–Revised April 2014 8051 CPU
Submit Documentation Feedback
Copyright © 2009–2014, Texas Instruments Incorporated
25
0 xFFFF
0x8000
0x0000
0x 6000
XREG(1KB)
0x63FF
SFR(128B)
0x 7080
SRAM_SIZE – 1
SRAMSIZE – 256
0x7 FFF
XBANK
(SELECTABLE32KBFLASHBANK)
8051SFRSPACE
8051DATA SPACE
INFORMATIONPAGE
(2KB)
0x70FF
0x 7800
M0097-02
SRAM
(SRAM_SIZEBytes)
Memory
www.ti.com
The second scheme is used for executing code from SRAM. In this mode, the SRAM is mapped into the
region of 0x8000 through (0x8000 + SRAM_SIZE – 1). The map is shown in Figure 2-3. Executing code
from SRAM improves performance and reduces power consumption.
The upper 32 KB of XDATA is a read-only area called XBANK (see Figure 2-1). Any of the available 32
KB flash banks can be mapped in here. This gives software access to the whole flash memory. This area
is typically used to store additional constant data.
Details about mapping of all 8051 memory spaces are given in Section 2.2.2.
The memory map showing how the different physical memories are mapped into the CPU memory spaces
is given in Figure 2-1 through Figure 2-3. The number of available flash banks depends on the flash size
option.
26
Figure 2-1. XDATA Memory Space (Showing SFR and DATA Mapping)
8051 CPU SWRU191F–April 2009–Revised April 2014
Copyright © 2009–2014, Texas Instruments Incorporated
Submit Documentation Feedback
0x 0000
0x7FFF
0x 8000
0 xFFFF
Bank0–7
(32KBFLASH)
Common Area/Bank0
(32KBFLASH)
M0098-02
0x 0000
0x7FFF
0x 8000
0 xFFFF
SRAM
0x8000 + SRAM_SIZE – 1
0x8000 + SRAM_SIZE
Banks 0–7
(Upper 24KB FLASH)
Common Area/Bank 0
(32KB FLASH)
M0099-04
www.ti.com
2.2.2 CPU Memory Space
Memory
Figure 2-2. CODE Memory Space Figure 2-3. CODE Memory Space for Running Code
From SRAM
XDATA memory space. The XDATA memory map is given in Figure 2-1.
The SRAM is mapped into address range of 0x0000 through (SRAM_SIZE – 1).
The XREG area is mapped into the 1 KB address range (0x6000–0x63FF). These registers are additional
registers, effectively extending the SFR register space. Some peripheral registers and most of the radio
control and data registers are mapped in here.
The SFR registers are mapped into address range (0x7080–0x70FF).
The flash information page (2 KB) is mapped into the address range (0x7800–0x7FFF). This is a read-only
area and contains various information about the device.
The upper 32 KB of the XDATA memory space (0x8000–0xFFFF) is a read-only flash code bank (XBANK)
and can be mapped to any of the available flash banks using the MEMCTR.XBANK[2:0] bits.
The mapping of flash memory, SRAM, and registers to XDATA allows the DMA controller and the CPU
access to all the physical memories in a single unified address space.
Writing to unimplemented areas in the memory map (shaded in the figure) has no effect. Reading from
unimplemented areas returns 0x00. Writes to read-only regions, that is, flash areas, are ignored.
CODE memory space. The CODE memory space is 64 KB and is divided into a common area
(0x0000–0x7FFF) and a bank area (0x8000–0xFFFF) as shown in Figure 2-2. The common area is
always mapped to the lower 32 KB of the physical flash memory (bank 0). The bank area can be mapped
to any of the available 32-KB flash banks (from 0 to 7). The number of available flash banks depends on
the flash size option. Use the flash-bank-select register, FMAP, to select the flash bank. On 32-KB
devices, no flash memory can be mapped into the bank area. Reads from this region return 0x00 on these
devices.
To allow program execution from SRAM, it is possible to map the available SRAM into the lower range of
the bank area from 0x8000 through (0x8000 + SRAM_SIZE – 1). The rest of of the currently selected bank
is still mapped into the address range from (0x8000 + SRAM_SIZE) through 0xFFFF). Set the
MEMCTR.XMAP bit to enable this feature.
DATA memory space. The 8-bit address range of DATA memory is mapped into the upper 256 bytes of
the SRAM, that is, the address range from (SRAM_SIZE – 256) through (SRAM_SIZE – 1).
SWRU191F–April 2009–Revised April 2014 8051 CPU
Submit Documentation Feedback
Copyright © 2009–2014, Texas Instruments Incorporated
27
Memory
SFR memory space. The 128-entry hardware register area is accessed through this memory space. The
SFR registers are also accessible through the XDATA address space at the address range
(0x7080–0x70FF). Some CPU-specific SFR registers reside inside the CPU core and can only be
accessed using the SFR memory space and not through the duplicate mapping into XDATA memory
space. These specific SFR registers are listed in SFR Registers.
2.2.3 Physical Memory
RAM. All devices contain static RAM. At power on, the content of RAM is undefined. RAM content is
retained in all power modes.
Flash Memory. The on-chip flash memory is primarily intended to hold program code and constant data.
The flash memory has the following features:
• Page size: 1 KB or 2 KB (details are given in the data sheet of the device.)
• Flash-page erase time: 20 ms
• Flash-chip (mass) erase time: 20 ms
• Flash write time (4 bytes): 20 μs
• Data retention (at room temperature): 100 years
• Program and erase endurance: 20,000 cycles
The flash memory is organized as a set of 1 or 2 KB pages. The 16 bytes of the upper available page
contain page-lock bits and the debug-lock bit. There is one lock bit for each page, except the lock-bit page
which is implicitly locked when not in debug mode. When the lock bit for a page is 0, it is impossible to
erase or write that page. When the debug lock bit is 0, most of the commands on the debug interface are
ignored. The primary purpose of the debug lock bit is to protect the contents of the flash against read-out.
The Flash Controller is used to write and erase the contents of the flash memory.
When the CPU reads instructions and constants from flash memory, it fetches the instructions through a
cache. Four bytes of instructions and four bytes of constant data are cached, at 4-byte boundaries. That
is, when the CPU reads from address 0x00F1 for example, bytes 0x00F0–0x00F3 are cached. A separate
prefetch unit is capable of prefetching 4 additional bytes of instructions. The cache is provided mainly to
reduce power consumption by reducing the amount of time the flash memory is accessed. The cache may
be disabled with the FCTL.CM[1:0] register bits. Doing so increases power consuption and is not
recommended. The execution time from flash is not cycle-accurate when using the default cache mode
and the cache mode with prefetch; that is, one cannot determine exactly the number of clock cycles a set
of instructions takes. To obtain cycle-accurate execution, enable the real-time cache mode and ensure all
DMA transfers have low priority. The prefetch mode improves performance by up to 33%, at the expense
of increased power consumption due to wasted flash reads. Typically, performance improves by
15%–20%. Total energy, however, may decrease (depending on the application) due to fewer wasted
clock cycles waiting for the flash to return instructions and/or data. Prefetching is very applicationdependent and requires the use of power modes to be effective.
The Information Page is a 2 KB read-only region that stores various device information. Among other
things, it contains for IEEE 802.15.4 or Bluetooth low energy compliant devices a unique IEEE address
from the TI range of addresses. For CC253x, this is a 64-bit IEEE address stored with least-significant
byte first at XDATA address 0x780C. For CC2540 and CC2541, this is a 48-bit IEEE address stored with
least-significant byte first at XDATA address 0x780E.
SFR Registers. The special function registers (SFRs) control several of the features of the 8051 CPU
core and/or peripherals. Many of the 8051 core SFRs are identical to the standard 8051 SFRs. However,
there are additional SFRs that control features that are not available in the standard 8051. The additional
SFRs are used to interface with the peripheral units and RF transceiver.
Table 2-1 shows the addresses of all SFRs in the device. The 8051 internal SFRs are shown with gray
background, whereas the other SFRs are the SFRs specific to the device.
www.ti.com
28
NOTE: All internal SFRs (shown with gray background in Table 2-1), can only be accessed through
SFR space, as these registers are not mapped into XDATA space. One exception is the port
registers (P0, P1, and P2) which are readable from XDATA.
8051 CPU SWRU191F–April 2009–Revised April 2014
Copyright © 2009–2014, Texas Instruments Incorporated
Submit Documentation Feedback
www.ti.com
Memory
Table 2-1. SFR Overview
Register SFR
Name Address
ADCCON1 0xB4 ADC ADC control 1
ADCCON2 0xB5 ADC ADC control 2
ADCCON3 0xB6 ADC ADC control 3
ADCL 0xBA ADC ADC data low
ADCH 0xBB ADC ADC data high
RNDL 0xBC ADC Random number generator data low
RNDH 0xBD ADC Random number generator data high
ENCDI 0xB1 AES Encryption or decryption input data
ENCDO 0xB2 AES Encryption or decryption output data
ENCCS 0xB3 AES Encryption or decryption control and status
P0 0x80 CPU Port 0. Readable from XDATA (0x7080)
SP 0x81 CPU Stack pointer
DPL0 0x82 CPU Data pointer 0 low byte
DPH0 0x83 CPU Data pointer 0 high byte
DPL1 0x84 CPU Data pointer 1 low byte
DPH1 0x85 CPU Data pointer 0 high byte
PCON 0x87 CPU Power mode control
TCON 0x88 CPU Interrupt flags
P1 0x90 CPU Port 1. Readable from XDATA (0x7090)
DPS 0x92 CPU Data pointer select
S0CON 0x98 CPU Interrupt flags 2
IEN2 0x9A CPU Interrupt enable 2
S1CON 0x9B CPU Interrupt flags 3
P2 0xA0 CPU Port 2. Readable from XDATA (0x70A0)
IEN0 0xA8 CPU Interrupt enable 0
IP0 0xA9 CPU Interrupt priority 0
IEN1 0xB8 CPU Interrupt enable 1
IP1 0xB9 CPU Interrupt priority 1
IRCON 0xC0 CPU Interrupt flags 4
PSW 0xD0 CPU Program status Word
ACC 0xE0 CPU Accumulator
IRCON2 0xE8 CPU Interrupt flags 5
B 0xF0 CPU B register
DMAIRQ 0xD1 DMA DMA interrupt flag
DMA1CFGL 0xD2 DMA DMA channel 1–4 configuration address low
DMA1CFGH 0xD3 DMA DMA channel 1–4 configuration address high
DMA0CFGL 0xD4 DMA DMA channel 0 configuration address low
DMA0CFGH 0xD5 DMA DMA channel 0 configuration address high
DMAARM 0xD6 DMA DMA channel armed
DMAREQ 0xD7 DMA DMA channel start request and status
— 0xAA — Reserved
— 0x8E — Reserved
— 0x99 — Reserved
— 0xB0 — Reserved
— 0xB7 — Reserved
— 0xC8 — Reserved
P0IFG 0x89 IOC Port 0 interrupt status flag
Module Description
SWRU191F–April 2009–Revised April 2014 8051 CPU
Submit Documentation Feedback
Copyright © 2009–2014, Texas Instruments Incorporated
29
Memory
Table 2-1. SFR Overview (continued)
Register SFR
Name Address
P1IFG 0x8A IOC Port 1 interrupt status flag
P2IFG 0x8B IOC Port 2 interrupt status flag
PICTL 0x8C IOC Port pins interrupt mask and edge
P0IEN 0xAB IOC Port 0 interrupt mask
P1IEN 0x8D IOC Port 1 interrupt mask
P2IEN 0xAC IOC Port 2 interrupt mask
P0INP 0x8F IOC Port 0 input mode
PERCFG 0xF1 IOC Peripheral I/O control
APCFG 0xF2 IOC Analog peripheral I/O configuration
P0SEL 0xF3 IOC Port 0 function select
P1SEL 0xF4 IOC Port 1 function select
P2SEL 0xF5 IOC Port 2 function select
P1INP 0xF6 IOC Port 1 input mode
P2INP 0xF7 IOC Port 2 input mode
P0DIR 0xFD IOC Port 0 direction
P1DIR 0xFE IOC Port 1 direction
P2DIR 0xFF IOC Port 2 direction
PMUX 0xAE IOC Power-down signal mux
MPAGE 0x93 MEMORY Memory page select
MEMCTR 0xC7 MEMORY Memory system control
FMAP 0x9F MEMORY Flash-memory bank mapping
RFIRQF1 0x91 RF RF interrupt flags MSB
RFD 0xD9 RF RF data
RFST 0xE1 RF RF command strobe
RFIRQF0 0xE9 RF RF interrupt flags LSB
RFERRF 0xBF RF RF error interrupt flags
ST0 0x95 ST Sleep Timer 0
ST1 0x96 ST Sleep Timer 1
ST2 0x97 ST Sleep Timer 2
STLOAD 0xAD ST Sleep-timer load status
SLEEPCMD 0xBE PMC Sleep-mode control command
SLEEPSTA 0x9D PMC Sleep-mode control status
CLKCONCMD 0xC6 PMC Clock control command
CLKCONSTA 0x9E PMC Clock control status
T1CC0L 0xDA Timer 1 Timer 1 channel 0 capture or compare value low
T1CC0H 0xDB Timer 1 Timer 1 channel 0 capture or compare value high
T1CC1L 0xDC Timer 1 Timer 1 channel 1 capture or compare value low
T1CC1H 0xDD Timer 1 Timer 1 channel 1 capture or compare value high
T1CC2L 0xDE Timer 1 Timer 1 channel 2 capture or compare value low
T1CC2H 0xDF Timer 1 Timer 1 channel 2 capture or compare value high
T1CNTL 0xE2 Timer 1 Timer 1 counter low
T1CNTH 0xE3 Timer 1 Timer 1 counter high
T1CTL 0xE4 Timer 1 Timer 1 control and status
T1CCTL0 0xE5 Timer 1 Timer 1 channel 0 capture or compare control
T1CCTL1 0xE6 Timer 1 Timer 1 channel 1 capture or compare control
T1CCTL2 0xE7 Timer 1 Timer 1 channel 2 capture or compare control
T1STAT 0xAF Timer 1 Timer 1 status
Module Description
www.ti.com
30
8051 CPU SWRU191F–April 2009–Revised April 2014
Copyright © 2009–2014, Texas Instruments Incorporated
Submit Documentation Feedback
Loading...