TEXAS INSTRUMENTS CC2500 Technical data

CC2500

Single Chip Low Cost Low Power RF Transceiver

Applications

• 2400-2483.5 MHz ISM/SRD band systems

• Consumer Electronics

• Wireless game controllers

Product Description

The

CC2500

GHz transceiver designed for very low power wireless applications. The circuit is intended for the ISM (Industrial, Scientific and Medical) and SRD (Short Range Device) frequency band at 2400-2483.5 MHz.

The RF transceiver is integrated with a highly configurable baseband modem. The modem supports various modulation formats and has a configurable data rate up to 500 kbps. The communication range can be increased by enabling a Forward Error Correction option, which is integrated in the modem.

is a low cost true single chip 2.4

• Wireless audio

• Wireless keyboard and mouse

a microcontroller and a few additional passive components.

CC2500

technology platform based on 0.18 µm CMOS technology.

is part of Chipcon’s 4th generation

CC2500

for packet handling, data buffering, burst transmissions, clear channel assessment, link quality indication and wake-on-radio.

The main operating parameters and the 64byte transmit/receive FIFOs of controlled via an SPI interface. In a typical system, the

This data sheet contains preliminary data, and supplementary data will be published at a later date. Chipcon reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. The product is not fully qualified at this point.

provides extensive hardware support

CC2500

will be used together with

can be

Key Features

•

Small size (QLP 4x4 mm package, 20

pins)

•

True single chip 2.4 GHz RF transceiver

•

Frequency range: 2400-2483.5 MHz

•

High sensitivity (–101 dBm at 10 kbps, 1%

packet error rate)

•

Programmable data rate up to 500 kbps

•

Low current consumption (13.3 mA in RX,

250 kbps, input 30 dB above sensitivity limit)

•

Programmable output power up to 0 dBm

•

Excellent receiver selectivity and blocking

performance

•

Very few external components:

Completely on-chip frequency synthesizer, no external filters or RF switch needed

•

Programmable baseband modem

•

Ideal for multi-channel operation

•

Configurable packet handling hardware

•

Suitable for frequency hopping systems

due to a fast settling frequency synthesizer

•

Optional Forward Error Correction with

interleaving

•

Separate 64-byte RX and TX data FIFOs

•

Efficient SPI interface: All registers can be

programmed with one “burst” transfer

•

Digital RSSI output

PRELIMINARY Data Sheet (Rev.1.2) SWRS040A Page 1 of 83

Features (continued from front page)

•

Suited for systems compliant with EN 300

328 and EN 300 440 class 2 (Europe), FCC CFR47 Part 15 (US), and ARIB STDT66 (Japan)

•

Wake-on-radio functionality for automatic

low-power RX polling

•

Many powerful digital features allow a

high-performance RF system to be made using an inexpensive microcontroller

•

Integrated analog temperature sensor

•

Lead-free “green“ package

•

Flexible support for packet oriented

systems: On chip support for sync word detection, address check, flexible packet length and automatic CRC handling.

•

Programmable channel filter bandwidth

•

FSK, GFSK and MSK supported

•

OOK supported

CC2500

•

Automatic Frequency Compensation

(AFC) can be used to align the frequency synthesizer to received centre frequency

•

Optional automatic whitening and de-

whitening of data

•

Support for asynchronous transparent

receive/transmit mode for backwards compatibility with existing radio communication protocols

•

Programmable Carrier Sense indicator

•

Programmable Preamble Quality Indicator

(PQI) for detecting preambles and improved protection against sync word detection in random noise

•

Support for automatic Clear Channel

Assessment (CCA) before transmitting (for listen-before-talk systems)

•

Support for per-package Link Quality

Indication

Abbreviations

Abbreviations used in this data sheet are described below.

ACP Adjacent Channel Power MSK Minimum Shift Keying

ADC Analog to Digital Converter NA Not Applicable

AFC Automatic Frequency Offset Compensation OOK On Off Keying

AGC Automatic Gain Control PA Power Amplifier

AMR Automatic Meter Reading PCB Printed Circuit Board

ARIB Association of Radio Industries and Businesses PD Power Down

BER Bit Error Rate PER Packet Error Rate

BT Bandwidth-Time product PLL Phase Locked Loop

CCA Clear Channel Assessment POR Power-on Reset

CFR Code of Federal Regulations PQI Preamble Quality Indicator

CRC Cyclic Redundancy Check PQT Preamble Quality Threshold

CS Carrier Sense RCOSC RC Oscillator

DC Direct Current QPSK Quadrature Phase Shift Keying

ESR Equivalent Series Resistance QLP Quad Leadless Package

FCC Federal Communications Commission RF Radio Frequency

FEC Forward Error Correction RSSI Received Signal Strength Indicator

FIFO First-In-First-Out RX Receive, Receive Mode

FHSS Frequency Hopping Spread Spectrum SMD Surface Mount Device

FSK Frequency Shift Keying SNR Signal to Noise Ratio

GFSK Gaussian shaped Frequency Shift Keying SPI Serial Peripheral Interface

IF Intermediate Frequency SRD Short Range Device

I/Q In-Phase/Quadrature T/R Transmit/Receive

ISM Industrial, Scientific and Medical TX Transmit, Transmit Mode

LBT Listen Before Transmit VCO Voltage Controlled Oscillator

LC Inductor-Capacitor WLAN Wireless Local Area Networks

LNA Low Noise Amplifier WOR Wake on Radio, Low power polling

LO Local Oscillator XOSC Crystal Oscillator

LQI Link Quality Indicator XTAL Crystal

MCU Microcontroller Unit

PRELIMINARY Data Sheet (Rev.1.2) SWRS040A Page 2 of 83

Table of Contents

CC2500

APPLICATIONS...........................................................................................................................................1

PRODUCT DESCRIPTION.........................................................................................................................1

KEY FEATURES..........................................................................................................................................1

FEATURES (CONTINUED FROM FRONT PAGE)................................................................................2

ABBREVIATIONS........................................................................................................................................2

TABLE OF CONTENTS..............................................................................................................................3

ABSOLUTE MAXIMUM RATINGS..............................................................................................6

OPERATING CONDITIONS ..........................................................................................................6

GENERAL CHARACTERISTICS..................................................................................................6

ELECTRICAL SPECIFICATIONS................................................................................................7

4.1 C

4.2 RF R

4.3 RF T

4.4 C

4.5 L

4.6 F

4.7 A

4.8 DC C

4.9 P

5 6 7 8 9

10 4-WIRE SERIAL CONFIGURATION AND DATA INTERFACE...........................................19

10.1 C

10.2 R

10.3 SPI R

10.4 C

10.5 FIFO A

10.6 PATABLE A

11 MICROCONTROLLER INTERFACE AND PIN CONFIGURATION...................................23

11.1 C

11.2 G

11.3 O

12 DATA RATE PROGRAMMING...................................................................................................24

13 RECEIVER CHANNEL FILTER BANDWIDTH.......................................................................24

14 DEMODULATOR, SYMBOL SYNCHRONIZER AND DATA DECISION............................25

14.1 F

14.2 B

14.3 B

15 PACKET HANDLING HARDWARE SUPPORT.......................................................................26

15.1 D

15.2 P

15.3 P

15.4 CRC C

15.5 P

15.6 P

16 MODULATION FORMATS..........................................................................................................30

16.1 F

16.2 M

URRENT CONSUMPTION

ECEIVE SECTION

RANSMIT SECTION RYSTAL OSCILLATOR OW POWER RC OSCILLATOR

REQUENCY SYNTHESIZER CHARACTERISTICS

NALOG TEMPERATURE SENSOR

HARACTERISTICS

OWER-ON RESET

PIN CONFIGURATION.................................................................................................................13

CIRCUIT DESCRIPTION.............................................................................................................15

APPLICATION CIRCUIT.............................................................................................................15

CONFIGURATION OVERVIEW.................................................................................................17

CONFIGURATION SOFTWARE.................................................................................................18

HIP STATUS BYTE EGISTER ACCESS

EAD

...........................................................................................................................................22

OMMAND STROBES

CCESS

.....................................................................................................................................22

CCESS

ONFIGURATION INTERFACE

ENERAL CONTROL AND STATUS PINS PTIONAL RADIO CONTROL FEATURE

REQUENCY OFFSET COMPENSATION

IT SYNCHRONIZATION YTE SYNCHRONIZATION

ATA WHITENING ACKET FORMAT ACKET FILTERING IN RECEIVE MODE

HECK ACKET HANDLING IN TRANSMIT MODE ACKET HANDLING IN RECEIVE MODE

REQUENCY SHIFT KEYING

INIMUM SHIFT KEYING

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PRELIMINARY Data Sheet (Rev.1.2) SWRS040A Page 3 of 83

CC2500

16.3 A

17 RECEIVED SIGNAL QUALIFIERS AND LINK QUALITY INFORMATION.....................31

17.1 S

17.2 P

17.3 RSSI...................................................................................................................................................31

17.4 C

17.5 C

17.6 L

18 FORWARD ERROR CORRECTION WITH INTERLEAVING..............................................34

18.1 F

18.2 I

19 RADIO CONTROL.........................................................................................................................35

19.1 P

19.2 C

19.3 V

19.4 A

19.5 W

19.6 T

19.7 RX T

20 DATA FIFO.....................................................................................................................................39

21 FREQUENCY PROGRAMMING.................................................................................................40

22 VCO..................................................................................................................................................41

22.1 VCO

23 VOLTAGE REGULATORS ..........................................................................................................41

24 OUTPUT POWER PROGRAMMING.........................................................................................42

25 SELECTIVITY................................................................................................................................43

26 CRYSTAL OSCILLATOR.............................................................................................................45

26.1 R

27 EXTERNAL RF MATCH ..............................................................................................................46

28 GENERAL PURPOSE / TEST OUTPUT CONTROL PINS......................................................46

29 ASYNCHRONOUS AND SYNCHRONOUS SERIAL OPERATION.......................................48

29.1 A

29.2 S

30 SYSTEM CONSIDERATIONS AND GUIDELINES..................................................................48

30.1 SRD R

30.2 F

30.3 W

30.4 D

30.5 C

30.6 C

30.7 S

30.8 L

30.9 B

30.10 I

31 CONFIGURATION REGISTERS.................................................................................................51

31.1 C

31.2 C

31.3 S

32 PACKAGE DESCRIPTION (QLP 20)..........................................................................................78

32.1 R

32.2 P

32.3 S

32.4 T

32.5 C

MPLITUDE MODULATION

YNC WORD QUALIFIER REAMBLE QUALITY THRESHOLD

ARRIER SENSE LEAR CHANNEL ASSESSMENT

INK QUALITY INDICATOR

ORWARD ERROR CORRECTION

NTERLEAVING

OWER-ON START-UP SEQUENCE

RYSTAL CONTROL

OLTAGE REGULATOR CONTROL CTIVE MODES

AKE ON RADIO

IMING

...............................................................................................................................................38

ERMINATION TIMER

AND

EFERENCE SIGNAL

SYNCHRONOUS OPERATION

YNCHRONOUS SERIAL OPERATION

EGULATIONS

REQUENCY HOPPING AND MULTI-CHANNEL SYSTEMS

IDEBAND MODULATION NOT USING SPREAD SPECTRUM

ATA BURST TRANSMISSIONS ONTINUOUS TRANSMISSIONS RYSTAL DRIFT COMPENSATION

PECTRUM EFFICIENT MODULATION OW COST SYSTEMS

ATTERY OPERATED SYSTEMS

NCREASING OUTPUT POWER

ONFIGURATION REGISTER DETAILS – REGISTERS WITH PRESERVED VALUES IN SLEEP STATE ONFIGURATION REGISTER DETAILS – REGISTERS THAT LOSE PROGRAMMING IN SLEEP STATE

TATUS REGISTER DETAILS

ECOMMENDED

ACKAGE THERMAL PROPERTIES OLDERING INFORMATION RAY SPECIFICATION

ARRIER TAPE AND REEL SPECIFICATION

(CS)..........................................................................................................................32

...................................................................................................................................34

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(WOR)...................................................................................................................37

PLL S

ELF-CALIBRATION

PCB

.................................................................................................................31

.....................................................................................................................31

(PQT)...........................................................................................31

(CCA) ..............................................................................................33

(LQI).......................................................................................................34

(FEC)...............................................................................................34

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LAYOUT FOR PACKAGE

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(QLP 20).....................................................................79

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..........55

........74

PRELIMINARY Data Sheet (Rev.1.2) SWRS040A Page 4 of 83

CC2500

33 ORDERING INFORMATION.......................................................................................................80

34 GENERAL INFORMATION.........................................................................................................80

34.1 D

34.2 P

35 ADDRESS INFORMATION..........................................................................................................82

36 TI WORLDWIDE TECHNICAL SUPPORT...............................................................................82

OCUMENT HISTORY

RODUCT STATUS DEFINITIONS

.........................................................................................................................80

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PRELIMINARY Data Sheet (Rev.1.2) SWRS040A Page 5 of 83

CC2500

1 Absolute Maximum Ratings

Under no circumstances must the absolute maximum ratings given in Table 1 be violated. Stress exceeding one or more of the limiting values may cause permanent damage to the device.

Caution! ESD sensitive device. Precaution should be used when handling the device in order to prevent permanent damage.

Parameter Min Max Units Condition

Supply voltage –0.3 3.6 V All supply pins must have the same voltage

Voltage on any digital pin –0.3 VDD+0.3,

Voltage on the pins RF_P, RF_N and DCOUPL

Voltage ramp-up rate 120 kV/µs

Input RF level +10 dBm

Storage temperature range –50 150

Solder reflow temperature 260

ESD <500 V According to JEDEC STD 22, method A114,

max 3.6

–0.3 2.0 V

°C

According to IPC/JEDEC J-STD-020C

°C

Human Body Model

Table 1: Absolute maximum r atings

2 Operating Conditions

The operating conditions for

Parameter Min Max Unit Condition

Operating temperature –40 85

Operating supply voltage 1.8 3.6 V All supply pins must have the same voltage

CC2500

are listed Table 2 in below.

Table 2: Operating conditions

°C

3 General Characteristics

Parameter Min Typ Max Unit Condition/Note

Frequency range 2400 2483.5 MHz

Data rate 1.2

1.2

500

250

500

kbps

FSK

GFSK and OOK

(Shaped) MSK (also known as differential offset QPSK)

Optional Manchester encoding (halves the data rate).

Table 3: General characteristics

PRELIMINARY Data Sheet (Rev.1.2) SWRS040A Page 6 of 83

CC2500

4 Electrical Specifications

4.1 Current Consumption

Tc = 25°C, VDD = 3.0 V if nothing else stated. All measurement results obtained using the CC2500EM reference design.

Parameter Min Typ Max Unit Condition

Current consumption in power down modes

Current consumption

Current consumption, RX states

400 nA Voltage regulator to digital part off, register values retained

900 nA Voltage regulator to digital part off, register values retained, low-

160

8.1

1.4

1.5 mA Only voltage regulator to digital part and crystal oscillator running

7.4 mA Only the frequency synthesizer running (after going from IDLE

15.3 mA Receive mode, 2.4 kbps, input at sensitivity limit,

12.8 mA Receive mode, 2.4 kbps, input 30 dB above sensitivity limit,

15.4 mA Receive mode, 10 kbps, input at sensitivity limit,

12.9 mA Receive mode, 10 kbps, input 30 dB above sensitivity limit,

18.8 mA Receive mode, 250 kbps, input at sensitivity limit,

15.7 mA Receive mode, 250 kbps, input 30 dB above sensitivity limit,

16.6 mA Receive mode, 250 kbps current optimized, input at sensitivity

13.3 mA Receive mode, 250 kbps current optimized, input 30 dB above

19.6 mA Receive mode, 500 kbps, input at sensitivity limit,

17.0 mA Receive mode, 500 kbps, input 30 dB above sensitivity limit,

(SLEEP state)

power RC oscillator running (SLEEP state with WOR enabled)

Voltage regulator to digital part off, register values retained,

µA

XOSC running (SLEEP state with MCSM0.OSC_FORCE_ON set)

Voltage regulator to digital part on, all other modules in power

µA

down (XOFF state)

Automatic RX polling once each second, using low-power RC

µA

oscillator, with 460 kHz filter bandwidth and 250 kbps data rate, PLL calibration every 4

channel below carrier sense level. Same as above, but with signal in channel above carrier sense

µA

level, 1.9 ms RX timeout, and no preamble/sync word found.

Automatic RX polling every 15th second, using low-power RC

µA

oscillator, with 460 kHz filter bandwidth and 250 kbps data rate, PLL calibration every 4 channel below carrier sense level.

Same as above, but with signal in channel above carrier sense

µA

level, 37 ms RX timeout, and no preamble/sync word found.

(IDLE state)

until reaching RX or TX states, and frequency calibration states)

MDMCFG2.DEM_DCFILT_OFF = 1

MDMCFG2.DEM_DCFILT_OFF = 0

limit, MDMCFG2.DEM_DCFILT_OFF = 1

sensitivity limit, MDMCFG2.DEM_DCFILT_OFF = 1

MDMCFG2.DEM_DCFILT_OFF = 0

wakeup. Average current with signal in

PRELIMINARY Data Sheet (Rev.1.2) SWRS040A Page 7 of 83

CC2500

Current consumption, TX states

11.1 mA Transmit mode, –12 dBm output power

15.1 mA Transmit mode, -6 dBm output power

21.2 mA Transmit mode, 0 dBm output power

Table 4: Current consumption

4.2 RF Receive Section

Tc = 25°C, VDD = 3.0 V if nothing else stated. All measurement results obtained using the CC2500EM reference design.

Parameter Min Typ Max Unit Condition/Note

Digital channel filter bandwidth

2.4 kbps data rate, current optimized, MDMCFG2.DEM_DCFILT_OFF = 1 (FSK, 1% packet error rate, 20 bytes packet length, 203 kHz digital channel filter bandwidth)

Receiver sensitivity –104 dBm The sensitivity can be improved to typically –106 dBm by

Saturation –13 dBm

Adjacent channel rejection

Alternate channel rejection

See Figure 22 for plot of selectivity versus frequency offset 10 kbps data rate, current optimized, MDMCFG2.DEM_DCFILT_OFF = 1

(FSK, 1% packet error rate, 20 bytes packet length, 232 kHz digital channel filter bandwidth)

Receiver sensitivity –99 dBm The sensitivity can be improved to typically –101 dBm by

Saturation –9 dBm

Adjacent channel rejection

Alternate channel rejection

See Figure 23 for plot of selectivity versus frequency offset 250 kbps data rate, MDMCFG2.DEM_DCFILT_OFF = 0

(MSK, 1% packet error rate, 20 bytes packet length, 540 kHz digital channel filter bandwidth)

Receiver sensitivity –89 dBm

Saturation –13 dBm

Adjacent channel rejection

Alternate channel rejection

See Figure 24 for plot of selectivity versus frequency offset

58 812 kHz User programmable. The bandwidth limits are proportional

to crystal frequency (given values assume a 26.0 MHz crystal).

setting MDMCFG2.DEM_DCFILT_OFF = 0 . The typical current consumption is in this case 17.0 mA at sensitivity llimit.

23 dB Desired channel 3 dB above the sensitivity limit. 250 kHz

channel spacing

31 dB Desired channel 3 dB above the sensitivity limit. 250 kHz

channel spacing

setting MDMCFG2.DEM_DCFILT_OFF = 0 . The typical current consumption is in this case 17.3 mA at sensitivity llimit.

18 dB Desired channel 3 dB above the sensitivity limit. 250 kHz

channel spacing

25 dB Desired channel 3 dB above the sensitivity limit. 250 kHz

channel spacing

21 dB Desired channel 3 dB above the sensitivity limit. 750 kHz

channel spacing

30 dB Desired channel 3 dB above the sensitivity limit. 750 kHz

channel spacing

PRELIMINARY Data Sheet (Rev.1.2) SWRS040A Page 8 of 83

CC2500

Parameter Min Typ Max Unit Condition/Note 250 kbps data rate, current optimized, MDMCFG2.DEM_DCFILT_OFF = 1

(MSK, 1% packet error rate, 20 bytes packet length, 540 kHz digital channel filter bandwidth)

Receiver sensitivity –87 dBm

Saturation –13 dBm

Adjacent channel rejection

Alternate channel rejection

See Figure 25 for plot of selectivity versus frequency offset 500 kbps data rate, MDMCFG2.DEM_DCFILT_OFF = 0

(MSK, 1% packet error rate, 20 bytes packet length, 812 kHz digital channel filter bandwidth)

Receiver sensitivity –82 dBm

Saturation –18 dBm

Adjacent channel rejection

Alternate channel rejection

See Figure 26 for plot of selectivity versus frequency offset

General

Blocking at ±10 MHz offset

Blocking at ±20 MHz offset

Blocking at ±50 MHz offset

Spurious emissions

25 MHz – 1 GHz

Above 1 GHz

21 dB Desired channel 3 dB above the sensitivity limit. 750 kHz

30 dB Desired channel 3 dB above the sensitivity limit. 750 kHz

14 dB Desired channel 3 dB above the sensitivity limit. 1 MHz

25 dB Desired channel 3 dB above the sensitivity limit. 1 MHz

47 dB Desired channel at –80 dBm. Compliant with ETSI EN 300

52 dB Desired channel at –80 dBm. Compliant with ETSI EN 300

54 dB Desired channel at –80 dBm. Compliant with ETSI EN 300

–57

–47

channel spacing

440 class 2 receiver requirements.

dBm

Table 5: RF receive parameters

PRELIMINARY Data Sheet (Rev.1.2) SWRS040A Page 9 of 83

CC2500

4.3 RF Transmit Section

Tc = 25°C, VDD = 3.0 V, 0 dBm if nothing else stated. All measurement results obtained using the CC2500EM reference design.

Parameter Min Typ Max Unit Condition/Note

Differential load impedance

Output power, highest setting

Output power, lowest setting

Spurious emissions

25 MHz – 1 GHz

47-74, 87.5-118, 174230, 470-862 MHz

1800-1900 MHz

At 2·RF and 3·RF

Otherwise above 1 GHz

80 + j74

0 dBm Output power is programmable and is available across the

–30 dBm Output power is programmable and is available across the

–36

–54

–47

–41

–30

Differential impedance as seen from the RF-port (RF_P and

Ω

RF_N) towards the antenna. Follow the CC2500EM reference design available from the TI and Chipcon websites.

entire frequency band.

Delivered to a 50 Ω single-ended load via CC2500EM reference design RF matching network.

entire frequency band.

Delivered to a 50 Ω single-ended load via CC2500EM reference design RF matching network.

dBm

Restricted band in Europe

dBm

Restricted bands in USA

dBm

Table 6: RF transmit parameters

4.4 Crystal Oscillator

Tc = 25°C, VDD = 3.0 V if nothing else stated.

Parameter Min Typ Max Unit Condition/Note

Crystal frequency 26 26 27 MHz

Tolerance ±40 ppm This is the total tolerance including a) initial tolerance, b) crystal

ESR 100

Start-up time 300 µs Measured on CC2500EM reference design.

loading, c) aging and d) temperature dependence.

The acceptable crystal tolerance depends on RF frequency and channel spacing / bandwidth.

Ω

Table 7: Crystal oscillator parameters

PRELIMINARY Data Sheet (Rev.1.2) SWRS040A Page 10 of 83

CC2500

4.5 Low Power RC Oscillator

Tc = 25°C, VDD = 3.0 V if nothing else stated. All measurement results obtained using the CC2500EM reference design.

Parameter Min Typ Max Unit Condition/Note

Calibrated frequency 34.6 34.7 36 kHz Calibrated RC Oscillator frequency is XTAL

Frequency accuracy after calibration

Temperature coefficient +0.4

Supply voltage coefficient +3 % / V Frequency drift when supply voltage changes

Initial calibration time 2 ms When the RC Oscillator is enabled, calibration

+0.3

-10

% / °C

% The RC oscillator contains an error in the

frequency divided by 750

calibration routine that statistically occurs in

17.3% of all calibrations performed. The given maximum accuracy figures account for the calibration error. Refer also to the Errata Note.

Frequency drift when temperature changes after calibration

after calibration

is continuously done in the background as long as the crystal oscillator is running.

CC2500

Table 8: RC oscillator parameters

4.6 Frequency Synthesizer Characteristics

Tc = 25°C, VDD = 3.0 V if nothing else stated. All measurement results obtained using the CC2500EM reference design.

Parameter Min Typ Max Unit Condition/Note

Programmed frequency resolution

Synthesizer frequency tolerance

RF carrier phase noise

PLL turn-on / hop time 88.4

PLL RX/TX settling time

PLL TX/RX settling time

PLL calibration time

397 F

0.69

XOSC

±40 ppm Given by crystal used. Required accuracy (including

–78 dBc/Hz @ 50 kHz offset from carrier

–78 dBc/Hz @ 100 kHz offset from carrier

–81 dBc/Hz @ 200 kHz offset from carrier

–90 dBc/Hz @ 500 kHz offset from carrier

–100 dBc/Hz @ 1 MHz offset from carrier

–108 dBc/Hz @ 2 MHz offset from carrier

–116 dBc/Hz @ 5 MHz offset from carrier

–127 dBc/Hz @ 10 MHz offset from carrier

9.6

21.5

18739

0.72

412 Hz 26-27 MHz crystal.

temperature and aging) depends on frequency band and channel bandwidth / spacing.

Time from leaving the IDLE state until arriving in the RX,

µs

FSTXON or TX state, when not performing calibration. Crystal oscillator running.

Settling time for the 1·IF frequency step from RX to TX

µs

Settling time for the 1·IF frequency step from TX to RX

µs

XOSC

0.72

cycles

Calibration can be initiated manually, or automatically before entering or after leaving RX/TX.

Min/typ/max time is for 27/26/26 MHz crystal frequency.

Table 9: Frequency synthesizer pa rameters

PRELIMINARY Data Sheet (Rev.1.2) SWRS040A Page 11 of 83

CC2500

4.7 Analog Temperature Sensor

The characteristics of the analog temperature sensor are listed in Table 10 below. Note that it is necessary to write 0xBF to the PTEST register to use the analog temperature sensor in the IDLE state.

Parameter Min Typ Max Unit Condition/Note

Output voltage at –40°C

Output voltage at 0°C

Output voltage at +40°C

Output voltage at +80°C

Temperature coefficient 2.54

Error in calculated temperature, calibrated

Current consumption increase when enabled

0.660 V

0.755 V

0.859 V

0.958 V

mV/°C Fitted from –20°C to +80°C

-2

0 2

0.3 mA

°C From –20°C to +80°C when using 2.54 mV / °C,

after 1-point calibration at room temperature

The indicated minimum and maximum error with 1point calibration is based on simulated values for typical process parameters

Table 10: Analog temperature sensor parameters

4.8 DC Characteristics

Tc = 25°C if nothing else stated.

Digital Inputs/Outputs Min Max Unit Condition

Logic "0" input voltage 0 0.7 V

Logic "1" input voltage VDD-0.7 VDD V

Logic "0" output voltage 0 0.5 V For up to 4 mA output current

Logic "1" output voltage VDD-0.3 VDD V For up to 4 mA output current

Logic "0" input current NA –50 nA Input equals 0 V

Logic "1" input current NA 50 nA Input equals VDD

Table 11: DC characteristics

4.9 Power-On Reset

When the power supply complies with the requirements in Table 12 below, proper Power-OnReset functionality is guaranteed. Otherwise, the chip should be assumed to have unknown state until transmitting an

SRES

strobe over the SPI interface. See Section 19.1 on page 36 for further

details.

Parameter Min Typ Max Unit Condition/Note

Power ramp-up time 5 ms From 0 V until reaching 1.8 V

Power off time 1 ms Minimum time between power-on and power-off.

Table 12: Power-on reset requirements

PRELIMINARY Data Sheet (Rev.1.2) SWRS040A Page 12 of 83

5 Pin Configuration

GND

RBIAS

DGUARD

GND

20 19 18 17 16

CC2500

SO (GDO1)

GDO2

DVDD

DCOUPL

Note: The exposed die attach pad ground connection for the chip.

SCLK

XOSC_Q1

AVDD

109876

XOSC_Q2

GDO0 (ATEST)

CSn

Figure 1: Pinout top view

must

be connected to a solid ground plane as this is the main

AVDD

RF_N

RF_P

AVDD

GND Exposed die attach pad

PRELIMINARY Data Sheet (Rev.1.2) SWRS040A Page 13 of 83

CC2500

Pin # Pin name Pin type Description

1 SCLK Digital Input Serial configuration interface, clock input

2 SO (GDO1) Digital Output Serial configuration interface, data output.

Optional general output pin when

3 GDO2 Digital Output Digital output pin for general use:

• Test signals

• FIFO status signals

• Clear Channel Indicator

• Clock output, down-divided from XOSC

• Serial output RX data

4 DVDD Power (Digital) 1.8 - 3.6 V digital power supply for digital I/O’s and for the digital core

5 DCOUPL Power (Digital) 1.6 - 2.0 V digital power supply output for decoupling.

6 GDO0

(ATEST)

7 CSn Digital Input Serial configuration interface, chip select

8 XOSC_Q1 Analog I/O Crystal oscillator pin 1, or external clock input

9 AVDD Power (Analog) 1.8 - 3.6 V analog power supply connection

10 XOSC_Q2 Analog I/O Crystal oscillator pin 2

11 AVDD Power (Analog) 1.8 - 3.6 V analog power supply connection

12 RF_P RF I/O Positive RF input signal to LNA in receive mode

13 RF_N RF I/O Negative RF input signal to LNA in receive mode

14 AVDD Power (Analog) 1.8 - 3.6 V analog power supply connection

15 AVDD Power (Analog) 1.8 - 3.6 V analog power supply connection

16 GND Ground (Analog) Analog ground connection

17 RBIAS Analog I/O External bias resistor for reference current

18 DGUARD Power (Digital) Power supply connection for digital noise isolation

19 GND Ground (Digital) Ground connection for digital noise isolation

20 SI Digital Input Serial configuration interface, data input

Digital I/O

voltage regulator

NOTE: This pin is intended for use with the used to provide supply voltage to other devices.

Digital output pin for general use:

• Test signals

• FIFO status signals

• Clear Channel Indicator

• Clock output, down-divided from XOSC

• Serial output RX data

• Serial input TX data

Also used as analog test I/O for prototype/production testing

Positive RF output signal from PA in transmit mode

Negative RF output signal from PA in transmit mode

CSn

is high

CC2500

only. It can not be

Table 13: Pinout overview

PRELIMINARY Data Sheet (Rev.1.2) SWRS040A Page 14 of 83

6 Circuit Description

LNA

RF_P RF_N

RC OSC

BIAS

RADIO CONTROL

ADC

XOSC

FREQ

SYNTH

DEMODULATOR

FEC / INTERLEAVER

MODULATOR

PACKET HANDLER

RXFIFO

DIGITAL INTERFACE TO MCU

TXFIFO

CC2500

SCLK SO (GDO1) SI

CSn

GDO0 (ATEST)

GDO2

RBIAS XOSC_Q1 XOSC_Q2

Figure 2:

CC2500

simplified block diagram

A simplified block diagram of

CC2500

is shown

in Figure 2.

CC2500

features a low-IF receiver. The received RF signal is amplified by the lownoise amplifier (LNA) and down-converted in quadrature (I and Q) to the intermediate frequency (IF). At IF, the I/Q signals are digitised by the ADCs. Automatic gain control (AGC), fine channel filtering, demodulation bit/packet synchronization is performed digitally.

The transmitter part of

CC2500

is based on

direct synthesis of the RF frequency.

The frequency synthesizer includes a completely on-chip LC VCO and a 90 degrees

7 Application Circuit

phase shifter for generating the I and Q LO signals to the down-conversion mixers in receive mode.

A crystal is to be connected to XOSC_Q1 and XOSC_Q2. The crystal oscillator generates the reference frequency for the synthesizer, as well as clocks for the ADC and the digital part.

A 4-wire SPI serial interface is used for configuration and data buffer access.

The digital baseband includes support for channel configuration, packet handling and data buffering.

Only a few external components are required for using the

CC2500

. The recommended application circuit is shown in Figure 3. The external components are described in Table 14, and typical values are given in Table 15.

Bias resistor

The bias resistor R171 is used to set an accurate bias current.

PRELIMINARY Data Sheet (Rev.1.2) SWRS040A Page 15 of 83

Balun and RF matching

C122, C132, L121 and L131 form a balun that converts the differential RF signal on

CC2500

to a single-ended RF signal. C121 and C131 are needed for DC blocking. Together with an appropriate LC network, the balun components also transform the impedance to match a 50

Ω

antenna (or cable). Component

values for the RF balun and LC network are

CC2500

easily found using the SmartRF® Studio software. Suggested values are listed in Table

15. The balun and LC filter component values and their placement are important to keep the performance optimized. It is highly recommended to follow the CC2500EM reference design.

Crystal

The crystal oscillator uses an external crystal with two loading capacitors (C81 and C101). See Section 26 on page 45 for details.

Component Description

C51 Decoupling capacitor for on-chip voltage regulator to digital part

C81/C101 Crystal loading capacitors, see Section 26 on page 45 for details

C121/C131 RF balun DC blocking capacitors

C122/C132 RF balun/matching capacitors

C123/C124 RF LC filter/matching capacitors

L121/L131 RF balun/matching inductors (inexpensive multi-layer type)

L122 RF LC filter inductor (inexpensive multi-layer type)

R171 Resistor for internal bias current reference

XTAL 26-27 MHz crystal, see Section 26 on page 45 for details

Power supply decoupling

The power supply must be properly decoupled close to the supply pins. Note that decoupling capacitors are not shown in the application circuit. The placement and the size of the decoupling capacitors are very important to achieve the optimum performance. The CC2500EM reference design should be followed closely.

Table 14: Overview of external components (excluding supply decoupling capacitors)

1.8V-3.6V power supply

Digital Inteface

SCLK

SO (GDO1) GDO2 (optional)

C51

GDO0 (optional) CSn

1 SCLK

2 SO (GDO1)

3 GDO2

4 DVDD

5 DCOUPL

SI 20

GND 19

CC2500

DIE ATTACH PAD:

6 GDO0

7 CSn

C81 C101

DGUARD 18

8 XOSC_Q1

XTAL

R171

RBIAS 17

9 AVDD

GND 16

AVDD 15

AVDD 14

RF_N 13

RF_P 12

AVDD 11

10 XOSC_Q2

L131

C131

C121

L121

C122

Alternative: Folded dipole PCB antenna (no external components needed)

Antenna

(50 Ohm)

C132

L122

C123 C124

Figure 3: Typical application and evaluation circuit (excluding supply decoupling capacitors)

PRELIMINARY Data Sheet (Rev.1.2) SWRS040A Page 16 of 83

CC2500

Component Value Manufacturer

C51 100 nF ±10%, 0402 X5R Murata GRM15 series

C81 27 pF ±5%, 0402 NP0 Murata GRM15 series

C101 27 pF ±5%, 0402 NP0 Murata GRM15 series

C121 100 pF ±5%, 0402 NP0 Murata GRM15 series

C122 1.0 pF ±0.25 pF, 0402 NP0 Murata GRM15 series

C123 1.8 pF ±0.25 pF, 0402 NP0 Murata GRM15 series

C124 1.5 pF ±0.25 pF, 0402 NP0 Murata GRM15 series

C131 100 pF ±5%, 0402 NP0 Murata GRM15 series

C132

L121

L122

L131

R171

XTAL

1.0 pF ±0.25 pF, 0402 NP0

1.2 nH ±0.3 nH, 0402 monolithic

56 kΩ ±1%, 0402

26.0 MHz surface mount crystal

Murata GRM15 series

Murata LQG15 series

Koa RK73 series

NDK, AT-41CD2

Table 15: Bill Of Materials for the application circuit

In the CC2500EM reference design shown in Figure 4, LQG15 series inductors from Murata have been used. Measurements have been performed with multi-layer inductors from other manufacturers (e.g. Würth) and the measurement results were the same as when using the Murata part.

The Gerber files for the CC2500EM reference design are available from the TI and Chipcon websites.

8 Configuration Overview

CC2500

performance for many different applications. Configuration is done using the SPI interface. The following key parameters can be programmed:

•

can be configured to achieve optimum

Power-down / power up mode Crystal oscillator power-up / power-down Receive / transmit mode RF channel selection Data rate Modulation format RX channel filter bandwidth RF output power Data buffering with separate 64-byte

receive and transmit FIFOs

Figure 4: CC2500EM reference design

•

Packet radio hardware support

•

Forward Error Correction with interleaving

•

Data Whitening

•

Wake-On-Radio (WOR)

Details of each configuration register can be found in Section 31, starting on page 51.

Figure 5 shows a simplified state diagram that explains the main

CC2500

states, together with typical usage and current consumption. For detailed information on controlling the

CC2500

state machine, and a complete state diagram, see Section 19, starting on page 35.

PRELIMINARY Data Sheet (Rev.1.2) SWRS040A Page 17 of 83

CC2500

Default state when the radio is not receiving or transmitting. Typ. current consumption: 1.5mA.

Used for calibrating frequency synthesizer upfront (entering receive or transmit mode can then be done quicker). Transitional state. Typ. current consumption: 7.4mA.

Frequency synthesizer is on, ready to start transmitting. Transmission starts very quickly after receiving the STX command strobe.Typ. current consumption: 7.4mA.

Typ. current consumption:

11.1mA at -12dBm output,

15.1mA at -6dBm output,

21.2mA at 0dBm output.

SPWD or wake-on-radio (WOR)

SIDLE

Idle

SCAL

Manual freq.

synth. calibration

Frequency

synthesizer on

STX

TXOFF_MODE=01

Transmit mode Receive mode

SRX or STX or SFSTXON or wake-on-radio (WOR)

Frequency

synthesizer startup,

SFSTXON

optional calibration,

settling

STX

SFSTXON or RXOFF_MODE=01

STX or RXOFF_MODE=10

SRX or TXOFF_MODE=11

CSn=0

SXOFF

CSn=0

Frequency synthesizer is turned on, can optionally be calibrated, and then settles to the correct frequency. Transitional state. Typ. current consumption: 7.4mA.

SRX or wake-on-radio (WOR)

Sleep

Crystal

oscillator off

Lowest power mode. Most register values are retained. Typ. current consumption 400nA, or 900nA when wake-on-radio (WOR) is enabled.

All register values are retained. Typ. current consumption; 0.16mA.

Typ. current consumption: from 13.3mA (strong input signal) to 16.6mA (weak input signal).

In FIFO-based modes, transmission is turned off and this state entered if the TX FIFO becomes empty in the middle of a packet. Typ. current consumption: 1.5mA.

TXOFF_MODE=00

TX FIFO

underflow

SFTX

Optional transitional state. Typ. current consumption: 7.4mA.

Optional freq.

synth. calibration

Idle

RXOFF_MODE=00

SFRX

RX FIFO

overflow

In FIFO-based modes, reception is turned off and this state entered if the RX FIFO overflows. Typ. current consumption:

1.5mA.

Figure 5: Simplified state diagram, with typical usage and current consumption at 250 kbps

data rate and

MDMCFG2.DEM_DCFILT_OFF

= 1 (current optimized)

9 Configuration Software

CC2500

Studio software, available for download from http://www.ti.com. The SmartRF

can be configured using the SmartRF®

Studio

software is highly recommended for obtaining

optimum register settings, and for evaluating performance and functionality. A screenshot of the SmartRF

Studio user interface for

is shown in Figure 6.

CC2500

PRELIMINARY Data Sheet (Rev.1.2) SWRS040A Page 18 of 83

CC2500

Figure 6: SmartRF® Studio user interface

10 4-wi re Serial Configuration and Data Interface

CSn

CC2500

compatible interface ( where

also used to read and write buffered data. All address and data transfer on the SPI interface is done most significant bit first.

All transactions on the SPI interface start with a header byte containing a read/write bit, a burst access bit and a 6-bit address.

During address and data transfer, the (Chip Select, active low) must be kept low. If

CSn

will be cancelled. The timing for the address and data transfer on the SPI interface is shown in Figure 7 with reference to Table 16.

is configured via a simple 4-wire SPI-

SI, SO, SCLK

CC2500

goes high during the access, the transfer

is the slave. This interface is

and

CSn

)

When

CC2500

transfer the header byte. This indicates that the voltage regulator has stabilized and the crystal is running. Unless the chip is in the SLEEP or XOFF states or an strobe is issued, the immediately after taking

Figure 8 gives a brief overview of different register access types possible.

goes low, the MCU must wait until

SO pin goes low before starting to

SRES

command

pin will always go low

CSn

low.

PRELIMINARY Data Sheet (Rev.1.2) SWRS040A Page 19 of 83

CC2500

SCLK:

CSn:

Hi-Z

Write to register :

S7 S 6 S 5 S4 S 3 S 2 S 1 S0 S7 S6 S5 S4 S3 S2 S1 S0 S7

Read from register:

S7 S 6 S 5 S4 S 3 S 2 S 1 S0

A6 A5 A4 A3 A2

A0A1

DW7 DW6 DW5 DW4 DW3 DW2 DW1 DW0

A0A1

DR7 DR6 DR5 DR4 DR3 DR2 DR1 D

Hi-Z

Figure 7: Configuration register write and read operations (A6 is the “burst” bit)

Parameter Description Min Max Units

tsp

SCLK

sp,pd

SCLK

frequency

100 ns delay inserted between address byte and data byte (single access), or between address and data, and between each data byte (burst access).

SCLK

frequency, single access

No delay between address and data byte

SCLK

frequency, burst access

No delay between address and data byte, or between data bytes

CSn

low to positive edge on

CSn

low to positive edge on

SCLK

, in power-down mode

SCLK

, in active mode

tch Clock high 50 - ns

tcl Clock low 50 - ns

Clock rise time - 5 ns

rise

Clock fall time - 5 ns

fall

Single access 55 - ns tsd

Burst access 76 - ns

thd

tns

SCLK

edge) to

SCLK

CSn

high

Setup data (negative positive edge on

(tsd applies between address and data bytes, and between data bytes)

SCLK

Hold data after positive edge on

Negative edge on

SCLK

- 10 MHz

9 MHz

6.5 MHz

200 -

µs

20 - ns

Table 16: SPI interface timing requirements

CSn:

Command strobe(s):

Read or write register(s):

ead or write consecutive registers (burst):

Read or write n+1 bytes from/to RF FIFO:

Combinations:

DDR

strobe

DDR

reg

DATAnDATA

reg n

DATA

FIFO

reg

DATA

strobe

byte 0

DDR

DATA

DDR

strobe

reg

n+1

byte 1

strobe

...

DATA

DDR

n+2

byte 2

reg

DDR

... ...

DATA

DDR

byte n-1

strobe

...

DATA

DDR

byte n

FIFO

DATA

byte 0

DATA

byte 1

...

reg

DATA

Figure 8: Register access types

PRELIMINARY Data Sheet (Rev.1.2) SWRS040A Page 20 of 83

CC2500

10.1 Chip Status Byte

When the header byte, data byte or command strobe is sent on the SPI interface, the chip

status byte is sent by the

CC2500

on the SO pin. The status byte contains key status signals, useful for the MCU. The first bit, s7, is

CHIP_RDYn

the before the first positive edge of

CHIP_RDYn

signal; this signal must go low

SCLK

. The

signal indicates that the crystal is running and the regulated digital supply voltage is stable.

Bits 6, 5 and 4 comprise the

STATE

value.

This value reflects the state of the chip. The

when the chip is in receive mode. Likewise, TX is active when the chip is transmitting.

The last four bits (3:0) in the status byte con-

FIFO_BYTES_AVAILABLE.

tains operations, the

FIFO_BYTES_AVAILABLE

For read

field contains the number of bytes available for reading from the RX FIFO. For write operations, the

FIFO_BYTES_AVAILABLE

field contains the number of bytes free for writing into the TX FIFO. When

FIFO_BYTES_AVAILABLE=15

, 15 or more

bytes are available/free.

Table 17 gives a status byte summary.

XOSC and power to the digital core is on in the IDLE state, but all other modules are in power down. The frequency and channel configuration should only be updated when the chip is in this state. The RX state will be active

Bits Name Description

7 CHIP_RDYn Stays high until power and crystal have stabilized. Should always be low when using

6:4 STATE[2:0] Indicates the current main state machine mode

3:0 FIFO_BYTES_AVAILABLE[3:0] The number of bytes available in the RX FIFO or free bytes in the TX FIFO

the SPI interface.

Value State Description

000 IDLE Idle state

001 RX Receive mode

010 TX Transmit mode

011 FSTXON Frequency synthesizer is on, ready to start

100 CALIBRATE Frequency synthesizer calibration is running

101 SETTLING PLL is settling

110 RXFIFO_OVERFLOW RX FIFO has overflowed. Read out any

111 TXFIFO_UNDERFLOW TX FIFO has underflowed. Acknowledge with

(depends on the read/write-bit). If FIFO_BYTES_AVAILABLE=15, there are 15 or more bytes in RX FIFO or 49 or less bytes in the TX FIFO.

(Also reported for some transitional states instead of SETTLING or CALIBRATE)

transmitting

useful data, then flush the FIFO with

SFTX

SFRX

Table 17: Status byte summary

10.2 Register Access

The configuration registers of the located on SPI addresses from

CC2500

0x00

are

0x2F

. Table 35 on page 52 lists all configuration registers. The detailed description of each register is found in Section 31.1, starting on page 55. All configuration registers can be both written to and read. The read/write bit controls if the register should be written to or

PRELIMINARY Data Sheet (Rev.1.2) SWRS040A Page 21 of 83

read. When writing to registers, the status byte

is sent on the or data byte is transmitted on the

pin each time a header byte

pin. When reading from registers, the status byte is sent on the transmitted on the

pin each time a header byte is

pin.

Registers with consecutive addresses can be accessed in an efficient way by setting the

burst bit in the address header. The address sets the start address in an internal address counter. This counter is incremented by one each new byte (every 8 clock pulses). The burst access is either a read or a write access

CSn

and must be terminated by setting

For register addresses in the range 0x300x3D, the “burst” bit is used to select between status registers and command strobes (see below). The status registers can only be read. Burst read is not available for status registers, so they must be read one at a time.

10.3 SPI Read

When reading register fields over the SPI interface while the register fields are updated by the radio hardware (e.g. MARCSTATE or TXBYTES), there is a small, but finite, probability that a single read from the register is being corrupt. As an example, the probability of any single read from TXBYTES being corrupt, assuming the maximum data rate is used, is approximately 80 ppm. Refer to

CC2500

the

10.4 Command Strobes

Command strobes may be viewed as single byte instructions to command strobe register, internal sequences will be started. These commands are used to disable the crystal oscillator, enable receive mode, enable wake-on-radio etc. The 14 command strobes are listed in Table 34 on page 51.

The command strobe registers are accessed in the same way as for a register write operation, but no data is transferred. That is, only the R/W bit (set to 0), burst access (set to

0) and the six address bits (in the range 0x30 through 0x3D) are written.

When writing command strobes, the status byte is sent on the

A command strobe may be followed by any other SPI access without pulling After issuing an next command strobe can be issued when the

pin goes low as shown in Figure 9. The command strobes are executed immediately, with the exception of the strobes that are executed when high.

Errata Note for more details.

CC2500

SRES

. By addressing a

pin.

command strobe the

SPWD

and the

high.

CSn

high.

SXOFF

goes

CC2500

Figure 9: SRES command strobe

10.5 FIFO Access

The 64-byte TX FIFO and the 64-byte RX FIFO are accessed through the 0x3F address. When the read/write bit is zero, the TX FIFO is accessed, and the RX FIFO is accessed when the read/write bit is one.

The TX FIFO is write-only, while the RX FIFO is read-only.

The burst bit is used to determine if FIFO access is single byte or a burst access. The single byte access method expects address with burst bit set to zero and one data byte. After the data byte a new address is expected;

CSn

hence, method expects one address byte and then consecutive data bytes until terminating the access by setting

The following header bytes access the FIFOs:

•

When writing to the TX FIFO, the status byte (see Section 10.1) is output for each new data byte on byte can be used to detect TX FIFO underflow while writing data to the TX FIFO. Note that the status byte contains the number of bytes

before

free TX FIFO. When the last byte that fits in the TX FIFO is transmitted to the byte received concurrently on the indicate that one byte is free in the TX FIFO.

The transmit FIFO may be flushed by issuing a

SFTX

command strobe will flush the receive FIFO. A

SFTX

issued in the IDLE, TXFIFO_UNDERLOW or RXFIFO_OVERFLOW state. Both FIFOs are flushed when going to the SLEEP state.

can remain low. The burst access

CSn

high.

0x3F: Single byte access to TX FIFO

0x7F: Burst access to TX FIFO

0xBF: Single byte access to RX FIFO

0xFF: Burst access to RX FIFO

, as shown in Figure 7. This status

writing the byte in progress to the

pin, the status

pin will

command strobe. Similarly, a

SFRX

command strobe can only be

SFRX

PRELIMINARY Data Sheet (Rev.1.2) SWRS040A Page 22 of 83

CC2500

10.6 PATABLE Access

The 0x3E address is used to access the

PATABLE

power control settings. The SPI expects up to eight data bytes after receiving the address. By programming the power ramp-up and ramp-down can be achieved. See Section 24 on page 42 for output power programming details.

The the PA control settings to use for each of the eight PA power values (selected by the 3-bit value written and read from the lowest setting (0) to the highest (7), one byte at a time. An index counter is used to control the access to the table. This counter is incremented each time a byte is read or written to the table, and set to

, which is used for selecting PA

PATABLE

is an 8-byte table that defines

FREND0.PA_POWER

PATABLE

, controlled PA

). The table is

the lowest index when highest value is reached the counter restarts at 0.

The access to the byte or burst access depending on the burst bit. When using burst access the index counter will count up; when reaching 7 the counter will restart at 0. The read/write bit controls whether the access is a write access (R/W=0) or a read access (R/W=1).

If one byte is written to the value is to be read out then high before the read access in order to set the index counter back to zero.

Note that the content of the when entering the SLEEP state, except for the first byte (index 0).

11 Microcontroller Interface and Pin Configuration

In a typical system, microcontroller. This microcontroller must be able to:

CC2500

will interface to a

In the synchronous and asynchronous serial modes, the data input pin while in transmit mode.

CSn

is high. When the

PATABLE

GDO0

pin is used as a serial TX

is either single

PATABLE

CSn

must be set

PATABLE

and this

is lost

•

Program

•

Read and write buffered data

•

Read back status information via the 4-wire

SPI-bus configuration interface (

SCLK

11.1 Configuration Interface

The microcontroller uses four I/O pins for the SPI configuration interface (

CSn

). The SPI is described in Section 10 on

page 19.

11.2 General Control and Status Pins

The

CC2500

pins and one shared pin that can output internal status information useful for control software. These pins can be used to generate interrupts on the MCU. See Section 28 on page 46 for more details on the signals that can be programmed. The dedicated pins are called

pin in the SPI interface. The default setting for

GDO1/SO

any other of the programming options the

GDO1/SO CSn

is low, the pin will always function as a

normal

CC2500

and

CSn

has two dedicated configurable

GDO0

and

is 3-state output. By selecting

pin will become a generic pin. When

pin.

into different modes

)

SI, SO, SCLK

GDO2

. The shared pin is the

SI, SO

and

GDO0

The analog temperature sensor. By measuring the voltage on the the temperature can be calculated. Specifications for the temperature sensor are found in Section 4.7 on page 12.

With default temperature sensor output is only available when the frequency synthesizer is enabled (e.g. the MANCAL, FSTXON, RX and TX states). It is necessary to write 0xBF to the

PTEST

sensor in the IDLE state. Before leaving the IDLE state, the restored to its default value (0x7F).

11.3 Optional Radio Control Feature

The the radio, by reusing the SPI interface. This feature allows for a simple three-pin control of the major states of the radio: SLEEP, IDLE, RX and TX.

This optional functionality is enabled with the

MCSM0.PIN_CTRL_EN

State changes are commanded as follows: When the desired state according to Table 18. When

CSn

latched and a command strobe is generated

pin can also be used for an on-chip

GDO0

pin with an external ADC,

PTEST

CC2500

goes low the state of SI and

has an optional way of controlling

CSn

is high the SI and

PTEST

SI, SCLK

configuration bit.

and

SCLK

CSn

is set to

SCLK

from

PRELIMINARY Data Sheet (Rev.1.2) SWRS040A Page 23 of 83

CC2500

internally according to the control coding. It is only possible to change state with this functionality. That means that for instance RX will not be restarted if RX and and

CSn

toggles. When

SCLK

has normal SPI functionality.

and

CSn

SCLK

are set to

is low the SI

All pin control command strobes are executed immediately, except the delayed until

CSn

goes high.

SPWD

strobe, which is

12 Data Rate Programming

The data rate used when transmitting, or the data rate expected in receive is programmed by the

MDMCFG4.DRATE_E

The data rate is given by the formula below. As the formula shows, the programmed data rate depends on the crystal frequency.

R ⋅

DATA

The following approach can be used to find suitable values for a given data rate:

MDMCFG3.DRATE_M

and the

configuration registers.

()

⎢

log_

EDRATE

⎢ ⎢

⎣

MDRATE

XOSC

MDRATE

⎛

⎜ ⎜

⎝

DATA

⋅

DATA

2_256

⋅+

⋅

XOSC

EDRATE

XOSC

⎥

⎞

⋅

⎟

⎥

⎟

⎥

⎠

⎦

−

256

EDRATE

CSn SCLK SI

1 X X

↓ ↓ ↓ ↓

0 0

0 1

1 0

1 1

SPI

mode

SPI

mode

Function

Chip unaffected by

SCLK/SI

Generates

SPI mode (wakes up into IDLE if in SLEEP/XOFF)

SPWD STX SIDLE SRX

strobe

Table 18: Optional pin c ontro l coding

DRATE_M

If and becomes 256, increment use

DRATE_M

is rounded to the nearest integer

DRATE_E

and

=0.

The data rate can be set from 1.2 kbps to 500 kbps with the minimum step size of:

Data rate

start

[kbps]

0.8 1.2/2.4 3.17 0.0062

3.17 4.8 6.35 0.0124

6.35 9.6 12.7 0.0248

12.7 19.6 25.4 0.0496

25.4 38.4 50.8 0.0992

50.8 76.8 101.6 0.1984

101.6 153.6 203.1 0.3967

203.1 250 406.3 0.7935

406.3 500 500 1.5869

Typical

data rate

[kbps]

Data rate

stop [kbps]

Data rate step size

[kbps]

Table 19: Data rate step size

13 Receiver Channel Filter Bandwidth

In order to meet different channel width requirements, the receiver channel filter is programmable. The

MDMCFG4.CHANBW_M

control the receiver channel filter bandwidth, which scales with the crystal oscillator frequency. The following formula gives the relation between the register settings and the channel filter bandwidth:

MDMCFG4.CHANBW_E

and

configuration registers

PRELIMINARY Data Sheet (Rev.1.2) SWRS040A Page 24 of 83

channel

The

CC2500

supports the following channel

filter bandwidths:

XOSC

ECHANBW

MCHANBW

2)·_4(8 +⋅

CC2500

MDMCFG4. MDMCFG4.CHANBW_E

CHANBW_M 00 01 10 11

00 812 406 203 102 01 650 325 162 81 10 541 270 135 68 11 464 232 116 58

Table 20: Channel filter bandwidths [kHz]

(assuming a 26 MHz crystal)

For best performance, the channel filter bandwidth should be selected so that the signal bandwidth occupies at most 80% of the channel filter bandwidth. The channel centre

tolerance due to crystal accuracy should also be subtracted from the signal bandwidth. The following example illustrates this:

With the channel filter bandwidth set to 600 kHz, the signal should stay within 80% of 600 kHz, which is 480 kHz. Assuming 2.44 GHz frequency and ±20 ppm frequency uncertainty for both the transmitting device and the receiving device, the total frequency uncertainty is ±40 ppm of 2.44 GHz, which is ±98 kHz. If the whole transmitted signal bandwidth is to be received within 480 kHz, the transmitted signal bandwidth should be maximum 480 kHz – 2·98 kHz, which is 284 kHz.

14 Demodulator, Symbol Synchronizer and Data Decision

CC2500

configurable demodulator. Channel filtering and frequency offset compensation is performed digitally. To generate the RSSI level (see Section 17.3 for more information) the signal level in the channel is estimated. Data filtering is also included for enhanced performance.

14.1 Frequency Offset Compensation

When using FSK, GFSK or MSK modulation, the demodulator will compensate for the offset between the transmitter and receiver frequency, within certain limits, by estimating the centre of the received data. This value is available in the Writing the value from

FSCTRL0.FREQOFF

synthesizer is automatically adjusted according to the estimated frequency offset.

Note that frequency offset compensation is not supported for OOK modulation.

14.2 Bit Synchronization

The bit synchronization algorithm extracts the clock from the incoming symbols. The algorithm requires that the expected data rate is programmed as described in Section 12 on page 24. Re-synchronization is performed continuously to adjust for error in the incoming symbol rate.

contains an advanced and highly

FREQEST

status register.

FREQEST

the frequency

into

14.3 Byte Synchronization

Byte synchronization is achieved by a continuous sync word search. The sync word is a 16 or 32 bit configurable field that is automatically inserted at the start of the packet by the modulator in transmit mode. The demodulator uses this field to find the byte boundaries in the stream of bits. The sync word will also function as a system identifier, since only packets with the correct predefined sync word will be received. The sync word detector correlates against the user-configured 16-bit sync word. The correlation threshold can be set to 15/16 bits match or 16/16 bits match. The sync word can be further qualified using the preamble quality indicator mechanism described below and/or a carrier sense condition. The sync word is programmed with

In order to make false detections of sync words less likely, a mechanism called preamble quality indication (PQI) can be used to qualify the sync word. A threshold value for the preamble quality must be exceeded in order for a detected sync word to be accepted. See Section 17.2 on page 31 for more details.

SYNC1

and

SYNC0.

PRELIMINARY Data Sheet (Rev.1.2) SWRS040A Page 25 of 83

15 Packet Handling Hardw are Support

The

CC2500

packet oriented radio protocols.

In transmit mode, the packet handler will add the following elements to the packet stored in the TX FIFO:

•

A programmable number of preamble

bytes.

•

A two byte synchronization (sync) word.

Can be duplicated to give a 4-byte sync word.

•

Optionally whiten the data with a PN9

sequence.

•

Optionally Interleave and Forward Error

Code the data.

•

Optionally compute and add a CRC

checksum over the data field.

•

The recommended setting is 4-byte

preamble and 4-byte sync word except for 500 kbps data rate where the recommended preamble length is 8 bytes.

In receive mode, the packet handling support will de-construct the data packet:

•

Preamble detection.

•

Sync word detection.

•

Optional one byte address check.

•

Optionally compute and check CRC.

•

Optionally append two status bytes (see

Table 21 and Table 22) with RSSI value, Link Quality Indication and CRC status.

Bit Field name Description

7:0 RSSI RSSI value

Table 21: Received packet status byte 1

(first byte appended after the data)

has built-in hardware support for

CC2500

Bit Field name Description

7 CRC_OK 1: CRC for received data OK (or

6:0 LQI The Link Quality Indicator

Table 22: Received packet status byte 2

(second byte appended after the data)

Note that register fields that control the packet handling features should only be altered when

CC2500

15.1 Data Whitening

From a radio perspective, the ideal over the air data are random and DC free. This results in the smoothest power distribution over the occupied bandwidth. This also gives the regulation loops in the receiver uniform operation conditions (no data dependencies).

Real world data often contain long sequences of zeros and ones. Performance can then be improved by whitening the data before transmitting, and de-whitening in the receiver. With by setting data, except the preamble and the sync word, are then XOR-ed with a 9-bit pseudo-random (PN9) sequence before being transmitted as shown in Figure 10. At the receiver end, the data are XOR-ed with the same pseudorandom sequence. This way, the whitening is reversed, and the original data appear in the receiver.

Data whitening can only be used when

PKTCTRL0.CC2400_EN

is in the IDLE state.

CC2500

CRC disabled)

0: CRC error in received data

estimates how easily a received signal can be demodulated

, this can be done automatically

PKTCTRL0.WHITE_DATA=1

= 0 (default).

. All

PRELIMINARY Data Sheet (Rev.1.2) SWRS040A Page 26 of 83

+ 58 hidden pages

TEXAS INSTRUMENTS CC2500 Technical data

Specifications and Main Features

Frequently Asked Questions

User Manual

Abbreviations

Current consumption

4.3 RF Transmit Section

4.5 Low Power RC Oscillator

4.6 Frequency Synthesizer Characteristics

4.7 Analog Temperature Sensor