Texas Instruments CC1111F32, CC1110 Datasheet

CC1110Fx / CC1111Fx

SWRS033E Page 1 of 239

Low-power sub-1 GHz RF System-on-Chip (SoC) with MCU, memory, transceiver, and USB controller

Applications

• Low-power SoC wireless applications

operating in the 315/433/868/915 MHz ISM/SRD bands

• Wireless alarm and security systems

• Industrial monitoring and control

• Wireless sensor networks

• AMR – Automatic Meter Reading

• Home and building automation

• Low power telemetry

•

CC1111Fx

: USB dongles

Product Description

The

CC1110Fx/CC1111Fx

is a true low-power sub1 GHz system-on-chip (SoC) designed for lowpower wireless applications. The

CC1110Fx/CC1111Fx

combines the excellent performance of the state-of-the-art RF transceiver

CC1101

with an industry-standard enhanced 8051 MCU, up to 32 kB of in-system programmable flash memory and up to 4 kB of RAM, and many other powerful features. The small 6x6 mm package makes it very suited for applications with size limitations.

The

CC1110Fx/CC1111Fx

is highly suited for systems where very low power consumption is required. This is ensured by several advanced low-power operating modes. The

CC1111Fx

adds a full-speed USB 2.0 interface to the feature set of the

CC1110Fx

. Interfacing to a PC using the USB interface is quick and easy, and the high data rate (12 Mbps) of the USB interface avoids the bottlenecks of RS-232 or low-speed USB interfaces.

RESET_N

P2_4

P2_3

P2_2

P2_1

P2_0

P1_4

P1_3

P1_2

P1_1

P1_0

P1_7

P1_6

P1_5

P0_4

P0_3

P0_2

P0_1

P0_0

P0_5

RF_P RF_N

XOSC_Q2

XOSC_Q1

VDD (2.0 - 3.6 V)

DCOUPL

DIGITAL

ANALOG

MIXED

P0_7

P0_6

Key Features

• Radio

o High-performance RF transceiver based on

the market-leading

CC1101

o Excellent receiver selectivity and blocking

performance

o High sensitivity (-110 dBm at 1.2 kBaud) o Programmable data rate up to 500 kBaud o Programmable output power up to +10 dBm

for all supported frequencies

o Frequency range: 300-348 MHz, 391-464

MHz and 782-928 MHz

o Digital RSSI / LQI support

• Low Power

o Low current consumption (RX: 16.2 mA @

1.2 kBaud, TX: 16 mA @ -6 dBm output power)

o 0.3 µA in PM3 (operating mode with the

lowest power consumption, only external interrupt wakeup)

o 0.5 µA in PM2 (operating mode with the

second lowest power consumption, timer or external interrupt wakeup)

• MCU, Memory, and Peripherals

o High performance and low power 8051

microcontroller core.

o Powerful DMA functionality o 8/16/32 KB in-system programmable flash,

and 1/2/4 KB RAM

o Full-Speed USB Controller with 1 KB FIFO

(

CC1111Fx

)

o 128-bit AES security coprocessor o 7-12 bit ADC with up to eight inputs o I

S interface

o Two USARTs o 16-bit timer with DSM mode o Three 8-bit timers o Hardware debug support o 21 (

CC1110Fx

) or 19 (

CC1111Fx

) GPIO pins

o SW compatible with

CC2510Fx/CC2511Fx

• General

o Wide supply voltage range (2.0V – 3.6V) o RoHS compliant 6x6 mm QLP36 package

CC1110Fx / CC1111Fx

SWRS033E Page 2 of 239

Table of Contents

1 ABBREVIATION...................................................................................................................................... 4

2 REGISTER CONVENTIONS.................................................................................................................. 5

3 KEY FEATURES (IN MORE DETAILS) ..............................................................................................6

3.1 HIGH-PERFORMANCE AND LOW-POWER 8051-COMPATIBLE MICROCONTROLLER....................................... 6

3.2 8/16/32 KB NON-VOLATILE PROGRAM MEMORY AND 1/2/4 KB DATA MEMORY ........................................6

3.3 FULL-SPEED USB CONTROLLER (

CC1111F

)................................................................................................. 6

3.4 I2S INTERFACE.............................................................................................................................................. 6

3.5 HARDWARE AES ENCRYPTION/DECRYPTION............................................................................................... 6

3.6 PERIPHERAL FEATURES ................................................................................................................................6

3.7 LOW POWER ................................................................................................................................................. 6

3.8 SUB-1 GHZ RADIO WITH BASEBAND MODEM ..............................................................................................6

4 ABSOLUTE MAXIMUM RATINGS...................................................................................................... 8

5 OPERATING CONDITIONS ..................................................................................................................8

5.1

CC1110F

OPERATING CONDITIONS ............................................................................................................... 8

5.2

CC1111F

OPERATING CONDITIONS ............................................................................................................... 8

6 GENERAL CHARACTERISTICS.......................................................................................................... 9

7 ELECTRICAL SPECIFICATIONS ...................................................................................................... 10

7.1 CURRENT CONSUMPTION ........................................................................................................................... 10

7.2 RF RECEIVE SECTION ................................................................................................................................. 14

7.3 RF TRANSMIT SECTION ..............................................................................................................................18

7.4 CRYSTAL OSCILLATORS ............................................................................................................................. 20

7.5 32.768 KHZ CRYSTAL OSCILLATOR ........................................................................................................... 21

7.6 LOW POWER RC OSCILLATOR.................................................................................................................... 21

7.7 HIGH SPEED RC OSCILLATOR .................................................................................................................... 22

7.8 FREQUENCY SYNTHESIZER CHARACTERISTICS ........................................................................................... 22

7.9 ANALOG TEMPERATURE SENSOR ............................................................................................................... 23

7.10 7-12 BIT ADC............................................................................................................................................. 23

7.11 CONTROL AC CHARACTERISTICS ...............................................................................................................25

7.12 SPI AC CHARACTERISTICS......................................................................................................................... 26

7.13 DEBUG INTERFACE AC CHARACTERISTICS ................................................................................................ 27

7.14 PORT OUTPUTS AC CHARACTERISTICS ...................................................................................................... 27

7.15 TIMER INPUTS AC CHARACTERISTICS ........................................................................................................28

7.16 DC CHARACTERISTICS ............................................................................................................................... 28

8 PIN AND I/O PORT CONFIGURATION ............................................................................................ 29

9 CIRCUIT DESCRIPTION ..................................................................................................................... 33

9.1 CPU AND PERIPHERALS ............................................................................................................................. 34

9.2 RADIO ........................................................................................................................................................ 36

10 APPLICATION CIRCUIT..................................................................................................................... 36

10.1 BIAS RESISTOR ...........................................................................................................................................36

10.2 BALUN AND RF MATCHING........................................................................................................................ 36

10.3 CRYSTAL ....................................................................................................................................................36

10.4 USB (

CC1111F

) ..........................................................................................................................................37

10.5 POWER SUPPLY DECOUPLING ..................................................................................................................... 37

10.6 PCB LAYOUT RECOMMENDATIONS............................................................................................................ 40

11 8051 CPU.................................................................................................................................................. 41

11.1 8051 INTRODUCTION .................................................................................................................................. 41

11.2 MEMORY ....................................................................................................................................................42

11.3 CPU REGISTERS ......................................................................................................................................... 54

11.4 INSTRUCTION SET SUMMARY ..................................................................................................................... 56

11.5 INTERRUPTS................................................................................................................................................ 61

12 DEBUG INTERFACE............................................................................................................................. 71

12.1 DEBUG MODE............................................................................................................................................. 71

12.2 DEBUG COMMUNICATION........................................................................................................................... 71

12.3 DEBUG LOCK BIT ....................................................................................................................................... 72

12.4 DEBUG COMMANDS.................................................................................................................................... 73

CC1110Fx / CC1111Fx

SWRS033E Page 3 of 239

13 PERIPHERALS....................................................................................................................................... 77

13.1 POWER MANAGEMENT AND CLOCKS.......................................................................................................... 77

13.2 RESET ......................................................................................................................................................... 84

13.3 FLASH CONTROLLER .................................................................................................................................. 85

13.4 I/O PORTS................................................................................................................................................... 91

13.5 DMA CONTROLLER ................................................................................................................................. 102

13.6 16-BIT TIMER, TIMER 1............................................................................................................................. 114

13.7 MAC TIMER (TIMER 2) ............................................................................................................................126

13.8 SLEEP TIMER ............................................................................................................................................ 128

13.9 8-BIT TIMERS, TIMER 3 AND TIMER 4 ....................................................................................................... 131

13.10 ADC......................................................................................................................................................... 141

13.11 RANDOM NUMBER GENERATOR............................................................................................................... 147

13.12 AES COPROCESSOR.................................................................................................................................. 149

13.13 WATCHDOG TIMER................................................................................................................................... 151

13.14 USART.................................................................................................................................................... 153

13.15 I2S ............................................................................................................................................................ 162

13.16 USB CONTROLLER................................................................................................................................... 169

14 RADIO.................................................................................................................................................... 185

14.1 COMMAND STROBES ................................................................................................................................185

14.2 RADIO REGISTERS .................................................................................................................................... 187

14.3 INTERRUPTS.............................................................................................................................................. 187

14.4 TX/RX DATA TRANSFER ......................................................................................................................... 189

14.5 DATA RATE PROGRAMMING..................................................................................................................... 190

14.6 RECEIVER CHANNEL FILTER BANDWIDTH ................................................................................................ 190

14.7 DEMODULATOR, SYMBOL SYNCHRONIZER, AND DATA DECISION ............................................................ 191

14.8 PACKET HANDLING HARDWARE SUPPORT ............................................................................................... 192

14.9 MODULATION FORMATS........................................................................................................................... 195

14.10 RECEIVED SIGNAL QUALIFIERS AND LINK QUALITY INFORMATION ......................................................... 196

14.11 FORWARD ERROR CORRECTION WITH INTERLEAVING.............................................................................. 199

14.12 RADIO CONTROL ...................................................................................................................................... 200

14.13 FREQUENCY PROGRAMMING ....................................................................................................................203

14.14 VCO......................................................................................................................................................... 203

14.15 OUTPUT POWER PROGRAMMING .............................................................................................................. 204

14.16 SHAPING AND PA RAMPING ..................................................................................................................... 204

14.17 SELECTIVITY ............................................................................................................................................ 206

14.18 SYSTEM CONSIDERATIONS AND GUIDELINES ............................................................................................ 206

14.19 RADIO REGISTERS .................................................................................................................................... 209

15 VOLTAGE REGULATORS ................................................................................................................226

15.1 VOLTAGE REGULATOR POWER-ON........................................................................................................... 226

16 RADIO TEST OUTPUT SIGNALS..................................................................................................... 226

17 REGISTER OVERVIEW..................................................................................................................... 227

18 PACKAGE DESCRIPTION (QLP 36)................................................................................................ 231

18.1 RECOMMENDED PCB LAYOUT FOR PACKAGE (QLP 36) ..........................................................................232

18.2 SOLDERING INFORMATION........................................................................................................................ 232

18.3 TRAY SPECIFICATION ............................................................................................................................... 232

18.4 CARRIER TAPE AND REEL SPECIFICATION ................................................................................................233

19 ORDERING INFORMATION............................................................................................................. 234

20 REFERENCES ......................................................................................................................................235

21 GENERAL INFORMATION............................................................................................................... 236

21.1 DOCUMENT HISTORY ............................................................................................................................... 236

21.2 PRODUCT STATUS DEFINITIONS ............................................................................................................... 237

22 ADDRESS INFORMATION................................................................................................................ 238

23 TI WORLDWIDE TECHNICAL SUPPORT..................................................................................... 238

CC1110Fx / CC1111Fx

SWRS033E Page 4 of 239

1 Abbreviation

∆Σ

Delta-Sigma

ADC Analog to Digital Converter

AES Advanced Encryption Standard

AGC Automatic Gain Control

ARIB

Association of Radio Industries and Businesses

ASK Amplitude Shift Keying

BCD Binary Coded Decimal

BER Bit Error Rate

BOD Brown Out Detector

CBC Cipher Block Chaining

CBC-MAC

Cipher Block Chaining Message Authentication Code

CCA Clear Channel Assessment

CCM Counter mode + CBC-MAC

CFB Cipher Feedback

CFR Code of Federal Regulations

CMOS Complementary Metal Oxide Semiconductor

CPU Central Processing Unit

CRC Cyclic Redundancy Check

CTR Counter mode (encryption)

DAC Digital to Analog Converter

DMA Direct Memory Access

DSM Delta-Sigma Modulator

ECB Electronic Code Book

EM Evaluation Module

ENOB Effective Number of Bits

EP{0-5} USB Endpoints 0 – 5

ESD Electro Static Discharge

ESR Equivalent Series Resistance

ETSI

European Telecommunications Standard Institute

FCC Federal Communications Commision

FIFO First In First Out

GPIO General Purpose Input / Output

HSSD High Speed Serial Debug

HW HardWare

I/O Input / Output

I/Q In-phase / Quadrature-phase

S Inter-IC Sound

IF Intermediate Frequency

IOC I/O Controller

ISM Industrial, Scientific and Medical

ISR Interrupt Service Routine

IV Initialization Vector

JEDEC Joint Electron Device Engineering Council

KB Kilo Bytes (1024 bytes)

kbps kilo bits per second

LFSR Linear Feedback Shift Register

LNA Low-Noise Amplifier

LO Local Oscillator

LQI Link Quality Indication

LSB Least Significant Bit / Byte

MAC Medium Access Control

MCU Microcontroller Unit

MISO Master In Slave Out

MOSI Master Out Slave In

MSB Most Significant Bit / Byte

NA Not Applicable

OFB Output Feedback (encryption)

OOK On-Off Keying

PA Power Amplifier

PCB Printed Circuit Board

PER Packet Error Rate

PLL Phase Locked Loop

PM{0-3} Power Mode 0-3

PMC Power Management Controller

POR Power On Reset

PQI Preamble Quality Indicator

PWM Pulse Width Modulator

QLP Quad Leadless Package

RAM Random Access Memory

RCOSC RC Oscillator

RF Radio Frequency

RoHS Restriction on Hazardous Substances

RSSI Receive Signal Strength Indicator

RX Receive

SCK Serial Clock

SFD Start of Frame Delimiter

SFR Special Function Register

SINAD Signal-to-noise and distortion ratio

SPI Serial Peripheral Interface

SRAM Static Random Access Memory

SW SoftWare

T/R Transmit / Receive

TX Transmit

UART Universal Asynchronous Receiver/Transmitter

USART

Universal Synchronous/Asynchronous Receiver/Transmitter

USB Universal Serial Bus

VCO Voltage Controlled Oscillator

VGA Variable Gain Amplifier

WDT Watchdog Timer

XOSC Crystal Oscillator

CC1110Fx / CC1111Fx

SWRS033E Page 5 of 239

2 Register Conventions

Each SFR is described in a separate table. The table heading is given in the following format:

Each RF register is described in a separate table. The table heading is given in the following format:

XDATA Address: REGISTER NAME - Register Description

All register descriptions include a symbol denoted R/W describing the accessibility of each bit in the register. The register values are always given in binary notation unless prefixed by ‘0x’, which indicates hexadecimal notation.

Symbol Access Mode

R/W Read/write

R Read only

R0 Read as 0

R1 Read as 1

W Write only

W0 Write as 0

W1 Write as 1

H0 Hardware clear

H1 Hardware set

Table 1: Register Bit Conventions

CC1110Fx / CC1111Fx

SWRS033E Page 6 of 239

3 Key Features (in more details)

3.1 High-Performance and Low-Power

8051-Compatible Microcontroller

• Optimized 8051 core which typically

gives 8x the performance of a standard 8051

• Two data pointers

• In-circuit interactive debugging is

supported by the IAR Embedded Workbench through a simple two-wire serial interface

• SW compatible with

CC2510Fx/CC2511Fx

3.2 8/16/32 KB Non-volatile Program

Memory and 1/2/4 kB Data Memory

• 8, 16, or 32 KB of non-volatile flash

memory, in-system programmable through a simple two-wire interface or by the 8051 core

• Minimum flash memory endurance:

1000 write/erase cycles

• Programmable read and write lock of

portions of flash memory for software security

• 1, 2, or 4 kB of internal SRAM

3.3 Full-Speed USB Controller (

CC1111Fx

)

• 5 bi-directional endpoints in addition to

control endpoint 0

• Full-Speed, 12 Mbps transfer rate

• Support for Bulk, Interrupt, and

Isochronous endpoints

• 1024 bytes of dedicated endpoint FIFO

memory

• 8 – 512 byte data packet size supported

• Configurable FIFO size for IN and OUT

direction of endpoint

3.4 I

S Interface

• Industry standard I

S interface for

transfer of digital audio data

• Full duplex

• Mono and stereo support

• Configurable sample rate and sample

size

• Support for µ-law compression and

expansion

• Typically used to connect to external

DAC or ADC

3.5 Hardware AES Encryption/Decryption

• 128-bit AES supported in hardware

coprocessor

3.6 Peripheral Features

• Powerful DMA Controller

• Power On Reset/Brown-Out Detection

• ADC with eight individual input

channels, single-ended or differential (

CC1111Fx

has six channels) and

configurable resolution

• Programmable watchdog timer

• Five timers: one general 16-bit timer

with DSM mode, two general 8-bit timers, one MAC timer, and one sleep timer

• Two programmable USARTs for

master/slave SPI or UART operation

• 21 configurable general-purpose digital

I/O-pins (

CC1111Fx

has 19)

• Random number generator

3.7 Low Power

• Four flexible power modes for reduced

power consumption

• System can wake up on external

interrupt or when the Sleep Timer expires

• 0.5 µA current consumption in PM2,

where external interrupts or the Sleep Timer can wake up the system

• 0.3 µA current consumption in PM3,

where external interrupts can wake up the system

• Low-power fully static CMOS design

• System clock source is either a high

speed crystal oscillator (26 – 27 MHz for

CC1110Fx

and 48 MHz for

CC1111Fx

) or a high speed RC oscillator (13 – 13.5 MHz for

CC1110Fx

and 12 MHz for

CC1111Fx

). The high speed crystal oscillator must be used when the radio is active.

• Clock source for ultra-low power

operation can be either a low-power RC oscillator or an optional 32.768 kHz crystal oscillator

• Very fast transition to active mode from

power modes enables ultra low average power consumption in low duty-cycle systems

3.8 Sub-1 GHz Radio with Baseband Modem

• Based on the industry leading

CC1101

radio core

• Few external components: No external

filters or RF switch needed, on-chip frequency synthesizer

CC1110Fx / CC1111Fx

SWRS033E Page 7 of 239

• Flexible support for packet oriented

systems: On-chip support for sync word detection, address check, flexible packet length, and automatic CRC handling

• Supports use of DMA for both RX and

TX resulting in minimal CPU intervention even on high data rates

• Programmable channel filter bandwidth

• 2-FSK, GFSK, MSK, ASK, and OOK

modulation formats supported

• Optional automatic whitening and de-

whitening of data

• Programmable Carrier Sense (CS)

indicator

• Programmable Preamble Quality

Indicator (PQI) for detecting preambles and improved protection against sync word detection in random noise

• Support for automatic Clear Channel

Assessment (CCA) before transmitting (for listen-before-talk systems)

• Support for per-package Link Quality

Indication (LQI)

CC1110Fx / CC1111Fx

SWRS033E Page 8 of 239

4 Absolute Maximum Ratings

Under no circumstances must the absolute maximum ratings given in Table 2 be violated. Stress exceeding one or more of the limiting values may cause permanent damage to the device.

Parameter Min Max Units Condition

Supply voltage (VDD) -0.3 3.9 V All supply pins must have the same voltage

Voltage on any digital pin -0.3 VDD + 0.3,

max 3.9

Voltage on the pins RF_P, RF_N and DCOUPL

-0.3 2.0 V

Voltage ramp-up rate 120 kV/µs

Input RF level +10 dBm

Storage temperature range -50 150

°C

Device not programmed

Solder reflow temperature 260

°C

According to IPC/JEDEC J-STD-020D

ESD

CC1110Fx

1000 V According to JEDEC STD 22, method A114, Human

Body Model (HBM)

ESD

CC1110Fx

750 V According to JEDEC STD 22, C101C, Charged Device

Model (CDM)

ESD

CC1111x

750 V According to JEDEC STD 22, method A114, Human

Body Model (HBM)

ESD

CC1111x

750 V According to JEDEC STD 22, C101C, Charged Device

Model (CDM)

Table 2: Absolute Maximum Ratings

Caution! ESD sensitive device. Precaution should be used when handling the device in order to prevent permanent damage.

5 Operating Conditions

5.1

CC1110Fx

Operating Conditions

The operating conditions for

CC1110Fx

are listed in Table 3 below.

Parameter Min Max Unit Condition

Operating ambient temperature, TA -40 85

°C

Operating supply voltage (VDD) 2.0 3.6 V All supply pins must have the same voltage

Table 3: Operating Conditions for

CC1110Fx

5.2

CC1111Fx

Operating Conditions

The operating conditions for

CC1111Fx

are listed in Table 4 below.

Parameter Min Max Unit Condition

Operating ambient temperature, TA 0 85

°C

Operating supply voltage (VDD) 3.0 3.6 V All supply pins must have the same voltage

Table 4: Operating Conditions for

CC1111Fx

CC1110Fx / CC1111Fx

SWRS033E Page 9 of 239

6 General Characteristics

TA = 25 °C, VDD = 3.0 V if nothing else stated

Parameter Min Typ Max Unit Condition/Note

Radio part

300 348 MHz

391 464 MHz

Frequency range

782 928 MHz

1.2 500 kBaud 2-FSK (500 kBaud only characterized @ 915 MHz on

CC1110Fx

)

1.2 250 kBaud GFSK, OOK, and ASK

Data rate

26 500 kBaud Shaped) MSK (also known as differential

offset QPSK) – 500 kBaud only characterized @ 915 MHz

Optional Manchester encoding (the data rate in kbps will be half the baud rate)

Wake-Up Timing

PM1 Æ Active Mode 4 µs Digital regulator on. HS RCOSC and high

speed crystal oscillator off. 32.768 kHz XOSC or low power RCOSC running.

SLEEP.OSC_PD=1 and CLKCON.OSC=1

PM2Æ Active Mode 100 µs Digital regulator off. HS RCOSC and high

speed crystal oscillator off. 32.768 kHz XOSC or low power RCOSC running

SLEEP.OSC_PD=1 and CLKCON.OSC=1

PM3Æ Active Mode 100 µs Digital regulator off. No crystal oscillators or

RC oscillators are running.

SLEEP.OSC_PD=1 and CLKCON.OSC=1

Table 5: General Characteristics

CC1110Fx / CC1111Fx

SWRS033E Page 10 of 239

7 Electrical Specifications

7.1 Current Consumption

= 25 °C, VDD = 3.0 V if nothing else stated. All measurement results are obtained using the

CC1110EM reference design ([1]).

Parameter Min Typ Max Unit Condition

Digital regulator on. High speed crystal oscillator and low power

RCOSC running. No peripherals running.

Low CPU activity: No flash access (i.e. only cache hit), no RAM access

5.0 mA System clock running at 26 MHz.

Active mode, full speed (high speed crystal oscillator)

Low CPU activity.

4.8 mA System clock running at 24 MHz.

CC1111Fx

runs on 48 MHz crystal giving 24 MHz system clock

Active mode, full speed (HS RCOSC)

Low CPU activity.

2.5 mA System clock running at 13 MHz.

Digital regulator on. HS RCOSC and low power RCOSC running. No peripherals running.

Low CPU activity: No flash access (i.e. only cache hit), no RAM access

Digital regulator on. High speed crystal oscillator and low power

RCOSC running. Radio in RX mode (sensitivity optimized MDMCFG2.DEM_DCFILT_OFF=1)

19.5

16.2

1.2 kBaud, input at sensitivity limit, system clock at 26 MHz.

1.2 kBaud, input at sensitivity limit, system clock at 24 MHz

1.2 kBaud, input at sensitivity limit, system clock at 203 kHz.

19.4

1.2 kBaud, input well above sensitivity limit, system clock at 26 MHz

1.2 kBaud, input well above sensitivity limit, system clock at 24 MHz

16.2

38.4 kBaud, input at sensitivity limit, system clock at 26 MHz.

38.4 kBaud, input at sensitivity limit, system clock at 203 kHz.

19 mA 38.4 kBaud, input well above sensitivity limit, system clock at 26 MHz.

17.2

250 kBaud, input at sensitivity limit, system clock at 26 MHz

250 kBaud, input at sensitivity limit, system clock at 24 MHz.

250 kBaud, input at sensitivity limit, system clock at 1.625 MHz.

Active mode with radio in RX, 315 MHz

250 kBaud, input well above sensitivity limit, system clock at 26 MHz.

250 kBaud, input well above sensitivity limit, system clock at 24 MHz.

Note: In order to reduce the current consumption in active mode, the clock speed can be reduced by

setting CLKCON.CLKSPD ≠ 000 (see section 13.1 for details). Figure 1 shows typical current consumption in active mode for different clock speeds

CC1110Fx / CC1111Fx

SWRS033E Page 11 of 239

Parameter Min Typ Max Unit Condition

Digital regulator on. High speed crystal oscillator and low power

RCOSC running. Radio in RX mode (sensitivity optimized MDMCFG2.DEM_DCFILT_OFF=1)

19.8

19.7

17.1

1.2 kBaud, input at sensitivity limit, system clock at 26 MHz.

1.2 kBaud, input at sensitivity limit, system clock at 24 MHz.

1.2 kBaud, input at sensitivity limit, system clock at 203 kHz.

19.8

19.7

1.2 kBaud, input well above sensitivity limit, system clock at 26 MHz.

1.2 kBaud, input well above sensitivity limit, system clock at 24 MHz.

19.8

17.1

38.4 kBaud, input at sensitivity limit, system clock at 26 MHz.

38.4 kBaud, input at sensitivity limit, system clock at 203 kHz

19.8 mA 38.4 kBaud, input well above sensitivity limit, system clock at 26 MHz.

20.5

21.5

18.1

250 kBaud, input at sensitivity limit, system clock at 26 MHz.

250 kBaud, input at sensitivity limit, system clock at 24 MHz.

250 kBaud, input at sensitivity limit, system clock at 1.625 MHz.

Active mode with radio in RX, 433 MHz

20.5

20.2

250 kBaud, input well above sensitivity limit, system clock at 26 MHz.

250 kBaud, input well above sensitivity limit, system clock at 24 MHz

See Figure 2 for typical variation over operating conditions

Digital regulator on. High speed crystal oscillator and low power

RCOSC running. Radio in RX mode (sensitivity optimized MDMCFG2.DEM_DCFILT_OFF=1). 24MHz system clock not measured

19.7

17.0

1.2 kBaud, input at sensitivity limit, system clock at 26 MHz.

1.2 kBaud, input at sensitivity limit, system clock at 203 kHz.

18.7 mA 1.2 kBaud, input well above sensitivity limit, system clock at 26 MHz.

19.7

17.0

38.4 kBaud, input at sensitivity limit, system clock at 26 MHz.

38.4 kBaud, input at sensitivity limit, system clock at 203 kHz.

18.7 mA 38.4 kBaud, input well above sensitivity limit, system clock at 26 MHz.

20.4

18.0

250 kBaud, input at sensitivity limit, system clock at 26 MHz.

250 kBaud, input at sensitivity limit, system clock at 1.625 MHz.

Active mode with radio in RX, 868, 915 MHz

19.1 mA 250 kBaud, input well above sensitivity limit, system clock at 26 MHz.

System clock running at 26 MHz or 24MHz.

Digital regulator on. High speed crystal oscillator and low power RCOSC running. Radio in TX mode

31.5 mA

+10 dBm output power (PA_TABLE0=0xC2)

19 mA

0 dBm output power (PA_TABLE0=0x51)

Active mode with radio in TX, 315 MHz

18 mA

-6 dBm output power (PA_TABLE0=0x2A)

CC1110Fx / CC1111Fx

SWRS033E Page 12 of 239

Parameter Min Typ Max Unit Condition

System clock running at 26 MHz or 24MHz.

Digital regulator on. High speed crystal oscillator and low power RCOSC running. Radio in TX mode

33.5 mA

+10 dBm output power (PA_TABLE0=0xC0)

20 mA

0 dBm output power (PA_TABLE0=0x60)

Active mode with radio in TX, 433 MHz

19 mA

-6 dBm output power (PA_TABLE0=0x2A)

System clock running at 26 MHz or 24MHz.

Digital regulator on. High speed crystal oscillator and low power RCOSC running. Radio in TX mode

36.2 mA

+10 dBm output power (PA_TABLE0=0xC2). See Table 7 for typical variation over operating conditions

21 mA

0 dBm output power (PA_TABLE0=0x50)

Active mode with radio in TX, 868, 915 MHz

20 mA

-6 dBm output power (PA_TABLE0=0x2B)

Power mode 0

4.3 mA Same as active mode, but the CPU is not running (see 13.1.2.2 for

details). System clock at 26 MHz or 24MHz

Power mode 1 220

µA

Digital regulator on. HS RCOSC and high speed crystal oscillator off.

32.768 kHz XOSC or low power RCOSC running (see 13.1.2.3 for details)

Power mode 2 0.5 µA Digital regulator off. HS RCOSC and high speed crystal oscillator off.

Low power RCOSC running (see 13.1.2.4 for details)

Power mode 3 0.3 1.0 µA Digital regulator off. No crystal oscillators or RC oscillators are

running (see 13.1.2.5 for details)

Peripheral Current Consumption

Add to the figures above if the peripheral unit is activated

Timer 1 2.7

µA/MHz

When running

Timer 2 1.3

µA/MHz

When running

Timer 3 1.6

µA/MHz

When running

Timer 4 2

µA/MHz

When running

ADC 1.2 mA When converting

Table 6: Current Consumption

CC1110Fx / CC1111Fx

SWRS033E Page 13 of 239

Figure 1: Current Consumption (Active Mode) vs. Clock Speed

Figure 2: Typical Variation in RX Current Consumption over Temperature and Input Power Level,

@ 433 MHz and 250 kBaud data rate.

Supply Voltage, VDD = 2 V Supply Voltage, VDD = 3 V Supply Voltage, VDD = 3.6 V

Temperature [°C] -40 +25 +85 -40 +25 +85 -40 +25 +85

Current [mA] 37 36 35.4 37.2 36.2 35.6 37.5 36.4 35.8

Table 7: Typical Variation in TX Current Consumption over Temperature and Supply Voltage,

@ 868 MHz and +10 dBm output power.

Current consumption Active Mode. No Peripherals Running. f

xosc

= 26MHz

0,0

1,0

2,0

3,0

4,0

5,0

6,0

0 2 4 6 8 10 12 14 16 18 20 22 24 26 28

Clock Speed [MHz]

Measurements done for all valid CLKCON.CLKSPD settings

(

000 – 111 for HS XOSC, 001 –111 for HS RCOSC

)

[

]

HS XOSC

HS RCOSC

RX current consumption, typical variation over temperature and input

power level

-110 -100

-90 -80

-70

-60 -50

-40 -30 -20 -10

Pin [dBm]

Current [mA]

Avg -40degC

Avg 25decC

vg 85degC

CC1110Fx / CC1111Fx

SWRS033E Page 14 of 239

7.2 RF Receive Section

= 25 °C, VDD = 3.0 V if nothing else stated. All measurement results are obtained using the

CC1110EM reference design ([1]) if nothing else is stated.

Parameter Min Typ Max Unit Condition/Note

Digital channel filter bandwidth

58 812 kHz User programmable (see section 14.6). The bandwidth limits are

proportional to crystal frequency (given values assume a 26MHz system clock).

315 MHz, 1.2 kBaud data rate, sensitivity optimized, MDMCFG2.DEM_DCFILT_OFF=0 (GSK, 1% packet error rate, 20 bytes packet length, 5.2 kHz deviation, 58 kHz digital channel filter bandwidth)

Receiver sensitivity

-110

-112

dBm

System clock running at 26 MHz

System clock running at 24MHz

The RX current consumption can be reduced by approximately 2.0 mA by setting MDMCFG2.DEM_DCFILT_OFF=1. The typical sensitivity is then

-107 dBm.

315 MHz, 38.4 kBaud data rate, sensitivity optimized, MDMCFG2.DEM_DCFILT_OFF=0 (GSK, 1% packet error rate, 20 bytes packet length, 20 kHz deviation, 100 kHz digital channel filter bandwidth)

Receiver sensitivity

-102

-103

dBm

System clock running at 26 MHz

System clock running at 24MHz

The RX current consumption can be reduced by approximately 2.1 mA by setting MDMCFG2.DEM_DCFILT_OFF=1. The typical sensitivity is then

-99 dBm.

315 MHz, 250 kBaud data rate, sensitivity optimized, MDMCFG2.DEM_DCFILT_OFF=0 (MDMCFG2.DEM_DCFILT_OFF=1 cannot be used for data rates > 100 kBaud) (GSK, 1% packet error rate, 20 bytes packet length, 127 kHz deviation, 540 kHz digital channel filter bandwidth)

Receiver sensitivity

-94

dBm

System clock running at 26 MHz

System clock running at 24MHz

433 MHz, 1.2 kBaud data rate, sensitivity optimized, MDMCFG2.DEM_DCFILT_OFF=0 (GSK, 1% packet error rate, 20 bytes packet length, 5.2 kHz deviation, 58 kHz digital channel filter bandwidth)

Receiver sensitivity

-110

dBm

System clock running at 26 MHz

System clock running at 24MHz

The RX current consumption can be reduced by approximately 2.6 mA by setting MDMCFG2.DEM_DCFILT_OFF=1. The typical sensitivity is then

-107 dBm.

433 MHz, 38.4 kBaud data rate, sensitivity optimized, MDMCFG2.DEM_DCFILT_OFF=0 (GSK, 1% packet error rate, 20 bytes packet length, 20 kHz deviation, 100 kHz digital channel filter bandwidth)

Receiver sensitivity

-102

-101

dBm

System clock running at 26 MHz

System clock running at 24MHz

The RX current consumption can be reduced by approximately 2.7 mA by setting MDMCFG2.DEM_DCFILT_OFF=1. The typical sensitivity is then

-99 dBm.

Parameter Min Typ Max Unit Condition/Note

433 MHz, 250 kBaud data rate, sensitivity optimized, MDMCFG2.DEM_DCFILT_OFF=0 (MDMCFG2.DEM_DCFILT_OFF=1

cannot be used for data rates > 100 kBaud) (GSK, 1% packet error rate, 20 bytes packet length, 127 kHz deviation, 540 kHz digital channel filter bandwidth)

Receiver sensitivity

-95

-93

System clock running at 26 MHz

System clock running at 24MHz

See Table 9 for typical variation over operating conditions

CC1110Fx / CC1111Fx

SWRS033E Page 15 of 239

Parameter Min Typ Max Unit Condition/Note

868 MHz, 1.2 kBaud data rate, sensitivity optimized, MDMCFG2.DEM_DCFILT_OFF=0

(GSK, 1% packet error rate, 20 bytes packet length, 5.2 kHz deviation, 58 kHz digital channel filter bandwidth)

Receiver sensitivity

-110

dBm

System clock running at 26 MHz

Tested conducted on [4] CC1111 USB-Dongle Reference Design, 24MHz clock

The RX current consumption can be reduced by approximately 2.0 mA by setting MDMCFG2.DEM_DCFILT_OFF=1. The typical sensitivity is then

-107 dBm.

Saturation -14 dBm

MCSM0.CLOSE_IN_RX=00

Adjacent channel rejection

38 dB Desired channel 3 dB above the sensitivity limit. 100 kHz channel

spacing

Alternate channel rejection

35 dB Desired channel 3 dB above the sensitivity limit. 100 kHz channel

spacing

See Figure 57 for plot of selectivity versus frequency offset

Image channel rejection, 868MHz

33 dB IF frequency 152 kHz

Desired channel 3 dB above the sensitivity limit.

868 MHz, 38.4 kBaud data rate, sensitivity optimized, MDMCFG2.DEM_DCFILT_OFF=0 (GSK, 1% packet error rate, 20 bytes packet length, 20 kHz deviation, 100 kHz digital channel filter bandwidth)

Receiver sensitivity

-102

-101

dBm

System clock running at 26 MHz

Tested conducted on [4] CC1111 USB-Dongle Reference Design, 24MHz clock

The RX current consumption can be reduced by approximately 2.2 mA by setting MDMCFG2.DEM_DCFILT_OFF=1. The typical sensitivity is then

-100 dBm.

Saturation -14 dBm

MCSM0.CLOSE_IN_RX=00

Adjacent channel rejection

19 dB Desired channel 3 dB above the sensitivity limit. 200 kHz channel

spacing

Alternate channel rejection

32 dB Desired channel 3 dB above the sensitivity limit. 200 kHz channel

spacing

See Figure 58 for plot of selectivity versus frequency offset

Image channel rejection, 868MHz

28 dB IF frequency 152 kHz

Desired channel 3 dB above the sensitivity limit.

CC1110Fx / CC1111Fx

SWRS033E Page 16 of 239

Parameter Min Typ Max Unit Condition/Note

868 MHz, 250 kBaud data rate, sensitivity optimized, MDMCFG2.DEM_DCFILT_OFF=0 (MDMCFG2.DEM_DCFILT_OFF=1

cannot be used for data rates > 100 kBaud) (GSK, 1% packet error rate, 20 bytes packet length, 127 kHz deviation, 540 kHz digital channel filter bandwidth)

Receiver sensitivity

-94

-91

dBm

System clock running at 26 MHz

Tested conducted on [4] CC1111 USB-Dongle Reference Design, 24MHz clock

Saturation -16 dBm

MCSM0.CLOSE_IN_RX=00

Adjacent channel rejection

27 dB Desired channel 3 dB above the sensitivity limit. 750 kHz channel

spacing

Alternate channel rejection

36 dB Desired channel 3 dB above the sensitivity limit. 750 kHz channel

spacing

See Figure 59 for plot of selectivity versus frequency offset

Image channel rejection, 868MHz

17 dB IF frequency 304 kHz

Desired channel 3 dB above the sensitivity limit.

915 MHz, 1.2 kBaud data rate, sensitivity optimized, MDMCFG2.DEM_DCFILT_OFF=0 (2-FSK, 5.2kHz deviation, 1% packet error rate, 20 bytes packet length, 58 kHz digital channel filter bandwidth)

Receiver sensitivity

-108

-110

dBm

System clock running at 26 MHz

Tested conducted on [4] CC1111 USB-Dongle Reference Design, 24MHz clock

The RX current consumption can be reduced by approximately 2.0 mA by setting MDMCFG2.DEM_DCFILT_OFF=1. The typical sensitivity is then

-107 dBm.

915 MHz, 38.4 kBaud data rate, sensitivity optimized, MDMCFG2.DEM_DCFILT_OFF=0 (2-FSK, 1% packet error rate, 20 bytes packet length, 100 kHz digital channel filter bandwidth)

Receiver sensitivity

-100

dBm

System clock running at 26 MHz

Tested conducted on [4] CC1111 USB-Dongle Reference Design, 24MHz clock

The RX current consumption can be reduced by approximately 2.1 mA by setting MDMCFG2.DEM_DCFILT_OFF=1. The typical sensitivity is then

-99 dBm.

915 MHz, 250 kBaud data rate, sensitivity optimized, MDMCFG2.DEM_DCFILT_OFF=0 (MDMCFG2.DEM_DCFILT_OFF=1 cannot be used for data rates > 100 kBaud) (MSK, 1% packet error rate, 20 bytes packet length, 540 kHz digital channel filter bandwidth)

Receiver sensitivity

–93

-91

dBm

System clock running at 26 MHz

Tested conducted on [4] CC1111 USB-Dongle Reference Design, 24MHz clock

915 MHz, 500 kBaud data rate, sensitivity optimized, MDMCFG2.DEM_DCFILT_OFF=0 (MDMCFG2.DEM_DCFILT_OFF=1 cannot be used for data rates > 100 kBaud) (MSK, 1% packet error rate, 20 bytes packet length, 812 kHz digital channel filter bandwidth)

Receiver sensitivity

–86 dBm

System clock running at 26 MHz.

Not tested on [4] CC1111 USB-Dongle Reference Design, 24MHz clock

CC1110Fx / CC1111Fx

SWRS033E Page 17 of 239

Parameter Min Typ Max Unit Condition/Note

Blocking

Blocking at ±2 MHz offset, 1.2 kBaud, 868 MHz

-45 dBm Desired channel 3dB above the sensitivity limit.

Blocking at ±2 MHz offset, 250 kBaud, 868 MHz

-50 dBm Desired channel 3dB above the sensitivity limit

Blocking at ±10 MHz offset, 1.2 kBaud, 868 MHz

-33 dBm Desired channel 3dB above the sensitivity limit.

Blocking at ±10 MHz offset, 250 kBaud, 868 MHz

-40 dBm Desired channel 3dB above the sensitivity limit.

Parameter Min Typ Max Unit Condition/Note

General

Spurious emissions

Conducted measurement in a 50 Ω single ended load. Complies with EN 300 328, EN 300 440 class 2, FCC CFR47, Part 15 and ARIB STD-T-66. Numbers are from

CC1101

(same radio on

CC1110

and

CC1111

) Typical radiated spurious emission is -49 dB measured at the VCO frequency.

25 MHz – 1 GHz

-68 -57 dBm Maximum figure is the ETSI EN 300 220 limit

Above 1 GHz -66 -47 dBm Maximum figure is the ETSI EN 300 220 limit

Table 8: RF Receive Section

Supply Voltage, VDD = 2 V Supply Voltage, VDD = 3 V Supply Voltage, VDD = 3.6 V

Temperature [°C] -40 25 85 -40 25 85 -40 25 85

Sensitivity [dBm] -96.4 -94.9 -92.6 -96.1 -95.0 -92.2 -96.1 -94.5 -92.2

Table 9: Typical Variation in Sensitivity over Temperature and Supply Voltage @ 433 MHz and 250

kBaud Data Rate

CC1110Fx / CC1111Fx

SWRS033E Page 18 of 239

7.3 RF Transmit Section

= 25 °C, VDD = 3.0 V if nothing else stated. All measurement results are obtained using the

CC1110EM reference designs ([1]) if nothing else is stated.

Parameter Min Typ Max Unit Condition/Note

Differential load impedance

315 MHz

433 MHz

868/915 MHz

122 + j31

116 + j41

86.5 + j43

Ω

Differential impedance as seen from the RF-port (RF_P and RF_N) towards the antenna. Follow the CC1110EM reference designs ([1], [2] and [3]) available from the TI website.

Output power, highest setting

+10 dBm Output power is programmable, and full range is available in

all frequency bands Output power may be restricted by regulatory limits. See Application Note AN050 [13] – note that this AN is for

CC1101

but the same limitations apply for

CC1110Fx

and

CC1111Fx

well. For

CC1111Fx

see in addition Design Note DN016 [14] for information on antenna solution and additional regulatory restrictions

See figure Figure 3 for typical variation over operating conditions

Delivered to 50 Ω single-ended load via CC1110EM reference design [3] RF matching network.

Output power, lowest setting

-30 dBm Output power is programmable and is available across the

entire frequency band

Delivered to 50 Ω single-ended load via CC1110EM reference design [3] RF matching network.

Harmonics, radiated

Harm, 433 MHz

Harm, 868 MHz

-51

-42

-37

-43

dBm

Measured on CC1110EM reference designs ([2] and [3]) with CW, 10dBm output power

The antennas used during the radiated measurements (SMAFF-433 from R.W.Badland and Nearson S331 868/915) play a part in attenuating the harmonics

Harmonics, radiated

Harm, 868 MHz

-55

dBm Measured on [4] CC1111 USB-Dongle Reference Design,

with CW, 10dBm output power. The chip antenna used during the radiated measurements play a part in attenuating the harmonics

Harmonics, conducted

Measured on CC1110EM reference designs ([1], [2] and [3])

with CW, 10dBm output power, TX frequency at 315.00 MHz, 433.00 MHz, 868.00 MHz, or 915.00 MHz

315 MHz < -35

< -52

dBm Frequencies below 960 MHz

Frequencies above 960 MHz

433 MHz < -44

< -35

Frequencies below 1 GHz

Frequencies above 1 GHz

868 MHz < -35 Frequencies above 1 GHz

915 MHz < -34 Frequencies above 1 GHz

CC1110Fx / CC1111Fx

SWRS033E Page 19 of 239

Parameter Min Typ Max Unit Condition/Note

Spurious emissions radiated, Harmonics not included

Measured on CC1110EM reference designs ([1], [2] and [3])

with 10 dBm CW, TX frequency at 315.00 MHz, 433.00 MHz,

868.00 or 915.00 MH. For

CC1111Fx

see DN016 [14]

Please refer to register TEST1 on page 222 for required settings in RX and TX

315 MHz < -58

< -53

dBm Frequencies below 960 MHz

Frequencies above 960 MHz

433 MHz < -50

< -54 < -56

dBm Frequencies below 1 GHz

Frequencies above 1 GHz Frequencies within 47-74, 87.5-118, 174-230, 470-862 MHz

868 MHz

< -56 < -54 < -56

dBm

Frequencies below 1 GHz Frequencies above 1 GHz Frequencies within 47-74, 87.5-118, 174-230, 470-862 MHz.

915 MHz < -51

< -60

dBm Frequencies below 960 MHz

Frequencies above 960 MHz

Table 10: RF Transmit Section

Figure 3: Typical Variation in Output Power over Frequency and Temperature

(+10 dBm output power)

Output power (10dBm), variation over frequency and temperature

750 800 850 900 950

Frequency [MHz]

Output power [dBm]

vg -40degC

vg 25degC

vg 85degC

CC1110Fx / CC1111Fx

SWRS033E Page 20 of 239

7.4 Crystal Oscillators

7.4.1

CC1110Fx

Crystal Oscillator (26 – 27 MHz)

= 25 °C, VDD = 3.0 V if nothing else is stated.

Parameter Min Typ Max Unit Condition/Note

Crystal frequency 26 26 27 MHz Referred to as f

XOSC.

Crystal frequency accuracy requirement

±40 ppm This is the total tolerance including a) initial tolerance, b) crystal

loading, c) aging, and d) temperature dependence.

The acceptable crystal tolerance depends on RF frequency and channel spacing / bandwidth.

C0 1 5 7 pF Simulated over operating conditions

Load capacitance 10 13 20 pF Simulated over operating conditions

ESR 100

Ω

Simulated over operating conditions

Start-up time 250 µs f

XOSC

= 26 MHz

Note: A Ripple counter of 12 bit is included to ensure duty-cycle requirements. Start-up time includes ripple counter delay until SLEEP.XOSC_STB is asserted

Power Down Guard Time

3 ms The crystal oscillator must be in power down for a guard time before it

is used again. This requirement is valid for all modes of operation. The need for power down guard time can vary with crystal type and load. Minimum figure is valid for reference crystal NDK, AT-41CD2 and load capacitance according to Table 29.

If power down guard time is violated increased CRC error can be present in the first few radio packets after power down.

Table 11:

CC1110Fx

Crystal Oscillator Parameters

7.4.2

CC1111Fx

Crystal Oscillator (48 MHz)

= 25 °C, VDD = 3.0 V if nothing else is stated.

Parameter Min Typ Max Unit Condition/Note

Crystal frequency 48 MHz Referred to as f

XOSC

48MHz crystal gives a system clock of 24MHz.

Please note that there are restricted usage in the frequency bands 863-870 MHz (due to spurious emission). See DN016 Compact antenna solutions for 868/915MHz [14]

Crystal frequency accuracy requirement

±40 ppm This is the total tolerance including a) initial tolerance, b) crystal

loading, c) aging, and d) temperature dependence.

The acceptable crystal tolerance depends on RF frequency and channel spacing / bandwidth.

Fundamental

0.85 1 1.15 pF

Simulated over operating conditions. Variation given by reference crystal NX2520SA from NDK (fundamental).

Load capacitance 15 16 17 pF Simulated over operating conditions

ESR 60

Ω

Simulated over operating conditions

Start-up time

Fundamental crystal

650

µs

Note: A Ripple counter of 14 bit is included to ensure duty-cycle requirements. Start-up time includes ripple counter delay until SLEEP.XOSC_STB is asserted

Table 12:

CC1111Fx

Crystal Oscillator Parameters

CC1110Fx / CC1111Fx

SWRS033E Page 21 of 239

7.5 32.768 kHz Crystal Oscillator

= 25 °C, VDD = 3.0V if nothing else is stated.

Parameter Min Typ Max Unit Condition/Note

Crystal frequency 32.768 kHz

Crystal shunt capacitance

0.9 2.0 pF Simulated over operating conditions

Load capacitance 12 16 pF Simulated over operating conditions

ESR 40 130

kΩ

Simulated over operating conditions

Start-up time 400 ms Value is simulated

Table 13: 32.768 kHz Crystal Oscillator Parameters

7.6 Low Power RC Oscillator

= 25 °C, VDD = 3.0 V if nothing else is stated.

Parameter Min Typ Max Unit Condition/Note

Calibrated frequency2 32.0 34.7 36.0 kHz Calibrated low power RC oscillator frequency is

XOSC

/ 750

Frequency accuracy after calibration

±1 %

Temperature coefficient +0.5

%/°C

Frequency drift when temperature changes after calibration

Supply voltage coefficient +3 %/V Frequency drift when supply voltage changes after

calibration

Initial calibration time 2 ms When the low power RC oscillator is enabled,

calibration is continuously done in the background as long as the high speed crystal oscillator is running.

Table 14: Low Power RC Oscillator Parameters

Min figures are given using f

XOSC

= 24 MHz. Typical figures are given using f

XOSC

= 26 MHz, and Max

figures are given using f

XOSC

= 27 MHz

CC1110Fx / CC1111Fx

SWRS033E Page 22 of 239

7.7 High Speed RC Oscillator

= 25 °C, VDD = 3.0 V if nothing else is stated.

Parameter Min Typ Max Unit Condition/Note

Calibrated frequency2 12 13 13.5 MHz Calibrated HS RCOSC frequency is f

XOSC

/ 2

Uncalibrated frequency accuracy

±15

Calibrated frequency accuracy

±1

Start-up time 10 µs

Temperature coefficient -325

ppm/°C

Frequency drift when temperature changes after calibration

Supply voltage coefficient 28 ppm/V Frequency drift when supply voltage changes after

calibration

Initial calibration time 65 µs The HS RCOSC will be calibrated once when the

high speed crystal oscillator is selected as system clock source (CLKCON.OSC is set to 0), and also when the system wakes up from PM{1-3}. See

13.1.5.1 for details).

Table 15: High Speed RC Oscillator Parameters

7.8 Frequency Synthesizer Characteristics

= 25 °C, VDD = 3.0 V if nothing else stated. All measurement results are obtained using the

CC1110EM reference designs ([1]).

Parameter Min Typ Max Unit Condition/Note

Programmed frequency resolution

367 397 412 Hz 24 - 27 MHz system clock.

Frequency resolution = f

XOSC

/ 216

Synthesizer frequency tolerance

±40 ppm Given by crystal used. Required accuracy (including

temperature and aging) depends on frequency band and channel bandwidth / spacing.

RF carrier phase noise -92 dBc/Hz @ 50 kHz offset from carrier

RF carrier phase noise -93 dBc/Hz @ 100 kHz offset from carrier

RF carrier phase noise -93 dBc/Hz @ 200 kHz offset from carrier

RF carrier phase noise -98 dBc/Hz @ 500 kHz offset from carrier

RF carrier phase noise -107 dBc/Hz @ 1 MHz offset from carrier

RF carrier phase noise -113 dBc/Hz @ 2 MHz offset from carrier

RF carrier phase noise -119 dBc/Hz @ 5 MHz offset from carrier

RF carrier phase noise -129 dBc/Hz @ 10 MHz offset from carrier

PLL turn-on / hop time3 85.1 88.4 95.8

µs

Time from leaving the IDLE state until arriving in the RX, FSTXON, or TX state, when not performing calibration. Crystal oscillator running.

PLL RX/TX settling time3 9.3 9.6 10.4

µs

Settling time for the 1·IF frequency step from RX to TX

PLL TX/RX settling time3 20.7 21.5 23.3

µs

Settling time for the 1·IF frequency step from TX to RX

PLL calibration time3 694 721 780.8

µs

Calibration can be initiated manually or automatically before entering or after leaving RX/TX.

Table 16: Frequency Synthesizer Parameters

Min figures are given using f

XOSC

= 27 MHz. Typ figures are given using f

XOSC

= 26 MHz, and Max

figures are given using f

XOSC

= 24 MHz.

CC1110Fx / CC1111Fx

SWRS033E Page 23 of 239

7.9 Analog Temperature Sensor

= 25 °C, VDD = 3.0V if nothing else stated. All measurement results are obtained using the

CC1110EM reference designs ([1]).

Parameter Min Typ Max Unit Condition/Note

Output voltage at -40 °C

0.660 V

Output voltage at 0 °C

0.755 V

Output voltage at +40 °C

0.859 V

Output voltage at +80 °C

0.958 V

Temperature coefficient 2.54

mV/°C Fitted from -20 °C to +80 °C

Error in calculated temperature, calibrated

-2

0 2

°C From –20°C to +80°C when using 2.43 mV / °C, after 1-point

calibration at room temperature

The indicated minimum and maximum error with 1-point calibration is based on measured values for typical process parameters

Current consumption increase when enabled

0.3 mA

Table 17: Analog Temperature Sensor Parameters

7.10 7-12 bit ADC

= 25 °C, VDD = 3.0V if nothing else stated. The numbers given here are based on tests performed

in accordance with IEEE Std 1241-2000 [8]. The ADC data are from

CC2430

characterization. As the

CC1110Fx/C1111Fx

uses the same ADC, the numbers listed in Table 18 should be good indicators of the

performance to be expected from

CC1110Fx

and

CC1111Fx

. Note that these numbers will apply for 24

MHz operated systems (like

CC1110Fx

using a 24 MHz crystal or

CC1111Fx

using a 48 MHz crystal).

Performance will be slightly different for other crystal frequencies (e.g. 26 MHz and 27 MHz).

Parameter Min Typ Max Unit Condition/Note

Input voltage 0 VDD V VDD is voltage on AVDD pin (2.0 – 3.6 V)

External reference voltage 0 VDD V VDD is voltage on AVDD pin (2.0 – 3.6 V)

External reference voltage differential

0 VDD V VDD is voltage on AVDD pin (2.0 – 3.6 V)

Input resistance, signal 197

kΩ

Simulated using 4 MHz clock speed (see section

13.10.2.7)

Full-Scale Signal4 2.97 V Peak-to-peak, defines 0 dBFS

ENOB4 5.7 bits 7-bits setting

Single ended input 7.5 9-bits setting

9.3 10-bits setting

10.8 12-bits setting

ENOB4 6.5 bits 7-bits setting

Differential input 8.3 9-bits setting

10.0 10-bits setting

11.5 12-bits setting

Useful Power Bandwidth 0-20 kHz 7-bits setting, both single and differential

THD4

-Single ended input -75.2 dB 12-bits setting, -6 dBFS

-Differential input -86.6 dB 12-bits setting, -6 dBFS

Measured with 300 Hz Sine input and VDD as reference.

CC1110Fx / CC1111Fx

SWRS033E Page 24 of 239

Parameter Min Typ Max Unit Condition/Note

Signal To Non-Harmonic Ratio4

-Single ended input 70.2 dB 12-bits setting

-Differential input 79.3 dB 12-bits setting

Spurious Free Dynamic Range4

-Single ended input 78.8 dB 12-bits setting, -6 dBFS

-Differential input 88.9 dB 12-bits setting, -6 dBFS

CMRR, differential input <-84 dB 12- bit setting, 1 kHz Sine (0 dBFS), limited by ADC

resolution

Crosstalk, single ended input <-84 dB 12- bit setting, 1 kHz Sine (0 dBFS), limited by ADC

resolution

Offset -3 mV Mid. Scale

Gain error 0.68 %

DNL4 0.05 LSB 12-bits setting, mean

0.9 LSB 12-bits setting, max

INL4 4.6 LSB 12-bits setting, mean

13.3 LSB 12-bits setting, max

SINAD4 35.4 dB 7-bits setting

Single ended input 46.8 dB 9-bits setting

(-THD+N) 57.5 dB 10-bits setting

66.6 dB 12-bits setting

SINAD4 40.7 dB 7-bits setting

Differential input 51.6 dB 9-bits setting

(-THD+N) 61.8 dB 10-bits setting

70.8 dB 12-bits setting

Conversion time 20

µs

7-bits setting

µs

9-bits setting

µs

10-bits setting

132

µs

12-bits setting

Current consumption 1.2 mA

Table 18: 7-12 bit ADC Characteristics

CC1110Fx / CC1111Fx

SWRS033E Page 25 of 239

7.11 Control AC Characteristics

= 25 °C, VDD = 3.0 V if nothing else stated. All measurement results are obtained using the

CC1110EM reference designs ([1]).

Parameter Min Typ Max Unit Condition/Note

0.1875 26 27

CC1110Fx

High speed crystal oscillator used as source (X).

0.1875 13 13.5

MHz

Calibrated HS RCOSC used as source (RC).

Source: X/RC

Min: f

XOSC

= 24 MHz, CLKCON.CLKSPD = 111/111

Typ: f

XOSC

= 26 MHz, CLKCON.CLKSPD = 000/001

Max: f

XOSC

= 27 MHz, CLKCON.CLKSPD = 000/001

0.1875 24 24

CC1111Fx

High speed crystal oscillator used as source (X).

0.1875 12 12

MHz

HS RCOSC used as source (RC).

System clock, f

SYSCLK

= 1/ f

SYSCLK

Source: X/RC

Min: f

XOSC

= 48 MHz, CLKCON.CLKSPD = 111/111

Typ/Max: f

XOSC

= 48 MHz, CLKCON.CLKSPD = 000/001

RESET_N low width

250 ns See item 1, Figure 4. This is the shortest pulse that is

guaranteed to be recognized as a reset pin request.

Note: Shorter pulses may be recognized but will not lead to complete reset of all modules within the chip.

Interrupt pulse width

SYSCLK

See item 2, Figure 4. This is the shortest pulse that is

guaranteed to be recognized as an interrupt request. In PM2/3 the internal synchronizers are bypassed so this requirement does not apply in PM2/3.

Table 19: Control Inputs AC Characteristics

Figure 4: Control Inputs AC Characteristics

CC1110Fx / CC1111Fx

SWRS033E Page 26 of 239

7.12 SPI AC Characteristics

= 25 °C, VDD = 3.0V if nothing else stated. All measurement results are obtained using the

CC1110EM reference designs ([1]).

Parameter Min Typ Max Unit Condition/Note

SCK period See

section

13.14.3

ns Master. See item 1, Figure 5

SCK duty cycle 50 % Master.

SSN low to SCK 2·t

SYSCLK

See item 5, Figure 5

SCK to SSN high 30 ns See item 6, Figure 5

MISO setup 10 ns Master. See item 2, Figure 5

MISO hold 10 ns Master. See item 3, Figure 5

SCK to MOSI 25 ns Master. See item 4, Figure 5, load = 10 pF

SCK period 100 ns Slave. See item 1, Figure 5

SCK duty cycle 50 % Slave.

MOSI setup 10 ns Slave. See item 2, Figure 5

MOSI hold 10 ns Slave. See item 3, Figure 5

SCK to MISO 25 ns Slave. See item 4, Figure 5, load = 10 pF

Table 20: SPI AC Characteristics

Figure 5: SPI AC Characteristics

CC1110Fx / CC1111Fx

SWRS033E Page 27 of 239

7.13 Debug Interface AC Characteristics

= 25 °C, VDD = 3.0 V if nothing else stated. All measurement results are obtained using the

CC1110EM reference designs ([1]).

Parameter Min Typ Max Unit Condition/Note

Debug clock period

125 ns See item 1, Figure 6

Note: CLKCON.CLKSPD must be 000 or 001 when using the debug interface

Debug data setup 5 ns See item 2, Figure 6

Debug data hold 5 ns See item 3, Figure 6

Clock to data delay

10 ns See item 4, Figure 6, load = 10 pF

RESET_N inactive after P2_2 rising

10 ns See item , Figure 6

Table 21: Debug Interface AC Characteristics

DEBUG CLK

P2_2

DEBUG DATA

P2_1

DEBUG DATA

P2_1

RESET_N

Figure 6: Debug Interface AC Characteristics

7.14 Port Outputs AC Characteristics

= 25 °C, VDD = 3.0 V if nothing else stated. All measurement results are obtained using the

CC1110EM reference designs ([1]).

Parameter Min Typ Max Unit Condition/Note

P0_[0:7], P1_[2:7], P2_[0:4] Port output rise time (PICTL.PADSC=0 / PICTL.PADSC=1)

3.15 /

1.34

ns Load = 10 pF

Timing is with respect to 10% VDD and 90% VDD levels.

Values are estimated

P0_[0:7], P1_[2:7], P2_[0:4] Port output fall time (PICTL.PADSC=0 / PICTL.PADSC=1)

3.2 /

1.44

ns Load = 10 pF

Timing is with respect to 90% VDD and 10% VDD.

Values are estimated

Table 22: Port Outputs AC Characteristics

CC1110Fx / CC1111Fx

SWRS033E Page 28 of 239

7.15 Timer Inputs AC Characteristics

= 25 °C, VDD = 3.0 V if nothing else stated. All measurement results are obtained using the

CC1110EM reference designs ([1]).

Parameter Min Typ Max Unit Condition/Note

Input capture pulse width

SYSCLK

Synchronizers determine the shortest input pulse that can

be recognized. The synchronizers operate from the current system clock rate (see Table 19)

Table 23: Timer Inputs AC Characteristics

7.16 DC Characteristics

The DC Characteristics of

CC1110Fx/CC1111Fx

are listed in Table 24 below.

= 25 °C, VDD = 3.0 V if nothing else stated. All measurement results are obtained using the

CC1110EM reference designs ([1]).

Digital Inputs/Outputs Min Typ Max Unit Condition

Logic "0" input voltage 30 % Of VDD supply (2.0 – 3.6 V)

Logic "1" input voltage 70 % Of VDD supply (2.0 – 3.6 V)

Logic "0" input current per pin N/A 12 nA Input equals 0 V

Logic "1" input current per pin N/A 12 nA Input equals VDD

Total logic “0” input current all pins 70 nA

Total logic “1” input current all pins 70 nA

I/O pin pull-up and pull-down resistor 20

kΩ

Table 24: DC Characteristics

CC1110Fx / CC1111Fx

SWRS033E Page 29 of 239

8 Pin and I/O Port Configuration

The

CC1110Fx

pin-out is shown in Figure 7 and Table 25. See section 13.4 for details on the I/O

configuration.

AGND Exposed die attached pad

RESET_N

DVDD

P1_6

36 35 34 33 32 31 30 29 28

10 11 12 13 14 15 16 17 18

P1_1

P1_0

P0_0

P0_1

P0_2

P0_3

P0_4

DVDD

P0_5

P0_6

P0_7

P2_0

P2_1

P2_2

P2_3/XSOC32_Q1

P2_4/XOSC32_Q2

AVDD

XOSC_Q2

AVDD

RF_N

AVDD

RBIAS

XOSC_Q1

RF_P

P1_3

P1_4

P1_5

P1_7

AVDD_DREG

GUARD

P1_2

DCOUPL

Figure 7:

CC1110Fx

Pinout Top View

Note: The exposed die attach pad must be connected to a solid ground plane as this is the ground connection for the chip.

CC1110Fx / CC1111Fx

SWRS033E Page 30 of 239

Pin Pin Name Pin Type Description

AGND Ground The exposed die attach pad must be connected to a solid ground

plane

1 P1_2 D I/O Port 1.2

2 DVDD Power (Digital) 2.0 V - 3.6 V digital power supply for digital I/O

3 P1_1 D I/O Port 1.1

4 P1_0 D I/O Port 1.0

5 P0_0 D I/O Port 0.0

6 P0_1 D I/O Port 0.1

7 P0_2 D I/O Port 0.2

8 P0_3 D I/O Port 0.3

9 P0_4 D I/O Port 0.4

10 DVDD Power (Digital) 2.0 V - 3.6 V digital power supply for digital I/O

11 P0_5 D I/O Port 0.5

12 P0_6 D I/O Port 0.6

13 P0_7 D I/O Port 0.7

14 P2_0 D I/O Port 2.0

15 P2_1 D I/O Port 2.1

16 P2_2 D I/O Port 2.2

17 P2_3/XOSC32_Q1 D I/O Port 2.3/32.768 kHz crystal oscillator pin 1

18 P2_4/XOSC32_Q2 D I/O Port 2.4/32.768 kHz crystal oscillator pin 2

19 AVDD Power (Analog) 2.0 V - 3.6 V analog power supply connection

20 XOSC_Q2 Analog I/O Crystal oscillator pin 2

21 XOSC_Q1 Analog I/O Crystal oscillator pin 1, or external clock input

22 AVDD Power (Analog) 2.0 V - 3.6 V analog power supply connection

23 RF_P RF I/O Positive RF input signal to LNA in receive mode

Positive RF output signal from PA in transmit mode

24 RF_N RF I/O Negative RF input signal to LNA in receive mode

Negative RF output signal from PA in transmit mode

25 AVDD Power (Analog) 2.0 V – 3.6 V analog power supply connection

26 AVDD Power (Analog) 2.0 V - 3.6 V analog power supply connection

27 RBIAS Analog I/O External precision bias resistor for reference current

28 GUARD Power (Digital) Power supply connection for digital noise isolation

29 AVDD_DREG Power (Digital) 2.0 V - 3.6 V digital power supply for digital core voltage regulator

30 DCOUPL Power decoupling 1.8 V digital power supply decoupling

31 RESET_N DI Reset, active low

32 P1_7 D I/O Port 1.7

33 P1_6 D I/O Port 1.6

34 P1_5 D I/O Port 1.5

35 P1_4 D I/O Port 1.4

36 P1_3 D I/O Port 1.3

Table 25:

CC1110Fx

Pin-out Overview

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