Texas Instruments CC1100 Datasheet

CC1100

Data Sheet (Rev.1.1) SWRS038A Page 1 of 89

CC1100

Single Chip Low Cost Low Power RF Transceiver

Applications

• Ultra low power UHF wireless transceivers

• 315/433/868 and 915 MHz ISM/SRD band

systems

• AMR – Automatic Meter Reading

• Consumer Electronics

• Two-way RKE –Remote Keyless Entry

• Low power telemetry

• Home and building automation

• Wireless alarm and security systems

• Industrial monitoring and control

• Wireless sensor networks

Product Description

The

CC1100

is a low cost true single chip UHF transceiver designed for very low power wireless applications. The circuit is mainly intended for the ISM (Industrial, Scientific and Medical) and SRD (Short Range Device) frequency bands at 315, 433, 868 and 915 MHz, but can easily be programmed for operation at other frequencies in the 300-348 MHz, 400-464 MHz and 800-928 MHz bands.

The RF transceiver is integrated with a highly configurable baseband modem. The modem supports various modulation formats and has a configurable data rate up to 500 kbps. The communication range can be increased by enabling a Forward Error Correction option, which is integrated in the modem.

CC1100

provides extensive hardware support for packet handling, data buffering, burst transmissions, clear channel assessment, link quality indication and wake-on-radio.

The main operating parameters and the 64byte transmit/receive FIFOs of

CC1100

can be controlled via an SPI interface. In a typical system, the

CC1100

will be used together with a

microcontroller and a few additional passive components.

CC1100

is part of Chipcon’s 4th generation

technology platform based on 0.18 µm CMOS technology.

Key Features

• Small size (QLP 4x4 mm package, 20

pins)

• True single chip UHF RF transceiver

• Frequency bands: 300-348 MHz, 400-464

MHz and 800-928 MHz

• High sensitivity (–110 dBm at 1.2 kbps,

1% packet error rate)

• Programmable data rate up to 500 kbps

• Low current consumption (15.4 mA in RX,

1.2 kbps, 433 MHz)

• Programmable output power up to +10

dBm for all supported frequencies

• Excellent receiver selectivity and blocking

performance

• Very few external components: Totally on-

chip frequency synthesizer, no external filters or RF switch needed

• Programmable baseband modem

• Ideal for multi-channel operation

• Configurable packet handling hardware

• Suitable for frequency hopping systems

due to a fast settling frequency synthesizer

• Optional Forward Error Correction with

interleaving

• Separate 64-byte RX and TX data FIFOs

• Efficient SPI interface: All registers can be

programmed with one “burst” transfer

CC1100

Data Sheet (Rev.1.1) SWRS038A Page 2 of 89

Features (continued from front page)

• Digital RSSI output

• Suited for systems compliant with EN 300

220 (Europe) and FCC CFR Part 15 (US)

• Wake-on-radio functionality for automatic

low-power RX polling

• Many powerful digital features allow a

high-performance RF system to be made using an inexpensive microcontroller

• Integrated analog temperature sensor

• Lead-free “green“ package

• Flexible support for packet oriented

systems: On chip support for sync word detection, address check, flexible packet length and automatic CRC handling

• Programmable channel filter bandwidth

• OOK and flexible ASK shaping supported

• FSK, GFSK and MSK supported.

• Automatic Frequency Compensation

(AFC) can be used to align the frequency

synthesizer to the received centre frequency

• Optional automatic whitening and de-

whitening of data

• Support for asynchronous transparent

receive/transmit mode for backwards compatibility with existing radio communication protocols

• Programmable Carrier Sense (CS)

indicator

• Programmable Preamble Quality Indicator

(PQI) for detecting preambles and improved protection against sync word detection in random noise

• Support for automatic Clear Channel

Assessment (CCA) before transmitting (for listen-before-talk systems)

• Support for per-package Link Quality

Indication

CC1100

Data Sheet (Rev.1.1) SWRS038A Page 3 of 89

Abbreviations

Abbreviations used in this data sheet are described below.

ADC Analog to Digital Converter NRZ Non Return to Zero (Coding)

AFC Automatic Frequency Compensation OOK On-Off Keying

AGC Automatic Gain Control PA Power Amplifier

AMR Automatic Meter Reading PCB Printed Circuit Board

ASK Amplitude Shift Keying PD Power Down

BER Bit Error Rate PER Packet Error Rate

CCA Clear Channel Assessment PLL Phase Locked Loop

CFR Code of Federal Regulations POR Power-On Reset

CRC Cyclic Redundancy Check PQI Preamble Quality Indicator

CW Contionus Wave (Unmodulated Carrier) PQT Preamble Quality Threshold

CS Carrier Sense PTAT Proportional To Absolute Temperature

DC Direct Current QLP Quad Leadless Package

DVGA Digital Variable Gain Amplifier QPSK Quadrature Phase Shift Keying

EIRP Equivalent Isotropic Radiated Power RC Resistor-Capacitor

ESR Equivalent Series Resistance RCOSC RC Oscillator

FCC Federal Communications Commission RF Radio Frequency

FEC Forward Error Correction RSSI Received Signal Strength Indicator

FIFO First-In-First-Out RX Receive, Receive Mode

FSK Frequency Shift Keying SAW Surface Aqustic Wave

GFSK Gaussian shaped Frequency Shift Keying SMD Surface Mount Device

IF Intermediate Frequency SNR Signal to Noise Ratio

ISM Industrial, Scientific, Medical SPI Serial Peripheral Interface

LBT Listen Before Transmit SRD Short Range Devices

LC Inductor-Capacitor TBD To Be Defined

LNA Low Noise Amplifier T/R Transmit/Receive

LO Local Oscillator TX Transmit, Transmit Mode

LSB Least Significant Byte UHF Ultra High frequency

LQI Link Quality Indicator VCO Voltage Controlled Oscillator

MCU Microcontroller Unit WOR Wake on Radio, Low power polling

MSK Minimum Shift Keying XOSC Crystal Oscillator

N/A Not Applicable XTAL Crystal

CC1100

Data Sheet (Rev.1.1) SWRS038A Page 4 of 89

Table Of Contents

APPLICATIONS...........................................................................................................................................1

PRODUCT DESCRIPTION.........................................................................................................................1

KEY FEATURES..........................................................................................................................................1

FEATURES (CONTINUED FROM FRONT PAGE)................................................................................2

ABBREVIATIONS........................................................................................................................................3

TABLE OF CONTENTS..............................................................................................................................4

ABSOLUTE MAXIMUM RATINGS..............................................................................................7

OPERATING CONDITIONS ..........................................................................................................7

GENERAL CHARACTERISTICS..................................................................................................7

ELECTRICAL SPECIFICATIONS................................................................................................8

4.1 C

URRENT CONSUMPTION

.....................................................................................................................8

4.2 RF R

ECEIVE SECTION

.........................................................................................................................10

4.3 RF T

RANSMIT SECTION

......................................................................................................................13

4.4 C

RYSTAL OSCILLATOR

.......................................................................................................................14

4.5 L

OW POWER RC OSCILLATOR

............................................................................................................14

4.6 F

REQUENCY SYNTHESIZER CHARACTERISTICS

...................................................................................15

4.7 A

NALOG TEMPERATURE SENSOR

........................................................................................................16

4.8 DC C

HARACTERISTICS

.......................................................................................................................16

4.9 P

OWER ON RESET

...............................................................................................................................16

PIN CONFIGURATION.................................................................................................................17

CIRCUIT DESCRIPTION.............................................................................................................19

APPLICATION CIRCUIT.............................................................................................................19

CONFIGURATION OVERVIEW.................................................................................................23

CONFIGURATION SOFTWARE.................................................................................................24

10 4-WIRE SERIAL CONFIGURATION AND DATA INTERFACE...........................................24

10.1 C

HIP STATUS BYTE

............................................................................................................................26

10.2 R

EGISTER ACCESS

..............................................................................................................................26

10.3 SPI R

EAD

...........................................................................................................................................27

10.4 C

OMMAND STROBES

..........................................................................................................................27

10.5 FIFO A

CCESS

.....................................................................................................................................27

10.6 PATABLE A

CCESS

............................................................................................................................28

11 MICROCONTROLLER INTERFACE AND PIN CONFIGURATION...................................28

11.1 C

ONFIGURATION INTERFACE

..............................................................................................................28

11.2 G

ENERAL CONTROL AND STATUS PINS

..............................................................................................28

11.3 O

PTIONAL RADIO CONTROL FEATURE

.................................................................................................29

12 DATA RATE PROGRAMMING...................................................................................................29

13 RECEIVER CHANNEL FILTER BANDWIDTH.......................................................................29

14 DEMODULATOR, SYMBOL SYNCHRONIZER AND DATA DECISION............................30

14.1 F

REQUENCY OFFSET COMPENSATION

.................................................................................................30

14.2 B

IT SYNCHRONIZATION

......................................................................................................................30

14.3 B

YTE SYNCHRONIZATION

...................................................................................................................30

15 PACKET HANDLING HARDWARE SUPPORT.......................................................................31

15.1 D

ATA WHITENING

...............................................................................................................................31

15.2 P

ACKET FORMAT

................................................................................................................................32

15.3 P

ACKET FILTERING IN RECEIVE MODE

...............................................................................................34

15.4 P

ACKET HANDLING IN TRANSMIT MODE

............................................................................................34

15.5 P

ACKET HANDLING IN RECEIVE MODE

..............................................................................................34

16 MODULATION FORMATS..........................................................................................................35

16.1 F

REQUENCY SHIFT KEYING

................................................................................................................35

16.2 M

INIMUM SHIFT KEYING

....................................................................................................................35

CC1100

Data Sheet (Rev.1.1) SWRS038A Page 5 of 89

16.3

MPLITUDE MODULATION

.................................................................................................................35

17 RECEIVED SIGNAL QUALIFIERS AND LINK QUALITY INFORMATION.....................36

17.1 S

YNC WORD QUALIFIER

.....................................................................................................................36

17.2 P

REAMBLE QUALITY THRESHOLD

(PQT)...........................................................................................36

17.3 RSSI...................................................................................................................................................36

17.4 C

ARRIER SENSE

(CS)..........................................................................................................................38

17.5 C

LEAR CHANNEL ASSESSMENT

(CCA) ..............................................................................................39

17.6 L

INK QUALITY INDICATOR

(LQI).......................................................................................................39

18 FORWARD ERROR CORRECTION WITH INTERLEAVING..............................................39

18.1 F

ORWARD ERROR CORRECTION

(FEC)...............................................................................................39

18.2 I

NTERLEAVING

...................................................................................................................................39

19 RADIO CONTROL.........................................................................................................................41

19.1 P

OWER ON START-UP SEQUENCE

.........................................................................................................41

19.2 C

RYSTAL CONTROL

............................................................................................................................42

19.3 V

OLTAGE REGULATOR CONTROL

.......................................................................................................42

19.4 A

CTIVE MODES

..................................................................................................................................43

19.5 W

AKE ON RADIO

(WOR) ...................................................................................................................43

19.6 T

IMING

...............................................................................................................................................44

19.7 RX T

ERMINATION TIMER

...................................................................................................................44

20 DATA FIFO.....................................................................................................................................45

21 FREQUENCY PROGRAMMING.................................................................................................46

22 VCO..................................................................................................................................................47

22.1 VCO

AND

PLL S

ELF-CALIBRATION

...................................................................................................47

23 VOLTAGE REGULATORS ..........................................................................................................47

24 OUTPUT POWER PROGRAMMING.........................................................................................48

25 SELECTIVITY................................................................................................................................49

26 CRYSTAL OSCILLATOR.............................................................................................................51

26.1 R

EFERENCE SIGNAL

............................................................................................................................51

27 EXTERNAL RF MATCH ..............................................................................................................51

28 GENERAL PURPOSE / TEST OUTPUT CONTROL PINS......................................................52

29 ASYNCHRONOUS AND SYNCHRONOUS SERIAL OPERATION.......................................54

29.1 A

SYNCHRONOUS OPERATION

..............................................................................................................54

29.2 S

YNCHRONOUS SERIAL OPERATION

....................................................................................................54

30 SYSTEM CONSIDERATIONS AND GUIDELINES..................................................................54

30.1 SRD R

EGULATIONS

............................................................................................................................54

30.2 F

REQUENCY HOPPING AND MULTI-CHANNEL SYSTEMS

.....................................................................55

30.3 W

IDEBAND MODULATION NOT USING SPREAD SPECTRUM

.................................................................55

30.4 D

ATA BURST TRANSMISSIONS

............................................................................................................55

30.5 C

ONTINUOUS TRANSMISSIONS

...........................................................................................................55

30.6 C

RYSTAL DRIFT COMPENSATION

.......................................................................................................55

30.7 S

PECTRUM EFFICIENT MODULATION

..................................................................................................56

30.8 L

OW COST SYSTEMS

..........................................................................................................................56

30.9 B

ATTERY OPERATED SYSTEMS

..........................................................................................................56

30.10 I

NCREASING OUTPUT POWER

.........................................................................................................56

31 CONFIGURATION REGISTERS.................................................................................................56

31.1 C

ONFIGURATION REGISTER DETAILS – REGISTERS WITH PRESERVED VALUES IN SLEEP STATE

..........61

31.2 C

ONFIGURATION REGISTER DETAILS – REGISTERS THAT LOOSE PROGRAMMING IN SLEEP STATE

......80

31.3 S

TATUS REGISTER DETAILS

.................................................................................................................81

32 PACKAGE DESCRIPTION (QLP 20)..........................................................................................84

32.1 R

ECOMMENDED

PCB

LAYOUT FOR PACKAGE

(QLP 20).....................................................................85

32.2 P

ACKAGE THERMAL PROPERTIES

........................................................................................................85

32.3 S

OLDERING INFORMATION

..................................................................................................................85

32.4 T

RAY SPECIFICATION

..........................................................................................................................86

32.5 C

ARRIER TAPE AND REEL SPECIFICATION

...........................................................................................86

CC1100

Data Sheet (Rev.1.1) SWRS038A Page 6 of 89

ORDERING INFORMATION.......................................................................................................86

34 GENERAL INFORMATION.........................................................................................................87

34.1 D

OCUMENT HISTORY

.........................................................................................................................87

34.2 P

RODUCT STATUS DEFINITIONS

.........................................................................................................87

35 ADDRESS INFORMATION..........................................................................................................88

36 TI WORLDWIDE TECHNICAL SUPPORT...............................................................................88

CC1100

Data Sheet (Rev.1.1) SWRS038A Page 7 of 89

1 Absolute Maximum Ratings

Under no circumstances must the absolute maximum ratings given in Table 1 be violated. Stress exceeding one or more of the limiting values may cause permanent damage to the device.

Caution! ESD sensitive device. Precaution should be used when handling the device in order to prevent permanent damage.

Parameter Min Max Units Condition

Supply voltage –0.3 3.6 V All supply pins must have the same voltage

Voltage on any digital pin –0.3 VDD+0.3

max 3.6

Voltage on the pins RF_P, RF_N and DCOUPL

–0.3 2.0 V

Voltage ramp-up 120 kV/µs

Input RF level +10 dBm

Storage temperature range –50 150

°C

Solder reflow temperature 260

°C

According to IPC/JEDEC J-STD-020C

ESD <500 V According to JEDEC STD 22, method A114,

Human Body Model

Table 1: Absolute Maximum Rati ngs

2 Operating Conditions

The operating conditions for

CC1100

are listed Table 2 in below.

Parameter Min Max Unit Condition

Operating temperature -40 85

°C

Operating supply voltage 1.8 3.6 V All supply pins must have the same voltage

Table 2: Operating Condi tions

3 General Characteristics

Parameter Min Typ Max Unit Condition/Note

Frequency range 300 348 MHz

400 464 MHz

800 928 MHz

Data rate 1.2

1.2

500

250

500

kbps

FSK

GFSK, OOK and ASK

(Shaped) MSK (also known as differential offset QPSK)

Optional Manchester encoding (halves the data rate).

Table 3: General Characteristics

CC1100

Data Sheet (Rev.1.1) SWRS038A Page 8 of 89

4 Electrical Specifications

4.1 Current Consumption

Tc = 25°C, VDD = 3.0V if nothing else stated. All measurement results are obtained using the CC1100EM reference design.

Reduced current settings (MDMCFG2.DEM_DCFILT_OFF = 1) gives a slightly lower current consumption at the cost of a reduction in sensitivity. See Table 5 for additional details on current consumption and sensitivity.

Parameter Min Typ Max Unit Condition

400 nA Voltage regulator to digital part off, register values retained

(SLEEP state)

900 nA Voltage regulator to digital part off, register values retained, low-

power RC oscillator running (SLEEP state with WOR enabled)

µA

Voltage regulator to digital part off, register values retained, XOSC running (SLEEP state with MCSM0.OSC_FORCE_ON set)

Current consumption in power down modes

160

µA

Voltage regulator to digital part on, all other modules in power down (XOFF state)

8.7

µA

Automatic RX polling once each second, using low-power RC oscillator, with 460 kHz filter bandwidth and 250 kbps data rate, PLL calibration every 4

wakeup. Average current with signal in

channel below carrier sense level.

µA

Same as above, but with signal in channel above carrier sense

level, 1.9ms RX timeout, and no preamble/sync word found.

1.5

µA

Automatic RX polling every 15th second, using low-power RC oscillator, with 460kHz filter bandwidth and 250kbps data rate, PLL calibration every 4

wakeup. Average current with signal in

channel below carrier sense level.

µA

Same as above, but with signal in channel above carrier sense

level, 37ms RX timeout, and no preamble/sync word found.

1.6 mA Only voltage regulator to digital part and crystal oscillator running (IDLE state)

Current consumption

8.2 mA Only the frequency synthesizer running (after going from IDLE until reaching RX or TX states, and frequency calibration states)

Current consumption, 315MHz

27.0

14.8

12.3

15.1

13.9

14.9

14.1

16.0

14.5

mA Transmit mode, +10dBm output power

Transmit mode, 0dBm output power

Transmit mode, –6dBm output power

Receive mode, 1.2kbps, reduced current, input at sensitivity limit

Receive mode, 1.2kbps, reduced current, input well above sensitivity limit

Receive mode, 38.4kbps, reduced current, input at sensitivity limit

Receive mode,38.4kbps, reduced current, input well above sensitivity limit

Receive mode, 250kbps, reduced current, input at sensitivity limit

Receive mode, 250kbps, reduced current, input well above sensitivity limit

CC1100

Data Sheet (Rev.1.1) SWRS038A Page 9 of 89

Parameter Min Typ Max Unit Condition

Current consumption, 433MHz

28.9

15.5

13.1

15.5

14.5

15.3

14.3

16.5

15.2

mA Transmit mode, +10dBm output power

Transmit mode, 0dBm output power

Transmit mode, –6dBm output power

Receive mode, 1.2kbps, reduced current, input at sensitivity limit

Receive mode, 1.2kbps, reduced current, input well above sensitivity limit

Receive mode, 38.4kbps, reduced current, input at sensitivity limit

Receive mode, 38.4kbps, reduced current, input well above sensitivity limit

Receive mode, 250kbps, reduced current, input at sensitivity limit

Receive mode, 250kbps, reduced current, input well above sensitivity limit

Current consumption, 868/915MHz

30.7

16.9

13.5

15.4

14.4

15.2

14.4

16.4

15.1

mA Transmit mode, +10dBm output power

Transmit mode, 0dBm output power

Transmit mode, –6dBm output power

Receive mode, 1.2kbps, reduced current, input at sensitivity limit

Receive mode, 1.2kbps, reduced current, input well above sensitivity limit

Receive mode, 38.4kbps, reduced current, input at sensitivity limit

Receive mode,38.4kbps, reduced current, input well above sensitivity limit

Receive mode, 250kbps, reduced current, input at sensitivity limit

Receive mode, 250kbps, reduced current, input well above sensitivity limit

Table 4: Electrical Specifications

CC1100

Data Sheet (Rev.1.1) SWRS038A Page 10 of 89

4.2 RF Receive Section

Tc = 25°C, VDD = 3.0V if nothing else stated. All measurement results are obtained using the CC1100EM reference design.

Parameter Min Typ Max Unit Condition/Note

Digital channel filter bandwidth

58 812 kHz User programmable. The bandwidth limits are proportional

to crystal frequency (stated values assume a 26.0 MHz crystal).

315 MHz, 1.2 kbps data rate (FSK, 5.2kHz deviation, 1% packet error rate, 20 bytes packet length, 58 kHz digital channel filter bandwidth)

Receiver sensitivity -111 dBm Sensitivity can be traded for current consumption by setting

MDMCFG2.DEM_DCFILT_OFF = 1. The typical current consumption is then reduced from 17.1 mA to 15.1 mA at sensitivity llimit. The sensitivity is typically reduced to -110 dBm

315 MHz, 500 kbps data rate (MSK, 1% packet error rate, 20 bytes packet length, 812 kHz digital channel filter bandwidth)

-88 dBm

433 MHz, 1.2 kbps data rate

(FSK, 5.2kHz deviation, 1% packet error rate, 20 bytes packet length, 58 kHz digital channel filter bandwidth)

Receiver sensitivity –111 dBm Sensitivity can be traded for current consumption by setting

MDMCFG2.DEM_DCFILT_OFF = 1. The typical current consumption is then reduced from 16.8 mA to 14.5 mA at sensitivity llimit. The sensitivity is typically reduced to -109 dBm

433 MHz, 38.4 kbps data rate (FSK, 20kHz deviation, 1% packet error rate, 20 bytes packet length, 100 kHz digital channel filter bandwidth)

Receiver sensitivity –102 dBm 433 MHz, 250 kbps data rate

(MSK, 1% packet error rate, 20 bytes packet length, 540 kHz digital channel filter bandwidth)

Receiver sensitivity –93 dBm 433 MHz, 500 kbps data rate

(MSK, 1% packet error rate, 20 bytes packet length, 812 kHz digital channel filter bandwidth) Receiver sensitivity –88 dBm

868 MHz, 1.2 kbps data rate

(FSK, 5.2kHz deviation, 1% packet error rate, 20 bytes packet length, 58 kHz digital channel filter bandwidth)

Receiver sensitivity –111 dBm Sensitivity can be traded for current consumption by setting

MDMCFG2.DEM_DCFILT_OFF = 1. The typical current consumption is then reduced from 17.7 mA to 15.4 mA at sensitivity llimit. The sensitivity is typically reduced to -109 dBm

Saturation –15 dBm

Adjacent channel rejection

32 dB Desired channel 3 dB above the sensitivity limit. 100 kHz

channel spacing

Alternate channel rejection

33 dB Desired channel 3 dB above the sensitivity limit. 100 kHz

channel spacing

See Figure 25 for plot of selectivity versus frequency offset

Image channel rejection, 868MHz

30 dB IF frequency 152 kHz

Desired channel 3 dB above the sensitivity limit.

CC1100

Data Sheet (Rev.1.1) SWRS038A Page 11 of 89

Parameter Min Typ Max Unit Condition/Note 868 MHz, 38.4 kbps data rate

(FSK, 20kHz deviation, 1% packet error rate, 20 bytes packet length, 100 kHz digital channel filter bandwidth)

Receiver sensitivity –103 dBm

Saturation –16 dBm

Adjacent channel rejection

20 dB Desired channel 3 dB above the sensitivity limit. 200 kHz

channel spacing

Alternate channel rejection

29 dB Desired channel 3 dB above the sensitivity limit. 200 kHz

channel spacing

See Figure 26 for plot of selectivity versus frequency offset

Image channel rejection, 868MHz

23 dB IF frequency 152 kHz

Desired channel 3 dB above the sensitivity limit.

868 MHz, 250 kbps data rate (MSK, 1% packet error rate, 20 bytes packet length, 540 kHz digital channel filter bandwidth)

Receiver sensitivity –93 dBm Sensitivity can be traded for current consumption by setting

MDMCFG2.DEM_DCFILT_OFF = 1. The typical current consumption is then reduced from 17.6 mA to 15.1 mA at sensitivity llimit. The sensitivity is typically reduced to -91 dBm

Saturation –16 dBm

Adjacent channel rejection

24 dB Desired channel 3 dB above the sensitivity limit. 750 kHz

channel spacing

Alternate channel rejection

38 dB Desired channel 3 dB above the sensitivity limit. 750 kHz

channel spacing

See Figure 27 for plot of selectivity versus frequency offset

Image channel rejection, 868MHz

14 dB IF frequency 254 kHz

Desired channel 3 dB above the sensitivity limit.

868 MHz, 500 kbps data rate (MSK, 1% packet error rate, 20 bytes packet length, 812 kHz digital channel filter bandwidth)

Receiver sensitivity –87 dBm 868 MHz, 250 kbps data rate

(OOK, 1% packet error rate, 20 bytes packet length, 540 kHz digital channel filter bandwidth)

Receiver sensitivity -88 dBm

915 MHz, 1.2 kbps data rate

(FSK, 5.2kHz deviation, 1% packet error rate, 20 bytes packet length, 58 kHz digital channel filter bandwidth)

Receiver sensitivity –111 dBm Sensitivity can be traded for current consumption by setting

MDMCFG2.DEM_DCFILT_OFF = 1. The typical current consumption is then reduced from 17.7 mA to 15.4 mA at sensitivity llimit. The sensitivity is typically reduced to -109 dBm

915 MHz, 38.4 kbps data rate (FSK, 20kHz deviation, 1% packet error rate, 20 bytes packet length, 100 kHz digital channel filter bandwidth)

Receiver sensitivity –103 dBm 915 MHz, 250 kbps data rate

(MSK, 1% packet error rate, 20 bytes packet length, 540 kHz digital channel filter bandwidth)

Receiver sensitivity –93 dBm Sensitivity can be traded for current consumption by setting

MDMCFG2.DEM_DCFILT_OFF = 1. The typical current consumption is then reduced from 17.6 mA to 15.1 mA at sensitivity llimit. The sensitivity is typically reduced to -91 dBm

915 MHz, 500 kbps data rate (MSK, 1% packet error rate, 20 bytes packet length, 812 kHz digital channel filter bandwidth)

Receiver sensitivity –87 dBm

CC1100

Data Sheet (Rev.1.1) SWRS038A Page 12 of 89

Parameter Min Typ Max Unit Condition/Note

Blocking at 2MHz offset, 1.2 kbps, 868 MHz

-53 dBm Desired channel 3dB above the sensitivity limit. Compliant to ETSI EN 300 220 class 2 receiver requirement.

Blocking at 2MHz offset, 500 kbps, 868 MHz

-51 dBm Desired channel 3dB above the sensitivity limit. Compliant to ETSI EN 300 220 class 2 receiver requirement.

Blocking at 10MHz offset, 1.2 kbps, 868 MHz

-43 dBm Desired channel 3dB above the sensitivity limit. Compliant to ETSI EN 300 220 class 2 receiver requirement.

Blocking at 10MHz offset, 500 kbps, 868 MHz

-43 dBm Desired channel 3dB above the sensitivity limit. Compliant to ETSI EN 300 220 class 2 receiver requirement.

Spurious emissions -68

-66

–57

–47

dBm

25 MHz – 1 GHz (Maximum figure is the ETSI EN 300 220 limit)

Above 1 GHz (Maximum figure is the ETSI EN 300 220 limit)

Table 5: RF Receive Section

CC1100

Data Sheet (Rev.1.1) SWRS038A Page 13 of 89

4.3 RF Transmit Section

Tc = 25°C, VDD = 3.0V, +10dBm if nothing else stated. All measurement results are obtained using the CC1100EM reference design.

Parameter Min Typ Max Unit Condition/Note

Differential load impedance

315 MHz

433 MHz

868/915 MHz

122 + j31

116 + j41

86.5 + j43

Ω

Differential impedance as seen from the RF-port (RF_P and RF_N) towards the antenna. Follow the CC1100EM reference design available from theTI and Chipcon websites.

Output power, highest setting

10 dBm Output power is programmable, and full range is available

in all frequency bands (Output power may be restricted by regulatory limits. See also application note 039).

Delivered to a 50Ω single-ended load via Chipcon reference RF matching network.

Output power, lowest setting

-30 dBm Output power is programmable, and full range is available in all frequency bands.

Delivered to a 50Ω single-ended load via Chipcon reference RF matching network.

Harmonics, radiated

Harm, 433 MHz

Harm, 868 MHz

-50

-40

-34

-45

dBm

Measured on CC1100EM reference design with CW, 10dBm output power

The antennas used during the radiated measurements (SMAFF-433 from R.W.Badland and Nearson S331 868/915) plays a part in attenuating the harmonics

Harmonics, conducted

315 MHz

433 MHz

868 MHz

915 MHz

< -33 < -38

< -51 < -34

< -32

< -31

dBm

Measured with 10dBm CW, TX frequency at 315.00 MHz,

433.00 MHz, 868.00 MHz or 915.00 MHz

Frequencies below 960 MHz Frequencies above 960 MHz

Frequencies below 1 GHz Frequencies above 1 GHz

Spurious emissions , conducted Harmonics not included

315 MHz

433 MHz

868 MHz

915 MHz

< -58 < -53

< -50 < -54 < -56

< -50 < -51 < -54

< -51 < -51

dBm

Measured with 10dBm CW, TX frequency at 315.00 MHz,

433.00 MHz, 868.00 MHz or 915.00 MHz

Frequencies below 960 MHz Frequencies above 960 MHz

Frequencies below 1 GHz Frequencies above 1 GHz Frequencies within 47-74, 87.5-118, 174-230, 470-862 MHz

Frequencies below 960 MHz Frequencies above 960 MHz

Table 6: RF Transmit Parame ters

CC1100

Data Sheet (Rev.1.1) SWRS038A Page 14 of 89

4.4 Crystal Oscillator

Tc = 25°C @ VDD = 3.0 V if nothing else is stated.

Parameter Min Typ Max Unit Condition/Note

Crystal frequency 26 26 27 MHz

Tolerance ±40 ppm This is the total tolerance including a) initial tolerance, b) aging

and c) temperature dependence.

The acceptable crystal tolerance depends on RF frequency and channel spacing / bandwidth.

ESR 100

Ω

Start-up time 180 µs Measured on the CC1100EM reference design. This parameter is

to a large degree crystal dependent.

Table 7: Crystal Oscillator Parameters

4.5 Low Power RC Oscillator

Tc = 25°C, VDD = 3.0 V if nothing else is stated. All measurement results obtained using the CC1100EM reference design.

Parameter Min Typ Max Unit Condition/Note

Calibrated frequency 34.67 34.67 36 kHz Calibrated RC Oscillator frequency is XTAL

frequency divided by 750

Frequency accuracy after calibration

±0.3 %

Temperature coefficient +0.5

% / °C

Frequency drift when temperature changes after calibration

Supply voltage coefficient +3 % / V Frequency drift when supply voltage changes

after calibration

Initial calibration time 2 ms

When the RC Oscillator is enabled, calibration is continuously done in the background as long as the crystal oscillator is running.

Table 8: RC Oscillator parameters

CC1100

Data Sheet (Rev.1.1) SWRS038A Page 15 of 89

4.6 Frequency Synthesizer Characteristics

Tc = 25°C @ VDD = 3.0 V if nothing else is stated. All measurement results are obtained using the CC1100EM reference design.

Parameter Min Typ Max Unit Condition/Note

Programmed frequency resolution

397 F

XOSC

412 Hz 26MHz-27MHz crystal.

The resolution (in Hz) is equal for all frequency bands.

Synthesizer frequency tolerance

±40 ppm Given by crystal used. Required accuracy (including

temperature and aging) depends on frequency band and channel bandwidth / spacing.

RF carrier phase noise –89 dBc/Hz @ 50 kHz offset from carrier

RF carrier phase noise –89 dBc/Hz @ 100 kHz offset from carrier

RF carrier phase noise –90 dBc/Hz @ 200 kHz offset from carrier

RF carrier phase noise –98 dBc/Hz @ 500 kHz offset from carrier

RF carrier phase noise –107 dBc/Hz @ 1 MHz offset from carrier

RF carrier phase noise –113 dBc/Hz @ 2 MHz offset from carrier

RF carrier phase noise –119 dBc/Hz @ 5 MHz offset from carrier

RF carrier phase noise –129 dBc/Hz @ 10 MHz offset from carrier

PLL turn-on / hop time 88.4

µs

Time from leaving the IDLE state until arriving in the RX, FSTXON or TX state, when not performing calibration. Crystal oscillator running.

PLL RX/TX settling time

9.6

µs

Settling time for the 1xIF frequency step from RX to TX

PLL TX/RX settling time

21.5

µs

Settling time for the 1xIF frequency step from TX to RX

PLL calibration time

0.69

18739

0.72

XOSC cycles

Calibration can be initiated manually, or automatically before entering or after leaving RX/TX.

Min/typ/max time is for 27/26/26MHz crystal frequency.

Table 9: Frequency Synthe sizer Pa rameter s

CC1100

Data Sheet (Rev.1.1) SWRS038A Page 16 of 89

4.7 Analog temperature sensor

The characteristics of the analog temperature sensor are listed in Table 10 below. Note that it is necessary to write 0xBF to the PTEST register to use the analog temperature sensor in the IDLE state.

Parameter Min Typ Max Unit Condition/Note

Output voltage at –40°C

0.651 V

Output voltage at 0°C

0.747 V

Output voltage at +40°C

0.847 V

Output voltage at +80°C

0.945 V

Temperature coefficient 2.45

mV/°C Fitted from –20°C to +80°C

Error in calculated temperature, calibrated

-2

0 2

°C From –20°C to +80°C when using 2.54mV / °C,

after 1-point calibration at room temperature

Indicated minimum and maximum error with 1point calibration is based on simulated values for typical process parameters

Current consumption increase when enabled

0.3 mA

Table 10: Analog Temperature Sensor Parameters

4.8 DC Characteristics

Tc = 25°C if nothing else stated.

Digital Inputs/Outputs Min Max Unit Condition

Logic "0" input voltage 0 0.7 V

Logic "1" input voltage VDD-0.7 VDD V

Logic "0" output voltage 0 0.5 V For up to 4mA output current

Logic "1" output voltage VDD-0.3 VDD V For up to 4mA output current

Logic "0" input current N/A –50 nA Input equals 0V

Logic "1" input current N/A 50 nA Input equals VDD

Table 11: DC Characteristics

4.9 Power On Reset

When the power supply complies with the requirements in Table 12 below, proper Power-OnReset functionality is guaranteed. Otherwise, the chip should be assumed to have unknown state until transmitting an SRES strobe over the SPI interface.

Parameter Min Typ Max Unit Condition/Note

Power-up ramp-up time. 5 ms From 0V until reaching 1.8V

Power off time 1 ms Minimum time between power-on and power-off.

Table 12: Power-on Reset Requirements

CC1100

Data Sheet (Rev.1.1) SWRS038A Page 17 of 89

5 Pin Configuration

20 19 18 17 16

109876

GND Exposed die attach pad

SCLK

SO (GDO1)

GDO2

DVDD

DCOUPL

GDO0 (ATEST)

XOSC_Q1

AVDD

XOSC_Q2

AVDD

RF_P

RF_N

GND

AVDD

RBIAS

DGUARD

GND

CSn

AVDD

Figure 1: Pinout top view

Note: The exposed die attach pad must be connected to a solid ground plane as this is the main

ground connection for the chip.

CC1100

Data Sheet (Rev.1.1) SWRS038A Page 18 of 89

Pin # Pin name Pin type Description

SCLK

Digital Input Serial configuration interface, clock input

SO (GDO1)

Digital Output Serial configuration interface, data output.

Optional general output pin when

CSn

is high

GDO2

Digital Output Digital output pin for general use:

• Test signals

• FIFO status signals

• Clear Channel Indicator

• Serial output RX data

DVDD

Power (Digital) 1.8-3.6 V digital power supply for digital I/O’s and for the digital core

voltage regulator

DCOUPL

Power (Digital) 1.6-2.0 V digital power supply output for decoupling.

NOTE: This pin is intended for use with the

CC1100

only. It can not be

used to provide supply voltage to other devices.

GDO0 (ATEST)

Digital I/O

Digital output pin for general use:

• Test signals

• FIFO status signals

• Clear Channel Indicator

• Serial output RX data

• Serial input TX data

Also used as analog test I/O for prototype/production testing

CSn

Digital Input Serial configuration interface, chip select

XOSC_Q1

Analog I/O Crystal oscillator pin 1, or external clock input

AVDD

Power (Analog) 1.8-3.6 V analog power supply connection

XOSC_Q2

Analog I/O Crystal oscillator pin 2

AVDD

Power (Analog) 1.8-3.6 V analog power supply connection

RF_P

RF I/O Positive RF input signal to LNA in receive mode

Positive RF output signal from PA in transmit mode

RF_N

RF I/O Negative RF input signal to LNA in receive mode

Negative RF output signal from PA in transmit mode

AVDD

Power (Analog) 1.8-3.6 V analog power supply connection

AVDD

Power (Analog) 1.8-3.6 V analog power supply connection

GND

Ground (Analog) Analog ground connection

RBIAS

Analog I/O External bias resistor for reference current

DGUARD

Power (Digital) Power supply connection for digital noise isolation

GND

Ground (Digital) Ground connection for digital noise isolation

Digital Input Serial configuration interface, data input

Table 13: Pinout overview

CC1100

Data Sheet (Rev.1.1) SWRS038A Page 19 of 89

6 Circuit Description

BIAS

RBI AS XOSC_Q1 XOSC_Q2

CSn

SO (GDO1)

XOSC

SCLK

LNA

FREQ

SYNTH

ADC

DEMODULATOR

FEC / INTERLEAVER

PACKET HANDLER

RXFIFO

MODULATOR

TXFIFO

DIGITAL INTERFACE TO MCU

RADIO CONTROL

RF_P RF_N

GDO2

GDO0 (ATEST)

RC OSC

Figure 2:

CC1100

Simplified Block Dia gram

A simplified block diagram of

CC1100

is shown

in Figure 2.

CC1100

features a low-IF receiver. The received RF signal is amplified by the lownoise amplifier (LNA) and down-converted in quadrature (I and Q) to the intermediate frequency (IF). At IF, the I/Q signals are digitised by the ADCs. Automatic gain control (AGC), fine channel filtering and demodulation bit/packet synchronization are performed digitally.

The transmitter part of

CC1100

is based on

direct synthesis of the RF frequency. The

frequency synthesizer includes a completely on-chip LC VCO and a 90 degree phase shifter for generating the I and Q LO signals to the down-conversion mixers in receive mode.

A crystal is to be connected to XOSC_Q1 and XOSC_Q2. The crystal oscillator generates the reference frequency for the synthesizer, as well as clocks for the ADC and the digital part.

A 4-wire SPI serial interface is used for configuration and data buffer access.

The digital baseband includes support for channel configuration, packet handling and data buffering.

7 Application Circuit

Only a few external components are required for using the

CC1100

. The recommended application circuits are shown in Figure 3 and Figure 4. The external components are described in Table 14, and typical values are given in Table 15.

Bias resistor

The bias resistor R171 is used to set an accurate bias current reference.

Balun and RF matching

The components between the RF_N/RF_P pins and the point where the two signals are

joined together (C131, C121, L121 and L131 for the 315/433 MHz desgn. L121, L131, C121, L122, C131, C122 and L132 for the 868/915 MHz reference design) form a balun that converts the differential RF signal on

CC1100

to a single-ended RF signal (C124 is also needed for DC blocking). Together with an appropriate LC network, the balun components also transform the impedance to match a 50Ω antenna (or cable). Suggested values for 315MHz, 433MHz and 868/915MHz are listed in Table 15.

The balun and LC filter component values and their placement are important to achieve

CC1100

Data Sheet (Rev.1.1) SWRS038A Page 20 of 89

optimal performance. It is highly recommended to follow the CC1100EM reference design.

Crystal

The crystal oscillator uses an external crystal with two loading capacitors (C81 and C101). See section 25 on page 49 for details.

Additional filtering

Additional external components (e.g. an RF SAW filter) may be used in order to improve the performance in specific applications.

Power supply decoupling

The power supply must be properly decoupled close to the supply pins. Note that decoupling capacitors are not shown in the application circuit. The placement and the size of the decoupling capacitors are very important to achieve the optimum performance. The CC1100EM reference design should be followed closely.

Component Description

C51 100nF decoupling capacitor for on-chip voltage regulator to digital part

C81/C101 Crystal loading capacitors, see section 25 on page 49 for details

C121/C131 RF balun/matching capacitors

C122 RF LC filter/matching filter capacitor (315 and 433 MHz). RF balun/matching

capacitor (868/915 MHz).

C123 RF LC filter/matching capacitor

C124 RF balun DC blocking capacitor

C125 RF LC filter DC blocking capacitor (only needed if there is a DC path in the antenna)

L121/L131 RF balun/matching inductors (inexpensive multi-layer type)

L122 RF LC filter/matching filter inductor (315 and 433 MHz). RF balun/matching inductor

(868/915 MHz). (inexpensive multi-layer type)

L123 RF LC filter/matching filter inductor (inexpensive multi-layer type)

L132 RF balun/matching inductor. (inexpensive multi-layer type)

R171 56kΩ resistor for internal bias current reference. 1% tolerance

XTAL 26MHz-27MHz crystal, see section 25 on page 49 for details

Table 14: Overview of external components (excluding supply decoupling capacitors)

CC1100

Data Sheet (Rev.1.1) SWRS038A Page 21 of 89

Antenna

(50 Ohm)

Digital Inteface

1.8V-3.6V power supply

6 GDO0

7 CSn

8 XOSC_Q1

9 AVDD

10 XOSC_Q2

SI 20

GND 19

DGUARD 18

RBIAS 17

GND 16

1 SCLK

2 SO (GDO1)

3 GDO2

4 DVDD

5 DCOUPL

AVDD 15

AVDD 14

RF_N 13

RF_P 12

AVDD 11

XTAL

L122 L123

C122 C123

C125

R171

C81 C101

C51

CSn

GDO0 (optional)

GDO2 (optional)

SO (GDO1)

SCLK

CC1100

DIE ATTACH PAD:

C131

C121

L121

L131

C124

Figure 3: Typical application and evaluation circuit 315/433 MHz (excluding supply decoupling

capacitors)

Antenna

(50 Ohm)

Digital Inteface

1.8V-3.6V power supply

6 GDO0

7 CSn

8 XOSC_Q1

9 AVDD

10 XOSC_Q2

SI 20

GND 19

DGUARD 18

RBIAS 17

GND 16

1 SCLK

2 SO (GDO1)

3 GDO2

4 DVDD

5 DCOUPL

AVDD 15

AVDD 14

RF_N 13

RF_P 12

AVDD 11

XTAL

C121

C122

L122

L132

C124

L131

L123

C125

R171

C81 C101

C51

CSn

GDO0 (optional)

GDO2 (optional)

SO (GDO1)

SCLK

DIE ATTACH PAD:

L121

C131

C123

Figure 4: Typical application and evaluation circuit 868/915 MHz (excluding supply

decoupling capacitors)

CC1100

Data Sheet (Rev.1.1) SWRS038A Page 22 of 89

Component Value at 315MHz

Value at 433MHz Value at 868/915MHz

C51 100nF±10%, 0402 X5R

C81 27pF±5%, 0402 NP0

C101 27pF±5%, 0402 NP0

C121 6.8pF±0.5pF, 0402 NP0 3.9pF±0.25pF, 0402 NP0 1.0pF±0.25pF, 0402 NP0

C122 12pF±5%, 0402 NP0 8.2pF±0.5pF, 0402 NP0 1.5pF±0.25pF, 0402 NP0

C123 6.8pF±0.5pF, 0402 NP0 5.6pF±0.5pF, 0402 NP0 1.8pF±0.25pF, 0402 NP0

C124 220pF±5%, 0402 NP0 220pF±5%, 0402 NP0 100pF±5%, 0402 NP0

C125 220pF±5%, 0402 NP0 220pF±5%, 0402 NP0 100pF±5%, 0402 NP0

C131 6.8pF±0.5pF, 0402 NP0 3.9pF±0.25pF, 0402 NP0 1.5pF±0.25pF, 0402 NP0

L121 33nH±5%, 0402 monolithic 27nH±5%, 0402 monolithic 12nH±5%, 0402 monolithic

L122 18nH±5%, 0402 monolithic 22nH±5%, 0402 monolithic 18nH±5%, 0402 monolithic

L123 33nH±5%, 0402 monolithic 27nH±5%, 0402 monolithic 6.2nH±5%, 0402 monolithic

L131 33nH±5%, 0402 monolithic 27nH±5%, 0402 monolithic 12nH±5%, 0402 monolithic

L132 18nH±5%, 0402 monolithic

R171 56kΩ±1%, 0402

XTAL 26.0MHz surface mount crystal

Table 15: Bill Of Materials for the application circuit

In the CC1100EM reference designs shown in Figure 5 and Figure 6, LQG-15HS series inductors and GRM1555C series capacitors from Murata have been used.

The Gerber files for the CC1100EM reference designs are available from the TI and Chipcon websites.

Figure 5: CC1100EM reference design, 433

MHz. Same PCB is used for 315 MHz

Figure 6: CC1100EM reference design,

868/915 MHz

CC1100

Data Sheet (Rev.1.1) SWRS038A Page 23 of 89

8 Configuration Overview

CC1100

can be configured to achieve optimum performance for many different applications. Configuration is done using the SPI interface. The following key parameters can be programmed:

• Power-down / power up mode

• Crystal oscillator power-up / power-down

• Receive / transmit mode

• RF channel selection

• Data rate

• Modulation format

• RX channel filter bandwidth

• RF output power

• Data buffering with separate 64-byte

receive and transmit FIFOs

• Packet radio hardware support

• Forward Error Correction with interleaving

• Data Whitening

• Wake-On-Radio (WOR)

Details of each configuration register can be found in section 31, starting on page 56.

Figure 7 shows a simplified state diagram that explains the main

CC1100

states, together with typical usage and current consumption. For detailed information on controlling the

CC1100

state machine, and a complete state diagram, see section 19, starting on page 41.

Transmit mode Receive mode

IDLE

Manual freq.

synth. calibration

RX FIFO

overflow

TX FIFO

underflow

Frequency

synthesizer on

SFSTXON

SRX or wake-on-radio (WOR)

STX

STX or RXOFF_MODE=10

RXOFF_MODE=00

SFTX

SRX or TXOFF_MODE=11

SIDLE

SCAL

SFRX

IDLE

TXOFF_MODE=00

SFSTXON or RXOFF_MODE=01

SRX or STX or SFSTXON or wake-on-radio (WOR)

Sleep

SPWD or w ake-on-radio (WO R)

Crystal

oscillator off

SXOFF

CSn=0

TXOFF_MODE=01

Frequency synthesizer startup, optional calibration,

settling

Optiona l freq.

synth. calibration

Default state when the radio is not receiving or transmitting. Typ. current consumption: 1.6mA.

Lowest power mode. Most register values are retained. Current consumption typ 400nA, or typ 900nA when wake-on -radio (W OR) is enabled.

All register values are retained. Typ. current consumption; 0.16mA.

Used for calibrating frequency synthesizer upfront (entering receive or transmit mode can then be done quicker). Transitional state. Typ. current consumption: 8.2mA.

Frequency synthesizer is turned on, can optionally be calibrated, and then settles to the correct frequency. Transitional state. Typ. current consumption: 8.2mA.

Frequency synthesizer is on, ready to s tart transm itting. Transmission starts very quickly after receiving the STX command strobe.Typ. current consumption: 8.2mA.

Typ. current consumption:

13.5mA at -6dBm output,

16.5mA at 0dBm output, 30mA at +10dBm output.

Typ. current consumption: from 14.4mA (strong input signal) to 15.4mA (weak input signal) at

1.2kbps.

Optional transitional state. Typ. current consumption: 8.2mA.

In FIFO-based modes, transmission is turned off and this state entered if the TX FIFO becomes empty in the middle of a packet. Typ. current consumption: 1.6mA.

In FIFO-based modes, reception is turned off and this state entered if the RX FIFO overflows. Typ. current consumption:

1.6mA.

Figure 7: Simplified state diagram, with typical usage and current consumption

CC1100

Data Sheet (Rev.1.1) SWRS038A Page 24 of 89

9 Configuration Software

CC1100

can be configured using the SmartRF® Studio software, available for download from http://www.chipcon.com or www.ti.com/lpw. The SmartRF

Studio software is highly

recommended for obtaining optimum register

settings, and for evaluating performance and functionality. A screenshot of the SmartRF

Studio user interface for

CC1100

is shown in

Figure 8.

Figure 8: SmartRF

Studio user interface

10 4-wire Serial Configuration and Data Interface

CC1100

is configured via a simple 4-wire SPI-

compatible interface (SI, SO, SCLK and CSn) where

CC1100

is the slave. This interface is also used to read and write buffered data. All address and data transfer on the SPI interface is done most significant bit first.

All transactions on the SPI interface start with a header byte containing a read/write bit, a burst access bit and a 6-bit address.

During address and data transfer, the CSn pin (Chip Select, active low) must be kept low. If CSn goes high during the access, the transfer

will be cancelled. The timing for the address and data transfer on the SPI interface is shown in Figure 9 with reference to Table 16.

When CSn goes low, the MCU must wait until

CC1100

SO pin goes low before starting to

transfer the header byte. This indicates that the voltage regulator has stabilized and the crystal is running. Unless the chip was in the SLEEP or XOFF states, the SO pin will always go low immediately after taking CSn low.

Figure 10 gives a brief overview of different register access types possible.

CC1100

Data Sheet (Rev.1.1) SWRS038A Page 25 of 89

A6 A5 A4 A3 A2

A0A1

DW7 DW6 DW5 DW4 DW3 DW2 DW1 DW0

A6 A5 A4 A3 A2

A0A1

DR7 DR6 DR5 DR4 DR3 DR2 DR1 D

Read from register:

Write to register:

Hi-Z

SCLK:

CSn:

Hi-Z

S7 S 6 S 5 S4 S 3 S 2 S 1 S0

Hi-Z

S7 S 6 S 5 S4 S 3 S 2 S 1 S0 S7 S6 S5 S4 S3 S 2 S1 S0 S7

Figure 9: Configuration registers write and read operations

Parameter Description Min Max Units

SCLK

frequency

100 ns delay inserted between address byte and data byte (single access), or between address and data, and between each data byte (burst access).

- 10

SCLK

frequency, single access

No delay between address and data byte

- 9

SCLK

frequency, burst access

No delay between address and data byte, or between data bytes

- 6.5

MHz

sp,pd

CSn

low to positive edge on

SCLK

, in power-down mode

200 -

µs

tsp

CSn

low to positive edge on

SCLK

, in active mode

20 - ns

tch Clock high 50 - ns

tcl Clock low 50 - ns

rise

Clock rise time - 5 ns

fall

Clock fall time - 5 ns

tsd Setup data (negative SCLK edge) to

positive edge on

SCLK

(tsd applies between address and data bytes, and between data bytes)

Single access

Burst access

thd

Hold data after positive edge on

SCLK

20 - ns

tns

Negative edge on

SCLK

CSn

high.

20 - ns

Table 16: SPI interface timing requirements

DATA

byte 0

DDR

FIFO

DATA

byte 1

DATA

byte 2

DATA

byte n-1

DATA

byte n

...

DDR

strobe

DATA

DDR

strobe

DDR

reg

DDR

reg n

DATAnDATA

n+1

DATA

n+2

...

DDR

strobe

...

CSn:

Command strobe(s):

Read or write register(s):

ead or write consecutive register s (burst):

DATA

DDR

reg

DATA

DDR

reg

...

DATA

byte 0

DDR

FIFO

DATA

byte 1

Combinations:

DATA

DDR

reg

DATA

DDR

reg

DDR

strobe

DDR

strobe

...

Read or write n+1 bytes from/to RF FIFO:

Figure 10: Register access types

CC1100

Data Sheet (Rev.1.1) SWRS038A Page 26 of 89

10.1 Chip Status Byte

When the header byte, data byte or command strobe is sent on the SPI interface, the chip

status byte is sent by the

CC1100

on the SO pin.

The status byte contains key status signals, useful for the MCU. The first bit, s7, is the CHIP_RDYn signal; this signal must go low before the first positive edge of SCLK. The CHIP_RDYn signal indicates that the crystal is running and the regulated digital supply voltage is stable.

Bits 6, 5 and 4 comprises the STATE value. This value reflects the state of the chip. The XOSC and power to the digital core is on in the IDLE state, but all other modules are in power down. The frequency and channel configuration should only be updated when the

chip is in this state. The RX state will be active when the chip is in receive mode. Likewise, TX is active when the chip is transmitting.

The last four bits (3:0) in the status byte contains FIFO_BYTES_AVAILABLE. For read operations, the FIFO_BYTES_AVAILABLE field contains the number of bytes available for reading from the RX FIFO. For write operations, the FIFO_BYTES_AVAILABLE field contains the number of bytes free for writing into the TX FIFO. When FIFO_BYTES_AVAILABLE=15, 15 or more bytes are available/free.

Table 17 gives a status byte summary.

Bits Name Description

7 CHIP_RDYn Stays high until power and crystal have stabilized. Should always be low when using

the SPI interface.

6:4 STATE[2:0] Indicates the current main state machine mode

Value State Description

000 Idle IDLE state

(Also reported for some transitional states instead of SETTLING or CALIBRATE, due to a small error)

001 RX Receive mode

010 TX Transmit mode

011 FSTXON Fast TX ready

100 CALIBRATE Frequency synthesizer calibration is running

101 SETTLING PLL is settling

110 RXFIFO_OVERFLOW RX FIFO has overflowed. Read out any

useful data, then flush the FIFO with

SFRX

111 TXFIFO_UNDERFLOW TX FIFO has underflowed. Acknowledge with

SFTX

3:0 FIFO_BYTES_AVAILABLE[3:0] The number of bytes available in the RX FIFO or free bytes in the TX FIFO

(depends on the read/write-bit). If FIFO_BYTES_AVAILABLE=15, it indicates that 15 or more bytes are available/free.

Table 17: Status byte summary

10.2 Register Access

The configuration registers on the

CC1100

are

located on SPI addresses from 0x00 to 0x2F. Table 35 on page 58 lists all configuration registers. The detailed description of each register is found in Section 31.1, starting on page 61. All configuration registers can be both written to and read. The read/write bit

controls if the register should be written to or read. When writing to registers, the status byte is sent on the SO pin each time a header byte or data byte is transmitted on the SI pin. When reading from registers, the status byte is

CC1100

Data Sheet (Rev.1.1) SWRS038A Page 27 of 89

sent on the SO pin each time a header byte is transmitted on the SI pin.

Registers with consecutive addresses can be accessed in an efficient way by setting the burst bit in the address header. The address sets the start address in an internal address counter. This counter is incremented by one each new byte (every 8 clock pulses). The burst access is either a read or a write access and must be terminated by setting CSn high.

For register addresses in the range 0x300x3D, the “burst” bit is used to select between status registers and command strobes (see below). The status registers can only be read. Burst read is not available for status registers, so they must be read one at a time.

10.3 SPI Read

When reading register fields over the SPI interface while the register fields are updated by the radio hardware (e.g. MARCSTATE or TXBYTES), there is a small, but finite, probability that a single read from the register being corrupt. As an example, the probability of any single read from TXBYTES being corrupt, assuming the maximum data rate is used, is approximately 80 ppm. Refer to the

CC1100

Errata Note for more details.

10.4 Command Strobes

Command Strobes may be viewed as single byte instructions to

CC1100

. By addressing a Command Strobe register, internal sequences will be started. These commands are used to disable the crystal oscillator, enable receive mode, enable wake-on-radio etc. The 14 command strobes are listed in Table 34 on page 57.

The command strobe registers are accessed in the same way as for a register write operation, but no data is transferred. That is, only the R/W bit (set to 0), burst access (set to

0) and the six address bits (in the range 0x30 through 0x3D) are written.

When writing command strobes, the status byte is sent on the SO pin.

A command strobe may be followed by any other SPI access without pulling CSn high. After issuing an SRES command strobe the next command strobe can be issued when the SO pin goes low as shown in Figure 11 The command strobes are executed immediately, with the exception of the SPWD and the SXOFF

strobes that are executed when CSn goes high.

Figure 11: SRES command strobe

10.5 FIFO Access

The 64-byte TX FIFO and the 64-byte RX FIFO are accessed through the 0x3F address. When the read/write bit is zero, the TX FIFO is accessed, and the RX FIFO is accessed when the read/write bit is one.

The TX FIFO is write-only, while the RX FIFO is read-only.

The burst bit is used to determine if FIFO access is single byte or a burst access. The single byte access method expects address with burst bit set to zero and one data byte. After the data byte a new address is expected; hence, CSn can remain low. The burst access method expects one address byte and then consecutive data bytes until terminating the access by setting CSn high.

The following header bytes access the FIFOs:

• 0x3F: Single byte access to TX FIFO

• 0x7F: Burst access to TX FIFO

• 0xBF: Single byte access to RX FIFO

• 0xFF: Burst access to RX FIFO

When writing to the TX FIFO, the status byte (see Section 10.1) is output for each new data byte on SO, as shown in Figure 9. This status byte can be used to detect TX FIFO underflow while writing data to the TX FIFO. Note that the status byte contains the number of bytes

free before writing the byte in progress to the

TX FIFO. When the last byte that fits in the TX FIFO is transmitted to the SI pin, the status byte received concurrently on the SO pin will indicate that one byte is free in the TX FIFO.

The transmit FIFO may be flushed by issuing a SFTX command strobe. Similarly, a SFRX command strobe will flush the receive FIFO. A SFTX or SFRX command strobe can only be issued in the IDLE, TXFIFO_UNDERLOW or

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