TEXAS INSTRUMENTS CC1021 Technical data

CC1021

CC1021

Applications

• Low power UHF wireless data

• 433, 868 and 915 MHz ISM/SRD band

• AMR ñ Automatic Meter Reading

Product Description

CC1021

ceiver designed for very low power and
very low voltage wireless applications. The
circuit is mainly intended for the ISM
(Industrial, Scientific and Medical) and
SRD (Short Range Device) frequency
bands at 433, 868 and 915 MHz, but can
easily be programmed for multi-channel
operation at other frequencies in the 402 ­470 and 804 - 940 MHz range.

The
narrowband systems with channel
spacings of 50 kHz and higher complying
with EN 300 220 and FCC CFR47 part 15.

The
can be programmed via a serial bus, thus
making
use transceiver.

Features

• True single chip UHF RF transceiver

• Frequency range 402 MHz - 470 MHz

• High sensitivity (up to ñ112 dBm for

• Programmable output power

• Low current consumption (RX: 19.9

• Low supply voltage (2.3 V to 3.6 V)

• Very few external components required

• Small size (QFN 32 package)

• Pb-free package

• Digital RSSI and carrier sense indicator

• Data rate up to 153.6 kBaud

Single Chip Low Power RF Transceiver for Narrowband Systems

transmitters and receivers with channel
spacings of 50 kHz or higher

systems

is a true single-chip UHF trans-

CC1021

is especially suited for

CC1021

main operating parameters

CC1021

a very flexible and easy to

and 804 MHz - 940 MHz

38.4 kHz and ñ106 dBm for 102.4 kHz
receiver channel filter bandwidths
respectively)

mA)

• Wireless alarm and security systems

• Home automation

• Low power telemetry

• Automotive (RKE/TPMS)

In a typical system
together with a microcontroller and a few
external passive components.

CC1021

is based on Chipconís SmartRF-

02 technology in 0.35 µm CMOS.

• OOK, FSK and GFSK data modulation

• Integrated bit synchronizer

• Image rejection mixer

• Programmable frequency

• Automatic frequency control (AFC)

• Suitable for frequency hopping systems

• Suited for systems targeting

compliance with EN 300 220 and FCC
CFR47 part 15

• Development kit available

• Easy-to-use software for generating the

CC1021

configuration data

• Fully compatible with
receiver channel filter bandwidths of

38.4 kHz and higher

CC1021

will be used

CC1020

for

SWRS045 Page 1 of 91

CC1021

Table of Contents

1. Abbreviations.................................................................................................................4

2. Absolute Maximum Ratings .........................................................................................5

3. Operating Conditions....................................................................................................5

4. Electrical Specifications...............................................................................................5

4.1. RF Transmit Section.............................................................................................6

4.2. RF Receive Section..............................................................................................8

4.3. RSSI / Carrier Sense Section.............................................................................11

4.4. IF Section............................................................................................................11

4.5. Crystal Oscillator Section ...................................................................................12

4.6. Frequency Synthesizer Section..........................................................................13

4.7. Digital Inputs / Outputs .......................................................................................14

4.8. Current Consumption .........................................................................................15

5. Pin Assignment ...........................................................................................................15

6. Circuit Description ......................................................................................................17

7. Application Circuit.......................................................................................................18

8. Configuration Overview..............................................................................................21

8.1. Configuration Software.......................................................................................21

9. Microcontroller Interface ............................................................................................22

9.1. 4-wire Serial Configuration Interface..................................................................23

9.2. Signal Interface...................................................................................................25

10. Data Rate Programming .............................................................................................27

11. Frequency Programming............................................................................................28

11.1. Dithering..........................................................................................................29

12. Receiver........................................................................................................................30

12.1. IF Frequency...................................................................................................30

12.2. Receiver Channel Filter Bandwidth ................................................................30

12.3. Demodulator, Bit Synchronizer and Data Decision.........................................31

12.4. Receiver Sensitivity versus Data Rate and Frequency Separation................32

12.5. RSSI................................................................................................................33

12.6. Image Rejection Calibration............................................................................35

12.7. Blocking and Selectivity..................................................................................36

12.8. Linear IF Chain and AGC Settings .................................................................38

12.9. AGC Settling ...................................................................................................40

12.10. Preamble Length and Sync Word...................................................................40

12.11. Carrier Sense..................................................................................................41

12.12. Automatic Power-up Sequencing ...................................................................41

12.13. Automatic Frequency Control .........................................................................42

12.14. Digital FM........................................................................................................43

SWRS045 Page 2 of 91

CC1021

13. Transmitter...................................................................................................................44

13.1. FSK Modulation Formats................................................................................44

13.2. Output Power Programming ...........................................................................44

13.3. TX Data Latency .............................................................................................45

13.4. Reducing Spurious Emission and Modulation Bandwidth ..............................46

14. Input / Output Matching and Filtering .......................................................................46

15. Frequency Synthesizer...............................................................................................50

15.1. VCO, Charge Pump and PLL Loop Filter .......................................................50

15.2. VCO and PLL Self-Calibration........................................................................51

15.3. PLL Turn-on Time versus Loop Filter Bandwidth ...........................................52

15.4. PLL Lock Time versus Loop Filter Bandwidth ................................................53

16. VCO and LNA Current Control...................................................................................53

17. Power Management.....................................................................................................54

18. On-Off Keying (OOK)...................................................................................................56

19. Crystal Oscillator.........................................................................................................58

20. Built-in Test Pattern Generator ..................................................................................59

21. Interrupt on Pin DCLK.................................................................................................60

21.1. Interrupt upon PLL Lock..................................................................................60

21.2. Interrupt upon Received Signal Carrier Sense...............................................60

22. PA_EN and LNA_EN Digital Output Pins ..................................................................60

22.1. Interfacing an External LNA or PA..................................................................60

22.2. General Purpose Output Control Pins ............................................................61

22.3. PA_EN and LNA_EN Pin Drive.......................................................................61

23. System Considerations and Guidelines ...................................................................61

24. PCB Layout Recommendations.................................................................................63

25. Antenna Considerations.............................................................................................64

26. Configuration Registers .............................................................................................64

26.1. CC1021 Register Overview ............................................................................65

27. Package Description (QFN 32)...................................................................................85

27.1. Package Marking ............................................................................................86

27.2. Recommended PCB Footprint for Package (QFN 32) ...................................87

27.3. Package Thermal Properties ..........................................................................87

27.4. Soldering Information......................................................................................87

27.5. Plastic Tube Specification...............................................................................88

27.6. Carrier Tape and Reel Specification...............................................................88

28. Ordering Information...................................................................................................88

29. General Information ....................................................................................................89

30. Address Information ...................................................................................................91

SWRS045 Page 3 of 91

CC1021

1. Abbreviations

ACP Adjacent Channel Power
ACR Adjacent Channel Rejection
ADC Analog-to-Digital Converter
AFC Automatic Frequency Control
AGC Automatic Gain Control
AMR Automatic Meter Reading
ASK Amplitude Shift Keying
BER Bit Error Rate
BOM Bill Of Materials
bps bits per second
BT Bandwidth-Time product (for GFSK)
ChBW Receiver Channel Filter Bandwidth
CW Continuous Wave
DAC Digital-to-Analog Converter
DNM Do Not Mount
ESR Equivalent Series Resistance
FHSS Frequency Hopping Spread Spectrum
FM Frequency Modulation
FS Frequency Synthesizer
FSK Frequency Shift Keying
GFSK Gaussian Frequency Shift Keying
IC Integrated Circuit
IF Intermediate Frequency
IP3 Third Order Intercept Point
ISM Industrial Scientific Medical
kbps kilo bits per second
LNA Low Noise Amplifier
LO Local Oscillator (in receive mode)
MCU Micro Controller Unit
NRZ Non Return to Zero
OOK On-Off Keying
PA Power Amplifier
PD Phase Detector / Power Down
PER Packet Error Rate
PCB Printed Circuit Board
PN9 Pseudo-random Bit Sequence (9-bit)
PLL Phase Locked Loop
PSEL Program Select
RF Radio Frequency
RKE Remote Keyless Entry
RSSI Received Signal Strength Indicator
RX Receive (mode)
SBW Signal Bandwidth
SPI Serial Peripheral Interface
SRD Short Range Device
TBD To Be Decided/Defined
TPMS Tire Pressure Monitoring
T/R Transmit/Receive (switch)
TX Transmit (mode)
UHF Ultra High Frequency
VCO Voltage Controlled Oscillator
VGA Variable Gain Amplifier
XOSC Crystal oscillator
XTAL Crystal

SWRS045 Page 4 of 91

CC1021

2. Absolute Maximum Ratings

The absolute maximum ratings given Table 1 should under no circumstances be violated.
Stress exceeding one or more of the limiting values may cause permanent damage to the
device.

Supply voltage, VDD -0.3 5.0 V All supply pins must have the

Voltage on any pin -0.3 VDD+0.3, max 5.0 V
Input RF level 10 dBm
Storage temperature range -50 150
Package body temperature 260
Humidity non-condensing 5 85 %
ESD
(Human Body Model)

1

The reflow peak soldering temperature (body temperature) is specified according to
IPC/JEDEC J-STD_020C ìMoisture/Reflow Sensitivity Classification for Nonhermetic Solid
State Surface Mount Devicesî.

3. Operating Conditions

The operating conditions for

RF Frequency Range 402

Operating ambient temperature

range

Supply voltage

4. Electrical Specifications

Table 3 to Table 10 gives the
performed using the 2 layer PCB CC1020EMX reference design. This is the same test circuit
as shown in Figure 3. Temperature = 25°C, supply voltage = AVDD = DVDD = 3.0 V if
nothing else stated. Crystal frequency = 14.7456 MHz.

The electrical specifications given for 868 MHz are also applicable for the 902 ñ 928 MHz
frequency range.

Parameter Min Max Unit Condition

same voltage

Norm: IPC/JEDEC J-STD-020C 1

All pads except RF
RF Pads

±1

±0.4

°C
°C

kV
kV

Table 1. Absolute maximum ratings

Caution! ESD sensitive device.
Precaution should be used when handling
the device in order to prevent permanent
damage.

CC1021

are listed in Table 2.

Parameter

Min Typ Max Unit Condition / Note

804

-40 85

2.3 3.0 3.6 V

470
940

MHz

Programmable in <300 Hz steps

MHz

Programmable in <600 Hz steps

°C

The same supply voltage should
be used for digital (DVDD) and
analog (AVDD) power.

Table 2. Operating conditions

CC1021

electrical specifications. All measurements were

SWRS045 Page 5 of 91

CC1021

4.1. RF Transmit Section

Parameter

Transmit data rate

Binary FSK frequency separation

Output power

433 MHz

868 MHz

Output power tolerance

Harmonics, radiated CW

nd

2

harmonic, 433 MHz, +10 dBm

rd

3

harmonic, 433 MHz, +10 dBm

nd

harmonic, 868 MHz, +5 dBm

2

rd

3

harmonic, 868 MHz, +5 dBm

Adjacent channel power (GFSK)

433 MHz

868 MHz

Occupied bandwidth (99.5%,GFSK)

433 MHz

868 MHz

Modulation bandwidth, 868 MHz

19.2 kBaud, ±9.9 kHz frequency

deviation

38.4 kBaud, ±19.8 kHz frequency

deviation

Min Typ Max Unit Condition / Note

0.45

0
0

-20 to +10

-20 to +5

153.6 kBaud The data rate is programmable.

108

-4

+3

-50

-50

-50

-50

-46

-42

60

60

48

106

216

See section 10 on page 27 for
details.

NRZ or Manchester encoding can
be used. 153.6 kBaud equals

153.6 kbps using NRZ coding
and 76.8 kbps using Manchester
coding. See section 9.2 on page
25 for details

Minimum data rate for OOK is 2.4
kBaud

kHz

in 402 - 470 MHz range

kHz

in 804 - 940 MHz range

108/216 kHz is the maximum
guaranteed separation at 1.84
MHz reference frequency. Larger
separations can be achieved at
higher reference frequencies.

Delivered to 50 Ω single-ended
load. The output power is

dBm

programmable and should not be
programmed to exceed +10/+5

dBm

dBm at 433/868 MHz under any
operating conditions. See section
14 on page 46 for details.

At maximum output power

dB

At 2.3 V, +85
At 3.6 V, -40

dB

Harmonics are measured as

dBc

EIRP values according to EN 300

dBc

220. The antenna (SMAFF-433
and SMAFF-868 from R.W.

dBc

Badland) plays a part in

dBc

attenuating the harmonics.

ACP is measured in a 100 kHz
bandwidth at ±100 kHz offset.

dBc

Modulation: 19.2 kBaud NRZ
PN9 sequence, ±19.8 kHz

dBc

frequency deviation.

Bandwidth for 99.5% of total
average power.

kHz

Modulation: 19.2 kBaud NRZ

kHz

PN9 sequence, ±19.8 kHz
frequency deviation.

Bandwidth where the power
envelope of modulation equals

kHz

ñ36 dBm. Spectrum analyzer
RBW = 1 kHz.

kHz

o

C

o

C

SWRS045 Page 6 of 91

Parameter

Spurious emission, radiated CW

47-74, 87.5-118,

174-230, 470-862 MHz

9 kHz ñ 1 GHz

1 ñ 4 GHz

Optimum load impedance

433 MHz

868 MHz

915 MHz

CC1021

Min Typ Max Unit Condition / Note

54 + j44

15 + j24

20 + j35

-54

-36

-30

Table 3. RF transmit parameters

At maximum output power,
+10/+5 dBm at 433/868 MHz.

dBm

To comply with EN 300 220,
FCC CFR47 part 15 and ARIB

dBm

STD T-67 an external (antenna)
filter, as implemented in the

dBm

application circuit in Figure 25,
must be used and tailored to
each individual design to reduce
out-of-band spurious emission
levels.

Spurious emissions can be
measured as EIRP values
according to EN 300 220. The
antenna (SMAFF-433 and
SMAFF-868 from R.W. Badland)
plays a part in attenuating the
spurious emissions.

If the output power is increased
using an external PA, a filter must
be used to attenuate spurs below
862 MHz when operating in the
868 MHz frequency band in
Europe. Application Note AN036

CC1020/1021 Spurious Emission

presents and discusses a solution
that reduces the TX mode
spurious emission close to 862
MHz by increasing the REF_DIV
from 1 to 7.

Transmit mode. For matching
details see section 14 on page

Ω

46.

Ω

Ω

SWRS045 Page 7 of 91

CC1021

4.2. RF Receive Section

Parameter

Receiver Sensitivity, 433 MHz, FSK

38.4 kHz channel filter BW (1)

102.4 kHz channel filter BW (2)

102.4 kHz channel filter BW (3)

307.2 kHz channel filter BW (4)

Receiver Sensitivity, 868 MHz, FSK

38.4 kHz channel filter BW (1)

102.4 kHz channel filter BW (2)

102.4 kHz channel filter BW (3)

307.2 kHz channel filter BW (4)

Receiver sensitivity, 433 MHz, OOK

9.6 kBaud

153.6 kBaud

Receiver sensitivity, 868 MHz, OOK

9.6 kBaud

153.6 kBaud

Saturation (maximum input level)

FSK and OOK

System noise bandwidth 38.4

Noise figure, cascaded

433 and 868 MHz

Min Typ Max Unit Condition / Note

-109

-104

-104

-108

-103

-103

-103

-104

307.2

7

-96

-94

-81

-87

10

to

kHz The receiver channel filter 6 dB

Sensitivity is measured with PN9
sequence at BER = 10

(1) 38.4 kHz receiver channel

dBm

filter bandwidth: 4.8 kBaud, NRZ
coded data, ±4.95 kHz frequency
deviation.

(2) 102.4 kHz receiver channel

dBm

filter bandwidth: 19.2 kBaud,
NRZ coded data, ±19.8 kHz
frequency deviation.

(3) 102.4 kHz receiver channel

dBm

filter bandwidth: 38.4 kBaud, NRZ
coded data, ±19.8 kHz frequency
deviation.

(4) 307.2 kHz receiver channel

dBm

filter bandwidth: 153.6 kBaud,
NRZ coded data, ±72 kHz
frequency deviation.

See Table 19 and Table 20 or
typical sensitivity figures at other

dBm

channel filter bandwidths.

dBm

dBm

dBm

Sensitivity is measured with PN9
sequence at BER = 10

dBm

Manchester coded data.

dBm

See Table 27 for typical
sensitivity figures at other data
rates.

dBm
dBm

dBm FSK: Manchester/NRZ coded

data
OOK: Manchester coded data
BER = 10

bandwidth is programmable from

38.4 kHz to 307.2 kHz. See
section 12.2 on page 30 for
details.

dB NRZ coded data

3

3

3

SWRS045 Page 8 of 91

Parameter

Input IP3

433 MHz 102.4 kHz channel filter BW

868 MHz 102.4 kHz channel filter BW

Co-channel rejection, FSK and OOK

433 MHz and 868 MHz,

102.4 kHz channel filter BW,

Adjacent channel rejection (ACR)

433 MHz 102.4 kHz channel filter BW

868 MHz 102.4 kHz channel filter BW

Image channel rejection

433/868 MHz

No I/Q gain and phase calibration

I/Q gain and phase calibrated

Selectivity*

433 MHz 102.4 kHz channel filter BW

±200 kHz offset

±300 kHz offset

868 MHz 102.4 kHz channel filter BW

±200 kHz offset

±300 kHz offset

(*Close-in spurious response

rejection)

Blocking / Desensitization*

433/868 MHz

± 1 MHz

± 2 MHz

± 5 MHz

± 10 MHz

(*Out-of-band spurious response

rejection)

Image frequency suppression,

433/868 MHz

No I/Q gain and phase calibration

I/Q gain and phase calibrated

CC1021

Min Typ Max Unit Condition / Note

-23

-18

-16

-18

-15

-13

-11

32

30

25/25

50/50

45
53

45
50

52/58
56/64
58/64
64/66

35/35

60/60

Two tone test (+10 MHz and +20
MHz)

dBm

LNA2 maximum gain

dBm

LNA2 medium gain

dBm

LNA2 minimum gain

dBm

LNA2 maximum gain

dBm

LNA2 medium gain

dBm

LNA2 minimum gain

dB Wanted signal 3 dB above the

sensitivity level, CW jammer at
operating frequency, BER = 10

Wanted signal 3 dB above the

dB

sensitivity level, CW jammer at
adjacent channel, BER = 10

dB

Measured at ±100 kHz offset.
See Figure 16 to Figure 19.

Wanted signal 3 dB above the
sensitivity level, CW jammer at
image frequency, BER = 10

102.4 kHz channel filter

dB

bandwidth. See Figure 16 to
Figure 19.

dB

Image rejection after calibration
will depend on temperature and
supply voltage. Refer to section

12.6 on page 35.

Wanted signal 3 dB above the
sensitivity level. CW jammer is

dB

swept in 20 kHz steps within ± 1

dB

MHz from wanted channel. BER
= 10
image channel are excluded.
See Figure 16 to Figure 19.

dB
dB

Wanted signal 3 dB above the
sensitivity level, CW jammer at ±

dB

1, 2, 5 and 10 MHz offset,

dB

BER = 10
filter bandwidth.

dB
dB

Complying with EN 300 220,
class 2 receiver requirements.

Ratio between sensitivity for a
signal at the image frequency to
the sensitivity in the wanted

dB

channel. Image frequency is RF
2 IF. BER = 10
channel filter bandwidth.

dB

3

. Adjacent channel and

3

. 102.4 kHz channel

3

. 102.4 kHz

3

3

.

3

.

SWRS045 Page 9 of 91

CC1021

Parameter

Spurious reception

LO leakage, 433/868 MHz <-80/-66 dBm

VCO leakage -64 dBm VCO frequency resides between

Spurious emission, radiated CW

9 kHz ñ 1 GHz

1 ñ 4 GHz

Input impedance

433 MHz

868 MHz

Matched input impedance, S11

433 MHz

868 MHz

Matched input impedance

433 MHz

868 MHz

Bit synchronization offset 8000 ppm The maximum bit rate offset

Data latency

NRZ mode

Manchester mode

Min Typ Max Unit Condition / Note

37 dB Ratio between sensitivity for an

<-60

<-60

58 - j10

54 - j22

-14

-12

39 - j14

32 - j10

4

8

Baud

Baud

unwanted frequency to the
sensitivity in the wanted channel.
The signal source is swept over
all frequencies 100 MHz ñ 2 GHz.
Signal level for BER = 10

102.4 kHz channel filter
bandwidth.

1608 ñ 1880 MHz

Complying with EN 300 220,

dBm

FCC CFR47 part 15 and ARIB
STD T-67.

dBm

Spurious emissions can be
measured as EIRP values
according to EN 300 220.

Receive mode. See section 14 on
page 46 for details.

Ω

Ω

Using application circuit matching

dB

network. See section 14 on page
46 for details.

dB

Using application circuit matching
network. See section 14 on page

Ω

46 for details.

Ω

tolerated by the bit
synchronization circuit for 6 dB
degradation (synchronous modes
only)

Time from clocking the data on
the transmitter DIO pin until data
is available on receiver DIO pin

Table 4. RF receive parameters

3

.

SWRS045 Page 10 of 91

CC1021

4.3. RSSI / Carrier Sense Section

Parameter

RSSI dynamic range

RSSI accuracy

RSSI linearity

RSSI attach time

51.2 kHz channel filter BW

102.4 kHz channel filter BW

307.2 kHz channel filter BW

Carrier sense programmable range

Carrier sense at ±100 kHz and ±200

kHz offset

102.4 kHz channel filter BW, 433 MHz

±100 kHz

±200 kHz

102.4 kHz channel filter BW, 868 MHz

±100 kHz

±200 kHz

Table 5. RSSI / Carrier sense parameters

4.4. IF Section

Parameter

Intermediate frequency (IF)

Digital channel filter bandwidth

AFC resolution

Min Typ Max Unit Condition / Note

55 dB See section 12.5 on page 33 for

40 dB Accuracy is as for RSSI

Min Typ Max Unit Condition / Note

307.2 kHz See section 12.1 on page 30 for

38.4
to

307.2

1200 Hz At 19.2 kBaud

Table 6. IF section parameters

± 3

± 1

730

380

140

-57

-44

-60

-44

details.

dB See section 12.5 on page 33 for

dB

kHz The channel filter 6 dB bandwidth

details.

Shorter RSSI attach times can be
traded for lower RSSI accuracy.
See section 12.5 on page 33 for

µs

details.

µs

Shorter RSSI attach times can
also be traded for reduced

µs

sensitivity and selectivity by
increasing the receiver channel
filter bandwidth.

At carrier sense level 98 dBm,
CW jammer at ±100 kHz and

±200 kHz offset.
dBm
dBm

Carrier sense is measured by

applying a signal at ±100 kHz and

±200 kHz offset and observe at
dBm

which level carrier sense is
dBm

indicated.

details.

is programmable from 9.6 kHz to

307.2 kHz. See section 12.2 on

page 30 for details.

Given as Baud rate/16. See

section 12.13 on page 42 for

details.

SWRS045 Page 11 of 91

CC1021

4.5. Crystal Oscillator Section

Parameter

Crystal Oscillator Frequency

Crystal operation

Crystal load capacitance

Crystal oscillator start-up time 1.55

External clock signal drive,
sine wave

External clock signal drive,
full-swing digital external clock

Min Typ Max Unit Condition / Note

4.9152 14.7456 19.6608 MHz Recommended frequency is

Parallel C4 and C5 are loading

12
12
12

1.0

0.90

0.95

0.60

0.63

300

0 - VDD

Table 7. Crystal oscillator parameters

22
16
16

14.7456 MHz. See section 19 on

page 58 for details.

capacitors. See section 19 on

page 58 for details.

30
30
16

ms

mVpp

V The external clock signal must be

pF

4.9-6 MHz, 22 pF recommended

pF

6-8 MHz, 16 pF recommended

pF

8-19.6 MHz, 16 pF recommended

4.9152 MHz, 12 pF load

ms

7.3728 MHz, 12 pF load

ms

9.8304 MHz, 12 pF load

ms

14.7456 MHz, 16 pF load

ms

17.2032 MHz, 12 pF load

ms

19.6608 MHz, 12 pF load

The external clock signal must be

connected to XOSC_Q1 using a

DC block (10 nF). Set

XOSC_BYPASS = 0 in the

INTERFACE register when using

an external clock signal with low

amplitude or a crystal.

connected to XOSC_Q1. No DC

block shall be used. Set

XOSC_BYPASS = 1 in the

INTERFACE register when using

a full-swing digital external clock.

SWRS045 Page 12 of 91

CC1021

4.6. Frequency Synthesizer Section

Parameter

Phase noise, 402 ñ 470 MHz

Phase noise, 804 ñ 940 MHz

PLL loop filter bandwidth

Loop filter 2, up to 19.2 kBaud

Loop filter 3, up to 38.4 kBaud

PLL lock time (RX / TX turn time)

Loop filter 2, up to 19.2 kBaud

Loop filter 3, up to 38.4 kBaud

Loop filter 5, up to 153.6 kBaud

PLL turn-on time. From power down
mode with crystal oscillator running.

Loop filter 2, up to 19.2 kBaud

Loop filter 3, up to 38.4 kBaud

Loop filter 5, up to 153.6 kBaud

Table 8. Frequency synthesizer parameters

Min Typ Max Unit Condition / Note

-79

-80

-87

-100

-105

-73

-74

-81

-94

-111

15

30.5

140

75

14

1300

1080

700

dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz

dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz

Unmodulated carrier

At 12.5 kHz offset from carrier

At 25 kHz offset from carrier

At 50 kHz offset from carrier

At 100 kHz offset from carrier

At 1 MHz offset from carrier

Measured using loop filter

components given in Table 13.

The phase noise will be higher for

larger PLL loop filter bandwidth.

Unmodulated carrier

At 12.5 kHz offset from carrier

At 25 kHz offset from carrier

At 50 kHz offset from carrier

At 100 kHz offset from carrier

At 1 MHz offset from carrier

Measured using loop filter

components given in Table 13.

The phase noise will be higher for

larger PLL loop filter bandwidth.

After PLL and VCO calibration.

The PLL loop bandwidth is

kHz

programmable.

kHz

See Table 25 on page 52 for loop

filter component values.

307.2 kHz frequency step to RF

frequency within ±10 kHz, ±15

us

kHz, ±50 kHz settling accuracy

for loop filter 2, 3 and 5

us

respectively. Depends on loop

filter component values and

us

PLL_BW register setting. See

Table 26 on page 53 for more

details.

Time from writing to registers to

RF frequency within ±10 kHz, ±15

us

kHz, ±50 kHz settling accuracy

for loop filter 2, 3 and 5

us

respectively. Depends on loop

filter component values and

us

PLL_BW register setting. See

Table 25 on page 53 for more

details.

SWRS045 Page 13 of 91

CC1021

4.7. Digital Inputs / Outputs

Parameter

Logic "0" input voltage

Logic "1" input voltage

Logic "0" output voltage 0

Logic "1" output voltage 2.5

Logic "0" input current

Logic "1" input current

DIO setup time 20 ns TX mode, minimum time DIO

DIO hold time

Serial interface (PCLK, PDI, PDO
and PSEL) timing specification

Pin drive, LNA_EN, PA_EN

Table 9. Digital inputs / outputs parameters

Min Typ Max Unit Condition / Note

0 0.3*

0.7*

VDD

NA 1

NA 1

10 ns TX mode, minimum time DIO

See Table 14 on page 24 for

VDD V

0.4 V Output current 2.0 mA,

VDD V Output current 2.0 mA,

0.90

0.87

0.81

0.69

0.93

0.92

0.89

0.79

VDD

V

3.0 V supply voltage

3.0 V supply voltage

Input signal equals GND.

µA

PSEL has an internal pull-up

resistor and during configuration

the current will be -350 µA.

Input signal equals VDD

µA

must be ready before the positive

edge of DCLK. Data should be

set up on the negative edge of

DCLK.

must be held after the positive

edge of DCLK. Data should be

set up on the negative edge of

DCLK.

more details

Source current

mA

0 V on LNA_EN, PA_EN pins

mA

0.5 V on LNA_EN, PA_EN pins

mA

1.0 V on LNA_EN, PA_EN pins

mA

1.5 V on LNA_EN, PA_EN pins

Sink current

mA

3.0 V on LNA_EN, PA_EN pins

mA

2.5 V on LNA_EN, PA_EN pins

mA

2.0 V on LNA_EN, PA_EN pins

mA

1.5 V on LNA_EN, PA_EN pins

See Figure 35 on page 61 for

more details.

SWRS045 Page 14 of 91

CC1021

4.8. Current Consumption

Parameter

Power Down mode

Current Consumption,
receive mode 433 and 868 MHz

Current Consumption,
transmit mode 433/868 MHz:

P = 20 dBm

P = 5 dBm

P = 0 dBm

P = +5 dBm

P = +10 dBm (433 MHz only)

Current Consumption, crystal
oscillator

Current Consumption, crystal
oscillator and bias

Current Consumption, crystal
oscillator, bias and synthesizer

5. Pin Assignment

Table 11 provides an overview of the

CC1021

pinout.

Min Typ Max Unit Condition / Note

0.2 1.8

19.9 mA

12.3/14.5

14.4/17.0

16.2/20.5

20.5/25.1

27.1

77

Table 10. Current consumption

500

7.5

Oscillator core off

µA

mA

The output power is delivered to

a 50 Ω single-ended load.

mA

See section 13.2 on page 44 for

mA

more details.

mA

mA

The

CC1021

14.7456 MHz, 16 pF load crystal

µA

14.7456 MHz, 16 pF load crystal

µA

14.7456 MHz, 16 pF load crystal

mA

comes in a QFN32 type

package (see page 85 for details).

32PSEL

31DVDD

30DGND

29AVDD

28CHP_OUT

27AVDD

26AD_REF

25AGND

PCLK 1

PDI

PDO

DGND

DVDD

DGND

DCLK

DIO 8

2
3
4
5
6
7

13

12

9

XOSC_Q211XOSC_Q110LOCK

AVDD

PA_EN15LNA_EN14AVDD

AVDD16

VC

24
23

AVDD

22

AVDD

21

RF_OUT

20

AVDD

19

RF_IN

18

AVDD

17

R_BIAS

AGND
Exposed die
attached pad

Figure 1.

SWRS045 Page 15 of 91

CC1021

package (top view)

CC1021

Pin no. Pin name Pin type Description

- AGND Ground (analog) Exposed die attached pad. Must be soldered to a solid ground plane as

1 PCLK Digital input Programming clock for SPI configuration interface
2 PDI Digital input Programming data input for SPI configuration interface
3 PDO Digital output Programming data output for SPI configuration interface
4 DGND Ground (digital) Ground connection (0 V) for digital modules and digital I/O
5 DVDD Power (digital) Power supply (3 V typical) for digital modules and digital I/O
6 DGND Ground (digital) Ground connection (0 V) for digital modules (substrate)
7 DCLK Digital output Clock for data in both receive and transmit mode.

8 DIO Digital input/output Data input in transmit mode; data output in receive mode

9 LOCK Digital output PLL Lock indicator, active low. Output is asserted (low) when PLL is in

10 XOSC_Q1 Analog input Crystal oscillator or external clock input
11 XOSC_Q2 Analog output Crystal oscillator
12 AVDD Power (analog) Power supply (3 V typical) for crystal oscillator
13 AVDD Power (analog) Power supply (3 V typical) for the IF VGA
14 LNA_EN Digital output General digital output. Can be used for controlling an external LNA if

15 PA_EN Digital output General digital output. Can be used for controlling an external PA if

16 AVDD Power (analog) Power supply (3 V typical) for global bias generator and IF anti-alias

17 R_BIAS Analog output
18 AVDD Power (analog) Power supply (3 V typical) for LNA input stage
19 RF_IN RF Input RF signal input from antenna (external AC-coupling)
20 AVDD Power (analog) Power supply (3 V typical) for LNA
21 RF_OUT RF output RF signal output to antenna
22 AVDD Power (analog) Power supply (3 V typical) for LO buffers, mixers, prescaler, and first PA

23 AVDD Power (analog) Power supply (3 V typical) for VCO
24 VC Analog input VCO control voltage input from external loop filter
25 AGND Ground (analog) Ground connection (0 V) for analog modules (guard)
26 AD_REF Power (analog) 3 V reference input for ADC
27 AVDD Power (analog) Power supply (3 V typical) for charge pump and phase detector
28 CHP_OUT Analog output PLL charge pump output to external loop filter
29 AVDD Power (analog) Power supply (3 V typical) for ADC
30 DGND Ground (digital) Ground connection (0 V) for digital modules (guard)
31 DVDD Power (digital) Power supply connection (3 V typical) for digital modules
32 PSEL Digital input Programming chip select, active low, for configuration interface. Internal

this is the ground connection for all analog modules. See page 63 for
more details.

Can be used as receive data output in asynchronous mode

Can also be used to start power-up sequencing in receive

lock. The pin can also be used as a general digital output, or as receive
data output in synchronous NRZ/Manchester mode

higher sensitivity is needed.

higher output power is needed.

filter
Connection for external precision bias resistor (82 kΩ, ± 1%)

stage

pull-up resistor.

Table 11. Pin assignment overview

Note:

DCLK, DIO and LOCK are high­impedance (3-state) in power down
(BIAS_PD = 1 in the MAIN register).

The exposed die attached pad must be
soldered to a solid ground plane as this is
the main ground connection for the chip.

SWRS045 Page 16 of 91

CC1021

6. Circuit Description

LNA

PA

LNA 2

PA_EN

Power

Control

LNA_EN

Figure 2.

Multiplexer

Multiplexer

BIAS

R_BIAS

CC1021

0

:2

90

XOSC_Q1 XOSC_Q2

simplified block diagram

RF_IN

RF_OUT

CC1021

A simplified block diagram of

is
shown in Figure 2. Only signal pins are
shown.

CC1021

features a low-IF receiver. The
received RF signal is amplified by the low­noise amplifier (LNA and LNA2) and
down-converted in quadrature (I and Q) to
the intermediate frequency (IF). At IF, the
I/Q signal is complex filtered and
amplified, and then digitized by the ADCs.
Automatic gain control, fine channel
filtering, demodulation and bit
synchronization is performed digitally.

CC1021

outputs the digital demodulated
data on the DIO pin. A synchronized data
clock is available at the DCLK pin. RSSI is
available in digital format and can be read
via the serial interface. The RSSI also
features a programmable carrier sense
indicator.

In transmit mode, the synthesized RF
frequency is fed directly to the power

DIGITAL

DEMODULATOR

- Digital RSSI

- Gain Control

- Image Suppression

- Channel Filtering

- Demodulation

DIGITAL

INTERFACE

TO µC

LOGIC

CONTROL

DIGITAL

MODULATOR

- Modulation

- Data shaping

- Power Control

0

90

XOSC

ADC

ADC

:2

SYNTH

VC

FREQ

CHP_OUT

amplifier (PA). The RF output is frequency
shift keyed (FSK) by the digital bit stream
that is fed to the DIO pin. Optionally, a
Gaussian filter can be used to obtain
Gaussian FSK (GFSK).

The frequency synthesizer includes a
completely on-chip LC VCO and a 90
degrees phase splitter for generating the
LO_I and LO_Q signals to the down­conversion mixers in receive mode. The
VCO operates in the frequency range

1.608-1.880 GHz. The CHP_OUT pin is
the charge pump output and VC is the
control node of the on-chip VCO. The
external loop filter is placed between these
pins. A crystal is to be connected between
XOSC_Q1 and XOSC_Q2. A lock signal is
available from the PLL.

The 4-wire SPI serial interface is used for
configuration.

LOCK

DIO

DCLK

PDO

PDI

PCLK

PSEL

SWRS045 Page 17 of 91

CC1021

7. Application Circuit

Very few external components are
required for the operation of

CC1021

. The
recommended application circuit is shown
in Figure 3. The external components are
described in Table 12 and values are
given in Table 13.

Input / output matching

L1 and C1 is the input match for the
receiver. L1 is also a DC choke for
biasing. L2 and C3 are used to match the
transmitter to 50 Ω. Internal circuitry
makes it possible to connect the input and
output together and match the

CC1021

to
50 Ω in both RX and TX mode. However, it
is recommended to use an external T/R
switch for optimum performance. See
section 14 on page 46 for details

.

Component values for the matching
network are easily found using the
SmartRF



Studio software.

Bias resistor

The precision bias resistor R1 is used to
set an accurate bias current.

PLL loop filter

The loop filter consists of two resistors (R2
and R3) and three capacitors (C6-C8). C7
and C8 may be omitted in applications

Ref Description

C1 LNA input match and DC block, see page 46
C3 PA output match and DC block, see page 46
C4 Crystal load capacitor, see page 58
C5 Crystal load capacitor, see page 58
C6 PLL loop filter capacitor
C7 PLL loop filter capacitor (may be omitted for highest loop bandwidth)
C8 PLL loop filter capacitor (may be omitted for highest loop bandwidth)
C60 Decoupling capacitor
L1 LNA match and DC bias (ground), see page 46
L2 PA match and DC bias (supply voltage), see page 46
R1 Precision resistor for current reference generator
R2 PLL loop filter resistor
R3 PLL loop filter resistor
R10 PA output match, see page 46
XTAL Crystal, see page 58

Table 12. Overview of external components (excluding supply decoupling capacitors)

where high loop bandwidth is desired. The
values shown in Table 13 are optimized
for 38.4 kBaud data rate. Component
values for other data rates are easily found
using the SmartRF



Studio software.

Crystal

An external crystal with two loading
capacitors (C4 and C5) is used for the
crystal oscillator. See section 19 on page
58 for details.

Additional filtering

Additional external components (e.g. RF
LC or SAW filter) may be used in order to
improve the performance in specific
applications. See section 14 on page 46
for further information.

Power supply decoupling and filtering

Power supply decoupling and filtering
must be used (not shown in the application
circuit). The placement and size of the
decoupling capacitors and the power
supply filtering are very important to
achieve the optimum performance for
narrowband applications. Chipcon
provides a reference design that should be
followed very closely.

SWRS045 Page 18 of 91

Microcontroller configuration interface and signal interface

Microcontroller configuration interface and signal interface

DVDD=3V

DVDD=3V

CC1021

AVDD=3V

31

31

32

32

PSEL

PSEL

DVDD

DVDD

CC1021

CC1021

XOSC_Q111XOSC_Q2

XOSC_Q111XOSC_Q2

9

10

9

10

XTAL

XTALXTAL

AVDD=3V

30

30

DGND

DGND

AVDD

AVDD

AVDD

AVDD

12

12

C6

C6

R2

29

27

26

29

28

28

CHP_OUT

CHP_OUT

AVDD

AVDD

LNA_EN

LNA_EN

AVDD

AVDD

13

13

25

27

26

25

C7 R3

AD_REF

AD_REF

AGND

AGND

AVDD

AVDD

AVDD

AVDD

RF_OUT

RF_OUT

AVDD

AVDD

RF_IN

RF_IN

AVDD

AVDD

R_BIAS

R_BIAS

PA_EN

PA_EN

AVDD

AVDD

16

16

14

15

14

15

AVDD=3V

AVDD=3V

C7 R3

24

24

VC

VC

23

23

22

22

21

21

20

20

19

19

18

18

17

17

R2

C8

C8

AVDD=3V

AVDD=3V

AVDD=3V

AVDD=3V

R1

R1

AVDD=3V

AVDD=3V

R10

R10

L2

L2

L1

L1

C60

C60

C3

C3

LC Filter

LC FilterLC Filter

C1

C1

DVDD=3V

DVDD=3V

1

1

PCLK

PCLK

2

2

PDI

PDI

3

3

PDO

PDO

4

4

DGND

DGND

5

5

DVDD

DVDD

6

6

DGND

DGND

7

7

DCLK

DCLK

8

8

DIO

DIO

LOCK

LOCK

Monopole

Monopole

antenna

antenna

(50 Ohm)

(50 Ohm)

T/R Switch

T/R Switch

C5

C5C5

C4

C4C4

Figure 3. Typical application and test circuit (power supply decoupling not shown)

Item 433 MHz 868 MHz 915 MHz

C1 10 pF, 5%, NP0, 0402 47 pF, 5%, NP0, 0402 47 pF, 5%, NP0, 0402
C3 5.6 pF, 5%, NP0, 0402 10 pF, 5%, NP0, 0402 10 pF, 5%, NP0, 0402
C4 22 pF, 5%, NP0, 0402 22 pF, 5%, NP0, 0402 22 pF, 5%, NP0, 0402
C5 12 pF, 5%, NP0, 0402 12 pF, 5%, NP0, 0402 12 pF, 5%, NP0, 0402
C6 3.9 nF, 10%, X7R, 0603 3.9 nF, 10%, X7R, 0603 3.9 nF, 10%, X7R, 0603
C7 120 pF, 10%, X7R, 0402 120 pF, 10%, X7R, 0402 120 pF, 10%, X7R, 0402
C8 33 pF, 10%, X7R, 0402 33 pF, 10%, X7R, 0402 33 pF, 10%, X7R, 0402
C60 220 pF, 5%, NP0, 0402 220 pF, 5%, NP0, 0402 220 pF, 5%, NP0, 0402
L1 33 nH, 5%, 0402 82 nH, 5%, 0402 82 nH, 5%, 0402
L2 22 nH, 5%, 0402 3.6 nH, 5%, 0402 3.6 nH, 5%, 0402
R1
R2
R3
R10
XTAL 14.7456 MHz crystal,

82 kΩ, 1%, 0402 82 kΩ, 1%, 0402 82 kΩ, 1%, 0402
12 kΩ, 5%, 0402 12 kΩ, 5%, 0402 12 kΩ, 5%, 0402
39 kΩ, 5%, 0402 39 kΩ, 5%, 0402 39 kΩ, 5%, 0402
82 Ω, 5%, 0402 82 Ω, 5%, 0402 82 Ω, 5%, 0402

16 pF load

14.7456 MHz crystal,
16 pF load

14.7456 MHz crystal,
16 pF load

Note: Items shaded vary for different frequencies.

Table 13. Bill of materials for the application circuit in Figure 3. The PLL loop filter is

optimized for 38.4 kBaud data rate.

Note:

The PLL loop filter component values in
Table 13 (R2, R3, C6-C8) are optimized
for 38.4 kBaud data rate. The SmartRF



Studio software provides component
values for other data rates using the

In the CC1020EMX reference design,
which is also applicable for
LQG15HS series inductors from Murata
have been used. The switch is SW-456
from M/A-COM.

equations on page 50.

CC1021

,

SWRS045 Page 19 of 91

CC1021

The LC filter in Figure 3 is inserted in the
TX path only. The filter will reduce the
emission of harmonics and the spurious
emissions in the TX path. An alternative is
to insert the LC filter between the antenna
and the T/R switch as shown in Figure 4.

AVDD=3V

Microcontroller configuration interface and signal interface

Microcontroller configuration interface and signal interface

DVDD=3V

DVDD=3V

DVDD=3V

DVDD=3V

1

1

PCLK

PCLK

2

2

PDI

PDI

3

3

PDO

PDO

4

4

DGND

DGND

5

5

DVDD

DVDD

6

6

DGND

DGND

7

7

DCLK

DCLK

8

8

DIO

DIO

LOCK

LOCK

31

31

32

32

PSEL

PSEL

DVDD

DVDD

CC1021

CC1021

XOSC_Q111XOSC_Q2

XOSC_Q111XOSC_Q2

9

10

9

10

AVDD=3V

30

30

DGND

DGND

AVDD

AVDD

AVDD

AVDD

12

12

29

27

29

27

28

28

AD_REF

AD_REF

CHP_OUT

CHP_OUT

AVDD

AVDD

LNA_EN

LNA_EN

PA_EN

PA_EN

AVDD

AVDD

14

14

13

13

The filter will reduce the emission of
harmonics and the spurious emissions in
the TX path as well as increase the
receiver selectivity. The sensitivity will be
slightly reduced due to the insertion loss of
the LC filter.

C6

C6

R2

26

25

26

25

C7 R3

AGND

AGND

AVDD

AVDD

AVDD

AVDD

RF_OUT

RF_OUT

AVDD

AVDD

RF_IN

RF_IN

AVDD

AVDD

R_BIAS

R_BIAS

AVDD

AVDD

16

16

15

15

C7 R3

24

24

VC

VC

23

23

22

22

21

21

20

20

19

19

18

18

17

17

R2

C8

C8

AVDD=3V

AVDD=3V

AVDD=3V

AVDD=3V

R1

R1

AVDD=3V

AVDD=3V

R10

R10

L2

L2

L1

L1

C60

C60

C3

C3

C1

C1

T/R Switch

T/R Switch

Monopole

Monopole

antenna

antenna

(50 Ohm)

(50 Ohm)

LC Filter

LC FilterLC Filter

AVDD=3V

AVDD=3V

XTAL

XTALXTAL

C5

C5C5

C4

C4C4

Figure 4. Alternative application circuit (power supply decoupling not shown)

SWRS045 Page 20 of 91

CC1021

8. Configuration Overview

CC1021

can be configured to achieve the
optimum performance for different
applications. Through the programmable
configuration registers the following key
parameters can be programmed:

• Receive / transmit mode

• RF output power

• Frequency synthesizer key parameters:

RF output frequency, FSK frequency

8.1. Configuration Software

Chipcon provides users of
software program, SmartRF
(Windows interface) that generates all
necessary
based on the user's selections of various
parameters. These hexadecimal numbers
will then be the necessary input to the
microcontroller for the configuration of

CC1021

configuration data

CC1021



Studio

with a

separation, crystal oscillator reference
frequency

• Power-down / power-up mode

• Crystal oscillator power-up / power-

down

• Data rate and data format (NRZ,
Manchester coded or UART interface)

• Synthesizer lock indicator mode

• Digital RSSI and carrier sense

• FSK / GFSK / OOK modulation

CC1021

. In addition, the program will
provide the user with the component
values needed for the input/output
matching circuit, the PLL loop filter and the
LC filter.

Figure 5 shows the user interface of the

CC1021

configuration software.



Figure 5. SmartRF

Note: The CC1020/1070DK Development Kit with a fully assembled CC1020EMX Evaluation

Module together with the
transceiver.

SWRS045 Page 21 of 91

CC1021

specific software should be used for evaluation of the

Studio user interface

CC1021

CC1021

9. Microcontroller Interface

CC1021

Used in a typical system,
interface to a microcontroller. This
microcontroller must be able to:

CC1021

• Program

into different modes via
the 4-wire serial configuration interface
(PDI, PDO, PCLK and PSEL)

• Interface to the bi-directional
synchronous data signal interface (DIO
and DCLK)

• Optionally, the microcontroller can do
data encoding / decoding

• Optionally, the microcontroller can
monitor the LOCK pin for frequency
lock status, carrier sense status or
other status information.

• Optionally, the microcontroller can read
back the digital RSSI value and other
status information via the 4-wire serial
interface

Configuration interface

The microcontroller interface is shown in
Figure 6. The microcontroller uses 3 or 4
I/O pins for the configuration interface
(PDI, PDO, PCLK and PSEL). PDO should
be connected to a microcontroller input.
PDI, PCLK and PSEL must be
microcontroller outputs. One I/O pin can
be saved if PDI and PDO are connected
together and a bi-directional pin is used at
the microcontroller.

will

The microcontroller pins connected to PDI,
PDO and PCLK can be used for other
purposes when the configuration interface
is not used. PDI, PDO and PCLK are high
impedance inputs as long as PSEL is not
activated (active low).

PSEL has an internal pull-up resistor and
should be left open (tri-stated by the
microcontroller) or set to a high level
during power down mode in order to
prevent a trickle current flowing in the pull­up.

Signal interface

A bi-directional pin is usually used for data
(DIO) to be transmitted and data received.
DCLK providing the data timing should be
connected to a microcontroller input.

As an option, the data output in receive
mode can be made available on a
separate pin. See section 9.2 on page for
25 further details.

PLL lock signal

Optionally, one microcontroller pin can be
used to monitor the LOCK signal. This
signal is at low logic level when the PLL is
in lock. It can also be used for carrier
sense and to monitor other internal test
signals.

PCLK

PCLK
PDI

PDI
PDO (Optional)

PDO (Optional)
PSEL

PSEL

DIO

DIO
DCLK

DCLK

LOCK

LOCK

(Optional)

(Optional)

Micro-

Micro­controller

controller

Figure 6. Microcontroller interface

SWRS045 Page 22 of 91

CC1021

9.1. 4-wire Serial Configuration Interface

CC1021

is configured via a simple 4-wire
SPI-compatible interface (PDI, PDO,
PCLK and PSEL) where

CC1021

is the
slave. There are 8-bit configuration
registers, each addressed by a 7-bit
address. A Read/Write bit initiates a read
or write operation. A full configuration of

CC1021

requires sending 33 data frames of
16 bits each (7 address bits, R/W bit and 8
data bits). The time needed for a full
configuration depends on the PCLK
frequency. With a PCLK frequency of 10
MHz the full configuration is done in less
than 53 µs. Setting the device in power
down mode requires sending one frame
only and will in this case take less than 2
µs. All registers are also readable.

During each write-cycle, 16 bits are sent
on the PDI-line. The seven most
significant bits of each data frame (A6:0)
are the address-bits. A6 is the MSB (Most
Significant Bit) of the address and is sent
as the first bit. The next bit is the R/W bit
(high for write, low for read). The 8 data­bits are then transferred (D7:0). During
address and data transfer the PSEL
(Program SELect) must be kept low. See
Figure 7.

The timing for the programming is also
shown in Figure 7 with reference to Table

T

SS

14. The clocking of the data on PDI is
done on the positive edge of PCLK. Data
should be set up on the negative edge of
PCLK by the microcontroller. When the
last bit, D0, of the 8 data-bits has been
loaded, the data word is loaded into the
internal configuration register.

The configuration data will be retained
during a programmed power down mode,
but not when the power supply is turned
off. The registers can be programmed in
any order.

The configuration registers can also be
read by the microcontroller via the same
configuration interface. The seven address
bits are sent first, then the R/W bit set low
to initiate the data read-back.
returns the data from the addressed
register. PDO is used as the data output
and must be configured as an input by the
microcontroller. The PDO is set at the
negative edge of PCLK and should be
sampled at the positive edge. The read
operation is illustrated in Figure 8.

PSEL must be set high between each
read/write operation.

CC1021

then

T

HS

T

HD

Data byte

T

SD

PCLK

PDI

PDO

PSEL

T

CL,min

Address Write mode

6543210

T

CH,min

7 6 5 4 3 2 1 0

W

Figure 7. Configuration registers write operation

SWRS045 Page 23 of 91

CC1021

T

SS

T

HS

PCLK

PDI

PDO

PSEL

T

CL,min

Address

6

5

4

3

T

SH

T

CH,min

Read mode

2

1

0

R

Data byte

7

6

5

4

3

2

1

0

Figure 8. Configuration registers read operation

Parameter Symbol Min Max Unit Conditions

PCLK, clock
frequency

PCLK low
pulse
duration

PCLK high
pulse
duration

PSEL setup
time

PSEL hold
time

PSEL high
time

PDI setup
time

PDI hold time

Rise time T

Fall time T

F

PCLK

T

50 ns The minimum time PCLK must be low.

CL,min

T

50 ns The minimum time PCLK must be high.

CH,min

T

SS

25 ns The minimum time PSEL must be held low after

T

HS

50 ns The minimum time PSEL must be high.

T

SH

T

SD

THD 25 ns The minimum time data must be held at PDI, after

100 ns The maximum rise time for PCLK and PSEL

rise

100 ns The maximum fall time for PCLK and PSEL

fall

10 MHz

25 ns The minimum time PSEL must be low before

25 ns The minimum time data on PDI must be ready

positive edge of PCLK.

negative edge of PCLK.

the

before the positive edge of PCLK.

positive edge of PCLK.

the

Note: The setup and hold times refer to 50% of VDD. The rise and fall times refer to 10% /
90% of VDD. The maximum load that this table is valid for is 20 pF.

Table 14. Serial interface, timing specification

SWRS045 Page 24 of 91

CC1021

9.2. Signal Interface

The

CC1021

can be used with NRZ (Non­Return-to-Zero) data or Manchester (also
known as bi-phase-level) encoded data.

CC1021

can also synchronize the data from
the demodulator and provide the data
clock at DCLK. The data format is
controlled by the DATA_FORMAT[1:0] bits
in the MODEM register.

CC1021

can be configured for three
different data formats:

Synchronous NRZ mode

In transmit mode
clock at DCLK and DIO is used as data
input. Data is clocked into
rising edge of DCLK. The data is
modulated at RF without encoding.

In receive mode
synchronization and provides received
data clock at DCLK and data at DIO. The
data should be clocked into the interfacing
circuit at the rising edge of DCLK. See
Figure 9.

Synchronous Manchester encoded
mode

In transmit mode
clock at DCLK and DIO is used as data
input. Data is clocked into
rising edge of DCLK and should be in NRZ
format. The data is modulated at RF with
Manchester code. The encoding is done
by

CC1021

. In this mode the effective bit
rate is half the baud rate due to the
coding. As an example, 19.2 kBaud
Manchester encoded data corresponds to

9.6 kbps.

In receive mode
synchronization and provides received
data clock at DCLK and data at DIO.

CC1021

performs the decoding and NRZ
data is presented at DIO. The data should
be clocked into the interfacing circuit at the
rising edge of DCLK. See Figure 10.

In synchronous NRZ or Manchester mode
the DCLK signal runs continuously both in
RX and TX unless the DCLK signal is
gated with the carrier sense signal or the
PLL lock signal. Refer to section 21 for
more details.

CC1021

provides the data

CC1021

performs the

CC1021

provides the data

CC102

performs the

CC1021

CC1021

at the

at the

If SEP_DI_DO = 0 in the INTERFACE
register, the DIO pin is the data output in
receive mode and data input in transmit
mode.

As an option, the data output can be made
available at a separate pin. This is done
by setting SEP_DI_DO = 1 in the
INTERFACE register. Then, the LOCK pin
will be used as data output in synchronous
mode, overriding other use of the LOCK
pin.

Transparent Asynchronous UART
mode

In transmit mode DIO is used as data
input. The data is modulated at RF without
synchronization or encoding.

In receive mode the raw data signal from
the demodulator is sent to the output
(DIO). No synchronization or decoding of

CC1021

the signal is done in
done by the interfacing circuit.

If SEP_DI_DO = 0 in the INTERFACE
register, the DIO pin is the data output in
receive mode and data input in transmit
mode. The DCLK pin is not active and can
be set to a high or low level by
DATA_FORMAT[0].

If SEP_DI_DO = 1 in the INTERFACE
register, the DCLK pin is the data output in
receive mode and the DIO pin is the data
input in transmit mode. In TX mode the
DCLK pin is not active and can be set to a
high or low level by DATA_FORMAT[0].
See Figure 11.

Manchester encoding and decoding
In the Synchronous Manchester encoded
mode
when modulating the data. The
also performs the data decoding and
synchronization. The Manchester code is
based on transitions; a ì0î is encoded as a
low-to-high transition, a ì1î is encoded as
a high-to-low transition. See Figure 12.

The Manchester code ensures that the
signal has a constant DC component,
which is necessary in some FSK
demodulators. Using this mode also

CC1021

uses Manchester coding

and should be

CC1021

SWRS045 Page 25 of 91

CC1021

ensures compatibility with CC400/CC900 designs.

Transmitter side:

Transmitter side:

DCLK

DCLK

DIO

DIO

ìRFî

ìRFî

Receiver side:

Receiver side:

ìRFî

ìRFî

DCLK

DCLK

DIO

DIO

Figure 9. Synchronous NRZ mode (SEP_DI_DO = 0)

Transmitter side:

Transmitter side:

Clock provided by CC1021

Clock provided by CC1021

Data provided by microcontroller

Data provided by microcontroller

FSK modulating signal (NRZ),

FSK modulating signal (NRZ),
internal in CC1021

internal in CC1021

Demodulated signal (NRZ),

Demodulated signal (NRZ),
internal in CC1021

internal in CC1021

Clock provided by CC1021

Clock provided by CC1021

Data provided by CC1021

Data provided by CC1021

DCLK

DCLK

DIO

DIO

ìRFî

ìRFî

Receiver side:

Receiver side:

ìRFî

ìRFî

DCLK

DCLK

DIO

DIO

Figure 10. Synchronous Manchester encoded mode (SEP_DI_DO = 0)

Clock provided by CC1021

Clock provided by CC1021

Data provided by microcontroller

Data provided by microcontroller

FSK modulating signal (Manchester

FSK modulating signal (Manchester
encoded), internal in CC1021

encoded), internal in CC1021

Demodulated signal (Manchester

Demodulated signal (Manchester
encoded), internal in CC1021

encoded), internal in CC1021

Clock provided by CC1021

Clock provided by CC1021

Data provided by CC1021

Data provided by CC1021

SWRS045 Page 26 of 91

Transmitter side:

Transmitter side:

DCLK

DCLK

DIO

DIO

ìRFî

ìRFî

Receiver side:

Receiver side:

ìRFî

ìRFî

DCLK

DCLK

DIO

DIO

Figure 11. Transparent Asynchronous UART mode (SEP_DI_DO = 1)

Tx

Tx
data

data

CC1021

DCLK is not used in transmit mode, and is

DCLK is not used in transmit mode, and is
used as data output in receive mode. It can be

used as data output in receive mode. It can be
set to default high or low in transmit mode.

set to default high or low in transmit mode.

Data provided by UART (TXD)

Data provided by UART (TXD)

FSK modulating signal,

FSK modulating signal,
internal in CC1021

internal in CC1021

Demodulated signal (NRZ),

Demodulated signal (NRZ),
internal in CC1021

internal in CC1021

DCLK is used as data output

DCLK is used as data output
provided by CC1021.

provided by CC1021.
Connect to UART (RXD)

Connect to UART (RXD)

DIO is not used in receive mode. Used only

DIO is not used in receive mode. Used only
as data input in transmit mode

as data input in transmit mode

1 0 1 1 0 0 0 1 1 0 1

1 0 1 1 0 0 0 1 1 0 1

Figure 12. Manchester encoding

10. Data Rate Programming

The data rate (baud rate) is programmable
and depends on the crystal frequency and
the programming of the CLOCK
(CLOCK_A and CLOCK_B) registers.

The baud rate (B.R) is given by

f

..

RB

=

xosc

⋅⋅+⋅

where DIV1 and DIV2 are given by the
value of MCLK_DIV1 and MCLK_DIV2.

Table 17 below shows some possible data
rates as a function of crystal frequency in
synchronous mode. In asynchronous
transparent UART mode any data rate up
to 153.6 kBaud can be used.

21)1_(8

DIVDIVDIVREF

Time

Time

MCLK_DIV2[1:0] DIV2

00 1
01 2
10 4
11 8

Table 15. DIV2 for different settings of

MCLK_DIV2

MCLK_DIV1[2:0] DIV1

000 2.5
001 3
010 4
011 7.5
100 12.5
101 40
110 48
111 64

Table 16. DIV1 for different settings of

MCLK_DIV1

SWRS045 Page 27 of 91

CC1021

[kBaud]

0.45 X X

0.5 X

0.6 X X X X X X X

0.9 X X
1 X

1.2 X X X X X X X

1.8 X X
2 X

2.4 X X X X X X X

3.6 X X
4 X

4.096 X X

4.8 X X X X X X X

7.2 X X
8 X

8.192 X X

9.6 X X X X X X X

14.4 X X
16 X

16.384 X X

19.2 X X X X X X X

28.8 X X
32 X

32.768 X X

38.4 X X X X X X X

57.6 X X
64 X

65.536 X

76.8 X X X X X X X

115.2 X X
128 X

153.6 X X X X X

4.9152 7.3728 9.8304 12.288 14.7456 17.2032 19.6608

Table 17. Some possible data rates versus crystal frequency

11. Frequency Programming

Programming the frequency word in the
configuration registers sets the operation
frequency. There are two frequency words
registers, termed FREQ_A and FREQ_B,
which can be programmed to two different
frequencies. One of the frequency words
can be used for RX (local oscillator
frequency) and the other for TX
(transmitting carrier frequency) in order to
be able to switch very fast between RX
mode and TX mode. They can also be
used for RX (or TX) at two different
channels. The F_REG bit in the MAIN
register selects frequency word A or B.

The frequency word is located in

FREQ_2A:FREQ_1A:FREQ_0A and
FREQ_2B:FREQ_1B:FREQ_0B for the
FREQ_A and FREQ_B word respectively.

The LSB of the FREQ_0 registers are
used to enable dithering, section 11.1.

Crystal frequency [MHz] Data rate

The PLL output frequency is given by:

5.0

3



ff

+⋅=



refc

4



⋅+

32768

in the frequency band 402 ñ 470 MHz, and

5.0

3



ff

+⋅=



refc

2



⋅+

16384

in the frequency band 804 ñ 940 MHz.

The BANDSELECT bit in the ANALOG
register controls the frequency band used.
BANDSELECT = 0 gives 402 - 470 MHz,
and BANDSELECT = 1 gives 804 - 940
MHz.

The reference frequency is the crystal
oscillator clock frequency divided by
REF_DIV (3 bits in the CLOCK_A or

DITHERFREQ

DITHERFREQ











SWRS045 Page 28 of 91