TEXAS INSTRUMENTS CC1021 Technical data

CC1021

Applications

• Low power UHF wireless data

• 433, 868 and 915 MHz ISM/SRD band

• AMR ñ Automatic Meter Reading

Product Description

CC1021

ceiver designed for very low power and very low voltage wireless applications. The circuit is mainly intended for the ISM (Industrial, Scientific and Medical) and SRD (Short Range Device) frequency bands at 433, 868 and 915 MHz, but can easily be programmed for multi-channel operation at other frequencies in the 402 470 and 804 - 940 MHz range.

The narrowband systems with channel spacings of 50 kHz and higher complying with EN 300 220 and FCC CFR47 part 15.

The can be programmed via a serial bus, thus making use transceiver.

Features

• True single chip UHF RF transceiver

• Frequency range 402 MHz - 470 MHz

• High sensitivity (up to ñ112 dBm for

• Programmable output power

• Low current consumption (RX: 19.9

• Low supply voltage (2.3 V to 3.6 V)

• Very few external components required

• Small size (QFN 32 package)

• Pb-free package

• Digital RSSI and carrier sense indicator

• Data rate up to 153.6 kBaud

Single Chip Low Power RF Transceiver for Narrowband Systems

transmitters and receivers with channel spacings of 50 kHz or higher

systems

is a true single-chip UHF trans-

CC1021

is especially suited for

CC1021

main operating parameters

CC1021

a very flexible and easy to

and 804 MHz - 940 MHz

38.4 kHz and ñ106 dBm for 102.4 kHz receiver channel filter bandwidths respectively)

mA)

• Wireless alarm and security systems

• Home automation

• Low power telemetry

• Automotive (RKE/TPMS)

In a typical system together with a microcontroller and a few external passive components.

CC1021

is based on Chipconís SmartRF-

02 technology in 0.35 µm CMOS.

• OOK, FSK and GFSK data modulation

• Integrated bit synchronizer

• Image rejection mixer

• Programmable frequency

• Automatic frequency control (AFC)

• Suitable for frequency hopping systems

• Suited for systems targeting

compliance with EN 300 220 and FCC CFR47 part 15

• Development kit available

• Easy-to-use software for generating the

CC1021

configuration data

• Fully compatible with receiver channel filter bandwidths of

38.4 kHz and higher

CC1021

will be used

CC1020

for

SWRS045 Page 1 of 91

CC1021

Table of Contents

1. Abbreviations.................................................................................................................4

2. Absolute Maximum Ratings .........................................................................................5

3. Operating Conditions....................................................................................................5

4. Electrical Specifications...............................................................................................5

4.1. RF Transmit Section.............................................................................................6

4.2. RF Receive Section..............................................................................................8

4.3. RSSI / Carrier Sense Section.............................................................................11

4.4. IF Section............................................................................................................11

4.5. Crystal Oscillator Section ...................................................................................12

4.6. Frequency Synthesizer Section..........................................................................13

4.7. Digital Inputs / Outputs .......................................................................................14

4.8. Current Consumption .........................................................................................15

5. Pin Assignment ...........................................................................................................15

6. Circuit Description ......................................................................................................17

7. Application Circuit.......................................................................................................18

8. Configuration Overview..............................................................................................21

8.1. Configuration Software.......................................................................................21

9. Microcontroller Interface ............................................................................................22

9.1. 4-wire Serial Configuration Interface..................................................................23

9.2. Signal Interface...................................................................................................25

10. Data Rate Programming .............................................................................................27

11. Frequency Programming............................................................................................28

11.1. Dithering..........................................................................................................29

12. Receiver........................................................................................................................30

12.1. IF Frequency...................................................................................................30

12.2. Receiver Channel Filter Bandwidth ................................................................30

12.3. Demodulator, Bit Synchronizer and Data Decision.........................................31

12.4. Receiver Sensitivity versus Data Rate and Frequency Separation................32

12.5. RSSI................................................................................................................33

12.6. Image Rejection Calibration............................................................................35

12.7. Blocking and Selectivity..................................................................................36

12.8. Linear IF Chain and AGC Settings .................................................................38

12.9. AGC Settling ...................................................................................................40

12.10. Preamble Length and Sync Word...................................................................40

12.11. Carrier Sense..................................................................................................41

12.12. Automatic Power-up Sequencing ...................................................................41

12.13. Automatic Frequency Control .........................................................................42

12.14. Digital FM........................................................................................................43

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CC1021

13. Transmitter...................................................................................................................44

13.1. FSK Modulation Formats................................................................................44

13.2. Output Power Programming ...........................................................................44

13.3. TX Data Latency .............................................................................................45

13.4. Reducing Spurious Emission and Modulation Bandwidth ..............................46

14. Input / Output Matching and Filtering .......................................................................46

15. Frequency Synthesizer...............................................................................................50

15.1. VCO, Charge Pump and PLL Loop Filter .......................................................50

15.2. VCO and PLL Self-Calibration........................................................................51

15.3. PLL Turn-on Time versus Loop Filter Bandwidth ...........................................52

15.4. PLL Lock Time versus Loop Filter Bandwidth ................................................53

16. VCO and LNA Current Control...................................................................................53

17. Power Management.....................................................................................................54

18. On-Off Keying (OOK)...................................................................................................56

19. Crystal Oscillator.........................................................................................................58

20. Built-in Test Pattern Generator ..................................................................................59

21. Interrupt on Pin DCLK.................................................................................................60

21.1. Interrupt upon PLL Lock..................................................................................60

21.2. Interrupt upon Received Signal Carrier Sense...............................................60

22. PA_EN and LNA_EN Digital Output Pins ..................................................................60

22.1. Interfacing an External LNA or PA..................................................................60

22.2. General Purpose Output Control Pins ............................................................61

22.3. PA_EN and LNA_EN Pin Drive.......................................................................61

23. System Considerations and Guidelines ...................................................................61

24. PCB Layout Recommendations.................................................................................63

25. Antenna Considerations.............................................................................................64

26. Configuration Registers .............................................................................................64

26.1. CC1021 Register Overview ............................................................................65

27. Package Description (QFN 32)...................................................................................85

27.1. Package Marking ............................................................................................86

27.2. Recommended PCB Footprint for Package (QFN 32) ...................................87

27.3. Package Thermal Properties ..........................................................................87

27.4. Soldering Information......................................................................................87

27.5. Plastic Tube Specification...............................................................................88

27.6. Carrier Tape and Reel Specification...............................................................88

28. Ordering Information...................................................................................................88

29. General Information ....................................................................................................89

30. Address Information ...................................................................................................91

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CC1021

1. Abbreviations

ACP Adjacent Channel Power ACR Adjacent Channel Rejection ADC Analog-to-Digital Converter AFC Automatic Frequency Control AGC Automatic Gain Control AMR Automatic Meter Reading ASK Amplitude Shift Keying BER Bit Error Rate BOM Bill Of Materials bps bits per second BT Bandwidth-Time product (for GFSK) ChBW Receiver Channel Filter Bandwidth CW Continuous Wave DAC Digital-to-Analog Converter DNM Do Not Mount ESR Equivalent Series Resistance FHSS Frequency Hopping Spread Spectrum FM Frequency Modulation FS Frequency Synthesizer FSK Frequency Shift Keying GFSK Gaussian Frequency Shift Keying IC Integrated Circuit IF Intermediate Frequency IP3 Third Order Intercept Point ISM Industrial Scientific Medical kbps kilo bits per second LNA Low Noise Amplifier LO Local Oscillator (in receive mode) MCU Micro Controller Unit NRZ Non Return to Zero OOK On-Off Keying PA Power Amplifier PD Phase Detector / Power Down PER Packet Error Rate PCB Printed Circuit Board PN9 Pseudo-random Bit Sequence (9-bit) PLL Phase Locked Loop PSEL Program Select RF Radio Frequency RKE Remote Keyless Entry RSSI Received Signal Strength Indicator RX Receive (mode) SBW Signal Bandwidth SPI Serial Peripheral Interface SRD Short Range Device TBD To Be Decided/Defined TPMS Tire Pressure Monitoring T/R Transmit/Receive (switch) TX Transmit (mode) UHF Ultra High Frequency VCO Voltage Controlled Oscillator VGA Variable Gain Amplifier XOSC Crystal oscillator XTAL Crystal

SWRS045 Page 4 of 91

CC1021

2. Absolute Maximum Ratings

The absolute maximum ratings given Table 1 should under no circumstances be violated. Stress exceeding one or more of the limiting values may cause permanent damage to the device.

Supply voltage, VDD -0.3 5.0 V All supply pins must have the

Voltage on any pin -0.3 VDD+0.3, max 5.0 V Input RF level 10 dBm Storage temperature range -50 150 Package body temperature 260 Humidity non-condensing 5 85 % ESD (Human Body Model)

1

The reflow peak soldering temperature (body temperature) is specified according to IPC/JEDEC J-STD_020C ìMoisture/Reflow Sensitivity Classification for Nonhermetic Solid State Surface Mount Devicesî.

3. Operating Conditions

The operating conditions for

RF Frequency Range 402

Operating ambient temperature

range

Supply voltage

4. Electrical Specifications

Table 3 to Table 10 gives the performed using the 2 layer PCB CC1020EMX reference design. This is the same test circuit as shown in Figure 3. Temperature = 25°C, supply voltage = AVDD = DVDD = 3.0 V if nothing else stated. Crystal frequency = 14.7456 MHz.

The electrical specifications given for 868 MHz are also applicable for the 902 ñ 928 MHz frequency range.

Parameter Min Max Unit Condition

same voltage

Norm: IPC/JEDEC J-STD-020C 1

All pads except RF RF Pads

±1

±0.4

°C °C

kV kV

Table 1. Absolute maximum ratings

Caution! ESD sensitive device. Precaution should be used when handling the device in order to prevent permanent damage.

CC1021

are listed in Table 2.

Parameter

Min Typ Max Unit Condition / Note

804

-40 85

2.3 3.0 3.6 V

470 940

MHz

Programmable in <300 Hz steps

MHz

Programmable in <600 Hz steps

°C

The same supply voltage should be used for digital (DVDD) and analog (AVDD) power.

Table 2. Operating conditions

CC1021

electrical specifications. All measurements were

SWRS045 Page 5 of 91

CC1021

4.1. RF Transmit Section

Parameter

Transmit data rate

Binary FSK frequency separation

Output power

433 MHz

868 MHz

Output power tolerance

Harmonics, radiated CW

nd

2

harmonic, 433 MHz, +10 dBm

rd

3

harmonic, 433 MHz, +10 dBm

nd

harmonic, 868 MHz, +5 dBm

2

rd

3

harmonic, 868 MHz, +5 dBm

Adjacent channel power (GFSK)

433 MHz

868 MHz

Occupied bandwidth (99.5%,GFSK)

433 MHz

868 MHz

Modulation bandwidth, 868 MHz

19.2 kBaud, ±9.9 kHz frequency

deviation

38.4 kBaud, ±19.8 kHz frequency

deviation

Min Typ Max Unit Condition / Note

0.45

0 0

-20 to +10

-20 to +5

153.6 kBaud The data rate is programmable.

108

-4

+3

-50

-46

-42

60

48

106

216

See section 10 on page 27 for details.

NRZ or Manchester encoding can be used. 153.6 kBaud equals

153.6 kbps using NRZ coding and 76.8 kbps using Manchester coding. See section 9.2 on page 25 for details

Minimum data rate for OOK is 2.4 kBaud

kHz

in 402 - 470 MHz range

kHz

in 804 - 940 MHz range

108/216 kHz is the maximum guaranteed separation at 1.84 MHz reference frequency. Larger separations can be achieved at higher reference frequencies.

Delivered to 50 Ω single-ended load. The output power is

dBm

programmable and should not be programmed to exceed +10/+5

dBm

dBm at 433/868 MHz under any operating conditions. See section 14 on page 46 for details.

At maximum output power

dB

At 2.3 V, +85 At 3.6 V, -40

dB

Harmonics are measured as

dBc

EIRP values according to EN 300

dBc

220. The antenna (SMAFF-433 and SMAFF-868 from R.W.

dBc

Badland) plays a part in

dBc

attenuating the harmonics.

ACP is measured in a 100 kHz bandwidth at ±100 kHz offset.

dBc

Modulation: 19.2 kBaud NRZ PN9 sequence, ±19.8 kHz

dBc

frequency deviation.

Bandwidth for 99.5% of total average power.

kHz

Modulation: 19.2 kBaud NRZ

kHz

PN9 sequence, ±19.8 kHz frequency deviation.

Bandwidth where the power envelope of modulation equals

kHz

ñ36 dBm. Spectrum analyzer RBW = 1 kHz.

kHz

o

C

o

C

SWRS045 Page 6 of 91

Parameter

Spurious emission, radiated CW

47-74, 87.5-118,

174-230, 470-862 MHz

9 kHz ñ 1 GHz

1 ñ 4 GHz

Optimum load impedance

433 MHz

868 MHz

915 MHz

CC1021

Min Typ Max Unit Condition / Note

54 + j44

15 + j24

20 + j35

-54

-36

-30

Table 3. RF transmit parameters

At maximum output power, +10/+5 dBm at 433/868 MHz.

dBm

To comply with EN 300 220, FCC CFR47 part 15 and ARIB

dBm

STD T-67 an external (antenna) filter, as implemented in the

dBm

application circuit in Figure 25, must be used and tailored to each individual design to reduce out-of-band spurious emission levels.

Spurious emissions can be measured as EIRP values according to EN 300 220. The antenna (SMAFF-433 and SMAFF-868 from R.W. Badland) plays a part in attenuating the spurious emissions.

If the output power is increased using an external PA, a filter must be used to attenuate spurs below 862 MHz when operating in the 868 MHz frequency band in Europe. Application Note AN036

CC1020/1021 Spurious Emission

presents and discusses a solution that reduces the TX mode spurious emission close to 862 MHz by increasing the REF_DIV from 1 to 7.

Transmit mode. For matching details see section 14 on page

Ω

46.

Ω

SWRS045 Page 7 of 91

CC1021

4.2. RF Receive Section

Parameter

Receiver Sensitivity, 433 MHz, FSK

38.4 kHz channel filter BW (1)

102.4 kHz channel filter BW (2)

102.4 kHz channel filter BW (3)

307.2 kHz channel filter BW (4)

Receiver Sensitivity, 868 MHz, FSK

38.4 kHz channel filter BW (1)

102.4 kHz channel filter BW (2)

102.4 kHz channel filter BW (3)

307.2 kHz channel filter BW (4)

Receiver sensitivity, 433 MHz, OOK

9.6 kBaud

153.6 kBaud

Receiver sensitivity, 868 MHz, OOK

9.6 kBaud

153.6 kBaud

Saturation (maximum input level)

FSK and OOK

System noise bandwidth 38.4

Noise figure, cascaded

433 and 868 MHz

Min Typ Max Unit Condition / Note

-109

-104

-108

-103

-104

307.2

7

-96

-94

-81

-87

10

to

kHz The receiver channel filter 6 dB

Sensitivity is measured with PN9 sequence at BER = 10

(1) 38.4 kHz receiver channel

dBm

filter bandwidth: 4.8 kBaud, NRZ coded data, ±4.95 kHz frequency deviation.

(2) 102.4 kHz receiver channel

dBm

filter bandwidth: 19.2 kBaud, NRZ coded data, ±19.8 kHz frequency deviation.

(3) 102.4 kHz receiver channel

dBm

filter bandwidth: 38.4 kBaud, NRZ coded data, ±19.8 kHz frequency deviation.

(4) 307.2 kHz receiver channel

dBm

filter bandwidth: 153.6 kBaud, NRZ coded data, ±72 kHz frequency deviation.

See Table 19 and Table 20 or typical sensitivity figures at other

dBm

channel filter bandwidths.

dBm

Sensitivity is measured with PN9 sequence at BER = 10

dBm

Manchester coded data.

dBm

See Table 27 for typical sensitivity figures at other data rates.

dBm dBm

dBm FSK: Manchester/NRZ coded

data OOK: Manchester coded data BER = 10

bandwidth is programmable from

38.4 kHz to 307.2 kHz. See section 12.2 on page 30 for details.

dB NRZ coded data

3

SWRS045 Page 8 of 91

Parameter

Input IP3

433 MHz 102.4 kHz channel filter BW

868 MHz 102.4 kHz channel filter BW

Co-channel rejection, FSK and OOK

433 MHz and 868 MHz,

102.4 kHz channel filter BW,

Adjacent channel rejection (ACR)

433 MHz 102.4 kHz channel filter BW

868 MHz 102.4 kHz channel filter BW

Image channel rejection

433/868 MHz

No I/Q gain and phase calibration

I/Q gain and phase calibrated

Selectivity*

433 MHz 102.4 kHz channel filter BW

±200 kHz offset

±300 kHz offset

868 MHz 102.4 kHz channel filter BW

±200 kHz offset

±300 kHz offset

(*Close-in spurious response

rejection)

Blocking / Desensitization*

433/868 MHz

± 1 MHz

± 2 MHz

± 5 MHz

± 10 MHz

(*Out-of-band spurious response

rejection)

Image frequency suppression,

433/868 MHz

No I/Q gain and phase calibration

I/Q gain and phase calibrated

CC1021

Min Typ Max Unit Condition / Note

-23

-18

-16

-18

-15

-13

-11

32

30

25/25

50/50

45 53

45 50

52/58 56/64 58/64 64/66

35/35

60/60

Two tone test (+10 MHz and +20 MHz)

dBm

LNA2 maximum gain

dBm

LNA2 medium gain

dBm

LNA2 minimum gain

dBm

LNA2 maximum gain

dBm

LNA2 medium gain

dBm

LNA2 minimum gain

dB Wanted signal 3 dB above the

sensitivity level, CW jammer at operating frequency, BER = 10

Wanted signal 3 dB above the

dB

sensitivity level, CW jammer at adjacent channel, BER = 10

dB

Measured at ±100 kHz offset. See Figure 16 to Figure 19.

Wanted signal 3 dB above the sensitivity level, CW jammer at image frequency, BER = 10

102.4 kHz channel filter

dB

bandwidth. See Figure 16 to Figure 19.

dB

Image rejection after calibration will depend on temperature and supply voltage. Refer to section

12.6 on page 35.

Wanted signal 3 dB above the sensitivity level. CW jammer is

dB

swept in 20 kHz steps within ± 1

dB

MHz from wanted channel. BER = 10 image channel are excluded. See Figure 16 to Figure 19.

dB dB

Wanted signal 3 dB above the sensitivity level, CW jammer at ±

dB

1, 2, 5 and 10 MHz offset,

dB

BER = 10 filter bandwidth.

dB dB

Complying with EN 300 220, class 2 receiver requirements.

Ratio between sensitivity for a signal at the image frequency to the sensitivity in the wanted

dB

channel. Image frequency is RF 2 IF. BER = 10 channel filter bandwidth.

dB

3

. Adjacent channel and

3

. 102.4 kHz channel

3

. 102.4 kHz

3

.

3

.

SWRS045 Page 9 of 91

CC1021

Parameter

Spurious reception

LO leakage, 433/868 MHz <-80/-66 dBm

VCO leakage -64 dBm VCO frequency resides between

Spurious emission, radiated CW

9 kHz ñ 1 GHz

1 ñ 4 GHz

Input impedance

433 MHz

868 MHz

Matched input impedance, S11

433 MHz

868 MHz

Matched input impedance

433 MHz

868 MHz

Bit synchronization offset 8000 ppm The maximum bit rate offset

Data latency

NRZ mode

Manchester mode

Min Typ Max Unit Condition / Note

37 dB Ratio between sensitivity for an

<-60

58 - j10

54 - j22

-14

-12

39 - j14

32 - j10

4

8

Baud

unwanted frequency to the sensitivity in the wanted channel. The signal source is swept over all frequencies 100 MHz ñ 2 GHz. Signal level for BER = 10

102.4 kHz channel filter bandwidth.

1608 ñ 1880 MHz

Complying with EN 300 220,

dBm

FCC CFR47 part 15 and ARIB STD T-67.

dBm

Spurious emissions can be measured as EIRP values according to EN 300 220.

Receive mode. See section 14 on page 46 for details.

Ω

Using application circuit matching

dB

network. See section 14 on page 46 for details.

dB

Using application circuit matching network. See section 14 on page

Ω

46 for details.

Ω

tolerated by the bit synchronization circuit for 6 dB degradation (synchronous modes only)

Time from clocking the data on the transmitter DIO pin until data is available on receiver DIO pin

Table 4. RF receive parameters

3

.

SWRS045 Page 10 of 91

CC1021

4.3. RSSI / Carrier Sense Section

Parameter

RSSI dynamic range

RSSI accuracy

RSSI linearity

RSSI attach time

51.2 kHz channel filter BW

102.4 kHz channel filter BW

307.2 kHz channel filter BW

Carrier sense programmable range

Carrier sense at ±100 kHz and ±200

kHz offset

102.4 kHz channel filter BW, 433 MHz

±100 kHz

±200 kHz

102.4 kHz channel filter BW, 868 MHz

±100 kHz

±200 kHz

Table 5. RSSI / Carrier sense parameters

4.4. IF Section

Parameter

Intermediate frequency (IF)

Digital channel filter bandwidth

AFC resolution

Min Typ Max Unit Condition / Note

55 dB See section 12.5 on page 33 for

40 dB Accuracy is as for RSSI

Min Typ Max Unit Condition / Note

307.2 kHz See section 12.1 on page 30 for

38.4 to

307.2

1200 Hz At 19.2 kBaud

Table 6. IF section parameters

± 3

± 1

730

380

140

-57

-44

-60

-44

details.

dB See section 12.5 on page 33 for

dB

kHz The channel filter 6 dB bandwidth

details.

Shorter RSSI attach times can be traded for lower RSSI accuracy. See section 12.5 on page 33 for

µs

details.

µs

Shorter RSSI attach times can also be traded for reduced

µs

sensitivity and selectivity by increasing the receiver channel filter bandwidth.

At carrier sense level 98 dBm, CW jammer at ±100 kHz and

±200 kHz offset. dBm dBm

Carrier sense is measured by

applying a signal at ±100 kHz and

±200 kHz offset and observe at dBm

which level carrier sense is dBm

indicated.

details.

is programmable from 9.6 kHz to

307.2 kHz. See section 12.2 on

page 30 for details.

Given as Baud rate/16. See

section 12.13 on page 42 for

details.

SWRS045 Page 11 of 91

CC1021

4.5. Crystal Oscillator Section

Parameter

Crystal Oscillator Frequency

Crystal operation

Crystal load capacitance

Crystal oscillator start-up time 1.55

External clock signal drive, sine wave

External clock signal drive, full-swing digital external clock

Min Typ Max Unit Condition / Note

4.9152 14.7456 19.6608 MHz Recommended frequency is

Parallel C4 and C5 are loading

12 12 12

1.0

0.90

0.95

0.60

0.63

300

0 - VDD

Table 7. Crystal oscillator parameters

22 16 16

14.7456 MHz. See section 19 on

page 58 for details.

capacitors. See section 19 on

page 58 for details.

30 30 16

ms

mVpp

V The external clock signal must be

pF

4.9-6 MHz, 22 pF recommended

pF

6-8 MHz, 16 pF recommended

pF

8-19.6 MHz, 16 pF recommended

4.9152 MHz, 12 pF load

ms

7.3728 MHz, 12 pF load

ms

9.8304 MHz, 12 pF load

ms

14.7456 MHz, 16 pF load

ms

17.2032 MHz, 12 pF load

ms

19.6608 MHz, 12 pF load

The external clock signal must be

connected to XOSC_Q1 using a

DC block (10 nF). Set

XOSC_BYPASS = 0 in the

INTERFACE register when using

an external clock signal with low

amplitude or a crystal.

connected to XOSC_Q1. No DC

block shall be used. Set

XOSC_BYPASS = 1 in the

INTERFACE register when using

a full-swing digital external clock.

SWRS045 Page 12 of 91

CC1021

4.6. Frequency Synthesizer Section

Parameter

Phase noise, 402 ñ 470 MHz

Phase noise, 804 ñ 940 MHz

PLL loop filter bandwidth

Loop filter 2, up to 19.2 kBaud

Loop filter 3, up to 38.4 kBaud

PLL lock time (RX / TX turn time)

Loop filter 2, up to 19.2 kBaud

Loop filter 3, up to 38.4 kBaud

Loop filter 5, up to 153.6 kBaud

PLL turn-on time. From power down mode with crystal oscillator running.

Loop filter 2, up to 19.2 kBaud

Loop filter 3, up to 38.4 kBaud

Loop filter 5, up to 153.6 kBaud

Table 8. Frequency synthesizer parameters

Min Typ Max Unit Condition / Note

-79

-80

-87

-100

-105

-73

-74

-81

-94

-111

15

30.5

140

75

14

1300

1080

700

dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz

Unmodulated carrier

At 12.5 kHz offset from carrier

At 25 kHz offset from carrier

At 50 kHz offset from carrier

At 100 kHz offset from carrier

At 1 MHz offset from carrier

Measured using loop filter

components given in Table 13.

The phase noise will be higher for

larger PLL loop filter bandwidth.

Unmodulated carrier

At 12.5 kHz offset from carrier

At 25 kHz offset from carrier

At 50 kHz offset from carrier

At 100 kHz offset from carrier

At 1 MHz offset from carrier

Measured using loop filter

components given in Table 13.

The phase noise will be higher for

larger PLL loop filter bandwidth.

After PLL and VCO calibration.

The PLL loop bandwidth is

kHz

programmable.

kHz

See Table 25 on page 52 for loop

filter component values.

307.2 kHz frequency step to RF

frequency within ±10 kHz, ±15

us

kHz, ±50 kHz settling accuracy

for loop filter 2, 3 and 5

us

respectively. Depends on loop

filter component values and

us

PLL_BW register setting. See

Table 26 on page 53 for more

details.

Time from writing to registers to

RF frequency within ±10 kHz, ±15

us

kHz, ±50 kHz settling accuracy

for loop filter 2, 3 and 5

us

respectively. Depends on loop

filter component values and

us

PLL_BW register setting. See

Table 25 on page 53 for more

details.

SWRS045 Page 13 of 91

CC1021

4.7. Digital Inputs / Outputs

Parameter

Logic "0" input voltage

Logic "1" input voltage

Logic "0" output voltage 0

Logic "1" output voltage 2.5

Logic "0" input current

Logic "1" input current

DIO setup time 20 ns TX mode, minimum time DIO

DIO hold time

Serial interface (PCLK, PDI, PDO and PSEL) timing specification

Pin drive, LNA_EN, PA_EN

Table 9. Digital inputs / outputs parameters

Min Typ Max Unit Condition / Note

0 0.3*

0.7*

VDD

NA 1

NA 1

10 ns TX mode, minimum time DIO

See Table 14 on page 24 for

VDD V

0.4 V Output current 2.0 mA,

VDD V Output current 2.0 mA,

0.90

0.87

0.81

0.69

0.93

0.92

0.89

0.79

VDD

V

3.0 V supply voltage

Input signal equals GND.

µA

PSEL has an internal pull-up

resistor and during configuration

the current will be -350 µA.

Input signal equals VDD

µA

must be ready before the positive

edge of DCLK. Data should be

set up on the negative edge of

DCLK.

must be held after the positive

edge of DCLK. Data should be

set up on the negative edge of

DCLK.

more details

Source current

mA

0 V on LNA_EN, PA_EN pins

mA

0.5 V on LNA_EN, PA_EN pins

mA

1.0 V on LNA_EN, PA_EN pins

mA

1.5 V on LNA_EN, PA_EN pins

Sink current

mA

3.0 V on LNA_EN, PA_EN pins

mA

2.5 V on LNA_EN, PA_EN pins

mA

2.0 V on LNA_EN, PA_EN pins

mA

1.5 V on LNA_EN, PA_EN pins

See Figure 35 on page 61 for

more details.

SWRS045 Page 14 of 91

CC1021

4.8. Current Consumption

Parameter

Power Down mode

Current Consumption, receive mode 433 and 868 MHz

Current Consumption, transmit mode 433/868 MHz:

P = 20 dBm

P = 5 dBm

P = 0 dBm

P = +5 dBm

P = +10 dBm (433 MHz only)

Current Consumption, crystal oscillator

Current Consumption, crystal oscillator and bias

Current Consumption, crystal oscillator, bias and synthesizer

5. Pin Assignment

Table 11 provides an overview of the

CC1021

pinout.

Min Typ Max Unit Condition / Note

0.2 1.8

19.9 mA

12.3/14.5

14.4/17.0

16.2/20.5

20.5/25.1

27.1

77

Table 10. Current consumption

500

7.5

Oscillator core off

µA

mA

The output power is delivered to

a 50 Ω single-ended load.

mA

See section 13.2 on page 44 for

mA

more details.

mA

The

CC1021

14.7456 MHz, 16 pF load crystal

µA

14.7456 MHz, 16 pF load crystal

µA

14.7456 MHz, 16 pF load crystal

mA

comes in a QFN32 type

package (see page 85 for details).

32PSEL

31DVDD

30DGND

29AVDD

28CHP_OUT

27AVDD

26AD_REF

25AGND

PCLK 1

PDI

PDO

DGND

DVDD

DGND

DCLK

DIO 8

2 3 4 5 6 7

13

12

9

XOSC_Q211XOSC_Q110LOCK

AVDD

PA_EN15LNA_EN14AVDD

AVDD16

VC

24 23

AVDD

22

AVDD

21

RF_OUT

20

AVDD

19

RF_IN

18

AVDD

17

R_BIAS

AGND Exposed die attached pad

Figure 1.

SWRS045 Page 15 of 91

CC1021

package (top view)

CC1021

Pin no. Pin name Pin type Description

- AGND Ground (analog) Exposed die attached pad. Must be soldered to a solid ground plane as

1 PCLK Digital input Programming clock for SPI configuration interface 2 PDI Digital input Programming data input for SPI configuration interface 3 PDO Digital output Programming data output for SPI configuration interface 4 DGND Ground (digital) Ground connection (0 V) for digital modules and digital I/O 5 DVDD Power (digital) Power supply (3 V typical) for digital modules and digital I/O 6 DGND Ground (digital) Ground connection (0 V) for digital modules (substrate) 7 DCLK Digital output Clock for data in both receive and transmit mode.

8 DIO Digital input/output Data input in transmit mode; data output in receive mode

9 LOCK Digital output PLL Lock indicator, active low. Output is asserted (low) when PLL is in

10 XOSC_Q1 Analog input Crystal oscillator or external clock input 11 XOSC_Q2 Analog output Crystal oscillator 12 AVDD Power (analog) Power supply (3 V typical) for crystal oscillator 13 AVDD Power (analog) Power supply (3 V typical) for the IF VGA 14 LNA_EN Digital output General digital output. Can be used for controlling an external LNA if

15 PA_EN Digital output General digital output. Can be used for controlling an external PA if

16 AVDD Power (analog) Power supply (3 V typical) for global bias generator and IF anti-alias

17 R_BIAS Analog output 18 AVDD Power (analog) Power supply (3 V typical) for LNA input stage 19 RF_IN RF Input RF signal input from antenna (external AC-coupling) 20 AVDD Power (analog) Power supply (3 V typical) for LNA 21 RF_OUT RF output RF signal output to antenna 22 AVDD Power (analog) Power supply (3 V typical) for LO buffers, mixers, prescaler, and first PA

23 AVDD Power (analog) Power supply (3 V typical) for VCO 24 VC Analog input VCO control voltage input from external loop filter 25 AGND Ground (analog) Ground connection (0 V) for analog modules (guard) 26 AD_REF Power (analog) 3 V reference input for ADC 27 AVDD Power (analog) Power supply (3 V typical) for charge pump and phase detector 28 CHP_OUT Analog output PLL charge pump output to external loop filter 29 AVDD Power (analog) Power supply (3 V typical) for ADC 30 DGND Ground (digital) Ground connection (0 V) for digital modules (guard) 31 DVDD Power (digital) Power supply connection (3 V typical) for digital modules 32 PSEL Digital input Programming chip select, active low, for configuration interface. Internal

this is the ground connection for all analog modules. See page 63 for more details.

Can be used as receive data output in asynchronous mode

Can also be used to start power-up sequencing in receive

lock. The pin can also be used as a general digital output, or as receive data output in synchronous NRZ/Manchester mode

higher sensitivity is needed.

higher output power is needed.

filter Connection for external precision bias resistor (82 kΩ, ± 1%)

stage

pull-up resistor.

Table 11. Pin assignment overview

Note:

DCLK, DIO and LOCK are highimpedance (3-state) in power down (BIAS_PD = 1 in the MAIN register).

The exposed die attached pad must be soldered to a solid ground plane as this is the main ground connection for the chip.

SWRS045 Page 16 of 91

CC1021

6. Circuit Description

LNA

PA

LNA 2

PA_EN

Power

Control

LNA_EN

Figure 2.

Multiplexer

BIAS

R_BIAS

CC1021

0

:2

90

XOSC_Q1 XOSC_Q2

simplified block diagram

RF_IN

RF_OUT

CC1021

A simplified block diagram of

is shown in Figure 2. Only signal pins are shown.

CC1021

features a low-IF receiver. The received RF signal is amplified by the lownoise amplifier (LNA and LNA2) and down-converted in quadrature (I and Q) to the intermediate frequency (IF). At IF, the I/Q signal is complex filtered and amplified, and then digitized by the ADCs. Automatic gain control, fine channel filtering, demodulation and bit synchronization is performed digitally.

CC1021

outputs the digital demodulated data on the DIO pin. A synchronized data clock is available at the DCLK pin. RSSI is available in digital format and can be read via the serial interface. The RSSI also features a programmable carrier sense indicator.

In transmit mode, the synthesized RF frequency is fed directly to the power

DIGITAL

DEMODULATOR

- Digital RSSI

- Gain Control

- Image Suppression

- Channel Filtering

- Demodulation

DIGITAL

INTERFACE

TO µC

LOGIC

CONTROL

DIGITAL

MODULATOR

- Modulation

- Data shaping

- Power Control

0

90

XOSC

ADC

:2

SYNTH

VC

FREQ

CHP_OUT

amplifier (PA). The RF output is frequency shift keyed (FSK) by the digital bit stream that is fed to the DIO pin. Optionally, a Gaussian filter can be used to obtain Gaussian FSK (GFSK).

The frequency synthesizer includes a completely on-chip LC VCO and a 90 degrees phase splitter for generating the LO_I and LO_Q signals to the downconversion mixers in receive mode. The VCO operates in the frequency range

1.608-1.880 GHz. The CHP_OUT pin is the charge pump output and VC is the control node of the on-chip VCO. The external loop filter is placed between these pins. A crystal is to be connected between XOSC_Q1 and XOSC_Q2. A lock signal is available from the PLL.

The 4-wire SPI serial interface is used for configuration.

LOCK

DIO

DCLK

PDO

PDI

PCLK

PSEL

SWRS045 Page 17 of 91

CC1021

7. Application Circuit

Very few external components are required for the operation of

CC1021

. The recommended application circuit is shown in Figure 3. The external components are described in Table 12 and values are given in Table 13.

Input / output matching

L1 and C1 is the input match for the receiver. L1 is also a DC choke for biasing. L2 and C3 are used to match the transmitter to 50 Ω. Internal circuitry makes it possible to connect the input and output together and match the

CC1021

to 50 Ω in both RX and TX mode. However, it is recommended to use an external T/R switch for optimum performance. See section 14 on page 46 for details

.

Component values for the matching network are easily found using the SmartRF



Studio software.

Bias resistor

The precision bias resistor R1 is used to set an accurate bias current.

PLL loop filter

The loop filter consists of two resistors (R2 and R3) and three capacitors (C6-C8). C7 and C8 may be omitted in applications

Ref Description

C1 LNA input match and DC block, see page 46 C3 PA output match and DC block, see page 46 C4 Crystal load capacitor, see page 58 C5 Crystal load capacitor, see page 58 C6 PLL loop filter capacitor C7 PLL loop filter capacitor (may be omitted for highest loop bandwidth) C8 PLL loop filter capacitor (may be omitted for highest loop bandwidth) C60 Decoupling capacitor L1 LNA match and DC bias (ground), see page 46 L2 PA match and DC bias (supply voltage), see page 46 R1 Precision resistor for current reference generator R2 PLL loop filter resistor R3 PLL loop filter resistor R10 PA output match, see page 46 XTAL Crystal, see page 58

Table 12. Overview of external components (excluding supply decoupling capacitors)

where high loop bandwidth is desired. The values shown in Table 13 are optimized for 38.4 kBaud data rate. Component values for other data rates are easily found using the SmartRF



Studio software.

Crystal

An external crystal with two loading capacitors (C4 and C5) is used for the crystal oscillator. See section 19 on page 58 for details.

Additional filtering

Additional external components (e.g. RF LC or SAW filter) may be used in order to improve the performance in specific applications. See section 14 on page 46 for further information.

Power supply decoupling and filtering

Power supply decoupling and filtering must be used (not shown in the application circuit). The placement and size of the decoupling capacitors and the power supply filtering are very important to achieve the optimum performance for narrowband applications. Chipcon provides a reference design that should be followed very closely.

SWRS045 Page 18 of 91

Microcontroller configuration interface and signal interface

DVDD=3V

CC1021

AVDD=3V

31

32

PSEL

DVDD

CC1021

XOSC_Q111XOSC_Q2

9

10

9

10

XTAL

XTALXTAL

AVDD=3V

30

DGND

AVDD

12

C6

R2

29

27

26

29

28

CHP_OUT

AVDD

LNA_EN

AVDD

13

25

27

26

25

C7 R3

AD_REF

AGND

AVDD

RF_OUT

AVDD

RF_IN

AVDD

R_BIAS

PA_EN

AVDD

16

14

15

14

15

AVDD=3V

C7 R3

24

VC

23

22

21

20

19

18

17

R2

C8

AVDD=3V

R1

AVDD=3V

R10

L2

L1

C60

C3

LC Filter

LC FilterLC Filter

C1

DVDD=3V

1

PCLK

2

PDI

3

PDO

4

DGND

5

DVDD

6

DGND

7

DCLK

8

DIO

LOCK

Monopole

antenna

(50 Ohm)

T/R Switch

C5

C5C5

C4

C4C4

Figure 3. Typical application and test circuit (power supply decoupling not shown)

Item 433 MHz 868 MHz 915 MHz

C1 10 pF, 5%, NP0, 0402 47 pF, 5%, NP0, 0402 47 pF, 5%, NP0, 0402 C3 5.6 pF, 5%, NP0, 0402 10 pF, 5%, NP0, 0402 10 pF, 5%, NP0, 0402 C4 22 pF, 5%, NP0, 0402 22 pF, 5%, NP0, 0402 22 pF, 5%, NP0, 0402 C5 12 pF, 5%, NP0, 0402 12 pF, 5%, NP0, 0402 12 pF, 5%, NP0, 0402 C6 3.9 nF, 10%, X7R, 0603 3.9 nF, 10%, X7R, 0603 3.9 nF, 10%, X7R, 0603 C7 120 pF, 10%, X7R, 0402 120 pF, 10%, X7R, 0402 120 pF, 10%, X7R, 0402 C8 33 pF, 10%, X7R, 0402 33 pF, 10%, X7R, 0402 33 pF, 10%, X7R, 0402 C60 220 pF, 5%, NP0, 0402 220 pF, 5%, NP0, 0402 220 pF, 5%, NP0, 0402 L1 33 nH, 5%, 0402 82 nH, 5%, 0402 82 nH, 5%, 0402 L2 22 nH, 5%, 0402 3.6 nH, 5%, 0402 3.6 nH, 5%, 0402 R1 R2 R3 R10 XTAL 14.7456 MHz crystal,

82 kΩ, 1%, 0402 82 kΩ, 1%, 0402 82 kΩ, 1%, 0402 12 kΩ, 5%, 0402 12 kΩ, 5%, 0402 12 kΩ, 5%, 0402 39 kΩ, 5%, 0402 39 kΩ, 5%, 0402 39 kΩ, 5%, 0402 82 Ω, 5%, 0402 82 Ω, 5%, 0402 82 Ω, 5%, 0402

16 pF load

14.7456 MHz crystal, 16 pF load

Note: Items shaded vary for different frequencies.

Table 13. Bill of materials for the application circuit in Figure 3. The PLL loop filter is

optimized for 38.4 kBaud data rate.

Note:

The PLL loop filter component values in Table 13 (R2, R3, C6-C8) are optimized for 38.4 kBaud data rate. The SmartRF



Studio software provides component values for other data rates using the

In the CC1020EMX reference design, which is also applicable for LQG15HS series inductors from Murata have been used. The switch is SW-456 from M/A-COM.

equations on page 50.

CC1021

,

SWRS045 Page 19 of 91

CC1021

The LC filter in Figure 3 is inserted in the TX path only. The filter will reduce the emission of harmonics and the spurious emissions in the TX path. An alternative is to insert the LC filter between the antenna and the T/R switch as shown in Figure 4.

AVDD=3V

Microcontroller configuration interface and signal interface

DVDD=3V

1

PCLK

2

PDI

3

PDO

4

DGND

5

DVDD

6

DGND

7

DCLK

8

DIO

LOCK

31

32

PSEL

DVDD

CC1021

XOSC_Q111XOSC_Q2

9

10

9

10

AVDD=3V

30

DGND

AVDD

12

29

27

29

27

28

AD_REF

CHP_OUT

AVDD

LNA_EN

PA_EN

AVDD

14

13

The filter will reduce the emission of harmonics and the spurious emissions in the TX path as well as increase the receiver selectivity. The sensitivity will be slightly reduced due to the insertion loss of the LC filter.

C6

R2

26

25

26

25

C7 R3

AGND

AVDD

RF_OUT

AVDD

RF_IN

AVDD

R_BIAS

AVDD

16

15

C7 R3

24

VC

23

22

21

20

19

18

17

R2

C8

AVDD=3V

R1

AVDD=3V

R10

L2

L1

C60

C3

C1

T/R Switch

Monopole

antenna

(50 Ohm)

LC Filter

LC FilterLC Filter

AVDD=3V

XTAL

XTALXTAL

C5

C5C5

C4

C4C4

Figure 4. Alternative application circuit (power supply decoupling not shown)

SWRS045 Page 20 of 91

CC1021

8. Configuration Overview

CC1021

can be configured to achieve the optimum performance for different applications. Through the programmable configuration registers the following key parameters can be programmed:

• Receive / transmit mode

• RF output power

• Frequency synthesizer key parameters:

RF output frequency, FSK frequency

8.1. Configuration Software

Chipcon provides users of software program, SmartRF (Windows interface) that generates all necessary based on the user's selections of various parameters. These hexadecimal numbers will then be the necessary input to the microcontroller for the configuration of

CC1021

configuration data

CC1021



Studio

with a

separation, crystal oscillator reference frequency

• Power-down / power-up mode

• Crystal oscillator power-up / power-

down

• Data rate and data format (NRZ, Manchester coded or UART interface)

• Synthesizer lock indicator mode

• Digital RSSI and carrier sense

• FSK / GFSK / OOK modulation

CC1021

. In addition, the program will provide the user with the component values needed for the input/output matching circuit, the PLL loop filter and the LC filter.

Figure 5 shows the user interface of the

CC1021

configuration software.



Figure 5. SmartRF

Note: The CC1020/1070DK Development Kit with a fully assembled CC1020EMX Evaluation

Module together with the transceiver.

SWRS045 Page 21 of 91

CC1021

specific software should be used for evaluation of the

Studio user interface

CC1021

9. Microcontroller Interface

CC1021

Used in a typical system, interface to a microcontroller. This microcontroller must be able to:

CC1021

• Program

into different modes via the 4-wire serial configuration interface (PDI, PDO, PCLK and PSEL)

• Interface to the bi-directional synchronous data signal interface (DIO and DCLK)

• Optionally, the microcontroller can do data encoding / decoding

• Optionally, the microcontroller can monitor the LOCK pin for frequency lock status, carrier sense status or other status information.

• Optionally, the microcontroller can read back the digital RSSI value and other status information via the 4-wire serial interface

Configuration interface

The microcontroller interface is shown in Figure 6. The microcontroller uses 3 or 4 I/O pins for the configuration interface (PDI, PDO, PCLK and PSEL). PDO should be connected to a microcontroller input. PDI, PCLK and PSEL must be microcontroller outputs. One I/O pin can be saved if PDI and PDO are connected together and a bi-directional pin is used at the microcontroller.

will

The microcontroller pins connected to PDI, PDO and PCLK can be used for other purposes when the configuration interface is not used. PDI, PDO and PCLK are high impedance inputs as long as PSEL is not activated (active low).

PSEL has an internal pull-up resistor and should be left open (tri-stated by the microcontroller) or set to a high level during power down mode in order to prevent a trickle current flowing in the pullup.

Signal interface

A bi-directional pin is usually used for data (DIO) to be transmitted and data received. DCLK providing the data timing should be connected to a microcontroller input.

As an option, the data output in receive mode can be made available on a separate pin. See section 9.2 on page for 25 further details.

PLL lock signal

Optionally, one microcontroller pin can be used to monitor the LOCK signal. This signal is at low logic level when the PLL is in lock. It can also be used for carrier sense and to monitor other internal test signals.

PCLK

PCLK PDI

PDI PDO (Optional)

PDO (Optional) PSEL

PSEL

DIO

DIO DCLK

DCLK

LOCK

(Optional)

Micro-

Microcontroller

controller

Figure 6. Microcontroller interface

SWRS045 Page 22 of 91

CC1021

9.1. 4-wire Serial Configuration Interface

CC1021

is configured via a simple 4-wire SPI-compatible interface (PDI, PDO, PCLK and PSEL) where

CC1021

is the slave. There are 8-bit configuration registers, each addressed by a 7-bit address. A Read/Write bit initiates a read or write operation. A full configuration of

CC1021

requires sending 33 data frames of 16 bits each (7 address bits, R/W bit and 8 data bits). The time needed for a full configuration depends on the PCLK frequency. With a PCLK frequency of 10 MHz the full configuration is done in less than 53 µs. Setting the device in power down mode requires sending one frame only and will in this case take less than 2 µs. All registers are also readable.

During each write-cycle, 16 bits are sent on the PDI-line. The seven most significant bits of each data frame (A6:0) are the address-bits. A6 is the MSB (Most Significant Bit) of the address and is sent as the first bit. The next bit is the R/W bit (high for write, low for read). The 8 databits are then transferred (D7:0). During address and data transfer the PSEL (Program SELect) must be kept low. See Figure 7.

The timing for the programming is also shown in Figure 7 with reference to Table

T

SS

14. The clocking of the data on PDI is done on the positive edge of PCLK. Data should be set up on the negative edge of PCLK by the microcontroller. When the last bit, D0, of the 8 data-bits has been loaded, the data word is loaded into the internal configuration register.

The configuration data will be retained during a programmed power down mode, but not when the power supply is turned off. The registers can be programmed in any order.

The configuration registers can also be read by the microcontroller via the same configuration interface. The seven address bits are sent first, then the R/W bit set low to initiate the data read-back. returns the data from the addressed register. PDO is used as the data output and must be configured as an input by the microcontroller. The PDO is set at the negative edge of PCLK and should be sampled at the positive edge. The read operation is illustrated in Figure 8.

PSEL must be set high between each read/write operation.

CC1021

then

T

HS

T

HD

Data byte

T

SD

PCLK

PDI

PDO

PSEL

T

CL,min

Address Write mode

6543210

T

CH,min

7 6 5 4 3 2 1 0

W

Figure 7. Configuration registers write operation

SWRS045 Page 23 of 91

CC1021

T

SS

T

HS

PCLK

PDI

PDO

PSEL

T

CL,min

Address

6

5

4

3

T

SH

T

CH,min

Read mode

2

1

0

R

Data byte

7

6

5

4

3

2

1

0

Figure 8. Configuration registers read operation

Parameter Symbol Min Max Unit Conditions

PCLK, clock frequency

PCLK low pulse duration

PCLK high pulse duration

PSEL setup time

PSEL hold time

PSEL high time

PDI setup time

PDI hold time

Rise time T

Fall time T

F

PCLK

T

50 ns The minimum time PCLK must be low.

CL,min

T

50 ns The minimum time PCLK must be high.

CH,min

T

SS

25 ns The minimum time PSEL must be held low after

T

HS

50 ns The minimum time PSEL must be high.

T

SH

T

SD

THD 25 ns The minimum time data must be held at PDI, after

100 ns The maximum rise time for PCLK and PSEL

rise

100 ns The maximum fall time for PCLK and PSEL

fall

10 MHz

25 ns The minimum time PSEL must be low before

25 ns The minimum time data on PDI must be ready

positive edge of PCLK.

negative edge of PCLK.

the

before the positive edge of PCLK.

positive edge of PCLK.

the

Note: The setup and hold times refer to 50% of VDD. The rise and fall times refer to 10% / 90% of VDD. The maximum load that this table is valid for is 20 pF.

Table 14. Serial interface, timing specification

SWRS045 Page 24 of 91

CC1021

9.2. Signal Interface

The

CC1021

can be used with NRZ (NonReturn-to-Zero) data or Manchester (also known as bi-phase-level) encoded data.

CC1021

can also synchronize the data from the demodulator and provide the data clock at DCLK. The data format is controlled by the DATA_FORMAT[1:0] bits in the MODEM register.

CC1021

can be configured for three different data formats:

Synchronous NRZ mode

In transmit mode clock at DCLK and DIO is used as data input. Data is clocked into rising edge of DCLK. The data is modulated at RF without encoding.

In receive mode synchronization and provides received data clock at DCLK and data at DIO. The data should be clocked into the interfacing circuit at the rising edge of DCLK. See Figure 9.

Synchronous Manchester encoded mode

In transmit mode clock at DCLK and DIO is used as data input. Data is clocked into rising edge of DCLK and should be in NRZ format. The data is modulated at RF with Manchester code. The encoding is done by

CC1021

. In this mode the effective bit rate is half the baud rate due to the coding. As an example, 19.2 kBaud Manchester encoded data corresponds to

9.6 kbps.

In receive mode synchronization and provides received data clock at DCLK and data at DIO.

CC1021

performs the decoding and NRZ data is presented at DIO. The data should be clocked into the interfacing circuit at the rising edge of DCLK. See Figure 10.

In synchronous NRZ or Manchester mode the DCLK signal runs continuously both in RX and TX unless the DCLK signal is gated with the carrier sense signal or the PLL lock signal. Refer to section 21 for more details.

CC1021

provides the data

CC1021

performs the

CC1021

provides the data

CC102

performs the

CC1021

at the

If SEP_DI_DO = 0 in the INTERFACE register, the DIO pin is the data output in receive mode and data input in transmit mode.

As an option, the data output can be made available at a separate pin. This is done by setting SEP_DI_DO = 1 in the INTERFACE register. Then, the LOCK pin will be used as data output in synchronous mode, overriding other use of the LOCK pin.

Transparent Asynchronous UART mode

In transmit mode DIO is used as data input. The data is modulated at RF without synchronization or encoding.

In receive mode the raw data signal from the demodulator is sent to the output (DIO). No synchronization or decoding of

CC1021

the signal is done in done by the interfacing circuit.

If SEP_DI_DO = 0 in the INTERFACE register, the DIO pin is the data output in receive mode and data input in transmit mode. The DCLK pin is not active and can be set to a high or low level by DATA_FORMAT[0].

If SEP_DI_DO = 1 in the INTERFACE register, the DCLK pin is the data output in receive mode and the DIO pin is the data input in transmit mode. In TX mode the DCLK pin is not active and can be set to a high or low level by DATA_FORMAT[0]. See Figure 11.

Manchester encoding and decoding In the Synchronous Manchester encoded mode when modulating the data. The also performs the data decoding and synchronization. The Manchester code is based on transitions; a ì0î is encoded as a low-to-high transition, a ì1î is encoded as a high-to-low transition. See Figure 12.

The Manchester code ensures that the signal has a constant DC component, which is necessary in some FSK demodulators. Using this mode also

CC1021

uses Manchester coding

and should be

CC1021

SWRS045 Page 25 of 91

CC1021

ensures compatibility with CC400/CC900 designs.

Transmitter side:

DCLK

DIO

ìRFî

Receiver side:

ìRFî

DCLK

DIO

Figure 9. Synchronous NRZ mode (SEP_DI_DO = 0)

Transmitter side:

Clock provided by CC1021

Data provided by microcontroller

FSK modulating signal (NRZ),

FSK modulating signal (NRZ), internal in CC1021

internal in CC1021

Demodulated signal (NRZ),

Demodulated signal (NRZ), internal in CC1021

internal in CC1021

Clock provided by CC1021

Data provided by CC1021

DCLK

DIO

ìRFî

Receiver side:

ìRFî

DCLK

DIO

Figure 10. Synchronous Manchester encoded mode (SEP_DI_DO = 0)

Clock provided by CC1021

Data provided by microcontroller

FSK modulating signal (Manchester

FSK modulating signal (Manchester encoded), internal in CC1021

encoded), internal in CC1021

Demodulated signal (Manchester

Demodulated signal (Manchester encoded), internal in CC1021

encoded), internal in CC1021

Clock provided by CC1021

Data provided by CC1021

SWRS045 Page 26 of 91

Transmitter side:

DCLK

DIO

ìRFî

Receiver side:

ìRFî

DCLK

DIO

Figure 11. Transparent Asynchronous UART mode (SEP_DI_DO = 1)

Tx

Tx data

data

CC1021

DCLK is not used in transmit mode, and is

DCLK is not used in transmit mode, and is used as data output in receive mode. It can be

used as data output in receive mode. It can be set to default high or low in transmit mode.

set to default high or low in transmit mode.

Data provided by UART (TXD)

FSK modulating signal,

FSK modulating signal, internal in CC1021

internal in CC1021

Demodulated signal (NRZ),

Demodulated signal (NRZ), internal in CC1021

internal in CC1021

DCLK is used as data output

DCLK is used as data output provided by CC1021.

provided by CC1021. Connect to UART (RXD)

Connect to UART (RXD)

DIO is not used in receive mode. Used only

DIO is not used in receive mode. Used only as data input in transmit mode

as data input in transmit mode

1 0 1 1 0 0 0 1 1 0 1

Figure 12. Manchester encoding

10. Data Rate Programming

The data rate (baud rate) is programmable and depends on the crystal frequency and the programming of the CLOCK (CLOCK_A and CLOCK_B) registers.

The baud rate (B.R) is given by

f

..

RB

=

xosc

⋅⋅+⋅

where DIV1 and DIV2 are given by the value of MCLK_DIV1 and MCLK_DIV2.

Table 17 below shows some possible data rates as a function of crystal frequency in synchronous mode. In asynchronous transparent UART mode any data rate up to 153.6 kBaud can be used.

21)1_(8

DIVDIVDIVREF

Time

MCLK_DIV2[1:0] DIV2

00 1 01 2 10 4 11 8

Table 15. DIV2 for different settings of

MCLK_DIV2

MCLK_DIV1[2:0] DIV1

000 2.5 001 3 010 4 011 7.5 100 12.5 101 40 110 48 111 64

Table 16. DIV1 for different settings of

MCLK_DIV1

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[kBaud]

0.45 X X

0.5 X

0.6 X X X X X X X

0.9 X X 1 X

1.2 X X X X X X X

1.8 X X 2 X

2.4 X X X X X X X

3.6 X X 4 X

4.096 X X

4.8 X X X X X X X

7.2 X X 8 X

8.192 X X

9.6 X X X X X X X

14.4 X X 16 X

16.384 X X

19.2 X X X X X X X

28.8 X X 32 X

32.768 X X

38.4 X X X X X X X

57.6 X X 64 X

65.536 X

76.8 X X X X X X X

115.2 X X 128 X

153.6 X X X X X

4.9152 7.3728 9.8304 12.288 14.7456 17.2032 19.6608

Table 17. Some possible data rates versus crystal frequency

11. Frequency Programming

Programming the frequency word in the configuration registers sets the operation frequency. There are two frequency words registers, termed FREQ_A and FREQ_B, which can be programmed to two different frequencies. One of the frequency words can be used for RX (local oscillator frequency) and the other for TX (transmitting carrier frequency) in order to be able to switch very fast between RX mode and TX mode. They can also be used for RX (or TX) at two different channels. The F_REG bit in the MAIN register selects frequency word A or B.

The frequency word is located in

FREQ_2A:FREQ_1A:FREQ_0A and FREQ_2B:FREQ_1B:FREQ_0B for the FREQ_A and FREQ_B word respectively.

The LSB of the FREQ_0 registers are used to enable dithering, section 11.1.

Crystal frequency [MHz] Data rate

The PLL output frequency is given by:

5.0

3



ff

+⋅=



refc

4



⋅+

32768

in the frequency band 402 ñ 470 MHz, and

5.0

3



ff

+⋅=



refc

2



⋅+

16384

in the frequency band 804 ñ 940 MHz.

The BANDSELECT bit in the ANALOG register controls the frequency band used. BANDSELECT = 0 gives 402 - 470 MHz, and BANDSELECT = 1 gives 804 - 940 MHz.

The reference frequency is the crystal oscillator clock frequency divided by REF_DIV (3 bits in the CLOCK_A or

DITHERFREQ

 



 



SWRS045 Page 28 of 91

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CLOCK_B register), a number between 1 and 7:

f

=

ref

xosc

DIVREF

FSK frequency deviation is programmed in the DEVIATION register. The deviation programming is divided into a mantissa (TXDEV_M[3:0]) and an exponent (TXDEV_X[2:0]).

Generally REF_DIV should be as low as possible but the following requirements must be met

8304.9 >≥

f

ref

256

in the frequency band 402 ñ 470 MHz, and

8304.9 >≥

f

ref

512

in the frequency band 804 - 940 MHz.

The PLL output frequency equations above give the carrier frequency, f transmit mode (centre frequency). The two FSK modulation frequencies are given by:

11.1. Dithering

Spurious signals will occur at certain frequencies depending on the division ratios in the PLL. To reduce the strength of these spurs, a common technique is to use a dithering signal in the control of the

1_ +

f

c

f

c

[]

MHz

[]

MHz

, in

c

= fc  f

f

0

f1 = fc + f

where f

is set by the DEVIATION

dev

register:

refdev

in the frequency band 402 ñ 470 MHz and

refdev

in the frequency band 804 - 940 MHz.

OOK (On-Off Keying) is used if TXDEV_M[3:0] = 0000.

The TX_SHAPING bit in the DEVIATION register controls Gaussian shaping of the modulation signal.

In receive mode the frequency must be programmed to be the LO frequency. Low side LO injection is used, hence:

f

LO

where f

is the IF frequency (ideally 307.2

IF

kHz).

frequency dividers. Dithering is activated by setting the DITHER bit in the FREQ_0 registers. It is recommended to use the dithering in order to achieve the best possible performance.

dev

MTXDEVff

= fc  fIF

)16_(

XTXDEV

2_−⋅⋅=

)15_(

XTXDEV

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12. Receiver

12.1. IF Frequency

The IF frequency is derived from the crystal frequency as

f

=

f

IF

where ADC_DIV[2:0] is set in the MODEM register.

The analog filter succeeding the mixer is used for wideband and anti-alias filtering which is important for the blocking performance at 1 MHz and larger offsets. This filter is fixed and centered on the nominal IF frequency of 307.2 kHz. The bandwidth of the analog filter is about 160 kHz.

Using crystal frequencies which gives an IF frequency within 300 ñ 320 kHz means that the analog filter can be used (assuming low frequency deviations and low data rates).

xoscx

[]

DIVADC

)10:2_(8 +⋅

12.2. Receiver Channel Filter Bandwidth

In order to meet different channel spacing requirements, the receiver channel filter bandwidth is programmable. It can be programmed from 38.4 to 307.2 kHz.

The minimum receiver channel filter bandwidth depends on data rate, frequency separation and crystal tolerance.

The signal bandwidth must be smaller than the available receiver channel filter bandwidth. The signal bandwidth (SBW) can be approximated by (Carsonís rule):

SBW = 2

where fm is the modulating signal. In Manchester mode the maximum modulating signal occurs when transmitting a continuous sequence of 0ís (or 1ís). In NRZ mode the maximum modulating signal occurs when

·

fm + 2 · frequency deviation

Large offsets, however, from the nominal IF frequency will give an un-symmetric filtering (variation in group delay and different attenuation) of the signal, resulting in decreased sensitivity and selectivity. See Application Note AN022 Crystal Frequency Selection for more details.

For IF frequencies other than 300 ñ 320 kHz and for high frequency deviation and high data rates (typically analog filter must be bypassed by setting FILTER_BYPASS = 1 in the FILTER register. In this case the blocking performance at 1 MHz and larger offsets will be degraded.

The IF frequency is always the ADC clock frequency divided by 4. The ADC clock frequency should therefore be as close to

1.2288 MHz as possible.

transmitting a 0-1-0 sequence. In both Manchester and NRZ mode 2 equal to the programmed baud rate. The equation for SBW can then be rewritten as

Furthermore, the frequency offset of the transmitter and receiver must also be considered. Assuming equal frequency error in the transmitter and receiver (same type of crystal) the total frequency error is:

where XTAL_ppm is the total accuracy of the crystal including initial tolerance, temperature drift, loading and ageing. f_RF is the RF operating frequency.

The minimum receiver channel filter bandwidth (ChBW) can then be estimated as

≥

76.8 kBaud) the

·

fm is then

SBW = Baud rate + frequency separation

f_error = ±2

·

XTAL_ppm · f_RF

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ChBW > SBW + 2 · f_error

The DEC_DIV[2:0] bits in the FILTER register control the receiver channel filter bandwidth. The 6 dB bandwidth is given by:

ChBW = 307.2 / (DEC_DIV + 1) [kHz]

where the IF frequency is set to 307.2 kHz. Table 18 shows the available channel filter bandwidths.

There is a tradeoff between selectivity as well as sensitivity and accepted frequency tolerance. In applications where larger

12.3. Demodulator, Bit Synchronizer and Data Decision

The block diagram for the demodulator, data slicer and bit synchronizer is shown in Figure 13. The built-in bit synchronizer synchronizes the internal clock to the incoming data and performs data decoding. The data decision is done using over-sampling and digital filtering of the incoming signal. This improves the reliability of the data transmission. Using the synchronous modes simplifies the data-decoding task substantially.

The recommended preamble is a ë010101Ö í bit pattern. The same bit pattern should also be used in Manchester mode, giving a ë011001100110Ö ëchipí pattern. This is necessary for the bit synchronizer to synchronize to the coding correctly.

The data slicer does the bit decision. Ideally the two received FSK frequencies are placed symmetrically around the IF frequency. However, if there is some frequency error between the transmitter and the receiver, the bit decision level should be adjusted accordingly. In this is done automatically by measuring the two frequencies and use the average value as the decision level.

The digital data slicer in

CC1021

average value of the minimum and maximum frequency deviation detected as the comparison level. The RXDEV_X[1:0] and RXDEV_M[3:0] in the AFC_CONTROL register are used to set

CC1021

uses an

frequency drift is expected, the filter bandwidth can be increased, but with reduced adjacent channel rejection (ACR) and sensitivity.

Filter bandwidth

[kHz]

38.4 7 (111b)

43.9 6 (110b)

51.2 5 (101b)

61.4 4 (100b)

76.8 3 (011b)

102.4 2 (010b)

153.6 1 (001b)

307.2 0 (000b)

Table 18. Channel filter bandwidth

the expected deviation of the incoming signal. Once a shift in the received frequency larger than the expected deviation is detected, a bit transition is recorded and the average value to be used by the data slicer is calculated.

The minimum number of transitions required to calculate a slicing level is 3. That is, a 010 bit pattern (NRZ).

The actual number of bits used for the averaging can be increased for better data decision accuracy. This is controlled by the SETTLING[1:0] bits in the AFC_CONTROL register. If RX data is present in the channel when the RX chain is turned on, then the data slicing estimate will usually give correct results after 3 bit transitions. The data slicing accuracy will increase after this, depending on the SETTLING[1:0] bits. If the start of transmission occurs after the RX chain has turned on, the minimum number of bit transitions (or preamble bits) before correct data slicing will depend on the SETTLING[1:0] bits.

The automatic data slicer average value function can be disabled by setting SETTLING[1:0] = 00. In this case a symmetrical signal around the IF frequency is assumed.

The internally calculated average FSK frequency value gives a measure for the frequency offset of the receiver compared

FILTER.DEC_DIV[2:0]

[decimal(binary)]

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to the transmitter. This information can also be used for an automatic frequency

control (AFC) as described in section

12.13.

Average

filter

Bit

synchronizer

and data

decoder

Digital filtering

Frequency

detector

Decimator

Data filter

Data slicer

comparator

Figure 13. Demodulator block diagram

12.4. Receiver Sensitivity versus Data Rate and Frequency Separation

The receiver sensitivity depends on the channel filter bandwidth, data rate, data format, FSK frequency separation and the RF frequency. Typical figures for the receiver sensitivity (BER = 10

3

) are shown in Table 19 and Table 20 for FSK. For best performance, the frequency deviation should be at least half the baud rate in FSK mode.

Data rate

[kBaud]

4.8

19.2

38.4

76.8

153.6

Table 19. Typical receiver sensitivity as a function of data rate at 433 MHz, FSK

modulation, BER = 10

Deviation

[kHz]

± 4.95

± 9.9 ± 19.8 ± 19.8 ± 36.0 ± 72.0

Filter BW

3

, pseudo-random data (PN9 sequence).

Data rate

[kBaud]

4.8

19.2

38.4

76.8

153.6

Table 20. Typical receiver sensitivity as a function of data rate at 868 MHz, FSK

modulation, BER = 10

Deviation

[kHz]

± 4.95

± 9.9 ± 19.8 ± 19.8 ± 36.0 ± 72.0

Filter BW

3

, pseudo-random data (PN9 sequence).

The sensitivity is measured using the matching network shown in the application circuit in Figure 3, which includes an external T/R switch.

Refer to Application Note AN029 CC1020/1021 AFC for plots of sensitivity versus frequency offset.

NRZ

mode

NRZ

mode

Sensitivity [dBm]

Manchester

mode

Sensitivity [dBm]

Manchester

mode

UART mode

[kHz]

38.4 -109 -112 -109

51.2 -107 -108 -107

102.4 -104 -106 -104

102.4 -104 -104 -104

153.6 -101 -101 -101

307.2 -96 -97 -96

[kHz]

38.4 -108 -111 -108

51.2 -107 -107 -107

102.4 -103 -106 -103

102.4 -103 -103 -103

153.6 -99 -100 -99

307.2 -94 -94 -94

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12.5. RSSI

CC1021

has a built-in RSSI (Received Signal Strength Indicator) giving a digital value that can be read form the RSSI register. The RSSI reading must be offset and adjusted for VGA gain setting (VGA_SETTING[4:0] in the VGA3 register).

The digital RSSI value is ranging from 0 to 106 (7 bits).

The RSSI reading is a logarithmic measure of the average voltage amplitude after the digital filter in the digital part of the IF chain:

RSSI = 4 log

The relative power is then given by RSSI x

1.5 dB in a logarithmic scale.

The number of samples used to calculate the average signal amplitude is controlled by AGC_AVG[1:0] in the VGA2 register. The RSSI update rate is given by:

where AGC_AVG[1:0] is set in the VGA2 register and

Maximum VGA gain is programmed by the VGA_SETTING[4:0] bits. The VGA gain is programmed in approximately 3 dB/LSB. The RSSI measurement can be referred to the power (absolute value) at the RF_IN pin by using the following equation:

(signal amplitude)

2

f

=

f

RSSI

2

clockfilter

_

clockfilter

[]

10:1_

+

AVGAGC

.

ChBWf

⋅= 2

P = 1.5

·

RSSI - 3·VGA_SETTING RSSI_Offset [dBm]

The RSSI_Offset depends on the channel filter bandwidth used due to different VGA settings. Figure 14 and Figure 15 show typical plots of RSSI reading as a function of input power for different channel filter bandwidths. Refer to Application Note AN030 CC1020/1021 RSSI for further details.

The following method can be used to calculate the power P in dBm from the RSSI readout values in Figure 14 and Figure 15:

P = 1.5

where P is the output power in dBm for the current RSSI readout value. RSSI_ref is the RSSI readout value taken from Figure 14 or Figure 15 for an input power level of P_ref. Note that the RSSI readings in decimal value changes for different channel filter bandwidths.

The analog filter has a finite dynamic range and is the reason why the RSSI reading is saturated at lower channel filter bandwidths. Higher channel filter bandwidths are typically used for high frequency deviation and data rates. The analog filter bandwidth is about 160 kHz and is bypassed for high frequency deviation and data rates and is the reason why the RSSI reading is not saturated for

153.6 kHz and 307.2 kHz channel filter bandwidths in Figure 14 and Figure 15.

·

[RSSI ñ RSSI_ref] + P_ref

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80

70

60

50

40

30

20

RSSI readout value [decimal]

10

0

-125 -115 -105 -95 -85 -75 -65 -55 -45 -35 -25

Input power level [dBm]

38.4 kHz 51.2 kHz 102.4 kHz 153.6 kHz 307.2 kHz

Figure 14. Typical RSSI value vs. input power for different channel filter bandwidths, 433

MHz

80

70

60

50

40

30

20

RSSI readout value [decimal]

10

0

-125 -115 -105 -95 -85 -75 -65 -55 -45 -35 -25

Input power level [dBm]

38.4 kHz 51.2 kHz 102.4 kHz 153.6 kHz 307.2 kHz

Figure 15. Typical RSSI value vs. input power for different channel filter bandwidths, 868

MHz

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12.6. Image Rejection Calibration

For perfect image rejection, the phase and gain of the ìIî and ìQî parts of the analog RX chain must be perfectly matched. To improve the image rejection, the ìIî and ìQî phase and gain difference can be finetuned by adjusting the PHASE_COMP and GAIN_COMP registers. This allows compensation for process variations and other nonidealities. The calibration is done by injecting a signal at the image frequency, and adjusting the phase and gain difference for minimum RSSI value.

During image rejection calibration, an unmodulated carrier should be applied at the image frequency (614.4 kHz below the desired channel), No signal should be present in the desired channel. The signal level should be 50 - 60 dB above the sensitivity in the desired channel, but the optimum level will vary from application to application. Too large input level gives poor results due to limited linearity in the analog IF chain, while too low input level gives poor results due to the receiver noise floor.

For best RSSI accuracy, use AGC_AVG(1:0] = 11 during image rejection calibration (RSSI value is averaged over 16 filter output samples). The RSSI register update rate then equals the receiver channel bandwidth (set in FILTER register) divided by 8, as the filter output rate is twice the receiver channel bandwidth. This gives the minimum waiting time between RSSI register reads (0.5 ms is used below). Chipcon recommends the following image calibration procedure:

1. Define 3 variables: XP = 0, XG = 0 and DX = 64.

Go to step 3.

2. Set DX = DX/2.

3. Write XG to GAIN_COMP register.

4. If XP+2∑DX < 127 then

write XP+2∑DX to PHASE_COMP register else write 127 to PHASE_COMP register.

5. Wait at least 3 ms. Measure signal strength Y4

as filtered average of 8 reads from RSSI register with 0.5 ms of delay between each RSSI read.

6. Write XP+DX to PHASE_COMP register.

7. Wait at least 3 ms. Measure signal strength Y3

as filtered average of 8 reads from RSSI register with 0.5 ms of delay between each RSSI read.

8. Write XP to PHASE_COMP register.

9. Wait at least 3 ms. Measure signal strength Y2 as filtered average of 8 reads from RSSI register with 0.5 ms of delay between each RSSI read.

10. Write XP-DX to PHASE_COMP register.

11. Wait at least 3 ms. Measure signal strength Y1 as filtered average of 8 reads from RSSI register with 0.5 ms of delay between each RSSI read.

12. Write XP-2∑DX to PHASE_COMP register.

13. Wait at least 3 ms. Measure signal strength Y0 as filtered average of 8 reads from RSSI register with 0.5 ms of delay between each RSSI read.

14. Set AP = 2∑(Y0-Y2+Y4) - (Y1+Y3).

15. If AP > 0 then set DP = ROUND( 7∑DX∑(2∑(Y0-Y4)+Y1- Y3) / (10∑AP) ) else if Y0+Y1 > Y3+Y4 then set DP = DX else set DP = -DX.

16. If DP > DX then set DP = DX else if DP < -DX then set DP = -DX.

17. Set XP = XP+DP.

18. Write XP to PHASE_COMP register.

19. If XG+2∑DX < 127 then write XG+2∑DX to GAIN_COMP register else write 127 to GAIN_COMP register.

20. Wait at least 3 ms. Measure signal strength Y4 as filtered average of 8 reads from RSSI register with 0.5 ms of delay between each RSSI read.

21. Write XG+DX to GAIN_COMP register.

22. Wait at least 3 ms. Measure signal strength Y3 as filtered average of 8 reads from RSSI register with 0.5 ms of delay between each RSSI read.

23. Write XG to GAIN_COMP register.

24. Wait at least 3 ms. Measure signal strength Y2 as filtered average of 8 reads from RSSI register with 0.5 ms of delay between each RSSI read.

25. Write XG-DX to GAIN_COMP register.

26. Wait at least 3 ms. Measure signal strength Y1 as filtered average of 8 reads from RSSI register with 0.5 ms of delay between each RSSI read.

27. Write XG-2∑DX to GAIN_COMP register.

28. Wait at least 3 ms. Measure signal strength Y0 as filtered average of 8 reads from RSSI register with 0.5 ms of delay between each RSSI read.

29. Set AG = 2∑(Y0-Y2+Y4) - (Y1+Y3).

30. If AG > 0 then set DG = ROUND( 7∑DX∑(2∑(Y0-Y4)+Y1- Y3) / (10∑AG) ) else if Y0+Y1 > Y3+Y4 then set DG = DX else set DG = -DX.

31. If DG > DX then set DG = DX else if DG < -DX then set DG = -DX.

32. Set XG = XG+DG.

33. If DX > 1 then go to step 2.

34. Write XP to PHASE_COMP register and

XG to GAIN_COMP register.

If repeated calibration gives varying results, try to change the input level or

SWRS045 Page 35 of 91

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increase the number of RSSI reads N. A good starting point is N=8. As accuracy is more important in the last fine-calibration steps, it can be worthwhile to increase N for each loop iteration.

For high frequency deviation and high data rates (typically

≥

76.8 kBaud) the analog

filter succeeding the mixer must be

12.7. Blocking and Selectivity

Figure 16 shows the blocking/selectivity for 102.4 kHz channel filter bandwidth at 433 MHz and 19.2 kBaud data rate. Figure 17 shows the blocking/selectivity for 102.4 kHz channel filter bandwidth at 433 MHz and 38.4 kBaud data rate. Figure 18 shows the blocking/selectivity for 102.4 kHz channel filter bandwidth at 868 MHz

65

60

55

50

45

40

35

30

25

20

Blocker rejection [dB]

15

10

5

0

-5

-10

-15

-1000 -900 -800 -7 00 -600 -500 -400 -300 -200 -100 0 100 200 300 400 500 600 700 800 900 1000

Figure 16. Typical blocker rejection. Carrier frequency set to 434.3072 MHz (102.4 kHz

channel filter bandwidth, 19.2 kBaud)

Blocker fre quency offset [kHz]

Not image c alibrated Image calibrated

bypassed by setting FILTER_BYPASS = 1 in the FILTER register. In this case the image rejection is degraded.

The image rejection is reduced for low supply voltages (typically <2.5 V) when operating in the 402 ñ 470 MHz frequency range.

and 19.2 kBaud data rate. Figure 19 shows the blocking/selectivity for 102.4 kHz channel filter bandwidth at 868 MHz and 38.4 kBaud data rate. The blocking rejection is the ratio between a blocker (interferer) and a wanted signal 3 dB above the sensitivity limit.

SWRS045 Page 36 of 91

CC1021

65

60

55

50

45

40

35

30

25

20

Blocker rej ection [dB]

15

10

5

0

-5

-10

-15

-1000 -900 -800 -700 -600 -500 -400 -300 -200 -100 0 10 0 200 300 4 00 500 600 700 800 900 1000

Figure 17. Typical blocker rejection. Carrier frequency set to 434.3072 MHz (102.4 kHz

channel filter bandwidth, 38.4 kBaud)

65

60

55

50

45

40

35

30

25

20

Blocker rejection [dB ]

15

10

5

0

-5

-10

-15

-1000 -900 -800 -700 -600 -50 0 -400 -300 -200 -100 0 1 00 200 300 400 500 600 700 800 900 1000

Figure 18. Typical blocker rejection. Carrier frequency set to 868.3072 MHz (102.4 kHz

channel filter bandwidth, 19.2 kBaud)

Blocker fre quency offset [kHz]

Not image c alibrated Image calibrated

Blocker frequency offset [kHz]

Not image calibrated Image ca librated

SWRS045 Page 37 of 91

CC1021

65

60

55

50

45

40

35

30

25

20

Blocker rejection [dB]

15

10

5

0

-5

-10

-15

-1000 -900 -800 -700 -600 -50 0 -400 -300 -200 -100 0 1 00 200 300 400 500 600 700 800 900 1000

Figure 19. Typical blocker rejection. Carrier frequency set to 868.3072 MHz (102.4 kHz

channel filter bandwidth, 38.4 kBaud)

12.8. Linear IF Chain and AGC Settings

CC1021

is based on a linear IF chain where the signal amplification is done in an analog VGA (Variable Gain Amplifier). The gain is controlled by the digital part of the IF chain after the ADC (Analog to Digital Converter). The AGC (Automatic Gain Control) loop ensures that the ADC operates inside its dynamic range by using an analog/digital feedback loop.

The maximum VGA gain is programmed by the VGA_SETTING[4:0] in the VGA3 register. The VGA gain is programmed in approximately 3 dB/LSB. The VGA gain should be set so that the amplified thermal noise from the front-end balance the quantization noise from the ADC. Therefore the optimum maximum VGA gain setting will depend on the channel filter bandwidth.

A digital RSSI is used to measure the signal strength after the ADC. The CS_LEVEL[4:0] in the VGA4 register is used to set the nominal operating point of the gain control (and also the carrier sense level). Further explanation can be found in Figure 20.

Blocker frequency offset [kHz]

Not image calibrated Image ca librated

The VGA gain will be changed according to a threshold set by the VGA_DOWN[2:0] in the VGA3 register and the VGA_UP[2:0] in the VGA4 register. Together, these two values specify the signal strength limits used by the AGC to adjust the VGA gain.

To avoid unnecessary tripping of the VGA, an extra hysteresis and filtering of the RSSI samples can be added. The AGC_HYSTERESIS bit in the VGA2 register enables this.

The time dynamics of the loop can be altered by the VGA_BLANKING bit in the ANALOG register, and VGA_FREEZE[1:0] and VGA_WAIT[2:0] bits in the VGA1 register.

When VGA_BLANKING is activated, the VGA recovery time from DC offset spikes after a gain step is reduced.

VGA_FREEZE determines the time to hold bit synchronization, VGA and RSSI levels after one of these events occur:

• RX power-up

• The PLL has been out of lock

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• Frequency register setting is switched

between A and B

This feature is useful to avoid AGC operation during start-up transients and to ensure minimum dwell time using frequency hopping. This means that bit synchronization can be maintained from hop to hop.

VGA_WAIT determines the time to hold the present bit synchronization and RSSI levels after changing VGA gain. This feature is useful to avoid AGC operation during the settling of transients after a VGA gain change. Some transients are expected due to DC offsets in the VGA.

At the sensitivity limit, the VGA gain is set by VGA_SETTING. In order to optimize selectivity, this gain should not be set higher than necessary. The SmartRF Studio software gives the settings for VGA1 ñ VGA4 registers. For reference, the following method can be used to find the AGC settings:



1. Disable AGC and use maximum LNA2 gain by writing BFh to the VGA2 register. Set minimum VGA gain by writing to the VGA3 register with VGA_SETTING = 0.

2. Apply no RF input signal, and measure ADC noise floor by reading the RSSI register.

3. Apply no RF input signal, and write VGA3 register with increasing VGA_SETTING value until the RSSI register value is approximately 4 larger than the value read in step 2. This places the front-end noise floor around 6 dB above the ADC noise floor.

4. Apply an RF signal with strength equal the desired carrier sense threshold. The RF signal should preferably be modulated with correct Baud rate and deviation. Read the RSSI register value, subtract 8, and write to CS_LEVEL in the VGA4 register. Vary the RF signal level slightly and check that carrier sense indication (bit 3 in STATUS register) switches at the desired input level.

5. If desired, adjust the VGA_UP and VGA_DOWN settings according to the explanation in Figure 20.

6. Enable AGC and select LNA2 gain change level. Write 55h to VGA2 register if the resulting VGA_SETTING>10. Otherwise, write 45h to VGA2. Modify AGC_AVG in the above VGA2 value if faster carrier sense and AGC settling is desired.

RSSI Level

Note that the AGC works with "raw" filter output signal strength, while the RSSI readout value is compensated for VGA gain changes by the AGC.

The AGC keeps the signal strength in this range. Minimize VGA_DOWN for best selectivity, but leave some margin to avoid frequent VGA gain changes during reception.

The AGC keeps the signal strength above carrier sense level + VGA_UP. Minimize VGA_UP for best selectivity, but increase if first VGA gain reduction occurs too close to the noise floor.

To set CS_LEVEL, subtract 8 from RSSI readout with RF input signal at desired carrier sense level.

Zero level depends on front-end settings and VGA_SETTING value.

Figure 20. Relationship between RSSI, carrier sense level, and AGC settings CS_LEVEL,

VGA_UP and VGA_DOWN

(signal strength, 1.5dB/step)

AGC decreases gain if above this level (unless at minimum).

VGA_DOWN+3

AGC increases gain if below this level (unless at maximum).

VGA_UP

Carrier sense is turned on here.

CS_LEVEL+8

0

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12.9. AGC Settling

After turning on the RX chain, the following occurs:

A) The AGC waits 16-128 ADC_CLK (1.2288 MHz) periods, depending on the VGA_FREEZE setting in the VGA1 register, for settling in the analog parts.

B) The AGC waits 16-48 FILTER_CLK periods, depending on the VGA_WAIT setting in the VGA1 register, for settling in the analog parts and the digital channel filter.

C) The AGC calculates the RSSI value as the average magnitude over the next 2-16 FILTER_CLK periods, depending of the AGC_AVG setting in the VGA2 register.

D) If the RSSI value is higher than CS_LEVEL+8, then the carrier sense indicator is set (if CS_SET = 0). If the RSSI value is too high according to the CS_LEVEL, VGA_UP and VGA_DOWN settings, and the VGA gain is not already

12.10. Preamble Length and Sync Word

The rules for choosing a good sync word are as follows:

1. The sync word should be significantly different from the preamble

2. A large number of transitions is good for the bit synchronization or clock recovery. Equal bits reduce the number of transitions. The recommended sync word has at the most 3 equal bits in a row.

3. Autocorrelation. The sync word should not repeat itself, as this will increase the likelihood for errors.

4. In general the first bit of sync should be opposite of last bit in preamble, to achieve one more transition.

The recommended sync words for are 2 bytes (D391), 3 bytes (D391DA) or 4 bytes (D391DA26) and are selected as the best compromise of the above criteria.

CC1021

at minimum, then the VGA gain is reduced and the AGC continues from B).

E) If the RSSI value is too low according to the CS_LEVEL and VGA_UP settings, and the VGA gain is not already at maximum (given by VGA_SETTING), then the VGA gain is increased and the AGC continues from B).

2-3 VGA gain changes should be expected before the AGC has settled. Increasing AGC_AVG increases the settling time, but may be worthwhile if there is the time in the protocol, and for reducing false wake-up events when setting the carrier sense close to the noise floor.

The AGC settling time depends on the FILTER_CLK (= 2 trade off between AGC settling time and

receiver sensitivity because the AGC settling time can be reduced for data rates lower than 76.8 kBaud by using a wider receiver channel filter bandwidth (i.e. larger ChBW).

Using the register settings provided by the SmartRF rates (PER) less than 0.5% can be achieved when using 24 bits of preamble and a 16 bit sync word (D391). Using a preamble longer than 24 bits will improve the PER.

When performing the PER measurements described above the packet format consisted of 10 bytes of random data, 2 bytes CRC and 1 dummy byte in addition to the sync word and preamble at the start of each package.

For the test 1000 packets were sent 10 times. The transmitter was put in power down between each packet. Any bit error in the packet, either in the sync word, in the data or in the CRC caused the packet to be counted as a failed packet.



Studio software, packet error

·

ChBW). Thus, there is a

SWRS045 Page 40 of 91

CC1021

12.11. Carrier Sense

The carrier sense signal is based on the RSSI value and a programmable threshold. The carrier sense function can be used to simplify the implementation of a CSMA (Carrier Sense Multiple Access) medium access protocol. Carrier sense threshold level is programmed by CS_LEVEL[4:0] in the VGA4 register and VGA_SETTING[4:0] in the VGA3 register.

VGA_SETTING[4:0] sets the maximum gain in the VGA. This value must be set so that the ADC works with optimum dynamic range for a certain channel filter bandwidth. The detected signal strength (after the ADC) will therefore depend on this setting.

12.12. Automatic Power-up Sequencing

CC1021

has a built-in automatic power-up

sequencing state machine. By setting the

CC1021

into this mode, the receiver can be powered-up automatically by a wake-up signal and will then check for a carrier signal (carrier sense). If carrier sense is not detected, it returns to power-down mode. A flow chart for automatic power-up sequencing is shown in Figure 21.

The automatic power-up sequencing mode is selected when PD_MODE[1:0] = 11 in the MAIN register. When the automatic power-up sequencing mode is selected, the functionality of the MAIN register is changed and used to control the sequencing.

By setting SEQ_PD = 1 in the MAIN

CC1021

register, mode. If SEQ_PSEL = 1 in the SEQUENCING register the automatic power-up sequence is initiated by a negative transition on the PSEL pin.

is set in power down

CS_LEVEL[4:0] sets the threshold for this specific VGA_SETTING[4:0] value. If the

VGA_SETTING[4:0] is changed, the CS_LEVEL[4:0] must be changed

accordingly to maintain the same absolute carrier sense threshold. See Figure 20 for an explanation of the relationship between RSSI, AGC and carrier sense settings.

The carrier sense signal can be read as the CARRIER_SENSE bit in the STATUS register.

The carrier sense signal can also be made available at the LOCK pin by setting LOCK_SELECT[3:0] = 0100 in the LOCK register.

If SEQ_PSEL = 0 in the SEQUENCING register, then the automatic power-up sequence is initiated by a negative transition on the DIO pin (as long as SEP_DI_DO = 1 in the INTERFACE register).

Sequence timing is controlled through

RX_WAIT[2:0] and CS_WAIT[3:0] in the SEQUENCING register.

VCO and PLL calibration can also be done automatically as a part of the sequence. This is controlled through SEQ_CAL[1:0] in the MAIN register. Calibration can be done every time, every 16 every 256 register description for details. A description of when to do, and how the VCO and PLL self-calibration is done, is given in section 15.2 on page 51.

th

sequence, or never. See the

th

sequence,

SWRS045 Page 41 of 91

CC1021

Turn on crystal oscillator/bias

Frequency synthesizer off

Receive chain off

Crystal oscillator and bias on

Turn on frequency synthesizer

Receive chain off

Sequencing wake-up event

(negative transition on

PSEL pin or DIO pin)

Power down

Crystal oscillator and bias off

Frequency synthesizer off

Receive chain off

Wait for PLL

lock or timeout,

127 filter clocks

PLL in lock

Optional waiting time before

turning on receive chain

Programmable:

32-256 ADC clocks

Crystal oscillator and bias on

Frequency synthesizer on

Turn on receive chain

Wait for

carrier sense or timeout

Programmable: 20-72

filter clocks

Carrier sense

Receive mode

Crystal oscillator and bias on

Frequency synthesizer on

Receive chain on

PLL timeout

(Positive transition on SEQ_PD in MAIN register)

Figure 21. Automatic power-up sequencing flow chart

Notes to Figure 21:

Filter clock (FILTER_CLK):

clockfilter

_

⋅= 2

ChBWf

where ChBW is defined on page 30.

12.13. Automatic Frequency Control

CC1021

has a built-in feature called AFC (Automatic Frequency Control) that can be used to compensate for frequency drift.

The average frequency offset of the received signal (from the nominal IF frequency) can be read in the AFC register. The signed (2ís-complement) 8bit value AFC[7:0] can be used to

Set

SEQ_ERROR

flag in STATUS

register

Carrier sense timeout

Sequencing power-down event

Optional calibration

Programmable: each time, once in 16, or once in 256

Receive chain off

ADC clock (ADC_CLK):

f

=

f

ADC

xoscx

[]

DIVADC

where ADC_DIV[2:0] is set in the MODEM register.

compensate for frequency offset between transmitter and receiver.

The frequency offset is given by:

·

∆F = AFC

Baud rate / 16

The receiver can be calibrated against the transmitter by changing the operating frequency according to the measured

)10:2_(2 +⋅

SWRS045 Page 42 of 91

CC1021

offset. The new frequency must be calculated and written to the FREQ register by the microcontroller. The AFC can be used for an FSK/GFSK signal, but not for OOK. Application Note AN029 CC1020/1021 AFC provides the procedure

12.14. Digital FM

It is possible to read back the instantaneous IF from the FM demodulator as a frequency offset from the nominal IF frequency. This digital value can be used to perform a pseudo analog FM demodulation.

The frequency offset can be read from the GAUSS_FILTER register and is a signed 8-bit value coded as 2-complement.

The instantaneous deviation is given by:

F = GAUSS_FILTER

The digital value should be read from the register and sent to a DAC and filtered in order to get an analog audio signal. The internal register value is updated at the MODEM_CLK rate. MODEM_CLK is available at the LOCK pin when LOCK_SELECT[3:0] = 1101 in the LOCK register, and can be used to synchronize the reading.

For audio (300 ñ 4000 Hz) the sampling rate should be higher than or equal to 8

·

Baud rate / 8

and equations necessary to implement AFC.

The AFC feature reduces the crystal accuracy requirement.

kHz (Nyquist) and is determined by the MODEM_CLK. The MODEM_CLK, which is the sampling rate, equals 8 times the baud rate. That is, the minimum baud rate, which can be programmed, is 1 kBaud. However, the incoming data will be filtered in the digital domain and the 3-dB cut-off frequency is 0.6 times the programmed Baud rate. Thus, for audio the minimum programmed Baud rate should be approximately 7.2 kBaud.

The GAUSS_FILTER resolution decreases with increasing baud rate. A accumulate and dump filter can be implemented in the uC to improve the resolution. Note that each GAUSS_FILTER reading should be synchronized to the MODEM_CLK. As an example, accumulating 4 readings and dividing the total by 4 will improve the resolution by 2 bits.

Furthermore, to fully utilize the GAUSS_FILTER dynamic range the frequency deviation must be 16 times the programmed baud rate.

SWRS045 Page 43 of 91

CC1021

13. Transmitter

13.1. FSK Modulation Formats

The data modulator can modulate FSK, which is a two level FSK (Frequency Shift Keying), or GFSK, which is a Gaussian filtered FSK with BT = 0.5. The purpose of the GFSK is to make a more bandwidth efficient system. The modulation and the Gaussian filtering are done internally in the

chip. The TX_SHAPING bit in the DEVIATION register enables the GFSK.

Figure 22 shows a typical eye diagram for

153.6 kBaud data rate at 868 MHz operation.

Figure 22. GFSK eye diagram. 153.6 kBaud, NRZ, ±79.2 kHz frequency deviation.

13.2. Output Power Programming

The RF output power from the device is programmable by the 8-bit PA_POWER register. Figure 23 and Figure 24 shows the output power and total current consumption as a function of the PA_POWER register setting. It is more efficient in terms of current consumption to

use either the lower or upper 4-bits in the register to control the power, as shown in the figures. However, the output power can be controlled in finer steps using all the available bits in the PA_POWER register.

SWRS045 Page 44 of 91

CC1021

35.0

30.0

25.0

20.0

15.0

10.0

5.0

0.0

-5.0

-10.0

-15.0

Current [mA] / Output power [dBm ]

-20.0

-25.0 01234567890A0B0C0D0E0F5060708090A0B0C0D0E0F0FF

PA_POWER [hex]

Current Consumption Output Power

Figure 23. Typical output power and current consumption, 433 MHz

35.0

30.0

25.0

20.0

15.0

10.0

5.0

0.0

-5.0

-10.0

-15.0

Current [mA] / Output power [dBm]

-20.0

-25.0 01234567890A0B0C0D0E0F5060708090A0B0C0D0E0F0FF

Current Consumption Output Power

Figure 24. Typical output power and current consumption, 868 MHz

13.3. TX Data Latency

The transmitter will add a delay due to the synchronization of the data with DCLK and further clocking into the modulator. The user should therefore add a delay

PA_POWER [hex]

equivalent to at least 2 bits after the data payload has been transmitted before switching off the PA (i.e. before stopping the transmission).

SWRS045 Page 45 of 91

CC1021

13.4. Reducing Spurious Emission and Modulation Bandwidth

Modulation bandwidth and spurious emission are normally measured with the PA continuously on and a repeated test sequence.

In cases where the modulation bandwidth and spurious emission are measured with the

CC1021

switching from power down mode to TX mode, a PA ramping sequence could be used to minimize modulation bandwidth and spurious emission.

14. Input / Output Matching and Filtering

When designing the impedance matching

CC1021

network for the matched correctly at the harmonic frequencies as well as at the fundamental tone. A recommended matching network is shown in Figure 25. Component values for various frequencies are given in Table 21. Component values for other frequencies can be found using the SmartRF software.

As can be seen from Figure 25 and Table 21, the 433 MHz network utilizes a T-type filter, while the 868/915 MHz network has a π-type filter topology.

It is important to remember that the physical layout and the components used contribute significantly to the reflection coefficient, especially at the higher harmonics. For this reason, the frequency response of the matching network should

Item 433 MHz 868 MHz 915 MHz

C1 10 pF, 5%, NP0, 0402 47 pF, 5%, NP0, 0402 47 pF, 5%, NP0, 0402 C3 5.6 pF, 5%, NP0, 0402 10 pF, 5%, NP0, 0402 10 pF, 5%, NP0, 0402 C60 220 pF, 5%, NP0, 0402 220 pF, 5%, NP0, 0402 220 pF, 5%, NP0, 0402 C71 DNM 8.2 pF 5%, NP0, 0402 8.2 pF 5%, NP0, 0402 C72 4.7 pF, 5%, NP0, 0402 8.2 pF 5%, NP0, 0402 8.2 pF 5%, NP0, 0402 L1 33 nH, 5%, 0402 82 nH, 5%, 0402 82 nH, 5%, 0402 L2 22 nH, 5%, 0402 3.6 nH, 5%, 0402 3.6 nH, 5%, 0402 L70 47 nH, 5%, 0402 5.1 nH, 5%, 0402 5.1 nH, 5%, 0402 L71 39 nH, 5%, 0402 R10

Table 21. Component values for the matching network described in Figure 25. (DNM = Do

the circuit must be



Studio

82 Ω, 5%, 0402 82 Ω, 5%, 0402 82 Ω, 5%, 0402

0 Ω resistor, 0402 0 Ω resistor, 0402

Not Mount)

PA ramping should then be used both when switching the PA on and off. A linear PA ramping sequence can be used where register PA_POWER is changed from 00h to 0Fh and then from 50h to the register setting that gives the desired output power (e.g. F0h for +10 dBm output power at 433 MHz operation). The longer the time per PA ramping step the better, but setting the total PA ramping time equal to 2 bit periods is a good compromise between performance and PA ramping time.

be measured and compared to the response of the Chipcon reference design. Refer to Figure 27 and Table 22 as well as Figure 28 and Table 23.

The use of an external T/R switch reduces current consumption in TX for high output power levels and improves the sensitivity in RX. A recommended application circuit is available from the Chipcon web site (CC1020EMX). The external T/R switch can be omitted in certain applications, but performance will then be degraded.

The match can also be tuned by a shunt capacitor array at the PA output (RF_OUT). The capacitance can be set in

0.4 pF steps and used either in RX mode or TX mode. The RX_MATCH[3:0] and TX_MATCH[3:0] bits in the MATCH register control the capacitor array.

SWRS045 Page 46 of 91

CC1021

RF_OUT

RF_IN

CC1021

AVDD=3V

R10

L2

C60

L2

L70 L71

C3

C71 C72

C1

L1

C71 C72

L70 L71

Figure 25. Input/output matching network

T/R SWITCH

ANTENNA

Figure 26. Typical LNA input impedance, 200 ñ 1000 MHz

SWRS045 Page 47 of 91

CC1021

433 MHz

Figure 27. Typical optimum PA load impedance, 433 MHz. The frequency is swept from

300 MHz to 2500 MHz. Values are listed in Table 22

Frequency (MHz) Real (Ohms) Imaginary (Ohms)

433 54 44

866 20 173 1299 288 -563 1732 14 -123 2165 5 -66

Table 22. Impedances at the first 5 harmonics (433 MHz matching network)

SWRS045 Page 48 of 91

CC1021

868 MHz

Figure 28: Typical optimum PA load impedance, 868/915 MHz. The frequency is swept

from 300 MHz to 2800 MHz. Values are listed in Table 23

Frequency (MHz) Real (Ohms) Imaginary (Ohms)

868 15 24

915 20 35 1736 1.5 18 1830 1.7 22 2604 3.2 44 2745 3.6 45

Table 23. Impedances at the first 3 harmonics (868/915 MHz matching network)

SWRS045 Page 49 of 91

CC1021

15. Frequency Synthesizer

15.1. VCO, Charge Pump and PLL Loop Filter

The VCO is completely integrated and operates in the 1608 ñ 1880 MHz range. A frequency divider is used to get a frequency in the UHF range (402 ñ 470 and 804 ñ 940 MHz). The BANDSELECT bit in the ANALOG register selects the frequency band.

The VCO frequency is given by:

⋅+



ff

+⋅=



refVCO



5.03DITHERFREQ

8192

 



The VCO frequency is divided by 2 and by 4 to generate frequencies in the two bands, respectively.

The VCO sensitivity (sometimes referred to as VCO gain) varies over frequency and operating conditions. Typically the VCO sensitivity varies between 12 and 36 MHz/V. For calculations the geometrical mean at 21 MHz/V can be used. The PLL calibration (explained below) measures the actual VCO sensitivity and adjusts the charge pump current accordingly to achieve correct PLL loop gain and bandwidth (higher charge pump current when VCO sensitivity is lower).

The following equations can be used for calculating PLL loop filter component values, see Figure 3, for a desired PLL loop bandwidth, BW:

C7 = 3037 (f R2 = 7126 (BW / f C6 = 80.75 (f R3 = 21823 (BW / f C8 = 839 (f

/ BW2) ñ7 [pF]

ref

) [kΩ]

ref

/ BW2) [nF]

ref

) [kΩ]

ref

/ BW2) ñ6 [pF]

Define a minimum PLL loop bandwidth as BW

= 22075.80

min

f⋅ . If BW

ref

min

>

Baud rate/3 then set BW = BW BW

< Baud rate/3 then set BW = Baud

min

rate/3 in the above equations.

There is one special case when using the recommended 14.7456 MHz crystal:

If the data rate is 4.8 kBaud or below the following loop filter components are recommended:

C6 = 100 nF C7 = 3900 pF C8 = 1000 pF R2 = 2.2 k R3 = 6.8 k

After calibration the PLL bandwidth is set by the PLL_BW register in combination with the external loop filter components calculated above. The PLL_BW can be found from

PLL_BW = 174 + 16 log

where f MHz). The PLL loop filter bandwidth increases with increasing PLL_BW setting.

After calibration the applied charge pump current (CHP_CURRENT[3:0]) can be read in the STATUS1 register. The charge pump current is approximately given by:

The combined charge pump and phase detector gain (in A/rad) is given by the charge pump current divided by 2π.

The PLL bandwidth will limit the maximum modulation frequency and hence data rate.

and if

min

Ω Ω

/7.126)

2(fref

is the reference frequency (in

ref

CHP

CURRENTCHP

216 ⋅=

4_

[]

uAI

SWRS045 Page 50 of 91

CC1021

15.2. VCO and PLL Self-Calibration

To compensate for supply voltage, temperature and process variations, the VCO and PLL must be calibrated. The calibration is performed automatically and sets the maximum VCO tuning range and optimum charge pump current for PLL stability. After setting up the device at the operating frequency, the self-calibration can be initiated by setting the CAL_START bit in the CALIBRATE register. The calibration result is stored internally in the chip, and is valid as long as power is not turned off. If large supply voltage drops (typically more than 0.25 V) or temperature variations (typically more than 40 calibration should be performed.

The nominal VCO control voltage is set by the CAL_ITERATE[2:0] bits in the CALIBRATE register.

The CAL_COMPLETE bit in the STATUS register indicates that calibration has finished. The calibration wait time (CAL_WAIT) is programmable and is proportional to the internal PLL reference frequency. The highest possible reference frequency should be used to get the minimum calibration time. It is recommended to use CAL_WAIT[1:0] = 11 in order to get the most accurate loop bandwidth.

The CAL_COMPLETE bit can also be monitored at the LOCK pin, configured by LOCK_SELECT[3:0] = 0101, and used as an interrupt input to the microcontroller.

o

C) occur after calibration, a new

Calibration

time [ms]

CAL_WAIT 1.8432 7.3728 9.8304

00 49 ms 12 ms 10 ms 01 60 ms 15 ms 11 ms 10 71 ms 18 ms 13 ms 11 109 ms 27 ms 20 ms

Reference frequency [MHz]

Table 24. Typical calibration times

To check that the PLL is in lock the user should monitor the LOCK_CONTINUOUS bit in the STATUS register. The LOCK_CONTINUOUS bit can also be monitored at the LOCK pin, configured by LOCK_SELECT[3:0] = 0010.

There are separate calibration values for the two frequency registers. However, dual calibration is possible if all of the below conditions apply:

• The two frequencies A and B differ by less than 1 MHz

• Reference frequencies are equal (REF_DIV_A[2:0] = REF_DIV_B[2:0] in the CLOCK_A/CLOCK_B registers)

• VCO currents are equal (VCO_CURRENT_A[3:0] = VCO_CURRENT_B[3:0] in the VCO register).

The CAL_DUAL bit in the CALIBRATE register controls dual or separate calibration.

The single calibration algorithm (CAL_DUAL=0) using separate calibration for RX and TX frequency is illustrated in Figure 29. The same algorithm is applicable for dual calibration if CAL_DUAL=1. Application Note AN023 CC1020 MCU Interfacing, available from the Chipcon web site, includes example source code for single calibration.

Chipcon recommends that single calibration be used for more robust operation.

There is a finite possibility that the PLL self-calibration will fail. The calibration routine in the source code should include a loop so that the PLL is re-calibrated until PLL lock is achieved if the PLL does not lock the first time. Refer to Note 002.

CC1021

Errata

SWRS045 Page 51 of 91

f

is the reference frequency (in

f

is the reference frequency (in

ref

MHz)

Calibrate RX frequency register A

(to calibrate TX frequency register

(to calibrate TX frequency register B write MAIN register = D1h).

B write MAIN register = D1h). Register CALIBRATE = 34h

Register CALIBRATE = 34h

Start calibration

CC1021

Start single calibration

Start single calibrationStart single calibration

Write FREQ_A, FREQ_B, VCO,

Write FREQ_A, FREQ_B, VCO, CLOCK_A and CLOCK_B registers.

CLOCK_A and CLOCK_B registers. PLL_BW = 174 + 16log

PLL_BW = 174 + 16log

Write MAIN register = 11h:

Write MAIN register = 11h: RXTX=0, F_REG=0, PD_MODE=1,

RXTX=0, F_REG=0, PD_MODE=1, FS_PD=0, CORE_PD=0, BIAS_PD=0,

FS_PD=0, CORE_PD=0, BIAS_PD=0, RESET_N=1

RESET_N=1

Write CALIBRATE register = B4h

2(fref

/7.126)

Wait for T≥100 us

Read STATUS register and wait until

Read STATUS register and wait until CAL_COMPLETE=1

CAL_COMPLETE=1

Read STATUS register and wait until

Read STATUS register and wait until LOCK_CONTINUOUS=1

LOCK_CONTINUOUS=1

Calibration OK?

Yes

End of calibration

End of calibrationEnd of calibration

Figure 29. Single calibration algorithm for RX and TX

15.3. PLL Turn-on Time versus Loop Filter Bandwidth

If calibration has been performed the PLL turn-on time is the time needed for the PLL to lock to the desired frequency when going from power down mode (with the crystal oscillator running) to TX or RX

mode. The PLL turn-on time depends on the PLL loop filter bandwidth. Table 25 gives the PLL turn-on time for different PLL loop filter bandwidths.

No

SWRS045 Page 52 of 91

CC1021

Loop

filter no.

1 56 2200 560 3.3 10 1400 Up to 9.6 kBaud data rate.

2 15 560 150 5.6 18 1300 Up to 19.2 kBaud data rate.

3 3.9 120 33 12 39 1080 Up to 38.4 kBaud data rate.

4 1.0 27 3.3 27 82 950 Up to 76.8 kBaud data rate.

5 0.2 1.5 - 47 150 700 Up to 153.6 kBaud data rate.

Table 25. Typical PLL turn-on time to within specified accuracy for different loop filter

15.4. PLL Lock Time versus Loop Filter Bandwidth

If calibration has been performed the PLL lock time is the time needed for the PLL to lock to the desired frequency when going from RX to TX mode or vice versa. The

Loop filter

no.

1 56 2200 560 3.3 10 400 140

2 15 560 150 5.6 18 140 70

3 3.9 120 33 12 39 75 50

4 1.0 27 3.3 27 82 30 15

5 0.2 1.5 - 47 150 14 14

Table 26. Typical PLL lock time to within specified accuracy for different loop filter

16. VCO and LNA Current Control

The VCO current is programmable and should be set according to operating frequency, RX/TX mode and output power. Recommended settings for the VCO_CURRENT bits in the VCO register are shown in the register overview and also given by SmartRF current for frequency FREQ_A and

C6

C7

C8

R2

R3

[nF]

[pF]

[kΩ]

PLL turn-on time

[kΩ]

[us]

±5 kHz settling accuracy

±10 kHz settling accuracy

±15 kHz settling accuracy

±20 kHz settling accuracy

±50 kHz settling accuracy

Comment

bandwidths.

PLL lock time depends on the PLL loop filter bandwidth. Table 26 gives the PLL lock time for different PLL loop filter bandwidths.

C6

[nF]

C7

[pF]

C8

[pF]

R2

[kΩ]

R3

[kΩ]

PLL lock time

[us]

1 2 3

490 Up to 9.6 kBaud data rate.

(50 kHz)

230 Up to 19.2 kBaud data rate.

(100 kHz)

180 Up to 38.4 kBaud data rate.

(150 kHz)

55 Up to 76.8 kBaud data rate.

(200 kHz)

28 Up to 153.6 kBaud data rate.

(500 kHz)

Comment

±5 kHz settling accuracy

±10 kHz settling accuracy

±15 kHz settling accuracy

±20 kHz settling accuracy

±50 kHz settling accuracy

bandwidths. 1) 307.2 kHz step, 2) step as given in brackets, 3) 1 MHz step.

FREQ_B can be programmed independently.

The bias currents for the LNA, mixer and the LO and PA buffers are also



Studio. The VCO

programmable. The FRONTEND and the BUFF_CURRENT registers control these currents.

SWRS045 Page 53 of 91

CC1021

17. Power Management

CC1021

offers great flexibility for power management in order to meet strict power consumption requirements in batteryoperated applications. Power down mode is controlled through the MAIN register. There are separate bits to control the RX part, the TX part, the frequency synthesizer and the crystal oscillator in the MAIN register. This individual control can be used to optimize for lowest possible current consumption in each application. Figure 30 shows a typical power-on and initializing sequence for minimum power consumption.

Figure 31 shows a typical sequence for activating RX and TX mode from power down mode for minimum power consumption.

Note that PSEL should be tri-stated or set to a high level during power down mode in order to prevent a trickle current from flowing in the internal pull-up resistor.

Application Note AN023 CC1020 MCU Interfacing is also applicable for the

CC1021

. This application note includes example source code and is available from the Chipcon web site.

Chipcon recommends resetting the (by clearing the RESET_N bit in the MAIN register) when the chip is powered up initially. All registers that need to be configured should then be programmed (those which differ from their default values). Registers can be programmed freely in any order. The

CC1021

should

then be calibrated in both RX and TX mode. After this is completed, the is ready for use. See the detailed procedure flowcharts in Figure 29 - Figure

31.

With reference to Application Note AN023 CC1020 MCU Interfacing Chipcon recommends the following sequence. Note that the applicable for the

After power up:

1) ResetCC1020

2) Initialize

3) WakeUpCC1020ToRX

4) Calibrate

5) WakeUpCC1020ToTX

6) Calibrate

After calibration is completed, enter TX mode (SetupCC1020TX), RX mode (SetupCC1020RX) or power down mode (SetupCC1020PD)

From power-down mode to RX:

1) WakeUpCC1020ToRX

2) SetupCC1020RX

From power-down mode to TX:

1) WakeUpCC1020ToTX

2) SetupCC1020TX

Switching from RX to TX mode:

1) SetupCC1020TX

Switching from TX to RX mode:

1) SetupCC1020RX

CC1020

sub-routines are equally

CC1021

.

CC1021

SWRS045 Page 54 of 91

CC1021

Power Off

Power OffPower Off

Turn on power

Reset CC1021

Reset CC1021 MAIN: RX_TX=0, F_REG=0,

MAIN: RX_TX=0, F_REG=0, PD_MODE=1, FS_PD=1,

PD_MODE=1, FS_PD=1, XOSC_PD=1, BIAS_PD=1

XOSC_PD=1, BIAS_PD=1 RESET_N=0

RESET_N=0

ResetCC1020

RESET_N=1

Program all necessary registers

Program all necessary registers except MAIN and RESET

except MAIN and RESET

Turn on crystal oscillator, bias

Turn on crystal oscillator, bias generator and synthesizer

generator and synthesizer successively

successively

WakeupCC1020ToTx

WakeupCC1020ToRx/

Calibrate VCO and PLL

MAIN: PD_MODE=1, FS_PD=1,

MAIN: PD_MODE=1, FS_PD=1, XOSC_PD=1, BIAS_PD=1

XOSC_PD=1, BIAS_PD=1 PA_POWER=00h

PA_POWER=00h

SetupCC1020PD

Power Down mode

Figure 30. Initializing sequence

SWRS045 Page 55 of 91

CC1021

*Time to wait depends

*Time to wait depends on the crystal frequency

on the crystal frequency and the load capacitance

and the load capacitance

WakeupCC1020ToTx

WakeupCC1020ToRxSetupCC1020RxSetupCC1020PD

Power Down mode

Power Down modePower Down mode

Turn on crystal oscillator core

Turn on crystal oscillator core MAIN: PD_MODE=1, FS_PD=1, XOSC_PD=0, BIAS_PD=1

MAIN: PD_MODE=1, FS_PD=1, XOSC_PD=0, BIAS_PD=1 Wait 1.2 ms*

Wait 1.2 ms*

Turn on bias generator. MAIN: BIAS_PD=0

Turn on bias generator. MAIN: BIAS_PD=0 Wait 150 us

Wait 150 us

RX TX

RX or TX?

Turn on frequency synthesizer

Turn on frequency synthesizer MAIN: RXTX=0, F_REG=0, FS_PD=0

MAIN: RXTX=0, F_REG=0, FS_PD=0

Wait until lock detected from LOCK pin

Wait until lock detected from LOCK pin or STATUS register

or STATUS register

or STATUS register Turn on RX: MAIN: PD_MODE = 0

Turn on RX: MAIN: PD_MODE = 0

RX mode

RX modeRX mode

Turn off RX/TX:

Turn off RX/TX: MAIN: PD_MODE = 1, FS_PD=1,

MAIN: PD_MODE = 1, FS_PD=1, XOSC_PD=1, BIAS_PD=1

XOSC_PD=1, BIAS_PD=1 PA_POWER=00h

PA_POWER=00h

Power Down mode

Power Down modePower Down mode

Figure 31. Sequence for activating RX or TX mode

18. On-Off Keying (OOK)

The data modulator can also provide OOK (On-Off Keying) modulation. OOK is an ASK (Amplitude Shift Keying) modulation using 100% modulation depth. OOK modulation is enabled in RX and in TX by setting TXDEV_M[3:0] = 0000 in the

Turn on frequency synthesizer

Turn on frequency synthesizer MAIN: RXTX=1, F_REG=1, FS_PD=0

MAIN: RXTX=1, F_REG=1, FS_PD=0

Wait until lock detected from LOCK pin

Wait until lock detected from LOCK pin or STATUS register

or STATUS register

or STATUS register Turn on TX: MAIN: PD_MODE = 0

Turn on TX: MAIN: PD_MODE = 0

Turn on TX: MAIN: PD_MODE = 0 Set PA_POWER

Set PA_POWER

SetupCC1020Tx

TX mode

TX modeTX mode

SetupCC1020PD

DEVIATION register. An OOK eye diagram is shown in Figure 32.

The data demodulator can also perform OOK demodulation. The demodulation is done by comparing the signal level with

SWRS045 Page 56 of 91

CC1021

the "carrier sense" level (programmed as CS_LEVEL in the VGA4 register). The signal is then decimated and filtered in the data filter. Data decision and bit synchronization are as for FSK reception.

In this mode AGC_AVG in the VGA2 register must be set to 3. The channel bandwidth must be 4 times the Baud rate for data rates up to 9.6 kBaud. For the highest data rates the channel bandwidth must be 2 times the Baud rate (see Table

27). Manchester coding must always be used for OOK.

Note that the automatic frequency control (AFC) cannot be used when receiving OOK, as it requires a frequency shift.

The AGC has a certain time-constant determined by FILTER_CLK, which depends on the IF filter bandwidth. There is a lower limit on FILTER_CLK and hence the AGC time constant. For low data rates the minimum time constant is too fast and the AGC will increase the gain when a "0" is received and decrease the gain when a "1" is received. For this reason the minimum data rate in OOK is 9.6 kBaud.

Typical figures for the receiver sensitivity (BER = 10 OOK.

3

) are shown in Table 27 for

Figure 32. OOK eye diagram. 9.6 kBaud.

Data rate

[kBaud]

9.6 38.4 -103 -104

19.2 51.2 -102 -101

38.4 102.4 -95 -97

76.8 153.6 -92 -94

153.6 307.2 -81 -87

Table 27. Typical receiver sensitivity as a function of data rate at 433 and 868 MHz, OOK

modulation, BER = 10

SWRS045 Page 57 of 91

Filter BW

[kHz]

3

Manchester mode

, pseudo-random data (PN9 sequence).

Sensitivity [dBm]

433 MHz

868 MHz

Manchester mode

CC1021

19. Crystal Oscillator

The recommended crystal frequency is

14.7456 MHz, but any crystal frequency in the range 4 - 20 MHz can be used. Using a crystal frequency different from 14.7456 MHz might in some applications give degraded performance. Refer to Application Note AN022 Crystal Frequency Selection for more details on the use of other crystal frequencies than

14.7456 MHz. The crystal frequency is used as reference for the data rate (as well as other internal functions) and in the 4 ñ 20 MHz range the frequencies 4.9152,

7.3728, 9.8304, 12.2880, 14.7456,

17.2032, 19.6608 MHz will give accurate data rates as shown in Table 17 and an IF frequency of 307.2 kHz. The crystal frequency will influence the programming of the CLOCK_A, CLOCK_B and MODEM registers.

An external clock signal or the internal crystal oscillator can be used as main frequency reference. An external clock signal should be connected to XOSC_Q1, while XOSC_Q2 should be left open. The XOSC_BYPASS bit in the INTERFACE register should be set to ë1í when an external digital rail-to-rail clock signal is used. No DC block should be used then. A sine with smaller amplitude can also be used. A DC blocking capacitor must then be used (10 nF) and the XOSC_BYPASS bit in the INTERFACE register should be set to ë0í. For input signal amplitude, see section 4.5 on page 12.

Using the internal crystal oscillator, the crystal must be connected between the XOSC_Q1 and XOSC_Q2 pins. The oscillator is designed for parallel mode operation of the crystal. In addition, loading capacitors (C4 and C5) for the crystal are required. The loading capacitor values depend on the total load capacitance, C The total load capacitance seen between the crystal terminals should equal C

, specified for the crystal.

L

for

XOSC_Q1 XOSC_Q2

L

the crystal to oscillate at the specified frequency.

C +

1

=

+

The parasitic capacitance is constituted by pin input capacitance and PCB stray capacitance. Total parasitic capacitance is typically 8 pF. A trimming capacitor may be placed across C5 for initial tuning if necessary.

The crystal oscillator circuit is shown in Figure 33. Typical component values for different values of C

28.

The crystal oscillator is amplitude regulated. This means that a high current is required to initiate the oscillations. When the amplitude builds up, the current is reduced to what is necessary to maintain approximately 600 mVpp amplitude. This ensures a fast start-up, keeps the drive level to a minimum and makes the oscillator insensitive to ESR variations. As long as the recommended load capacitance values are used, the ESR is not critical.

The initial tolerance, temperature drift, aging and load pulling should be carefully specified in order to meet the required frequency accuracy in a certain application. By specifying the total expected frequency accuracy in SmartRF Studio together with data rate and frequency separation, the software will estimate the total bandwidth and compare to the available receiver channel filter bandwidth. The software will report any contradictions and a more accurate crystal will be recommended if required.

C

11

CC

54

are given in Table

L

parasiticL



XTAL

C5C4

Figure 33. Crystal oscillator circuit

SWRS045 Page 58 of 91

CC1021

Item CL= 12 pF CL= 16 pF CL= 22 pF

C4 6.8 pF 15 pF 27 pF C5 6.8 pF 15 pF 27 pF

Table 28. Crystal oscillator component values

20. Built-in Test Pattern Generator

The

CC1021

has a built-in test pattern generator that generates a PN9 pseudo random sequence. The PN9_ENABLE bit in the MODEM register enables the PN9 generator. A transition on the DIO pin is required after enabling the PN9 pseudo random sequence.

The PN9 pseudo random sequence is defined by the polynomial x

The PN9 sequence is ëXORíed with the DIO signal in both TX and RX mode as shown in Figure 34. Hence, by transmitting only zeros (DIO = 0), the BER (Bit Error Rate) can be tested by counting the

Tx pseudo random sequence

9

+ x5 + 1.

number of received ones. Note that the 9 first received bits should be discarded in this case. Also note that one bit error will generate 3 received ones.

Transmitting only ones (DIO = 1), the BER can be tested by counting the number of received zeroes.

The PN9 generator can also be used for transmission of ëreal-lifeí data when measuring narrowband ACP (Adjacent Channel Power), modulation bandwidth or occupied bandwidth.

Tx out (modulating signal)

Tx data (DIO pin)

XOR

Rx pseudo random sequence

Rx in (Demodulated Rx data)

XOR

Rx out (DIO pin)

8 7 6 5 4 3 2 1 0

XOR

8 7 6 5 4 3 2 1 0

XOR

Figure 34. PN9 pseudo random sequence generator in TX and RX mode

SWRS045 Page 59 of 91

CC1021

21. Interrupt on Pin DCLK

21.1. Interrupt upon PLL Lock

In synchronous mode the DCLK pin on

CC1021

can be used to give an interrupt signal to wake the microcontroller when the PLL is locked.

PD_MODE[1:0] in the MAIN register should be set to 01. If DCLK_LOCK in the INTERFACE register is set to 1 the DCLK signal is always logic high if the PLL is not in lock. When the PLL locks to the desired frequency the DCLK signal changes to

21.2. Interrupt upon Received Signal Carrier Sense

In synchronous mode the DCLK pin on

CC1021

interrupt signal to the microcontroller when the RSSI level exceeds a certain threshold (carrier sense threshold). This function can be used to wake or interrupt the microcontroller when a strong signal is received.

Gating the DCLK signal with the carrier sense signal makes the interrupt signal.

This function should only be used in receive mode and is enabled by setting DCLK_CS = 1 in the INTERFACE register.

can also be used to give an

22. PA_EN and LNA_EN Digital Output Pins

22.1. Interfacing an External LNA or PA

CC1021

has two digital output pins, PA_EN and LNA_EN, which can be used to control an external LNA or PA. The functionality of these pins are controlled through the INTERFACE register. The outputs can also be used as general digital output control signals.

EXT_PA_POL and EXT_LNA_POL control the active polarity of the signals.

EXT_PA and EXT_LNA control the function of the pins. If EXT_PA = 1, then

logic 0. When this interrupt has been detected write PD_MODE[1:0] = 00. This will enable the DCLK signal.

This function can be used to wait for the PLL to be locked before the PA is ramped up in transmit mode. In receive mode, it can be used to wait until the PLL is locked before searching for preamble.

The DCLK signal is always logic high unless carrier sense is indicated. When carrier sense is indicated the DCLK starts running. When gating the DCLK signal with the carrier sense signal at least 2 dummy bits should be added after the data payload in TX mode. The reason being that the carrier sense signal is generated earlier in the receive chain (i.e. before the demodulator), causing it to be updated 2 bits before the corresponding data is available on the DIO pin.

In transmit mode DCLK_CS must be set to

0. Refer to

the PA_EN pin will be activated when the internal PA is turned on. Otherwise, the EXT_PA_POL bit controls the PA_EN pin directly. If EXT_LNA = 1, then the LNA_EN pin will be activated when the internal LNA is turned on. Otherwise, the EXT_LNA_POL bit controls the LNA_EN pin directly.

These two pins can therefore also be used as two general control signals, section

21.2. In the Chipcon reference design

CC1021

Errata Note 001.

SWRS045 Page 60 of 91

CC1021

V

LNA_EN and PA_EN are used to control the external T/R switch.

22.2. General Purpose Output Control Pins

The two digital output pins, PA_EN and LNA_EN, can be used as two general control signals by setting EXT_PA = 0 and EXT_LNA = 0. The output value is then set directly by the value written to EXT_PA_POL and EXT_LNA_POL.

The LOCK pin can also be used as a general-purpose output pin. The LOCK pin

22.3. PA_EN and LNA_EN Pin Drive

Figure 35 shows the PA_EN and LNA_EN pin drive currents. The sink and source

1400

is controlled by LOCK_SELECT[3:0] in the

LOCK register. The LOCK pin is low when LOCK_SELECT[3:0] = 0000, and high

when LOCK_SELECT[3:0] = 0001.

These features can be used to save I/O pins on the microcontroller when the other functions associated with these pins are not used.

currents have opposite signs but absolute values are used in Figure 35.

1200

1000

800

600

Current [uA]

400

200

0

0.2

0.4

0.6

source current, 3 V sink current, 3V source current, 2.3 V sink current, 2.3 V source current, 3.6 V sink current, 3.6 V

1

0.8

1.2

1.4

1.6

oltage on PA_EN/L NA_EN pin [V]

1.8

2

Figure 35. PA_EN and LNA_EN pin drive

23. System Considerations and Guidelines

SRD regulations

International regulations and national laws regulate the use of radio receivers and transmitters. SRDs (Short Range Devices) for license free operation are allowed to operate in the 433 and 868 - 870 MHz bands in most European countries. In the United States, such devices operate in the

260 ñ 470 and 902 - 928 MHz bands. A summary of the most important aspects of these regulations can be found in Application Note AN001 SRD regulations for license free transceiver operation, available from the Chipcon web site.

2.2

2.4

2.6

3

2.8

3.2

3.4

3.6

SWRS045 Page 61 of 91

CC1021

Narrowband systems

CC1021

is recommended for narrowband applications with channel spacings of 50 kHz and higher complying with FCC CFR47 part 15 and EN 300 220.

CC1020

is recommended in narrowband applications with channel spacings of 12.5 or 25 kHz complying with ARIB STD T-67 and EN 300 220.

CC1020

and

CC1021

are fully compatible for channel spacings of 50 kHz and higher (receiver channel filter bandwidths of 38.4 kHz and higher).

Due to on-chip complex filtering, the image frequency is removed. An on-chip calibration circuit is used to get the best possible image rejection. A narrowband preselector filter is not necessary to achieve image rejection.

A unique feature in frequency resolution. This can be used for temperature compensation of the crystal if the temperature drift curve is known and a temperature sensor is included in the system. Even initial adjustment can be performed using the frequency programmability. This eliminates the need for an expensive TCXO and trimming in some applications. For more details refer to Application Note AN027 Temperature Compensation available from the Chipcon web site.

In less demanding applications, a crystal with low temperature drift and low aging could be used without further compensation. A trimmer capacitor in the crystal oscillator circuit (in parallel with C5) could be used to set the initial frequency accurately.

The frequency offset between a transmitter and receiver is measured in the

CC1021

and can be read back from the AFC register. The measured frequency offset can be used to calibrate the receiver frequency using the transmitter as the reference. For more details refer to Application Note AN029 CC1020/1021 AFC available from the Chipcon web site.

CC1021

also has the possibility to use Gaussian shaped FSK (GFSK). This

CC1021

is the very fine

spectrum-shaping feature improves adjacent channel power (ACP) and occupied bandwidth. In ëtrueí FSK systems with abrupt frequency shifting, the spectrum is inherently broad. By making the frequency shift ësofterí, the spectrum can be made significantly narrower. Thus, higher data rates can be transmitted in the same bandwidth using GFSK.

Low cost systems

As the multi-channel performance without any external filters, a very low cost high performance system can be achieved. The oscillator crystal can then be a low cost crystal with 50 ppm frequency tolerance using the on-chip frequency tuning possibilities.

Battery operated systems

In low power applications, the power down mode should be used when being active. Depending on the start-up time requirement, the oscillator core can be powered during power down. See section 17 page 54 for information on how effective power management can be implemented.

High reliability systems

Using a SAW filter as a preselector will improve the communication reliability in harsh environments by reducing the probability of blocking. The receiver sensitivity and the output power will be reduced due to the filter insertion loss. By inserting the filter in the RX path only, together with an external RX/TX switch, only the receiver sensitivity is reduced and output power is remained. The PA_EN and LNA_EN pin can be configured to control an external LNA, RX/TX switch or power amplifier. This is controlled by the INTERFACE register.

Frequency hopping spread spectrum systems (FHSS)

Due to the very fast locking properties of the PLL, the frequency hopping systems. Hop rates of 1-100 hops/s are commonly used depending on the bit rate and the amount of data to be sent during each transmission. The two frequency registers (FREQ_A and FREQ_B) are designed such that the ënextí frequency can be programmed while the ëpresentí frequency

CC1021

provide true narrowband

CC1021

is also very suitable for

is not

SWRS045 Page 62 of 91

CC1021

is used. The switching between the two frequencies is done through the MAIN register. Several features have been included to do the hopping without a need to re-synchronize the receiver. For more details refer to Application Note AN014 Frequency Hopping Systems available from the Chipcon web site.

In order to implement a frequency hopping system with

Set the desired frequency, calibrate and store the following register settings in nonvolatile memory:

STATUS1[3:0]: CHP_CURRENT[3:0] STATUS2[4:0]: VCO_ARRAY[4:0] STATUS3[5:0]:VCO_CAL_CURRENT[5:0]

Repeat the calibration for each desired frequency. VCO_CAL_CURRENT[5:0] is not dependent on the RF frequency and the same value can be used for all frequencies. When performing frequency hopping, write the stored values to the corresponding TEST1, TEST2 and TEST3 registers, and enable override:

TEST1[3:0]: CHP_CO[3:0] TEST2[4:0]: VCO_AO[4:0] TEST2[5]: VCO_OVERRIDE TEST2[6]: CHP_OVERRIDE

24. PCB Layout Recommendations

The top layer should be used for signal routing, and the open areas should be filled with metallization connected to ground using several vias.

The area under the chip is used for grounding and must be connected to the bottom ground plane with several vias. In the Chipcon reference designs we have placed 9 vias inside the exposed die attached pad. These vias should be ìtentedî (covered with solder mask) on the component side of the PCB to avoid migration of solder through the vias during the solder reflow process.

Each decoupling capacitor should be placed as close as possible to the supply pin it is supposed to decouple. Each decoupling capacitor should be connected

CC1021

do the following:

TEST3[5:0]: VCO_CO[5:0] TEST3[6]: VCO_CAL_OVERRIDE

CHP_CO[3:0] is the register setting read

from CHP_CURRENT[3:0], VCO_AO[4:0] is the register setting read from VCO_ARRAY[4:0] and VCO_CO[5:0] is the register setting read from VCO_CAL_CURRENT[5:0].

Assume channel 1 defined by register FREQ_A is currently being used and that

CC1021

should operate on channel 2 next (to change channel simply write to register MAIN[6]). The channel 2 frequency can be set by register FREQ_B which can be written to while operating on channel 1. The calibration data must be written to the TEST1-3 registers after switching to the next frequency. That is, when hopping to a new channel write to register MAIN[6] first and the test registers next. The PA should be switched off between each hop and the PLL should be checked for lock before switching the PA back on after a hop has been performed.

Note that the override bits

VCO_OVERRIDE, CHP_OVERRIDE and VCO_CAL_OVERRIDE must be disabled

when performing a re-calibration.

to the power line (or power plane) by separate vias. The best routing is from the power line (or power plane) to the decoupling capacitor and then to the

CC1021

is very important, especially for pins 23, 22, 20 and 18.

Each decoupling capacitor ground pad should be connected to the ground plane using a separate via. Direct connections between neighboring power pins will increase noise coupling and should be avoided unless absolutely necessary.

The external components should ideally be as small as possible and surface mount devices are highly recommended.

supply pin. Supply power filtering

SWRS045 Page 63 of 91

CC1021

Precaution should be used when placing the microcontroller in order to avoid noise interfering with the RF circuitry.

The recommended the same as for the CC1020/1070DK Development Kit with a

25. Antenna Considerations

CC1021

can be used together with various types of antennas. The most common antennas for short-range communication are monopole, helical and loop antennas.

Monopole antennas are resonant antennas with a length corresponding to one quarter of the electrical wavelength (λ/4). They are very easy to design and can be implemented simply as a ìpiece of wireî or even integrated onto the PCB.

Non-resonant monopole antennas shorter than λ/4 can also be used, but at the expense of range. In size and cost critical applications such an antenna may very well be integrated onto the PCB.

Helical antennas can be thought of as a combination of a monopole and a loop antenna. They are a good compromise in size critical applications. But helical antennas tend to be more difficult to optimize than the simple monopole.

Loop antennas are easy to integrate into the PCB, but are less effective due to

26. Configuration Registers

The configuration of programming the 8-bit configuration registers. The configuration data based on selected system parameters are most easily found by using the SmartRF software. Complete descriptions of the registers are given in the following tables. After a RESET is programmed, all the registers have default values. The TEST registers also get default values after a

CC1021

PCB layout is

CC1021

CC1020.

is done by



Studio

A

fully assembled CC1020EMX Evaluation Module is available. It is strongly advised that this reference layout is followed very closely in order to get the best performance. The layout Gerber files are available from the Chipcon web site.

difficult impedance matching because of their very low radiation resistance.

For low power applications the λ/4- monopole antenna is recommended due to its simplicity as well as providing the best range.

The length of the λ/4-monopole antenna is given by:

L = 7125 / f

where f is in MHz, giving the length in cm. An antenna for 868 MHz should be 8.2 cm, and 16.4 cm for 433 MHz.

The antenna should be connected as close as possible to the IC. If the antenna is located away from the input pin the antenna should be matched to the feeding transmission line (50 Ω).

For a more thorough background on antennas, please refer to Application Note AN003 SRD Antennas available from the Chipcon web site.

RESET, and should not be altered by the user.

Chipcon recommends using the register settings found using the SmartRF software. These are the register settings that Chipcon can guarantee across temperature, voltage and process. Please check the Chipcon web site for regularly updates to the SmartRF



Studio software.



Studio

SWRS045 Page 64 of 91

CC1021

26.1. CC1021 Register Overview

ADDRESS Byte Name Description

00h MAIN Main control register 01h INTERFACE Interface control register 02h RESET Digital module reset register 03h SEQUENCING Automatic power-up sequencing control register 04h FREQ_2A Frequency register 2A 05h FREQ_1A Frequency register 1A 06h FREQ_0A Frequency register 0A 07h CLOCK_A Clock generation register A 08h FREQ_2B Frequency register 2B 09h FREQ_1B Frequency register 1B 0Ah FREQ_0B Frequency register 0B 0Bh CLOCK_B Clock generation register B 0Ch VCO VCO current control register 0Dh MODEM Modem control register 0Eh DEVIATION TX frequency deviation register 0Fh AFC_CONTROL RX AFC control register 10h FILTER Channel filter / RSSI control register 11h VGA1 VGA control register 1 12h VGA2 VGA control register 2 13h VGA3 VGA control register 3 14h VGA4 VGA control register 4 15h LOCK Lock control register 16h FRONTEND Front end bias current control register 17h ANALOG Analog modules control register 18h BUFF_SWING LO buffer and prescaler swing control register 19h BUFF_CURRENT LO buffer and prescaler bias current control register 1Ah PLL_BW PLL loop bandwidth / charge pump current control register 1Bh CALIBRATE PLL calibration control register 1Ch PA_POWER Power amplifier output power register 1Dh MATCH Match capacitor array control register, for RX and TX impedance matching 1Eh PHASE_COMP Phase error compensation control register for LO I/Q 1Fh GAIN_COMP Gain error compensation control register for mixer I/Q 20h POWERDOWN Power-down control register 21h TEST1 Test register for overriding PLL calibration 22h TEST2 Test register for overriding PLL calibration 23h TEST3 Test register for overriding PLL calibration 24h TEST4 Test register for charge pump and IF chain testing 25h TEST5 Test register for ADC testing 26h TEST6 Test register for VGA testing 27h TEST7 Test register for VGA testing 40h STATUS Status information register (PLL lock, RSSI, calibration ready, etc.) 41h RESET_DONE Status register for digital module reset 42h RSSI Received signal strength register 43h AFC Average received frequency deviation from IF (can be used for AFC) 44h GAUSS_FILTER Digital FM demodulator register 45h STATUS1 Status of PLL calibration results etc. (test only) 46h STATUS2 Status of PLL calibration results etc. (test only) 47h STATUS3 Status of PLL calibration results etc. (test only) 48h STATUS4 Status of ADC signals (test only) 49h STATUS5 Status of channel filter ìIî signal (test only) 4Ah STATUS6 Status of channel filter ìQî signal (test only) 4Bh STATUS7 Status of AGC (test only)

SWRS045 Page 65 of 91

CC1021

MAIN Register (00h)

REGISTER NAME Default

value MAIN[7] RXTX - - RX/TX switch, 0: RX , 1: TX MAIN[6] F_REG - - Selection of Frequency Register,

MAIN[5:4] PD_MODE[1:0] - - Power down mode

MAIN[3] FS_PD - H Power Down of Frequency Synthesizer MAIN[2] XOSC_PD - H Power Down of Crystal Oscillator Core MAIN[1] BIAS_PD - H Power Down of BIAS (Global Current Generator) and Crystal

MAIN[0] RESET_N - L Reset, active low. Writing RESET_N low will write default values to

MAIN Register (00h) when using automatic power-up sequencing (RXTX = 0, PD_MODE[1:0] =11)

REGISTER NAME Default

value MAIN[7] RXTX - - Automatic power-up sequencing only works in RX (RXTX=0) MAIN[6] F_REG - - Selection of Frequency Register, 0: Register A, 1: Register B

MAIN[5:4] PD_MODE[1:0] - H Set PD_MODE[1:0]=3 (11) to enable sequencing MAIN[3:2] SEQ_CAL[1:0] - - Controls PLL calibration before re-entering power-down

MAIN[1] SEQ_PD -

MAIN[0] RESET_N - L Reset, active low. Writing RESET_N low will write default values to

Active Description

0: Register A, 1: Register B

0 (00): Receive Chain in power-down in TX, PA in power-down in RX 1 (01): Receive Chain and PA in power-down in both TX and RX 2 (10): Individual modules can be put in power-down by programming the POWERDOWN register 3 (11): Automatic power-up sequencing is activated (see below)

Oscillator Buffer

all other registers than MAIN. Bits in MAIN do not have a default value and will be written directly through the configuration interface. Must be set high to complete reset.

Active Description

0: Never perform PLL calibration as part of sequence 1: Always perform PLL calibration at end of sequence 2: Perform PLL calibration at end of every 16 3: Perform PLL calibration at end of every 256

↑ ↑1: Put the chip in power down and wait for start of new power-up

sequence

all other registers than MAIN. Bits in MAIN do not have a default value and will be written directly through the configuration interface. Must be set high to complete reset.

th

sequence

th

sequence

SWRS045 Page 66 of 91

CC1021

INTERFACE Register (01h)

REGISTER NAME Default

value

INTERFACE[7] XOSC_BYPASS 0 H Bypass internal crystal oscillator, use external clock

INTERFACE[6] SEP_DI_DO 0 H Use separate pin for RX data output

INTERFACE[5] DCLK_LOCK 0 H Gate DCLK signal with PLL lock signal in synchronous mode

INTERFACE[4] DCLK_CS 0 H Gate DCLK signal with carrier sense indicator in

INTERFACE[3] EXT_PA 0 H Use PA_EN pin to control external PA

INTERFACE[2] EXT_LNA 0 H Use LNA_EN pin to control external LNA

INTERFACE[1] EXT_PA_POL 0 H Polarity of external PA control

INTERFACE[0] EXT_LNA_POL 0 H Polarity of external LNA control

Note: If TF_ENABLE=1 or TA_ENABLE=1 in TEST4 register, then INTERFACE[3:0] controls analog test module: INTERFACE[3] = TEST_PD, INTERFACE[2:0] = TEST_MODE[2:0]. Otherwise, TEST_PD=1 and TEST_MODE[2:0]=001.

RESET Register (02h)

REGISTER NAME Default

RESET[7] ADC_RESET_N 0 L Reset ADC control logic RESET[6] AGC_RESET_N 0 L Reset AGC (VGA control) logic RESET[5] GAUSS_RESET_N 0 L Reset Gaussian data filter RESET[4] AFC_RESET_N 0 L Reset AFC / FSK decision level logic RESET[3] BITSYNC_RESET_N 0 L Reset modulator, bit synchronization logic and PN9

RESET[2] SYNTH_RESET_N 0 L Reset digital part of frequency synthesizer RESET[1] SEQ_RESET_N 0 L Reset power-up sequencing logic RESET[0] CAL_LOCK_RESET_N 0 L Reset calibration logic and lock detector

Note: For reset of CC1021 write RESET_N=0 in the MAIN register. The reset register should not be used during normal operation.

Bits in the RESET register are self-clearing (will be set to 1 when the reset operation starts). Relevant digital clocks must be running for the resetting to complete. After writing to the RESET register, the user should verify that all reset operations have been completed, by reading the RESET_DONE status register (41h) until all bits equal 1.

Active Description

0: Internal crystal oscillator is used, or external sine wave fed through a coupling capacitor 1: Internal crystal oscillator in power down, external clock with rail-to-rail swing is used

0: DIO is data output in RX and data input in TX. LOCK pin is available (Normal operation). 1: DIO is always input, and a separate pin is used for RX data output (synchronous mode: LOCK pin, asynchronous mode: DCLK pin).

If SEP_DI_DO=1 and SEQ_PSEL=0 in SEQUENCING register then negative transitions on DIO is used to start power-up sequencing when PD_MODE=3 (power-up sequencing is enabled).

Only applies when PD_MODE = ì01î 0: DCLK is always 1 1: DCLK is always 1 unless PLL is in lock

synchronous mode Use when receive chain is active (in power-up) Always set to 0 in TX mode. 0: DCLK is independent of carrier sense indicator. 1: DCLK is always 1 unless carrier sense is indicated

0: PA_EN pin always equals EXT_PA_POL bit 1: PA_EN pin is asserted when internal PA is turned on

0: LNA_EN pin always equals EXT_LNA_POL bit 1: LNA_EN pin is asserted when internal LNA is turned on

0: PA_EN pin is ì0î when activating external PA 1: PA_EN pin is ì1î when activating external PA

0: LNA_EN pin is ì0î when activating external LNA 1: LNA_EN pin is ì1î when activating external LNA

Active Description

value

PRBS generator

SWRS045 Page 67 of 91

CC1021

SEQUENCING Register (03h)

REGISTER NAME Default

value

SEQUENCING[7] SEQ_PSEL 1 H Use PSEL pin to start sequencing

SEQUENCING[6:4] RX_WAIT[2:0] 0 - Waiting time from PLL enters lock until RX power-up

SEQUENCING[3:0] CS_WAIT[3:0] 10 - Waiting time for carrier sense from RX power-up

FREQ_2A Register (04h)

REGISTER NAME Default

value

FREQ_2A[7:0] FREQ_A[22:15] 131 - 8 MSB of frequency control word A

FREQ_1A Register (05h)

REGISTER NAME Default

value

FREQ_1A[7:0] FREQ_A[14:7] 177 - Bit 15 to 8 of frequency control word A

FREQ_0A Register (06h)

REGISTER NAME Default

value

FREQ_0A[7:1] FREQ_A[6:0] 124 - 7 LSB of frequency control word A

FREQ_0A[0] DITHER_A 1 H Enable dithering for frequency A

Active Description

0: PSEL pin does not start sequencing. Negative transitions on DIO starts power-up sequencing if SEP_DI_DO=1. 1: Negative transitions on the PSEL pin will start powerup sequencing

0: Wait for approx. 32 ADC_CLK periods (26 1: Wait for approx. 44 ADC_CLK periods (36 2: Wait for approx. 64 ADC_CLK periods (52 3: Wait for approx. 88 ADC_CLK periods (72 4: Wait for approx. 128 ADC_CLK periods (104 5: Wait for approx. 176 ADC_CLK periods (143 6: Wait for approx. 256 ADC_CLK periods (208 7: No additional waiting time before RX power-up

0: Wait 20 FILTER_CLK periods before power down 1: Wait 22 FILTER_CLK periods before power down 2: Wait 24 FILTER_CLK periods before power down 3: Wait 26 FILTER_CLK periods before power down 4: Wait 28 FILTER_CLK periods before power down 5: Wait 30 FILTER_CLK periods before power down 6: Wait 32 FILTER_CLK periods before power down 7: Wait 36 FILTER_CLK periods before power down 8: Wait 40 FILTER_CLK periods before power down 9: Wait 44 FILTER_CLK periods before power down 10: Wait 48 FILTER_CLK periods before power down 11: Wait 52 FILTER_CLK periods before power down 12: Wait 56 FILTER_CLK periods before power down 13: Wait 60 FILTER_CLK periods before power down 14: Wait 64 FILTER_CLK periods before power down 15: Wait 72 FILTER_CLK periods before power down

Active Description

µ

s)

µ

s)

µ

s)

µ

s)

µ µ µ

s) s) s)

SWRS045 Page 68 of 91

CC1021

CLOCK_A Register (07h)

REGISTER NAME Default

value

CLOCK_A[7:5] REF_DIV_A[2:0] 2 - Reference frequency divisor (A):

CLOCK_A[4:2] MCLK_DIV1_A[2:0] 4 - Modem clock divider 1 (A):

CLOCK_A[1:0] MCLK_DIV2_A[1:0] 0 - Modem clock divider 2 (A):

FREQ_2B Register (08h)

REGISTER NAME Default

value

FREQ_2B[7:0] FREQ_B[22:15] 131 - 8 MSB of frequency control word B

FREQ_1B Register (09h)

REGISTER NAME Default

value

FREQ_1B[7:0] FREQ_B[14:7] 189 - Bit 15 to 8 of frequency control word B

FREQ_0B Register (0Ah)

REGISTER NAME Default

value

FREQ_0B[7:1] FREQ_B[6:0] 124 - 7 LSB of frequency control word B

FREQ_0B[0] DITHER_B 1 H Enable dithering for frequency B

Active Description

0: Not supported 1: REF_CLK frequency = Crystal frequency / 2 Ö 7: REF_CLK frequency = Crystal frequency / 8

It is recommended to use the highest possible reference clock frequency that allows the desired Baud rate.

0: Divide by 2.5 1: Divide by 3 2: Divide by 4 3: Divide by 7.5 (2.5∑3) 4: Divide by 12.5 (2.5∑5) 5: Divide by 40 (2.5∑16) 6: Divide by 48 (3∑16) 7: Divide by 64 (4∑16)

0: Divide by 1 1: Divide by 2 2: Divide by 4 3: Divide by 8

MODEM_CLK frequency is FREF frequency divided by the product of divider 1 and divider 2.

Baud rate is MODEM_CLK frequency divided by 8.

Active Description

SWRS045 Page 69 of 91

CC1021

CLOCK_B Register (0Bh)

REGISTER NAME Default

value

CLOCK_B[7:5] REF_DIV_B[2:0] 2 - Reference frequency divisor (B):

CLOCK_B[4:2] MCLK_DIV1_B[2:0] 4 - Modem clock divider 1 (B):

CLOCK_B[1:0] MCLK_DIV2_B[1:0] 0 - Modem clock divider 2 (B):

VCO Register (0Ch)

REGISTER NAME Default

VCO[7:4] VCO_CURRENT_A[3:0] 8 - Control of current in VCO core for frequency A

VCO[3:0] VCO_CURRENT_B[3:0] 8 - Control of current in VCO core for frequency B

Active Description

0: Not supported 1: REF_CLK frequency = Crystal frequency / 2 Ö 7: REF_CLK frequency = Crystal frequency / 8

0: Divide by 2.5 1: Divide by 3 2: Divide by 4 3: Divide by 7.5 (2.5∑3) 4: Divide by 12.5 (2.5∑5) 5: Divide by 40 (2.5∑16) 6: Divide by 48 (3∑16) 7: Divide by 64 (4∑16)

0: Divide by 1 1: Divide by 2 2: Divide by 4 3: Divide by 8

MODEM_CLK frequency is FREF frequency divided by the product of divider 1 and divider 2.

Baud rate is MODEM_CLK frequency divided by 8.

Active Description

value

0: 1.4 mA current in VCO core 1: 1.8 mA current in VCO core 2: 2.1 mA current in VCO core 3: 2.5 mA current in VCO core 4: 2.8 mA current in VCO core 5: 3.2 mA current in VCO core 6: 3.5 mA current in VCO core 7: 3.9 mA current in VCO core 8: 4.2 mA current in VCO core 9: 4.6 mA current in VCO core 10: 4.9 mA current in VCO core 11: 5.3 mA current in VCO core 12: 5.6 mA current in VCO core 13: 6.0 mA current in VCO core 14: 6.4 mA current in VCO core 15: 6.7 mA current in VCO core

Recommended setting: VCO_CURRENT_A=4

The current steps are the same as for VCO_CURRENT_A

Recommended setting: VCO_CURRENT_B=4

SWRS045 Page 70 of 91

CC1021

MODEM Register (0Dh)

REGISTER NAME Default

value

MODEM[7] - 0 - Reserved, write 0

MODEM[6:4] ADC_DIV[2:0] 3 - ADC clock divisor

MODEM[3] - 0 - Reserved, write 0 MODEM[2] PN9_ENABLE 0 H Enable scrambling of TX and RX with PN9 pseudo-

MODEM[1:0] DATA_FORMAT[1:0] 0 - Modem data format

DEVIATION Register (0Eh)

REGISTER NAME Default

value

DEVIATION[7] TX_SHAPING 1 H Enable Gaussian shaping of transmitted data

DEVIATION[6:4] TXDEV_X[2:0] 6 - Transmit frequency deviation exponent

DEVIATION [3:0] TXDEV_M[3:0] 8 - Transmit frequency deviation mantissa

Active Description

0: Not supported 1: ADC frequency = XOSC frequency / 4 2: ADC frequency = XOSC frequency / 6 3: ADC frequency = XOSC frequency / 8 4: ADC frequency = XOSC frequency / 10 5: ADC frequency = XOSC frequency / 12 6: ADC frequency = XOSC frequency / 14 7: ADC frequency = XOSC frequency / 16

Note that the intermediate frequency should be as close to 307.2 kHz as possible. ADC clock frequency is always 4 times the intermediate frequency and should therefore be as close to 1.2288 MHz as possible.

random bit sequence 0: PN9 scrambling is disabled 1: PN9 scrambling is enabled (x

The PN9 pseudo-random bit sequence can be used for BER testing by only transmitting zeros, and then counting the number of received ones.

0 (00): NRZ operation 1 (01): Manchester operation 2 (10): Transparent asynchronous UART operation, set DCLK=0 3 (11): Transparent asynchronous UART operation, set DCLK=1

Active Description

Recommended setting: TX_SHAPING=1

Deviation in 402-470 MHz band:

∑TXDEV_M ∑2

F

REF

Deviation in 804-940 MHz band:

F

∑TXDEV_M ∑2

REF

On-off-keying (OOK) is used in RX/TX if TXDEV_M[3:0]=0

To find TXDEV_M given the deviation and TXDEV_X:

TXDEV_M = deviation∑2

in 402-470 MHz band,

TXDEV_M = deviation∑2

in 804-940 MHz band.

Decrease TXDEV_X and try again if TXDEV_M < 8. Increase TXDEV_X and try again if TXDEV_M ≥ 16.

(TXDEV_X16)

(TXDEV_X15)

(16TXDEV_X)

(15TXDEV_X)

9+x5

+1)

/F

REF

/F

REF

SWRS045 Page 71 of 91

CC1021

AFC_CONTROL Register (0Fh)

REGISTER NAME Default

value

AFC_CONTROL[7:6] SETTLING[1:0] 2 - Controls AFC settling time versus accuracy

AFC_CONTROL[5:4] RXDEV_X[1:0] 1 - RX frequency deviation exponent AFC_CONTROL[3:0] RXDEV_M[3:0] 12 - RX frequency deviation mantissa

Note: The RX frequency deviation should be close to half the TX frequency deviation for GFSK at 100 kBaud data rate and below. The RX frequency deviation should be close to the TX frequency deviation for FSK and for GFSK at 100 kBaud data rate and above.

FILTER Register (10h)

REGISTER NAME Default

value

FILTER[7] FILTER_BYPASS 0 H Bypass analog image rejection / anti-alias filter. Set to 1 for

FILTER[6:5] DEC_SHIFT[1:0] 0 - Number of extra bits to shift decimator input

FILTER[4:3] - - - Reserved FILTER[2:0] DEC_DIV[2:0] 0 - Decimation clock divisor

Active Description

0: AFC off; zero average frequency is used in demodulator 1: Fastest settling; frequency averaged over 1 0/1 bit pair 2: Medium settling; frequency averaged over 2 0/1 bit pairs 3: Slowest settling; frequency averaged over 4 0/1 bit pairs

Recommended setting: AFC_CONTROL=3 for higher accuracy unless it is essential to have the fastest settling time when transmission starts after RX is activated.

Expected RX deviation should be:

Baud rate ∑ RXDEV_M ∑2

To find RXDEV_M given the deviation and RXDEV_X:

RXDEV_M = 3 ∑ deviation ∑2

Decrease RXDEV_X and try again if RXDEV_M<8. Increase RXDEV_X and try again if RXDEV_M≥16.

Active Description

increased dynamic range at high Baud rates.

Recommended setting: FILTER_BYPASS=0 below 76.8 kBaud, FILTER_BYPASS=1 for 76.8 kBaud and up.

(may improve filter accuracy and lower power consumption).

Recommended settings: DEC_SHIFT=0 when DEC_DIV

≥

153.6 kHz), DEC_SHIFT=1 when DEC_DIV >1 (receiver channel bandwidth < 153.6 kHz).

0: Decimation clock divisor = 1, 307.2 kHz channel filter BW. 1: Decimation clock divisor = 2, 153.6 kHz channel filter BW. Ö 6: Decimation clock divisor = 7, 43.9 kHz channel filter BW. 7: Decimation clock divisor = 8, 38.4 kHz channel filter BW.

Channel filter bandwidth is 307.2 kHz divided by the decimation clock divisor.

(RXDEV_X3)

/ 3

(3RXDEV_X)

≤

1 (receiver channel bandwidth

/ Baud rate

SWRS045 Page 72 of 91

CC1021

VGA1 Register (11h)

REGISTER NAME Default

value

VGA1[7:6] CS_SET[1:0] 1 - Sets the number of consecutive samples at or above carrier

VGA1[5] CS_RESET 1 - Sets the number of consecutive samples below carrier sense

VGA1[4:2] VGA_WAIT[2:0] 1 - Controls how long AGC, bit synchronization, AFC and RSSI

VGA1[1:0] VGA_FREEZE[1:0] 1 - Controls the additional time AGC, bit synchronization, AFC

Active Description

sense level before carrier sense is indicated (e.g. on LOCK pin) 0: Set carrier sense after first sample at or above carrier sense level 1: Set carrier sense after second sample at or above carrier sense level 2: Set carrier sense after third sample at or above carrier sense level 3: Set carrier sense after fourth sample at or above carrier sense level

Increasing CS_SET reduces the number of ìfalseî carrier sense events due to noise at the expense of increased carrier sense response time.

level before carrier sense indication (e.g. on lock pin) is reset 0: Carrier sense is reset after first sample below carrier sense level 1: Carrier sense is reset after second sample below carrier sense level

Recommended setting: CS_RESET=1 in order to reduce the chance of losing carrier sense due to noise.

levels are frozen after VGA gain is changed when frequency is changed between A and B or PLL has been out of lock or after RX power-up 0: Freeze operation for 16 filter clocks, 8/(filter BW) seconds 1: Freeze operation for 20 filter clocks, 10/(filter BW) seconds 2: Freeze operation for 24 filter clocks, 12/(filter BW) seconds 3: Freeze operation for 28 filter clocks, 14/(filter BW) seconds 4: Freeze operation for 32 filter clocks, 16/(filter BW) seconds 5: Freeze operation for 40 filter clocks, 20/(filter BW) seconds 6: Freeze operation for 48 filter clocks, 24/(filter BW) seconds 7: Freeze present levels unconditionally

and RSSI levels are frozen when frequency is changed between A and B or PLL has been out of lock or after RX power-up 0: Freeze levels for approx. 16 ADC_CLK periods (13 1: Freeze levels for approx. 32 ADC_CLK periods (26 2: Freeze levels for approx. 64 ADC_CLK periods (52 3: Freeze levels for approx. 128 ADC_CLK periods (104

µ

s)

µ

s)

µ

s)

µ

s)

SWRS045 Page 73 of 91

CC1021

VGA2 Register (12h)

REGISTER NAME Default

value

VGA2[7] LNA2_MIN 0 - Minimum LNA2 setting used in VGA

VGA2[6] LNA2_MAX 1 - Maximum LNA2 setting used in VGA

VGA2[5:4] LNA2_SETTING[1:0] 3 - Selects at what VGA setting the LNA gain should be

VGA2[3] AGC_DISABLE 0 H Disable AGC

VGA2[2] AGC_HYSTERESIS 1 H Enable AGC hysteresis

VGA2[1:0] AGC_AVG[1:0] 1 - Sets how many samples that are used to calculate average

Active Description

0: Minimum LNA2 gain 1: Medium LNA2 gain

Recommended setting: LNA2_MIN=0 for best selectivity.

0: Medium LNA2 gain 1: Maximum LNA2 gain

Recommended setting: LNA2_MAX=1 for best sensitivity.

changed 0: Apply LNA2 change below min. VGA setting. 1: Apply LNA2 change at approx. 1/3 VGA setting (around VGA setting 10). 2: Apply LNA2 change at approx. 2/3 VGA setting (around VGA setting 19). 3: Apply LNA2 change above max. VGA setting.

Recommended setting: LNA2_SETTING=0 if VGA_SETTING<10, LNA2_SETTING=1 otherwise.

If LNA2_MIN=1 and LNA2_MAX=0, then the LNA2 setting is controlled by LNA2_SETTING: 0: Between medium and maximum LNA2 gain 1: Minimum LNA2 gain 2: Medium LNA2 gain 3: Maximum LNA2 gain

0: AGC is enabled 1: AGC is disabled (VGA_SETTING determines VGA gain)

Recommended setting: AGC_DISABLE=0 for good dynamic range.

0: No hysteresis. Immediate gain change for smallest up/down step 1: Hysteresis enabled. Two samples in a row must indicate gain change for smallest up/down step

Recommended setting: AGC_HYSTERESIS=1.

output magnitude for AGC/RSSI. 0: Magnitude is averaged over 2 filter output samples 1: Magnitude is averaged over 4 filter output samples 2: Magnitude is averaged over 8 filter output samples 3: Magnitude is averaged over 16 filter output samples

Recommended setting: AGC_AVG=1. For best AGC/RSSI accuracy AGC_AVG=3.

For automatic power-up sequencing, the AGC_AVG and CS_SET values must be chosen so that carrier sense is available in time to be detected before the chip re-enters power-down.

SWRS045 Page 74 of 91

CC1021

VGA3 Register (13h)

REGISTER NAME Default

value

VGA3[7:5] VGA_DOWN[2:0] 1 - Decides how much the signal strength must be above

VGA3[4:0] VGA_SETTING[4:0] 24 H VGA setting to be used when receive chain is turned on

VGA4 Register (14h)

REGISTER NAME Default

value

VGA4[7:5] VGA_UP[2:0] 1 - Decides the level where VGA gain is increased if it is not

VGA4[4:0] CS_LEVEL[4:0] 24 H Reference level for Received Signal Strength Indication

Active Description

CS_LEVEL+VGA_UP before VGA gain is decreased. 0: Gain is decreased 4.5 dB above CS_LEVEL+VGA_UP 1: Gain is decreased 6 dB above CS_LEVEL+VGA_UP Ö 6: Gain is decreased 13.5 dB above CS_LEVEL+VGA_UP 7: Gain is decreased 15 dB above CS_LEVEL+VGA_UP

See Figure 20 on page 39 for an explanation of the relationship between RSSI, AGC and carrier sense settings.

This is also the maximum gain that the AGC is allowed to use.

See Figure 20 on page 39 for an explanation of the relationship between RSSI, AGC and carrier sense settings.

Active Description

already at the maximum set by VGA_SETTING. 0: Gain is increased when signal is below CS_LEVEL 1: Gain is increased when signal is below CS_LEVEL+1.5 dB Ö 6: Gain is increased when signal is below CS_LEVEL+9 dB 7: Gain is increased when signal below CS_LEVEL+10.5 dB

See Figure 20 on page 39 for an explanation of the relationship between RSSI, AGC and carrier sense settings.

(carrier sense level) and AGC.

See Figure 20 on page 39 for an explanation of the relationship between RSSI, AGC and carrier sense settings.

SWRS045 Page 75 of 91

CC1021

LOCK Register (15h)

REGISTER NAME Default

value

LOCK[7:4] LOCK_SELECT[3:0] 0 - Selection of signals to LOCK pin

LOCK[3] WINDOW_WIDTH 0 - Selects lock window width

LOCK[2] LOCK_MODE 0 - Selects lock detector mode

LOCK[1:0] LOCK_ACCURACY[1:0] 0 - Selects lock accuracy (counter threshold values)

Note: Set LOCK_SELECT=2 to use the LOCK pin as a lock indicator.

Active Description

0: Set to 0 1: Set to 1 2: LOCK_CONTINUOUS (active low) 3: LOCK_INSTANT (active low) 4: CARRIER_SENSE (RSSI above threshold, active low) 5: CAL_COMPLETE (active low) 6: SEQ_ERROR (active low) 7: FXOSC 8: REF_CLK 9: FILTER_CLK 10: DEC_CLK 11: PRE_CLK 12: DS_CLK 13: MODEM_CLK 14: VCO_CAL_COMP 15: F_COMP

0: Lock window is 2 prescaler clock cycles wide 1: Lock window is 4 prescaler clock cycles wide

Recommended setting: WINDOW_WIDTH=0.

0: Counter restart mode 1: Up/Down counter mode

Recommended setting: LOCK_MODE=0.

0: Declare lock at counter value 127, out of lock at value 111 1: Declare lock at counter value 255, out of lock at value 239 2: Declare lock at counter value 511, out of lock at value 495 3: Declare lock at counter value 1023, out of lock at value 1007

SWRS045 Page 76 of 91

CC1021

FRONTEND Register (16h)

REGISTER NAME Default

value

FRONTEND[7:6] LNAMIX_CURRENT[1:0] 2 - Controls current in LNA, LNA2 and mixer

FRONTEND[5:4] LNA_CURRENT[1:0] 1 - Controls current in the LNA

FRONTEND[3] MIX_CURRENT 0 - Controls current in the mixer

FRONTEND[2] LNA2_CURRENT 0 - Controls current in LNA 2

FRONTEND[1] SDC_CURRENT 0 - Controls current in the single-to-diff. converter

FRONTEND[0] LNAMIX_BIAS 1 - Controls how front-end bias currents are generated

Active Description

Recommended setting: LNAMIX_CURRENT=1

Recommended setting: LNA_CURRENT=3.

Can be lowered to save power, at the expense of reduced sensitivity.

Recommended setting: MIX_CURRENT=1 at 402-470 MHz, MIX_CURRENT=0 at 804-940 MHz..

Recommended settings: LNA2_CURRENT=0 at 402-470 MHz, LNA2_CURRENT=1 at 804-940 MHz.

Recommended settings: SDC_CURRENT=0 at 402-470 MHz, SDC_CURRENT=1 at 804-940 MHz.

0: Constant current biasing 1: Constant Gm

Recommended setting: LNAMIX_BIAS=0.

·

R biasing (reduces gain variation)

SWRS045 Page 77 of 91

CC1021

ANALOG Register (17h)

REGISTER NAME Default

ANALOG[7] BANDSELECT 1 - Frequency band selection

ANALOG[6] LO_DC 1 - Lower LO DC level to mixers

ANALOG[5] VGA_BLANKING 1 H Enable analog blanking switches in VGA when

ANALOG[4] PD_LONG 0 H Selects short or long reset delay in phase

ANALOG[3] - 0 - Reserved, write 0 ANALOG[2] PA_BOOST 0 H Boost PA bias current for higher output power

ANALOG[1:0]

DIV_BUFF_CURRENT[1:0] 3 - Overall bias current adjustment for VCO divider

value

BUFF_SWING Register (18h)

REGISTER NAME Default

BUFF_SWING[7:6] PRE_SWING[1:0] 3 - Prescaler swing. Fractions for PRE_CURRENT=0:

BUFF_SWING[5:3] RX_SWING[2:0] 4 - LO buffer swing, in RX (to mixers)

BUFF_SWING[2:0] TX_SWING[2:0] 1 - LO buffer swing, in TX (to power amplifier driver)

value

Active Description

0: 402-470 MHz band 1: 804-940 MHz band

0: High LO DC level to mixers 1: Low LO DC level to mixers

Recommended settings: LO_DC=1 for 402-470 MHz, LO_DC=0 for 804-940 MHz.

changing VGA gain. 0: Blanking switches are disabled 1: Blanking switches are turned on for approx.

0.8

µ

AGC_DISABLE=1)

Recommended setting: VGA_BLANKING=0.

detector 0: Short reset delay 1: Long reset delay

Recommended setting: PD_LONG=0.

Recommended setting: PA_BOOST=1.

and buffers 0: 4/6 of nominal VCO divider and buffer current 1: 4/5 of nominal VCO divider and buffer current 2: Nominal VCO divider and buffer current 3: 4/3 of nominal VCO divider and buffer current

Recommended setting: DIV_BUFF_CURRENT=3

Active Description

0: 2/3 of nominal swing 1: 1/2 of nominal swing 2: 4/3 of nominal swing 3: Nominal swing

Recommended setting: PRE_SWING=0

0: Smallest load resistance (smallest swing) Ö 7: Largest load resistance (largest swing)

Recommended setting: RX_SWING=2.

0: Smallest load resistance (smallest swing) Ö 7: Largest load resistance (largest swing)

Recommended settings: TX_SWING=4 for 402-470 MHz, TX_SWING=0 for 804-940 MHz.

s when gain is changed (always on if

SWRS045 Page 78 of 91

CC1021

BUFF_CURRENT Register (19h)

REGISTER NAME Default

BUFF_CURRENT[7:6] PRE_CURRENT[1:0] 1 - Prescaler current scaling

BUFF_CURRENT[5:3] RX_CURRENT[2:0] 4 - LO buffer current, in RX (to mixers)

BUFF_CURRENT[2:0] TX_CURRENT[2:0] 5 - LO buffer current, in TX (to PA driver)

value

PLL_BW Register (1Ah)

REGISTER NAME Default

PLL_BW[7:0] PLL_BW[7:0] 134 - Charge pump current scaling/rounding factor.

value

CALIBRATE Register (1Bh)

REGISTER NAME Default

value

CALIBRATE[7] CAL_START 0

CALIBRATE[6] CAL_DUAL 0 H Use calibration results for both frequency A and B

CALIBRATE[5:4] CAL_WAIT[1:0] 0 - Selects calibration wait time (affects accuracy)

CALIBRATE[3] - 0 - Reserved, write 0

CALIBRATE[2:0] CAL_ITERATE[2:0] 5 - Iteration start value for calibration DAC

Active Description

↑ ↑ 1: Calibration started

Active Description

0: Nominal current 1: 2/3 of nominal current 2: 1/2 of nominal current 3: 2/5 of nominal current

Recommended setting: PRE_CURRENT=0.

0: Minimum buffer current Ö 7: Maximum buffer current

Recommended setting: RX_CURRENT=4.

0: Minimum buffer current Ö 7: Maximum buffer current

Recommended settings: TX_CURRENT=2 for 402-470 MHz, TX_CURRENT=5 for 804-940 MHz.

Active Description

Used to calibrate charge pump current for the desired PLL loop bandwidth. The value is given by: PLL_BW = 174 + 16 log reference frequency in MHz.

0: Calibration inactive

0: Store results in A or B defined by F_REG (MAIN[6]) 1: Store calibration results in both A and B

0 (00): Calibration time is approx. 90000 F_REF periods 1 (01): Calibration time is approx. 110000 F_REF periods 2 (10): Calibration time is approx. 130000 F_REF periods 3 (11): Calibration time is approx. 200000 F_REF periods

Recommended setting: CAL_WAIT=3 for best accuracy in calibrated PLL loop filter bandwidth.

0 (000): DAC start value 1, VC<0.49 V after calibration 1 (001): DAC start value 2, VC<0.66 V after calibration 2 (010): DAC start value 3, VC<0.82 V after calibration 3 (011): DAC start value 4, VC<0.99 V after calibration 4 (100): DAC start value 5, VC<1.15 V after calibration 5 (101): DAC start value 6, VC<1.32 V after calibration 6 (110): DAC start value 7, VC<1.48 V after calibration 7 (111): DAC start value 8, VC<1.65 V after calibration

Recommended setting: CAL_ITERATE=4.

/7.126) where f

2(fref

is the

ref

SWRS045 Page 79 of 91

CC1021

PA_POWER Register (1Ch)

REGISTER NAME Default

value

PA_POWER[7:4] PA_HIGH [3:0] 0 - Controls output power in high-power array

PA_POWER[3:0] PA_LOW[3:0] 15 - Controls output power in low-power array

MATCH Register (1Dh)

REGISTER NAME Default value Active Description

Active Description

0: High-power array is off 1: Minimum high-power array output power Ö 15: Maximum high-power array output power

0: Low-power array is off 1: Minimum low-power array output power Ö 15: Maximum low-power array output power

It is more efficient in terms of current consumption to use either the lower or upper 4-bits in the PA_POWER register to control the power.

MATCH[7:4] RX_MATCH[3:0] 0 - Selects matching capacitor array value for RX. Each

MATCH[3:0] TX_MATCH[3:0] 0 - Selects matching capacitor array value for TX.

step is approximately 0.4 pF.

Each step is approximately 0.4 pF.

PHASE_COMP Register (1Eh)

REGISTER NAME Default

value

PHASE_COMP[7:0] PHASE_COMP[7:0] 0 - Signed compensation value for LO I/Q phase error.

Active Description

Used for image rejection calibration. 128: approx. 6.2∞ adjustment between I and Q phase 1: approx. 0.02∞ adjustment between I and Q phase 0: approx. +0.02∞ adjustment between I and Q phase 127: approx. +6.2∞ adjustment between I and Q phase

GAIN_COMP Register (1Fh)

REGISTER NAME Default

value

GAIN_COMP[7:0] GAIN_COMP[7:0] 0 - Signed compensation value for mixer I/Q gain error. Used

Active Description

for image rejection calibration. 128: approx. 1.16 dB adjustment between I and Q gain 1: approx. 0.004 dB adjustment between I and Q gain 0: approx. +0.004 dB adjustment between I and Q gain 127: approx. +1.16 dB adjustment between I and Q gain

POWERDOWN Register (20h)

REGISTER NAME Default

value POWERDOWN[7] PA_PD 0 H Sets PA in power-down when PD_MODE[1:0]=2 POWERDOWN[6] VCO_PD 0 H Sets VCO in power-down when PD_MODE[1:0]=2 POWERDOWN[5] BUFF_PD 0 H Sets VCO divider, LO buffers and prescaler in power-down

POWERDOWN[4] CHP_PD 0 H Sets charge pump in power-down when PD_MODE[1:0]=2 POWERDOWN[3] LNAMIX_PD 0 H Sets LNA/mixer in power-down when PD_MODE[1:0]=2 POWERDOWN[2] VGA_PD 0 H Sets VGA in power-down when PD_MODE[1:0]=2 POWERDOWN[1] FILTER_PD 0 H Sets image filter in power-down when PD_MODE[1:0]=2 POWERDOWN[0] ADC_PD 0 H Sets ADC in power-down when PD_MODE[1:0]=2

Active Description

when PD_MODE[1:0]=2

SWRS045 Page 80 of 91

CC1021

TEST1 Register (21h, for test only)

REGISTER NAME Default

TEST1[7:4] CAL_DAC_OPEN[3:0] 4 - Calibration DAC override value, active when

TEST1[3:0] CHP_CO[3:0] 13 - Charge pump current override value

value

TEST2 Register (22h, for test only)

REGISTER NAME Default

TEST2[7] BREAK_LOOP 0 H 0: PLL loop closed

TEST2[6] CHP_OVERRIDE 0 H 0: use calibrated value

TEST2[5] VCO_OVERRIDE 0 H 0: use calibrated value

TEST2[4:0] VCO_AO[4:0] 16 - VCO_ARRAY override value

value

TEST3 Register (23h, for test only)

REGISTER NAME Default

TEST3[7] VCO_CAL_MANUAL 0 H Enables ìmanualî VCO calibration (test only) TEST3[6] VCO_CAL_OVERRIDE 0 H Override VCO current calibration

TEST3[5:0] VCO_CO[5:0] 6 - VCO_CAL_CURRENT override value

value

TEST4 Register (24h, for test only)

REGISTER NAME Default

TEST4[7] CHP_DISABLE 0 H Disable normal charge pump operation TEST4[6] CHP_TEST_UP 0 H Force charge pump to output ìupî current TEST4[5] CHP_TEST_DN 0 H Force charge pump to output ìdownî current

TEST4[4:3] TM_IQ[1:0] 0 - Value of differential I and Q outputs from mixer when

TEST4[2] TM_ENABLE 0 H Enable DC control of mixer output (for testing) TEST4[1] TF_ENABLE 0 H Connect analog test module to filter inputs TEST4[0] TA_ENABLE 0 H Connect analog test module to ADC inputs

value

If TF_ENABLE=1 or TA_ENABLE=1 in TEST4 register, then INTERFACE[3:0] controls analog test module: INTERFACE[3] = TEST_PD, INTERFACE[2:0] = TEST_MODE[2:0]. Otherwise, TEST_PD=1 and TEST_MODE[2]=1.

TEST5 Register (25h, for test only)

REGISTER NAME Default

TEST5[7] F_COMP_ENABLE 0 H Enable frequency comparator output F_COMP from

TEST5[6] SET_DITHER_CLOCK 1 H Enable dithering of delta-sigma clock TEST5[5] ADC_TEST_OUT 0 H Outputs ADC samples on LOCK and DIO, while

TEST5[4] CHOP_DISABLE 0 H Disable chopping in ADC integrators TEST5[3] SHAPING_DISABLE 0 H Disable ADC feedback mismatch shaping TEST5[2] VCM_ROT_DISABLE 0 H Disable rotation for VCM mismatch shaping

TEST5[1:0] ADC_ROTATE[1:0] 0 - Control ADC input rotation

value

Active Description

BREAK_LOOP=1

Active Description

1: PLL loop open

1: use CHP_CO[3:0] value

1: use VCO_AO[4:0] value

Active Description

0: Use calibrated value 1: Use VCO_CO[5:0] value

VCO_CAL_OVERRIDE controls VCO_CAL_CLK if VCO_CAL_MANUAL=1. Negative transitions are then used to sample VCO_CAL_COMP.

Active Description

TM_ENABLE=1 0: I output negative, Q output negative 1: I output negative, Q output positive 2: I output positive, Q output negative 3: I output positive, Q output positive

Active Description

phase detector

ADC_CLK is output on DCLK

0: Rotate in 00 01 10 11 sequence 1: Rotate in 00 10 11 01 sequence 2: Always use 00 position 3: Rotate in 00 10 00 10 sequence

SWRS045 Page 81 of 91

CC1021

TEST6 Register (26h, for test only)

REGISTER NAME Default

value

TEST6[7:4] - 0 - Reserved, write 0

TEST6[3] VGA_OVERRIDE 0 - Override VGA settings TEST6[2] AC1O 0 - Override value to first AC coupler in VGA

TEST6[1:0] AC2O[1:0] 0 - Override value to second AC coupler in VGA

TEST7 Register (27h, for test only)

REGISTER NAME Default

value TEST7[7:6] - 0 - Reserved, write 0 TEST7[5:4] VGA1O[1:0] 0 - Override value to VGA stage 1 TEST7[3:2] VGA2O[1:0] 0 - Override value to VGA stage 2 TEST7[1:0] VGA3O[1:0] 0 - Override value to VGA stage 3

STATUS Register (40h, read only)

REGISTER NAME Default

STATUS[7] CAL_COMPLETE - H Set to 0 when PLL calibration starts, and set to 1 when

STATUS[6] SEQ_ERROR - H Set to 1 when PLL failed to lock during automatic power-

STATUS[5] LOCK_INSTANT - H Instantaneous PLL lock indicator STATUS[4] LOCK_CONTINUOUS - H PLL lock indicator, as defined by LOCK_ACCURACY.

STATUS[3] CARRIER_SENSE - H Carrier sense when RSSI is above CS_LEVEL STATUS[2] LOCK - H Logical level on LOCK pin STATUS[1] DCLK - H Logical level on DCLK pin STATUS[0] DIO - H Logical level on DIO pin

RESET_DONE Register (41h, read only)

REGISTER NAME Default

RESET_DONE[7] ADC_RESET_DONE - H Reset of ADC control logic done RESET_DONE[6] AGC_RESET_DONE - H Reset of AGC (VGA control) logic done RESET_DONE[5] GAUSS_RESET_DONE - H Reset of Gaussian data filter done RESET_DONE[4] AFC_RESET_DONE - H Reset of AFC / FSK decision level logic done RESET_DONE[3] BITSYNC_RESET_DONE - H Reset of modulator, bit synchronization logic

RESET_DONE[2] SYNTH_RESET_DONE - H Reset digital part of frequency synthesizer

RESET_DONE[1] SEQ_RESET_DONE - H Reset of power-up sequencing logic done RESET_DONE[0] CAL_LOCK_RESET_DONE - H Reset of calibration logic and lock detector

RSSI Register (42h, read only)

REGISTER NAME Default

value

RSSI[7] - - - Not in use, will read 0

RSSI[6:0] RSSI[6:0] - - Received signal strength indicator.

Active Description

0: Approx. 0 dB gain 1: Approx. 12 dB gain

0: Approx. 0 dB gain 1: Approx. 3 dB gain 2: Approx. 12 dB gain 3: Approx. 15 dB gain

Active Description

value

calibration has finished

up sequencing

Set to 1 when PLL is in lock

Active Description

value

and PN9 PRBS generator done

done

Active Description

The relative power is given by RSSI x 1.5 dB in a logarithmic scale.

The VGA gain set by VGA_SETTING must be taken into account. See page 33 for more details.

SWRS045 Page 82 of 91

CC1021

AFC Register (43h, read only)

REGISTER NAME Default

value

AFC[7:0] AFC[7:0] - - Average received frequency deviation from IF. This 8-bit 2-

GAUSS_FILTER Register (44h)

REGISTER NAME Default

GAUSS_FILTER[7:0] GAUSS_FILTER[7:0] - - Readout of instantaneous IF frequency offset

STATUS1 Register (45h, for test only)

REGISTER NAME Default

STATUS1[7:4] CAL_DAC[3:0] - - Status vector defining applied Calibration DAC value STATUS1[3:0] CHP_CURRENT[3:0] - - Status vector defining applied CHP_CURRENT value

STATUS2 Register (46h, for test only)

REGISTER NAME Default

STATUS2[7:5] CC1021_VERSION[2:0] - - CC1021 version code:

STATUS2[4:0] VCO_ARRAY[4:0] - - Status vector defining applied VCO_ARRAY

STATUS3 Register (47h, for test only)

REGISTER NAME Default

STATUS3[7] F_COMP - - Frequency comparator output from phase

STATUS3[6] VCO_CAL_COMP - - Readout of VCO current calibration comparator.

STATUS3[5:0] VCO_CAL_CURRENT[5:0] - - Status vector defining applied

STATUS4 Register (48h, for test only)

REGISTER NAME Default

STATUS4[7:6] ADC_MIX[1:0] - - Readout of mixer input to ADC STATUS4[5:3] ADC_I[2:0] - - Readout of ADC ìIî output STATUS4[2:0] ADC_Q[2:0] - - Readout of ADC ìQî output

STATUS5 Register (49h, for test only)

REGISTER NAME Default

STATUS5[7:0] FILTER_I[7:0] - - Upper bits of ìIî output from channel filter

STATUS6 Register (4Ah, for test only)

REGISTER NAME Default

STATUS6[7:0] FILTER_Q[7:0] - - Upper bits of ìQî output from channel filter

Active Description

complement signed value equals the demodulator decision level and can be used for AFC. The average frequency offset from the IF frequency is ∆F = Baud rate ∑ AFC / 16

Active Description

value

from nominal IF. Signed 8-bit value. ∆F = Baud rate ∑ GAUSS_FILTER/8

Active Description

value

Active Description

value

0: Pre-production version 1: First production version 2-7: Reserved for future use

value

Active Description

value

detector

Equals 1 if current defined by VCO_CURRENT_A/B is larger than the VCO core current

VCO_CAL_CURRENT value

Active Description

value

Active Description

value

Active Description

value

SWRS045 Page 83 of 91

CC1021

STATUS7 Register (4Bh, for test only)

REGISTER NAME Default

value STATUS7[7:5] - - - Not in use, will read 0 STATUS7[4:0] VGA_GAIN_OFFSET[4:0] - - Readout of offset between VGA_SETTING and

Active Description

actual VGA gain set by AGC

SWRS045 Page 84 of 91

CC1021

27. Package Description (QFN 32)

SWRS045 Page 85 of 91

CC1021

D E A A1 e b L D1 E1 P QFN 32 Min

Max

All dimensions in mm. Angles are in degrees.

Package is compliant with JEDEC: MO-220.

Note: Do not place a via underneath connected to the exposed die attached pad, which is the main ground connection for the chip.

27.1. Package Marking

When contacting technical support with a chip-related question, please state the entire marking information, not just the date code.

Standard leaded

Quad Flat Pack - No Lead Package (QFN)

0.8

7.0

0.9

1.0

0.203 0.65

CC1021

at ìpin #1 cornerî as this pin is internally

0.25

0.30

0.35

0.45

0.55

0.65

4.18

4.28

4.38

4.18

4.28

4.38

45°

0409 is the date code (year 04, week 09) 123 is the lot code

RoHS compliant Pb-free

A409123

409 is the date code (year 4, week 09) 123 is the lot code A means RoHS compliant Pb-free

0409123

SWRS045 Page 86 of 91

CC1021

27.2. Recommended PCB Footprint for Package (QFN 32)

Note: The figure is an illustration only and not to scale. There are nine 14 mil (0.36 mm)

diameter via holes distributed symmetrically in the ground plane under the package. See also the CC1020EMX reference design.

27.3. Package Thermal Properties

Air velocity

Thermal resistance

[m/s]

Rth,j-a [K/W] 21.4 18.9 17.0

0 1 2

27.4. Soldering Information

Recommended soldering profile for both standard leaded packages and Pb-free packages is according to IPC/JEDEC J-STD-020C.

SWRS045 Page 87 of 91

CC1021

27.5. Plastic Tube Specification

QFN 7x7 mm antistatic tube.

Package Tube Width Tube Height Tube Length Units per Tube QFN 32

8.5 ± 0.2 mm

27.6. Carrier Tape and Reel Specification

Carrier tape and reel is in accordance with EIA Specification 481.

Package Tape Width Component

QFN 32 16 mm 12 mm 4 mm 13î 4000

28. Ordering Information

Ordering part number Description MOQ

1135 CC1021-RTB1 CC1021, QFN32 package, standard leaded assembly, tubes

1136 CC1021-RTR1 CC1021, QFN32 package, RoHS compliant Pb-free assembly,

1115 CC1020_1070DK-433 CC1020_1070 Development Kit, 433 MHz

1116 CC1020_1070DK-868/915 CC1020/1070 Development Kit, 868/915 MHz

1159 CC1021SK RoHS CC1021 Sample Kit, QFN32 package, RoHS compliant Pb-

MOQ = Minimum Order Quantity T&R = tape and reel

Note: The CC1020/1070DK Development Kit with a fully assembled CC1020EMX Evaluation Module should be used for evaluation of the

Tube Specification

2.2 +0.2/-0.1 mm

Tape and Reel Specification

Pitch

with 43 pcs per tube, Single Chip RF Transceiver.

T&R with 4000 pcs per reel, Single Chip RF Transceiver.

free assembly, 5 pcs

CC1021

315 ± 1.25 mm

Hole Pitch

Reel Diameter

transceiver.

43

Units per Reel

43

4000

1

SWRS045 Page 88 of 91

CC1021

29. General Information

Document Revision History

Revision Date Description/Changes

1.0 February 2004 First edition

1.1 December 2004 The various sections have been reorganized to improve readability

1.2 October 2005 RSSI dynamic range changed from 63 dB to 55 dB

1.3 January 2006 Updates to Ordering Information and Address Information

Product Status Definitions

Data Sheet Identification Product Status Definition

Advance Information Planned or Under

Preliminary Engineering Samples

No Identification Noted Full Production This data sheet contains the final specifications.

Obsolete Not In Production This data sheet contains specifications on a product

Added chapter numbering Reorganized electrical specification section Electrical specifications updated Changes to sensitivity figures Changes to TX spurious emission and harmonics figures Changes to current consumption figures in RX and TX mode and crystal oscillator, bias and synthesizer mode Changes to noise figure Added figures on modulation bandwidth Updates to section on input / output matching Updates to section on VCO and PLL self-calibration Updates to section on VCO, charge pump and PLL loop filter Updates to section on receiver channel filter bandwidth Updates to section on RSSI Updates to section on image rejection calibration Updates to section on preamble length and sync word Description of OOK modulation and demodulation merged into one section New bill of materials for operation at 433 MHz and 868/915 MHz Added recommended PCB footprint for package (QFN 32) Added information that there should be no via at ìpin #1 cornerî (section 27.2) Added list of abbreviations Changes to ordering information

Recommended CAL_ITERATE changed from 5 to 4 PLL timeout in ìAutomatic power-up sequencing flow chartî changed from 1024 filter clocks to 127 filter clocks Calibration routine flow chart changed in accordance to CC1021 Errata Note 002 Added chapter on TX data latency

Development

and First Production

This data sheet contains the design specifications for product development. Specifications may change in any manner without notice. This data sheet contains preliminary data, and supplementary data will be published at a later date. Chipcon reserves the right to make changes at any time without notice in order to improve design and supply the best possible product.

Chipcon reserves the right to make changes at any time without notice in order to improve design and supply the best possible product.

that has been discontinued by Chipcon. The data sheet is printed for reference information only.

SWRS045 Page 89 of 91

CC1021

Disclaimer

Chipcon AS believes the information contained herein is correct and accurate at the time of this printing. However, Chipcon AS reserves the right to make changes to this product without notice. Chipcon AS does not assume any responsibility for the use of the described product; neither does it convey any license under its patent rights, or the rights of others. The latest updates are available at the Chipcon website or by contacting Chipcon directly.

To the extent possible, major changes of product specifications and functionality will be stated in product specific Errata Notes published at the Chipcon website. Customers are encouraged to sign up for the Developerís Newsletter for the most recent updates on products and support tools.

When a product is discontinued this will be done according to Chipconís procedure for obsolete products as described in Chipconís Quality Manual. This includes informing about last-time-buy options. The Quality Manual can be downloaded from Chipconís website.

Compliance with regulations is dependent on complete system performance. It is the customerís responsibility to ensure that the system complies with regulations.

Trademarks

SmartRF

cells, modules and design expertise. Based on SmartRF circuits as well as full custom ASICs based on customer requirements and this technology.

All other trademarks, registered trademarks and product names are the sole property of their respective owners.



is a registered trademark of Chipcon AS. SmartRF is Chipcon's RF technology platform with RF library

Life Support Policy

This Chipcon product is not designed for use in life support appliances, devices, or other systems where malfunction can reasonably be expected to result in significant personal injury to the user, or as a critical component in any life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. Chipcon AS customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Chipcon AS for any damages resulting from any improper use or sale.



technology Chipcon develops standard component RF

SWRS045 Page 90 of 91

SmartRF

30. Address Information

Web site: http://www.chipcon.com E-mail: wireless@chipcon.com Technical Support Email: support@chipcon.com Technical Support Hotline: +47 22 95 85 45

Headquarters:

Chipcon AS GaustadallÈen 21 N-0349 Oslo NORWAY Tel: +47 22 95 85 44 Fax: +47 22 95 85 46 E-mail: wireless@chipcon.com

US Offices:

Chipcon Inc., Western US Sales Office 1455 Frazee Road, Suite 800 San Diego, CA 92108 USA Tel: +1 619 542 1200 Fax: +1 619 542 1222 Email: USsales@chipcon.com

Sales Office Germany:

Chipcon AS Riedberghof 3 D-74379 Ingersheim GERMANY Tel: +49 7142 9156815 Fax: +49 7142 9156818 Email: Germanysales@chipcon.com

Chipcon Inc., Eastern US Sales Office 35 Pinehurst Avenue Nashua, New Hampshire, 03062 USA Tel: +1 603 888 1326 Fax: +1 603 888 4239 Email: eastUSsales@chipcon.com

Sales Office Asia:

Chipcon AS Unit 503, 5/F Silvercord Tower 2, 30 Canton Road Tsimshatsui, Hong Kong Tel: +852 3519 6226 Fax: +852 3519 6520 Email: Asiasales@chipcon.com



CC1021

Sales Office Asia:

Chipcon AS Unit 503, 5/F Silvercord Tower 2, 30 Canton Road Tsimshatsui HONG KONG Tel: +852 3519 6226 Fax: +852 3519 6520 Email:

Asiasales@chipcon.com SEAsales@chipcon.com

India, Australia and New Zealand)

(China, Hong Kong, Taiwan) (Korea, South East Asia,

Sales Office Japan:

Chipcon AS #403, Bureau Shinagawa 4-1-6, Konan, Minato-Ku Tokyo, Zip 108-0075 JAPAN Tel: +81 3 5783 1082 Fax: +81 3 5783 1083 Email: Japansales@chipcon.com

SWRS045 Page 91 of 91

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TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty . Except where mandated by government requirements, testing of all parameters of each product is not necessarily performed.

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TEXAS INSTRUMENTS CC1021 Technical data

Specifications and Main Features

Frequently Asked Questions

User Manual