Texas Instruments CC1010PAGRG3, CC1010 Datasheet
CC1010
SWRS047 Page 1 of 152
CC1010
Single Chip Very Low Power RF Transceiver with
8051-Compatible Microcontroller
Applications
Very low power UHF wireless data
transmitters and receivers
315 / 433 / 868 and 915 MHz ISM/SRD
band systems
Home automation and security
AMR – Automatic Meter Reading
RKE – Remote Keyless Entry with
acknowledgement
Low power telemetry
Toys
Product Description
The
CC1010
is a true single-chip UHF
transceiver with an integrated high
performance 8051 microcontroller with 32
kB of Flash program memory. The RF
transceiver can be programmed for
operation in the 300 – 1000 MHz range,
and is designed for very low power
wireless applications.
The
CC1010
together with a few external
passive components constitutes a
powerful embedded system with wireless
communication capabilities.
CC1010
is based on Chipcon’s SmartRF02
technology in 0.35 m CMOS.
Key Features
300-1000 MHz RF Transceiver
Very low current consumption (9.1
mA in RX)
High sensitivity (typically -107 dBm)
Programmable output power up to
+10 dBm
Data rate up to 76.8 kbps
Very few external components
Fast PLL settling allowing frequency
hopping protocols
RSSI
EN 300 220 and FCC CFR47 part
15 compliant
8051-Compatible Microcontroller
Typically 2.5 times the performance
of a standard 8051
32 kB Flash, 2048 + 128 Byte SRAM
3 channel 10 bit ADC, 4 timers / 2
PWMs, 2 UARTs, RTC, Watchdog,
SPI, DES encryption, 26 general I/O
pins
In-circuit interactive debugging is
supported for the Keil Vision2 IDE
through a simple serial interface.
2.7 - 3.6 V supply voltage
64-lead TQFP
CC1010
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Table Of Contents
1. FEATURES..................................................................................................................... 4
2. ABSOLUTE MAXIMUM RATINGS ................................................................................ 5
3. RECOMMENDED OPERATING CONDITIONS............................................................. 5
4. DC CHARACTERISTICS ............................................................................................... 6
5. ELECTRICAL SPECIFICATIONS.................................................................................. 7
6. ADC ................................................................................................................................ 8
7. RF SECTION, GENERAL .............................................................................................. 8
8. RF TRANSMIT SECTION .............................................................................................. 9
9. RF RECEIVE SECTION ............................................................................................... 10
10. IF SECTION.................................................................................................................. 11
11. FREQUENCY SYNTHESIZER SECTION.................................................................... 12
12. PIN CONFIGURATION ................................................................................................ 13
13. PIN DESCRIPTION ...................................................................................................... 15
14. BLOCK DIAGRAM....................................................................................................... 18
15. 8051 CORE .................................................................................................................. 19
15.1 GENERAL DESCRIPTION............................................................................................ 19
15.2 RESET..................................................................................................................... 19
15.3 MEMORY MAP ......................................................................................................... 20
15.4 CPU REGISTERS ..................................................................................................... 23
15.5 INSTRUCTION SET SUMMARY.................................................................................... 24
15.6 INTERRUPTS ............................................................................................................ 28
15.7 EXTERNAL INTERRUPTS............................................................................................ 32
15.8 MAIN CRYSTAL OSCILLATOR..................................................................................... 32
15.9 POWER AND CLOCK MODES ..................................................................................... 34
15.10 FLASH PROGRAM MEMORY ...................................................................................... 37
15.11 SPI FLASH PROGRAMMING....................................................................................... 37
15.12 SERIAL PROGRAMMING ALGORITHM.......................................................................... 37
15.13 8051 FLASH PROGRAMMING .................................................................................... 42
15.14 FLASH POWER CONTROL ......................................................................................... 44
15.15 IN CIRCUIT DEBUGGING............................................................................................ 44
15.16 CHIP VERSION / REVISION ........................................................................................ 45
16. 8051 PERIPHERALS ................................................................................................... 47
16.1 GENERAL PURPOSE I/O ........................................................................................... 47
16.2 TIMER 0 / TIMER 1.................................................................................................... 52
16.3 TIMER 2 / 3 WITH PWM ............................................................................................ 59
16.4 POWER ON RESET (BROWN-OUT DETECTION) .......................................................... 62
16.5 WATCHDOG TIMER................................................................................................... 63
16.6 REAL-TIME CLOCK ................................................................................................... 65
16.7 SERIAL PORT 0 AND 1 .............................................................................................. 66
16.8 SPI MASTER ........................................................................................................... 71
16.9 DES ENCRYPTION / DECRYPTION ............................................................................. 75
16.10 RANDOM BIT GENERATION ....................................................................................... 78
16.11 ADC ....................................................................................................................... 79
17. RF TRANSCEIVER ...................................................................................................... 83
17.1 GENERAL DESCRIPTION............................................................................................ 83
17.2 RF TRANSCEIVER BLOCK DIAGRAM .......................................................................... 83
17.3 RF APPLICATION CIRCUIT ........................................................................................ 85
17.4 TRANSCEIVER CONFIGURATION OVERVIEW ............................................................... 88
17.5 RF TRANSCEIVER RX/TX CONTROL AND POWER MANAGEMENT ................................. 89
17.6 DATA MODEM AND DATA MODES .............................................................................. 91
17.7 BAUD RATES............................................................................................................ 94
17.8 TRANSMITTING AND RECEIVING DATA ........................................................................ 95
CC1010
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17.9 DEMODULATION AND DATA DECISION......................................................................... 97
17.10 SYNCHRONIZATION AND PREAMBLE DETECTION ....................................................... 102
17.11 RECEIVER SENSITIVITY VERSUS DATA RATE AND FREQUENCY SEPARATION................ 105
17.12 FREQUENCY PROGRAMMING................................................................................... 107
17.13 LOCK INDICATION................................................................................................... 110
17.14 RECOMMENDED SETTINGS FOR ISM FREQUENCIES................................................. 111
17.15 VCO..................................................................................................................... 113
17.16 VCO AND PLL SELF-CALIBRATION .......................................................................... 113
17.17 VCO, LNA AND BUFFER CURRENT CONTROL........................................................... 118
17.18 INPUT / OUTPUT MATCHING .................................................................................... 120
17.19 OUTPUT POWER PROGRAMMING ............................................................................ 123
17.20 RSSI OUTPUT ....................................................................................................... 126
17.21 IF OUTPUT ............................................................................................................. 127
17.22 OPTIONAL LC FILTER ............................................................................................. 128
18. RESERVED REGISTERS AND TEST REGISTERS ................................................. 129
19. SYSTEM CONSIDERATIONS AND GUIDELINES ................................................... 131
19.1 SRD REGULATIONS................................................................................................ 131
19.2 LOW COST SYSTEMS .............................................................................................. 131
19.3 BATTERY OPERATED SYSTEMS................................................................................ 131
19.4 NARROW-BAND SYSTEMS ....................................................................................... 131
19.5 HIGH RELIABILITY SYSTEMS .................................................................................... 131
19.6 FREQUENCY HOPPING SPREAD SPECTRUM SYSTEMS................................................ 132
19.7 SOFTWARE ............................................................................................................ 132
19.8 DEVELOPMENT TOOLS............................................................................................ 132
19.9 PA “SPLATTERING”................................................................................................. 132
19.10 PCB LAYOUT RECOMMENDATIONS ......................................................................... 133
19.11 ANTENNA CONSIDERATIONS ................................................................................... 133
20. PACKAGE DESCRIPTION (TQFP-64)...................................................................... 135
21. SOLDERING INFORMATION.................................................................................... 136
22. PACKAGE MARKING................................................................................................ 137
22.1 STANDARD LEADED ................................................................................................ 137
22.2 ROHS COMPLIANT PB-FREE ................................................................................... 137
23. RECOMMENDED PCB FOOTPRINT ........................................................................ 138
24. PACKAGE THERMAL COEFFICIENTS.................................................................... 138
25. TRAY SPECIFICATION ............................................................................................. 139
26. CARRIER TAPE AND REEL SPECIFICATION ........................................................ 139
27. LIST OF ABBREVIATIONS ....................................................................................... 140
28. SFR SUMMARY ......................................................................................................... 141
29. ALPHABETIC REGISTER INDEX ............................................................................. 145
30. ORDERING INFORMATION...................................................................................... 148
31. GENERAL INFORMATION........................................................................................ 149
31.1 DOCUMENT HISTORY ............................................................................................. 149
31.2 PRODUCT STATUS DEFINITIONS.............................................................................. 150
31.3 DISCLAIMER........................................................................................................... 150
31.4 TRADEMARKS ........................................................................................................ 150
31.5 LIFE SUPPORT POLICY ........................................................................................... 150
32. ADDRESS INFORMATION........................................................................................ 152
CC1010
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1. Features
Fully Integrated UHF RF Transceiver
Programmable frequency in the
range 300 – 1000 MHz
High sensitivity (typically -107 dBm
at 2.4 kBaud)
Programmable output power –20 to
+10 dBm
Very low current consumption (RX:
9.1 mA)
Very few external components
required and no external RF switch
or IF filter required
Single port antenna connection
Fast PLL settling allows frequency
hopping protocols
FSK modulation with a data rate of
up to 76.8 kBaud
Manchester or NRZ coding and
decoding of data performed in
hardware. Byte delineation of data
can be performed in hardware to
lessen the processor burden
RSSI output which can be sampled
by on-chip ADC
Complies with EN 300 220 and FCC
CFR47 part 15
High-Performance and Low-Power
8051-Compatible Microcontroller
Optimised 8051-core which typically
gives 2.5x the performance of a
standard 8051
Dual data pointers
Idle and sleep modes
In-circuit interactive debugging is
supported for the Keil Vision IDE
through a simple serial interface
Data and Non-volatile Program Memory
32 kB of non-volatile Flash memory
in-system programmable through a
simple SPI interface or by the 8051
core.
Typical Flash memory endurance:
20 000 write/erase cycles
Programmable read and write lock of
portions of Flash memory for software
security
2048 + 128 Byte of internal SRAM
Hardware DES Encryption / Decryption
DES supported in hardware
Output Feedback Mode or Cipher
Feedback Mode DES to avoid the
requirement that data length must
be a multiple of eight bytes
Peripheral Features
Power On Reset / Brown-Out
Detection
Three channel, max 23 kSample/s,
10 bit ADC
Programmable watchdog timer.
Real time clock with 32 kHz crystal
oscillator
Two timers / pulse counters and two
timers / pulse width modulators
Two programmable serial UARTs.
Master SPI interface
26 configurable general-purpose
I/O-pins
Random bit generator in hardware
Low Power
8051 core and peripherals can use
the RTC's 32 kHz clock
Idle and sleep modes for reduced
power consumption. System can
wake up on interrupt or when ADC
input exceeds a set threshold
Low-power fully static CMOS design
Operating Conditions
2.7 - 3.6 V supply voltage
-40 - 85 C operational temperature
3 - 24 MHz crystal (up to 50 ppm)
for the main crystal oscillator
Packaging
64-lead TQFP
CC1010
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2. Absolute Maximum Ratings
Under no circumstances must the absolute maximum ratings given in Table 1 be violated.
Stress exceeding one or more of the limiting values may cause permanent damage to the
device.
Parameter Min. Max. Units Condition
Supply voltage, VDD -0.3 5.0 V
Voltage on any pin -0.3 VDD+0.3,
max 5.0
V
Input RF level 10 dBm
Storage temperature range -50 150
C
Un-programmed device
Storage temperature range -40 125
C
Programmed device, data
retention > 0.49 years at
125C
Lead temperature 260
C
T = 10 s
Table 1. Absolute Maximum Ratings
Caution! ESD sensitive device.
Precaution should be used when handling
the device in order to prevent permanent
damage.
3. Recommended Operating Conditions
Tc = -40 to 85C, VDD = 2.7 to 3.6 V if nothing else stated
Parameter
Min Typ Max Unit Condition
Supply voltage, DVDD, AVDD 2.7 3.3 3.6 V
Supply voltage during
normal operation
Supply voltage, DVDD, AVDD 2.7 3.6 V Supply voltage during
program/erase Flash
memory
Operating temperature, free-air -40 85
C
Main oscillator frequency
3 24 MHz
RTC oscillator frequency 32768 Hz
Table 2. Recommended Operating Conditions
CC1010
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4. DC Characteristics
The DC Characteristics of
CC1010
are listed in Table 3 below.
Tc = 25C, VDD = 3.3 V if nothing else stated
Digital Inputs/Outputs
Min Max Unit Condition
Logic "0" input voltage
0 0.3*VDD V
Logic "1" input voltage
0.7*VDD VDD V
Logic "0" output voltage 0
0.4 V Output current -2.0 mA,
ports P0.3-P0.0, P1.7P1.0, P2.7-P2.4, P2.2P2.0
Logic "1" output voltage 2.5
VDD V Output current 2.0mA,
ports P0.3-P0.0, P1.7P1.0, P2.7-P2.4, P2.2P2.0
Logic "0" output voltage 0
0.4 V Output current -8.0 mA,
port P2.3
Logic "1" output voltage 2.5
VDD V Output current 8.0mA,
port P2.3
Logic "0" input current
NA -1
A
Input signal equals GND
Logic "1" input current
NA 1
A
Input signal equals VDD
Table 3. DC Characteristics
0
5
10
15
20
25
04812162024
Frequency [MHz]
Supply current [m A]
Figure 1. Typical CPU core supply current vs. clock frequency
CC1010
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5. Electrical Specifications
Tc = 25C, VDD = 3.3 V if nothing else stated
All electrical specifications are measured on Chipcon’s CC1010EM reference design.
Parameter
Min. Typ. Max. Unit Condition
Power on reset (POR) voltage 2.7 2.9 3.1 V Tc = -40 to 85°C
Brown out voltage 2.7 2.9 3.1 V Tc = -40 to 85°C
RTC start-up time 160 ms
Current consumption MCU,
Active mode
14.8
1.3
mA
mA
14.7456 MHz, main oscillator
32 kHz, RTC oscillator
See page 33 for explanation
of modes. See Figure 1 page
6 for supply current vs. clock
frequency
Current consumption MCU, Idle
mode
12.8
29.4
mA
A
14.7456 MHz, main oscillator
32 kHz, RTC oscillator
Current consumption, Power
Down mode
0.2 1
A
Current consumption, Poweron reset circuit (when enabled)
34 uA
Current consumption Main
crystal oscillator
67 µA 14.7456 MHz crystal
Current consumption RF
Transceiver, Receive mode,
433/868 MHz
9.1/
11.9
mA Current for RF transceiver
alone
Current consumption RF
Transceiver, Transmit mode,
433/868 MHz
P=0.01 mW (-20 dBm)
P=0.3 mW (-5 dBm)
P=1 mW (0 dBm)
P=2.5 mW (4 dBm)
P=10 mW (10 dBm)
5.3/8.6
8.9/13.8
10.4/17
24.8/
23.5
26.6/NA
mA
mA
mA
mA
mA
The output power is delivered
to a single-ended 50 load,
see also page 123. Current is
for RF transceiver alone
32 kHz oscillator crystal load
capacitance
12 pF
Table 4. Electrical specifications
CC1010
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6. ADC
Parameter
Min. Typ. Max. Unit Condition
Number of bits 10 bits
Differential Nonlinearity (DNL) +/-0.2 LSB VDD is reference voltage
Integral Nonlinearity (INL)
+/-1.3 LSB VDD is reference voltage
Offset 3 LSB 7 Hz test tone
Total Harmonic Distortion
(THD)
59 dB 7 Hz test tone
SINAD 54
9
dB
bits
7 Hz test tone
Internal reference tolerance
± 10 %
Conversion time 44 µs When ADC is operated at 250
kHz
Clock frequency 32 250 250 kHz 250 kHz recommended for full
10-bit performance
External reference voltage 1.3 2.7 V External reference voltage
should never exceed 2.7 V. It
is recommended to use a
reference voltage close to 1.3
V to have the best possible
linearity.
Input voltage 0 Vref V
Table 5. ADC characteristics
7. RF section, general
Parameter
Min. Typ. Max. Unit Condition
RF Frequency Range 300
1000 MHz Programmable in steps of
< 250 Hz
Data rate
0.6 76.8 kBaud NRZ or Manchester encoding.
76.8 kBaud equals 76.8 kbps
using NRZ coding. See page
94
Table 6 General RF characteristics
CC1010
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8. RF transmit section
Parameter
Min. Typ. Max. Unit Condition
Binary FSK frequency
separation
0 64 65 kHz The frequency corresponding
to the digital "0" is denoted f
0
,
while f
1
corresponds to a
digital "1".
The frequency separation is
f
1-f0
. The RF carrier
frequency, f
c
, is then given by
f
c
=(f0+f1)/2.
(The frequency deviation is
given by fd=+/-(f1-f0)/2 )
The frequency separation is
programmable in 250 Hz
steps. Separations up to 65
kHz are guaranteed at 1 MHz
reference frequency. Larger
separations can be achieved
at higher reference
frequencies
Output power
433 / 868 MHz
-20 0 10/4 dBm Delivered to single-ended 50
load.
The output power is
programmable, see page 123
RF output impedance
433 / 868 MHz
140/80
Transmit mode, optimum load
impedance. For matching
details see “Input/ output
matching” p.120
Harmonics
2
nd
harmonic, 433 / 868 MHz
3
rd
harmonic, 433 / 868 MHz
-7/-15
-27/-29
dBm
Conducted measur at
maximum output power. An
external LC filter should be
used to reduce harmonics
emission to comply with SRD
requirements. See p.128
Table 7. RF transmit characteristics
CC1010
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9. RF receive section
Parameter
Min. Typ. Max. Unit Condition
Receiver Sensitivity,
433 / 868 MHz
-107/
-106
dBm 2.4 kBaud, Manchester coded
data, 64 kHz frequency
separation, BER = 10-3
See Table 33 and Table
34page 105 for typical
sensitivity figures at other
data rates.
System noise bandwidth 30 kHz 2.4 kBaud, Manchester coded
data
Cascaded noise figure
433/868 MHz
12/13 dB
Saturation (maximum input
level)
10 dBm 2.4 kBaud, Manchester coded
data, BER = 10
-3
-1 dBm 76.8 kBaud NRZ, BER = 10-3
Input IP3 -26 dBm From LNA to IF output
Blocking 40 dBc At +/- 1 MHz
LO leakage -57 dBm
Input impedance
90-j13
68-j24
36-j11
36-j13
Receive mode, series
equivalent
at 315 MHz
at 433 MHz
at 868 MHz
at 915 MHz
For matching details see
“Input/ output matching” p.
120.
Turn on time 11 128 Baud The demodulator settling
time, which is programmable,
determines the turn-on time.
See page 97 for details.
Table 8. RF receive characteristics
CC1010
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10. IF section
Parameter
Min. Typ. Max. Unit Condition
Intermediate frequency (IF)
433/868 MHz
150/
130
10.7
kHz
MHz
Internal IF filter
External IF filter
IF bandwidth (noise bandwidth) 175 kHz
RSSI dynamic range
-105 -60 dBm
RSSI 3-dB bandwidth 260 kHz 868 MHz CW, -70 dBm
RSSI accuracy
6
dB See p. 126 for details
RSSI linearity
2
dB
Table 9 IF characteristics
CC1010
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11. Frequency synthesizer section
Parameter
Min. Typ. Max. Unit Condition
Crystal Oscillator Frequency 3 24 MHz Crystal frequency can be 3-4,
6-8 or 9-24 MHz.
Recommended frequencies
are 3.6864, 7.3728, 11.0592,
14.7456, 18.4320 and
22.1184 MHz. See page 32
for details
Crystal frequency accuracy
requirement
50
25
ppm 433 MHz
868 MHz
The crystal frequency
accuracy and drift (ageing
and temperature
dependency) will determine
the frequency accuracy of the
transmitted signal.
Crystal operation
Parallel
C171 and C181 are loading
capacitors
Crystal load capacitance 12
12
12
12
20
16
16
12
30
30
16
16
pF
pF
pF
pF
3-4 MHz, 20 pF recommended
6-8 MHz, 16 pF recommended
9-16 MHz, 16 pF recommended
16-24 MHz, 12 pF recommended
Crystal oscillator start-up time 5
1.5
2
ms
ms
ms
3.6864 MHz, 16 pF load
7.3728 MHz, 16 pF load
16 MHz, 16 pF load
Output signal phase noise
-85 dBc/Hz At 100 kHz offset from carrier
PLL lock time (RX / TX turn
time)
200
s
PLL turn-on time 250
s
Table 10. Frequency synthesizer characteristics
CC1010
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12. Pin Configuration
17
AGND
CC1010
1AVDD
2AVDD
3AGND
4RF_IN
5RF_OUT
6AVDD
7AGND
8AGND
9AGND
10L1
11L2
12AVDD
13CHP_OUT
14R_BIAS
15AVDD
16AGND
18
XOSC_Q119XOSC_Q2
20
XOSC32_Q2
21
XOSC32_Q1
22
AGND
23
DGND24DGND
25
POR_E
26
P1.0
27
(RXD1) P2.0
28
(TXD1) P2.1
29
(PWM3) P3.5
30
(PWM2) P3.4
31
(INT1) P3.3
32
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
DGND
P3.0 (RXD0)
P3.1 (TXD0)
P3.2 (INT0)
P2.5
P2.4
DVDD
P2.3
DGND
DVDD
P2.2
P1.4
P1.3
P1.2
P1.1
P0.1 (MOSI)
P0.0 (SCK)
AGND
AD2 (RSSI/IF)
AD1
AD0
DVDD
RESET
PROG
P2.7
P2.6
P1.7
P1.6
P1.5
P0.3
P0.2 (MISO)
DVDD
DGND
(Top view)
Pin
#
Pin name Alternate
function
Pin type Description
1 AVDD - Power (A) Power supply ADC
2 AVDD - Power (A) Power supply Mixer and IF
3 AGND - Power (A) Ground connection Mixer and IF
4 RF_IN - RF input RF signal input from antenna (external AC-
coupling)
5 RF_OUT - RF output RF signal output to antenna
6 AVDD - Power (A) Power supply LNA and PA
7 AGND - Power (A) Ground connection LNA and PA
8 AGND - Power (A) Ground connection PA
9 AGND - Power (A) Ground connection VCO and prescaler
10 L1 - Analog Connection #1 for external VCO tank
inductor
11 L2 - Analog Connection #2 for external VCO tank
inductor
12 AVDD - Power (A) Power supply VCO and prescaler
CC1010
SWRS047 Page 14 of 152
Pin
#
Pin name Alternate
function
Pin type Description
13 CHP_OUT - Analog output Charge pump current output when external
loop filter is used
14 R_BIAS - Analog Connection for external precision bias
resistor (82 k, 1%)
15 AVDD - Power (A) Power supply misc. analog modules
16 AGND - Power (A) Ground connection misc. analog modules
17 AGND - Power (A) Analog ground connection
18 XOSC_Q1 - Analog input 3-24 MHz crystal, pin 1 or external clock
input
19 XOSC_Q2 - Analog output 3-24 MHz crystal, pin 2
20 XOSC32_Q2 - Analog output 32 kHz crystal pin2
21 XOSC32_Q1 - Analog input 32 kHz crystal pin1 or external clock input
22 AGND - Power (A) Analog ground connection
23 DGND - Power (D) Digital ground connection
24 DGND - Power (D) Digital ground connection
25 POR_E - Digital input Power-on reset enable.
0: Disable internal power-on reset module
1: Enable internal power-on reset module
26 P1.0 - Digital high-Z I/O 8051 port 1, bit 0
27 P2.0 RXD1 (I) Digital high-Z I/O 8051 port 2, bit 0 or RX of serial port 1
28 P2.1 TXD1 (O) Digital high-Z I/O 8051 port 2, bit 1 or TX of serial port 1
29 P3.5 PWM3 (O)
T1 (I)
Digital high-Z I/O 8051 port 3, bit 5 or pulse width modulator
3's output or Timer / Counter 1 external input
30 P3.4 PWM2 (O)
T0 (I)
Digital high-Z I/O 8051 port 3, bit 4 or pulse width modulator
2's output or Timer / Counter 0 external input
31 P3.3
INT1
(I)
Digital high-Z I/O 8051 port 3, bit 3 or interrupt 1 input
configurable as level or edge sensitive
32 DGND - Power (D) Ground connection digital part
33 P0.0 SCK (O)
SCK (I)
Digital high-Z I/O 8051 port 0, bit 0 or SPI master interface
serial clock output or Flash programming
SPI slave clock input.
34 P0.1 MO (O)
SI (I)
Digital high-Z I/O 8051 port 0, bit 1 or SPI interface master
output or Flash programming SPI slave
serial data input
35 P1.1 - Digital high-Z I/O 8051 port 1, bit 1
36 P1.2 - Digital high-Z I/O 8051 port 1, bit 2
37 P1.3 - Digital high-Z I/O 8051 port 1, bit 3
38 P1.4 - Digital high-Z I/O 8051 port 1, bit 4
39 P2.2 - Digital high-Z I/O
(Schmitt trigger
input)
8051 port 2, bit 2
40 DVDD - Power (D) Digital power supply
41 DGND - Power (D) Ground connection digital part
42 P2.3 - Digital high-Z I/O (8
mA)
8051 port 2, bit 3
43 DVDD - Power (D) Digital power supply
44 P2.4 - Digital high-Z I/O 8051 port 2, bit 4
45 P2.5 - Digital high-Z I/O 8051 port 2, bit 5
46 P3.2
INT0
(I)
Digital high-Z I/O 8051 port 3, bit 2 or interrupt 0 input
configurable as level or edge sensitive
47 P3.1 TXD0 (O) Digital high-Z I/O 8051 port 3, bit 1 or TX of serial port 0
48 P3.0 RXD0 (I) Digital high-Z I/O 8051 port 3, bit 0 or RX of serial port 1
49 DGND - Power (D) Digital ground connection
50 DVDD - Power (D) Digital power supply
CC1010
SWRS047 Page 15 of 152
Pin
#
Pin name Alternate
function
Pin type Description
51 P0.2 MI (I)
SO (O)
Digital high-Z I/O 8051 port 0, bit 2 or SPI interface master
input or Flash programming SPI slave serial
data output
52 P0.3 - Digital high-Z I/O 8051 port 0, bit 3
53 P1.5 - Digital high-Z I/O 8051 port 1, bit 5
54 P1.6 - Digital high-Z I/O 8051 port 1, bit 6
55 P1.7 - Digital high-Z I/O 8051 port 1, bit 7
56 P2.6 - Digital high-Z I/O 8051 port 2, bit 6
57 P2.7 - Digital high-Z I/O 8051 port 2, bit 7
58
PROG
- Digital input Flash program enable pad, active low
59
RESET
- Digital input (pull-up) System reset pin, active low
60 DVDD - Power (D) Digital power supply
61 AD0 - Analog input ADC input channel 0
62 AD1 - Analog input ADC input channel 1
63 AD2 RSSI (O),
IF (O)
Analog input/output ADC input channel 2, RSSI (Receiver signal
strength indicator) output, or IF output when
using external demodulator
64 AGND - Power (A) Analog ground connection ADC
A = Analog, D = Digital, I = input, O= Output
13. Pin description
AVDD, DVDD
Supply voltages for analog and digital
modules respectively. All supply pins
should be decoupled by capacitors. In
particular, the digital and analog supply
domains should be properly decoupled
from each other (a ferrite bead can be
used to prevent high-frequency noise from
coupling from one supply domain to
another). The placement and size of
decoupling capacitors and supply filtering
are critical with respect to LO leakage and
sensitivity. Chipcon’s reference layout
designs should be used (available from
Chipcon’s website). See also page 133 for
layout recommendations.
AGND, DGND
Ground for analog and digital modules
respectively. Normally one common
ground plane is recommended. If two
separate analog and digital grounds are
used they should be interconnected in one
place, and one place only.
RFIN
This is the RF input, internally connected
to the low noise amplifier (LNA). The
signal source (antenna) should be
matched to the input impedance. A DC
ground is needed for LNA biasing.
RFOUT
This is the RF output, internally connected
to the power amplifier (PA). The external
load (antenna) should be matched to the
output impedance (optimum load
impedance). This pin must be DC coupled
to AVDD for PA biasing (open drain
output).
L1, L2
Connection to internal voltage controlled
oscillator (VCO). An inductor should be
connected between these pins. The
inductor value will determine the VCO
tuning range. The inductor should be place
very close to the pins in order to minimize
paracitic inductance.
CHP_OUT
Charge Pump output. If the RF transceiver
is configured for external loop filter this is
the current output from the charge pump.
Normally the internal loop filter should be
used and this pin should be left open (not
connected).
CC1010
SWRS047 Page 16 of 152
RBIAS
Current output from internal band gap cell
bias generator. A precision resistor (82
k, 1%) should be connected between
this pin and ground to set the correct bias
current level.
XOSC_Q1, XOSC_Q2
These are the main oscillator connection
pins. An external crystal should be
connected between these pins, and load
capacitors should be connected between
each pin and ground. If an external
oscillator is used, the clock signal should
be connected to the XOSC_Q1 pin, and
XOSC_Q2 should be left open (not
connected).
XOSC32_Q1, XOSC32_Q2
These are the real time clock (RTC)
oscillator connection pins. An external
crystal should be connected between
these pins, and load capacitors should be
connected between each pin and ground.
If an external oscillator is used, the clock
signal should be connected to the
XOSC32_Q1 pin, and XOSC32_Q2
should be left open (not connected).
POR_E
Enable signal for the on-chip power-on
reset module. The power-on reset is
enabled when POR_E is connected to
DVDD and disabled when connected to
DGND.
PROG
Active low Flash programming enable pin.
When this signal is active (driven to DGND)
a Flash programmer can be connected to
the SPI interface. Under normal operation
it must be driven to DVDD.
RESET
Active low asynchronous system reset. It
has an internal pull-up resistor and can be
left unconnected during normal operation.
AD0, AD1
Analog inputs to A/D converter channels 0
and 1 respectively. When not used these
pins can be left open (not connected).
AD2 (RSSI/IF)
Analog input to A/D converter channel 2.
This pin can also be configured to be RSSI
output or IF output. The pin is configured
by the FREND register. When not used this
pin can be left open (not connected).
PORT 0
Port 0 is a 4-bit (P0.3-P0.0) bi-directional
CMOS I/O port with 2 mA drivers. A
direction register (P0DIR) controls whether
each pin is an output or input and the
register P0 is used to read the input or
control the logical value of the output.
Pins P0.0 - P0.2 can be configured to
become a master SPI interface in register
SPCR and will then override P0(2:0),
P0DIR(2) and P0DIR(1).
Used as SPI interface, P0.0 is SCK,
P0.1 is MOSI, and P0.2 is MISO.
PORT 1
Port 1 is an 8-bit (P1.7-P1.0) bidirectional CMOS I/O port with 2 mA
drivers. A direction register (P1DIR)
controls whether each pin is an output or
input and the register P1 is used to read
the input or control the logical value of the
output.
PORT 2
Port 2 is an 8-bit (P2.7-P2.0) bidirectional CMOS I/O port with 2 mA
drivers, except for P2.3 that has an 8 mA
output buffer. A direction register (P2DIR)
controls whether each pin is an output or
input and the register P2 is used to read
the input or control the logical value of the
output.
Pins P2.0 and P2.1 can be configured to
become the RXD1 and TXD1 pin,
respectively, of UART 1.
Pin P2.2 has a Schmitt-trigger input
stage. Note that while this pin does have
hysteresis, it will draw a large input current
(~0.5 mA) if the input voltage is close to
VDD/2.
PORT 3
Port 3 is a 6-bit (P3.5-P3.0) bi-directional
CMOS I/O port with 2 mA drivers. A
direction register (P3DIR) controls whether
each pin is an output or input. The register
P3 is used to read the input or control the
logical value of the output.
CC1010
SWRS047 Page 17 of 152
Pins P3.0 and P3.1 can be configured to
become the RXD0 and TXD0 pin,
respectively, of UART 0.
Pins P3.2 and P3.3 are connected to the
external interrupt inputs
INT0 and
INT1
,
respectively, and can cause interrupts if
the corresponding interrupt enable flags
are set in register
IE. The interrupts inputs
can be configured to be either levelsensitive or edge-sensitive.
Pins
P3.4 and P3.5 can be configured to
become the pulse width modulator (PWM)
outputs of Timer/PWM 2 and Timer/PWM
3, respectively. When pulse width
modulation is enabled the corresponding
bits in
P3DIR and P3 are overridden.
CC1010
SWRS047 Page 18 of 152
14. Block Diagram
The
CC1010
Block Diagram is shown in Figure 2 below.
Figure 2. CC1010 Block Diagram
32 kB
FLASH
128 byte
SRAM
Special Function
Registers
(SFRs)
Interrupt
Controller
Realtime
Clock
Watchdog
Timer
SPI
Timers/
Counters
Timers/
PWMs
UARTs
UARTs
General
purpose I/O
CODEC, Bit synchronizer,
Serializer/Deserializer
IF stage MODEM
RF Transceiver
8051 core
FLASH
Programming DMA
DES Module
2048 byte
SRAM
RAM Arbiter
Reset
Generation
3-24 MHz crystal
32 kHz crystal
Clock
Multiplexer
System
clock
Port 0
Port 1
Port 2
Port 3
RESET
PROG
RF_IN
ADC
Programmable I/O (General purpose or alternate function)
Power-on
reset
POR_E
Main Crystal
Oscillator
:R
:N.n
RF_OUT
LPF CHP PD
MUX
RSSIIF
Bias
Bias resistor
VCO inductor
VCO
CHP_OUT
AD2
(RSSI/IF)
AD0
AD1
PA
LNA
MIXER
L1 L2
CC1010
SWRS047 Page 19 of 152
15. 8051 Core
15.1 General description
The
CC1010
microcontroller core is based
on the industry-standard 8051
architecture. The MCU core is 8-bit, with
program and data memory located in
separate memory spaces (Harvard
architecture). The internal registers are
organised as four banks of 8 registers
each. The instruction set supports direct,
indirect and register addressing modes.
Program memory can be addressed using
indexed addressing. The core registers
are comprised of an accumulator, a stack
pointer and dual data pointer registers in
addition to the general registers.
Data memory is split into internal and
external RAM. The name "external RAM"
is in fact misleading since in the case of
the
CC1010
all the RAM is internal to the
chip. The difference between external and
internal is that external RAM can only be
accessed by a few instructions. Therefore,
frequently-accessed variables as well as
the stack should be kept in internal RAM.
The various peripherals are controlled
through Special Function Registers
(SFRs) located in the internal RAM space.
The 8051 core is instruction set
compatible with the industry standard
8051. It also has one additional instruction,
TRAP, to enable advanced in-circuit-
debugging features. This is described on
page 44.
The instruction cycle time is 4 clock
cycles, which typically gives a 2.5X
average reduction in instruction execution
time over the original Intel 8051.
Peripheral units, including general purpose
I/O, 2 standard 8051 timers, 2 extra timers
with PWM functionality, a watchdog timer,
a real-time clock, an SPI master interface,
hardware DES encryption, a true random
bit generator and ADC are all described
from page 47 and out. Dual data pointers
are available for faster data transfer.
15.2 Reset
CC1010
must be reset at start-up. There
are several sources for reset in
CC1010
:
External reset pin, RESET
. Applying
a low signal to this pin at any time will
reset almost all registers in
CC1010
.
Exceptions can be found in Table 41
on page 144. The input is
asynchronous and is synchronised
internally, so that the reset can be
released independent of the timing of
the active clock signal. If the main
crystal oscillator is inactive, the reset
input should be held long enough for
the oscillator to start up and stabilize.
See Electrical Specifications page 7
for oscillator start-up timing.
Power On Reset (POR). The internal
POR module can generate reset upon
power-up. Special requirements for
power consumption or power supply
voltage may require an external POR
module, as described in the Power On
Reset (Brown-Out Detection) section
at page 62.
Brown-out detection reset. The POR
will also detect low supply voltage and
generate a reset.
Watchdog timer reset. The watchdog
timer can generate a reset, as
described in the section on page 63.
ADC reset. The ADC module can be
programmed to generate a reset
signal if its inputs exceed a
programmed threshold. See the ADC
section on page 79 for details.
The POR and ADC reset signals will be
held for 1024 clock periods after the signal
is released. This will ensure a safe clock
start-up if the crystal oscillator is currently
not running.
CC1010
SWRS047 Page 20 of 152
15.3 Memory Map
The
CC1010
memory map is shown in
Figure 3.
CC1010
has 2 blocks of RAM on chip. This
includes the 128 bytes Internal RAM and
the 2048 bytes External RAM. (The 2048byte RAM will be referred to as External
RAM, although it is on-chip. Direct access
to off-chip RAM is not implemented.)
Access to the internal RAM is performed
using the MOV instruction. MOV A, @Ri,
MOV @Ri, A and MOV @Ri, #data use
indirect addressing. MOV A, direct,
MOV Rn, direct, MOV direct, A,
MOV direct, Rn, MOV direct,
direct and MOV direct, #data use
direct addressing. MOV @Ri, direct
uses indirect and direct addressing.
All direct addressing instructions can also
be used to access the SFRs.
CC1010
also
implements the option to access SFRs
indirectly, as described in the In Circuit
Debugging section on page 44.
CC1010
has
dual data pointers to external RAM,
provided in the 16 bit registers
DPTR0 and
DPTR1 (SFRs DPH0, DPL0, DPH1 and
DPL1). If a high-level language compilator
is used, it should be set up to make use of
both pointers for better performance. The
data pointer is selected through
DPS.SEL.
Access to the external RAM is performed
using the MOVX instruction and indirect
addressing using either the 16 bit data
pointers or the 8 bit registers R0 or R1
together with
MPAGE. MOVX A, @DPTR
and MOVX @DPTR, A
moves data to (from) the accumulator,
from (to) the address pointed to by the
currently selected data pointer.
The instructions MOVX A, @Ri and MOVX
@Ri, A moves data to (from) the
accumulator, from (to) the address given
by the memory page address register
MPAGE and the register Ri (R0 or R1).
MPAGE gives the 8 most significant
address bits, while the register Ri gives
the 8 least significant bits. In many 8051
implementations, this type of external
RAM access is performed using
P2 to give
the most significant address bits. Existing
software may therefore have to be
adapted to make use of
MPAGE instead of
P2.
The program memory can be read using
the MOVC A, @A+DPTR and MOVC A,
@A+PC instructions, which moves a byte
from the program memory address given
by A+DPTR or A+PC respectively. The
program memory can not be written using
MOV commands, but uses the method
described in the 8051 Flash Programming
section on page 42.
CC1010
also provides a possibility to stretch
the access cycle to external RAM, through
CKCON.MD(2:0) (see page 55). The
default value for
CKCON.MD is "001". It is
recommended to set
CKCON.MD to "000"
for faster RAM access.
CC1010
SWRS047 Page 21 of 152
Internal RAM
Accessible
through Direct
and Indirect
Addressing
0x00
0x7F
Special Function
Registers (SFR),
accessible
through Direct
Addressing
0xFF
Accesible
through indirect
addressing
0x7FF
Internal RAM / SFR
External RAM
0x00
Flash Program
Memory
0x00
Accesible
through indirect
addressing
0x7FFF
Figure 3. Memory Map
DPL0 (0x82) - Data Pointer 0, low byte
Bit Name R/W Reset value Description
7:0
DPL0(7:0)
R/W 0x00 Data Pointer 0, low byte
DPH0 (0x83) - Data Pointer 0, high byte
Bit Name R/W Reset value Description
0
DPH0(7:0)
R/W 0x00 Data Pointer 0, high byte
DPL1 (0x84) - Data Pointer 1, low byte
Bit Name R/W Reset value Description
7:0
DPL1(7:0)
R/W 0x00 Data Pointer 1, low byte
DPH1 (0x85) - Data Pointer 1, high byte
Bit Name R/W Reset value Description
7:0
DPH1(7:0)
R/W 0x00 Data Pointer 1, high byte
CC1010
SWRS047 Page 22 of 152
DPS (0x86) - Data Pointer Select
Bit Name R/W Reset value Description
7:1
-
R0 0x00 Reserved, read as 0
0
SEL
R/W 0x00 Data Pointer Select for external RAM access
0 :
DPH0 and DPL0 are used
1 :
DPH1 and DPL1 are used
MPAGE (0x92) - Memory Page Select Register
Bit Name R/W Reset value Description
7:0
MPAGE(7:0)
R/W 0x00 Memory Page
A total of 119 Special Function Registers
(SFRs) are accessible from the
microcontroller core. The names and
addresses of all SFRs are listed in Table
11. All standard 8051 registers are
available, in addition to SFRs which are
CC1010
specific, controlling modules such
as the RF Transceiver, DES encryption,
ADC and Real-Time Clock.
All SFRs will be described in the following
sections. A more detailed overview is
provided in Table 41 on page 144, which
also includes all reset values. SFRs with
addresses ending with 0 or 8 (leftmost
column of Table 11) are bit adressable.
0/8 1/9 2/A 3/B 4/C 5/D 6/E 7/F
0xF8
EIP TEST0 TEST1 TEST2 TEST3 TEST4 TEST5 TEST6
0xF0
B FSHAPE7 FSHAPE6 FSHAPE5 FSHAPE4 FSHAPE3 FSHAPE2 FSHAPE1
0xE8
EIE FSDELAY FSEP0 FSEP1 FSCTRL RTCON FREND TESTMUX
0xE0
ACC CURRENT PA_POW PLL LOCK CAL PRESCALER RESERVED
0xD8
EICON MODEM2 MODEM1 MODEM0 MATCH FLTIM - -
0xD0
PSW X32CON WDT PDET BSYNC - - -
0xC8
RFMAIN RFBUF FREQ_0A FREQ_1A FREQ_2A FREQ_0B FREQ_1B FREQ_2B
0xC0
SCON1 SBUF1 RFCON CRPCON CRPKEY CRPDAT CRPCNT RANCON
0xB8
IP RDATA RADRL RADRH CRPINI4 CRPINI5 CRPINI6 CRPINI7
0xB0
P3 - - - CRPINI0 CRPINI1 CRPINI2 CRPINI3
0xA8
IE TCON2 T2PRE T3PRE T2 T3 FLADR FLCON
0xA0
P2 SPCR SPDR SPSR P0DIR P1DIR P2DIR P3DIR
0x98
SCON0 SBUF0 - - - - - CHVER
0x90
P1 EXIF MPAGE ADCON ADDATL ADDATH ADCON2 ADTRH
0x88
TCON TMOD TL0 TL1 TH0 TH1 CKCON -
0x80
P0 SP DPL0 DPH0 DPL1 DPH1 DPS PCON
Table 11
CC1010
SFR Overview
CC1010
SWRS047 Page 23 of 152
15.4 CPU Registers
CC1010
provides 4 register banks of 8
registers each. These register banks are
mapped in the the internal data memory
(see the Memory section on page 33) at
addresses 0x00 - 0x07, 0x08 - 0x0F, 0x10
- 0x17 and 0x18 - 0x1F. Each register
bank contains the 8 8-bit registers R0
through R7. The different register banks
are selected through the Program Status
Word
PSW.RS(1:0) as shown below.
PSW also contains carry, overflow and
parity flags that reflect the current CPU
state.
In addition, the CPU uses the accumulator
register
A (accessed via the SFR space as
ACC), B (for multiplication and division) and
the stack pointer
SP. These registers are
shown below. Note that the hardware
stack pointer
SP is increased when
pushing and decreased when popping
data, unlike many other microcontroller
architectures.
PSW (0xD0) - Program Status Word
Bit Name R/W Reset value Description
7
CY
R/W 0 Carry Flag, set to 1 when the last arithmetic
operation resulted in a carry (during addition) or
borrow (during subtraction), otherwise cleared to
0 by all arithmetic operations.
CY is also used for
rotation instructions.
6
AC
R/W 0 Auxiliary carry flag. Set to 1 when the last
arithmetic operation resulted in a carry into
(during addition) or borrow from (during
subtraction) the high order nibble, otherwise
cleared to 0 by all arithmetic operations.
5
F0
R/W 0 Flag 0 (Available to the user for general purpose)
4
RS1
R/W 0
3
RS0
R/W 0
Register bank select.
RS1 RS0 Working register bank and address
0 0 Bank0 0x00-0x07
0 1 Bank1 0x08-0x0F
1 0 Bank2 0x10-0x17
1 1 Bank3 0x18-0x1F
2
OV
R/W 0 Overflow flag. Set to 1 when the last arithmetic
operation resulted in a carry (addition), borrow
(subtraction), or overflow (multiply or divide).
Otherwise, the bit cleared to 0 by all arithmetic
operations.
1
F1
R/W 0 Flag 1 (Available to the user for general purpose)
0
P
R/W 0 Parity flag. Set to 1 when the modulo-2 sum of
the 8 bits in the accumulator is 1 (odd parity),
cleared to 0 on even parity.
ACC (0xE0) - Accumulator Register
Bit Name R/W Reset value Description
7:0
ACC(7:0)
R/W 0x00 Accumulator
B (0xF0) - B Register
Bit Name R/W Reset value Description
7:0
B(7:0)
R/W 0x00
B is used for multiplication and division
CC1010
SWRS047 Page 24 of 152
SP (0x81) - Stack Pointer
Bit Name R/W Reset value Description
7:0
SP(7:0)
R/W 0x07 Stack Pointer, used for pushing and poping data
to and from the stack. Note that the reset value
for
SP is 0x07
15.5 Instruction Set Summary
The 8051 instruction set is summarised in
Table 12 below. All mnemonics are
Copyright Intel Corporation 1980.
One non-standard 8051 instruction, TRAP,
with opcode 0xA5 is included to enable
setting of breakpoints. This instruction is
described in the In Circuit Debugging
section at page 44. Symbols used in the
table are:
A - Accumulator
AB - Register pair A and B
B - Multiplication register
C - Carry flag
DPTR - Data pointer
Rn - Register R0 - R7
PC - Program counter
direct - 8-bit data address (Internal
RAM 0x00 - 0x7F, SFRs 0x80-0xFF)
@Ri - Internal register pointed to by R0
or R1 (except MOVX)
rel - Two's complement offset byte
used by SJMP and conditional jumps
bit - Direct bit address
#data - 8-bit constant
#data 16 - 16-bit constant
addr 16 - 16-bit destination address
addr 11 - 11-bit destination address,
used by ACALL and AJMP. The branch
will be within the same 2 kB block of
program memory of the first byte of
the following instruction.
The ‘Bytes’ column shows the number of
bytes of Flash memory used. Further, the
number of instruction cycles is shown.
Each instruction cycle requires four clock
cycles. The 4 rightmost columns shows
which flags in the program status word
PSW (see page 23) are affected by the
instructions.
Mnemonic Description
Bytes
Instr. Cycles
Hex Opcode
CY
AC
OV
P
Arithmetic
ADD A, Rn
Add register to A 1 1 28-2F x x x x
ADD A, direct
Add direct byte to A 2 2 25 x x x x
ADD A, @Ri
Add data memory to A 1 1 26-27 x x x x
ADD A, #data
Add immediate to A 2 2 24 x x x x
ADDC A, Rn
Add register to A with carry 1 1 38-3F x x x x
ADDC A, direct
Add direct byte to A with carry 2 2 35 x x x x
ADDC A, @Ri
Add data memory to A with carry 1 1 36-37 x x x x
ADDC A, #data
Add immediate to A with carry 2 2 34 x x x x
SUBB A, Rn
Subtract register from A with
borrow
1 1 98-9F x x x x
SUBB A, direct
Subtract direct byte from A with
borrow
2 2 95 x x x x
CC1010
SWRS047 Page 25 of 152
Mnemonic Description
Bytes
Instr. Cycles
Hex Opcode
CY
AC
OV
P
SUBB A, @Ri
Subtract data memory from A with
borrow
1 1 96-97 x x x x
SUBB A, #data
Subtract immediate from A with
borrow
2 2 94 x x x x
INC A
Increment A 1 1 04 x
INC Rn
Increment register 1 1 08-0F
INC direct
Increment direct byte 2 2 05
INC @Ri
Increment data memory 1 1 06-07
DEC A
Decrement A 1 1 14 x
DEC Rn
Decrement register 1 1 18-1F
DEC direct
Decrement direct byte 2 2 15
DEC @Ri
Decrement data memory 1 1 16-17
INC DPTR
Increment data pointer 1 3 A3
MUL AB
Multiply A by B 1 5 A4 x x x
DIV AB
Divide A by B 1 5 84 x x x
DA A
Decimal adjust A 1 1 D4 x x
Logical
ANL A, Rn
AND register to A 1 1 58-5F x
ANL A, direct
AND direct byte to A 2 2 55 x
ANL A, @Ri
AND data memory to A 1 1 56-57 x
ANL A, #data
AND immediate to A 2 2 54 x
ANL direct, A
AND A to direct byte 2 2 52
ANL direct, #data
AND immediate data to direct byte 3 3 53
ORL A, Rn
OR register to A 1 1 48-4F x
ORL A, direct
OR direct byte to A 2 2 45 x
ORL A, @Ri
OR data memory to A 1 1 46-47 x
ORL A, #data
OR immediate to A 2 2 44 x
ORL direct, A
OR A to direct byte 2 2 42
ORL direct, #data
OR immediate data to direct byte 3 3 43
XRL A, Rn
Exclusive-OR register to A 1 1 68-6F x
XRL A, direct
Exclusive-OR direct byte to A 2 2 65 x
XRL A, @Ri
Exclusive-OR data memory to A 1 1 66-67 x
XRL A, #data
Exclusive-OR immediate to A 2 2 64 x
XRL direct, A
Exclusive-OR A to direct byte 2 2 62
XRL direct, #data
Exclusive-OR immediate to direct
byte
3 3 63
CLR A
Clear A 1 1 E4 x
CPL A
Complement A 1 1 F4 x
SWAP A
Swap nibbles of A 1 1 C4
RL A
Rotate A left 1 1 23
RLC A
Rotate A left through carry 1 1 33 x x
RR A
Rotate A right 1 1 03
RRC A
Rotate A right through carry 1 1 13 x x
Data Transfer
MOV A, Rn
Move register to A 1 1 E8-
EF
x
MOV A, direct
Move direct byte to A 2 2 E5 x
CC1010
SWRS047 Page 26 of 152
Mnemonic Description
Bytes
Instr. Cycles
Hex Opcode
CY
AC
OV
P
MOV A, @Ri
Move data memory to A 1 1 E6-
E7
x
MOV A, #data
Move immediate to A 2 2 74 x
MOV Rn, A
Move A to register 1 1 F8-FF
MOV Rn, direct
Move direct byte to register 2 2 A8-
AF
MOV Rn, #data
Move immediate to register 2 2 78-7F
MOV direct, A
Move A to direct byte 2 2 F5
MOV direct, Rn
Move register to direct byte 2 2 88-8F
MOV direct,
direct
Move direct byte to direct byte 3 3 85
MOV direct, @Ri
Move data memory to direct byte 2 2 86-87
MOV direct, #data
Move immediate to direct byte 3 3 75
MOV @Ri, A
MOV A to data memory 1 1 F6-F7
MOV @Ri, direct
Move direct byte to data memory 2 2 A6-
A7
MOV @Ri, #data
Move immediate to data memory 2 2 76-77
MOV DPTR, #data
Move immediate to data pointer 3 3 90
MOVC A, @A+DPTR
Move code byte relative DPTR to A 1 3 93 x
MOVC A, @A+PC
Move code byte relative PC to A 1 3 83 x
MOVX A, @Ri
Move external data (A8) to A 1 2-9 E2-
E3
x
MOVX A, @DPTR
Move external data (A16) to A 1 2-9 E0 x
MOVX @Ri, A
Move A to external data (A8) 1 2-9 F2-F3
MOVX @DPTR, A
Move A to external data (A16) 1 2-9 F0
PUSH direct
Push direct byte onto stack 2 2 C0
POP direct
Pop direct byte from stack 2 2 D0
XCH A, Rn
Exchange A and register 1 1 C8-
CF
x
XCH A, direct
Exchange A and direct byte 2 2 C5 x
XCH A, @Ri
Exchange A and data memory 1 1 C6-
C7
x
XCHD A, @Ri
Exchange A and data memory
nibble
1 1 D6-
D7
x
Boolean
CLR C
Clear carry 1 1 C3 x
CLR bit
Clear direct bit 2 2 C2
SETB C
Set carry 1 1 D3 x
SETB bit
Set direct bit 2 2 D2
CPL C
Complement carry 1 1 B3 x
CPL bit
Complement direct bit 2 2 B2
ANL C, bit
AND direct bit to carry 2 2 82 x
ANL C, /bit
AND direct bit inverse to carry 2 2 B0 x
ORL C, bit
OR direct bit to carry 2 2 72 x
ORL C, /bit
OR direct bit inverse to carry 2 2 A0 x
MOV C, bit
Move direct bit to carry 2 2 A2 x
MOV bit, C
Move carry to direct bit 2 2 92
CC1010
SWRS047 Page 27 of 152
Mnemonic Description
Bytes
Instr. Cycles
Hex Opcode
CY
AC
OV
P
Branching
ACALL addr 11
Absolute call to subroutine 2 3 11-F1
LCALL addr 16
Long call to subroutine 3 4 12
RET
Return from subroutine 1 4 22
RETI
Return from interrupt 1 4 32
AJMP addr 11
Absolute jump unconditional 2 3 01-E1
LJMP addr 16
Long jump unconditional 3 4 02
SJMP rel
Short jump (relative address) 2 3 80
JC rel
Jump on carry = 1 2 3 40
JNC rel
Jump on carry = 0 2 3 50
JB bit, rel
Jump on direct bit = 1 3 4 20
JNB bit, rel
Jump on direct bit = 0 3 4 30
JBC bit, rel
Jump on direct bit = 1 and clear 3 4 10
JMP @A+DPTR
Jump indirect relative DPTR 1 3 73
JZ rel
Jump on accumulator = 0 2 3 60
JNZ rel
Jump on accumulator /= 0 2 3 70
CJNE A, direct,
rel
Compare A and direct, jump
relative if not equal
3 4 B5 x
CJNE A, #d, rel
Compare A and immediate, jump
relative if not equal
3 4 B4 x
CJNE Rn, #d, rel
Compare reg and immediate,
jump relative if not equal
3 4 B8-
BF
x
CJNE @Ri, #d, rel
Compare ind and immediate, jump
relative if not equal
3 4 B6-
B7
x
DJNZ Rn, rel
Decrement register, jump relative
if not zero
2 3 D8-
DF
DJNZ direct, rel
Decrement direct byte, jump
relative if not zero
3 4 D5
Misc.
NOP
No operation 1 1 00
TRAP
Set EICON.FDIF = 1, used for
breakpoints
1 3 A5
Table 12. Instruction Set Summary
CC1010
SWRS047 Page 28 of 152
15.6 Interrupts
In
CC1010
there are a total of 15 interrupt
sources, which share 12 interrupt lines.
These are all shown in Table 13. Each
interrupt’s natural priority, interrupt vector,
interrupt enable and interrupt flag, is also
shown in the table, and will be described
below.
Interrupt Natural
Priority
Priority
Control
Interrupt
Vector
Interrupt
Enable
Interrupt Flag
Flash / Debug interrupt 0
-
0x33
EICON.
FDIE
EICON.
FDIF
External Interrupt 0 1
IP.PX0
0x03
IE.EX0 TCON.IE0
(*)
Timer 0 Interrupt 2
IP.PT0
0x0B
IE.ET0 TCON.TF0
(*)
External Interrupt 1 3
IP.PX1
0x13
IE.EX1 TCON.IE1
(*)
Timer 1 Interrupt 4
IP.PT1
0x1B
IE.ET1 TCON.TF1
(*)
Serial Port 0 Transmit Interrupt
SCON0.TI_0
Serial Port 0 Receive Interrupt
5
IP.PS0
0x23
IE.ES0
SCON0.RI_0
Serial Port 1 Transmit Interrupt
SCON1.TI_1
Serial Port 1 Receive Interrupt
6
IP.PS1
0x3B
IE.ES1
SCON1.TI_1
RF Transmit / Receive Interrupt 7
EIP.PRF
0x43
EIE.RFIE EXIF.RFIF
Timer 2 Interrupt 8
EIP.PT2
0x4B
EIE.ET2 EXIF.TF2
ADC Interrupt
EIE.ADIE
and
ADCON2.
ADCIE
EXIF.ADIF
and
ADCON2.
ADCIF
DES Encryption / Decryption
Interrupt
9
EIP.PAD
0x53
EIE.ADIE
and
CRPCON.
CRPIE
EXIF.ADIF
and
CRPCON.
CRPIF
Timer 3 Interrupt 10
EIP.PT3
0x5B
EIE.ET3 EXIF.TF3
Realtime Clock Interrupt 11
EIP.PRTC
0x63
EIE.RTCIE EICON.RTCIF
(*)
- Interrupt flag is cleared by hardware.
Table 13.
CC1010
Interrupt overview
15.6.1 Interrupt Masking
IE.EA is the global interrupt enable for all
interrupts, except the Flash / Debug
interrupt. When
IE.EA is set, each
interrupt is masked by the interrupt enable
bits listed in Table 13. When
IE.EA is
cleared, all interrupts are masked, except
the Flash / Debug interrupt, which has its
own interrupt mask bit,
EICON.FDIE.
15.6.2 Interrupt Processing
When an enabled interrupt occurs, the
CPU jumps to the address of the interrupt
service routine (ISR) associated with that
interrupt, as shown in Table 13. Most
interrupts can also be initiated by setting
the associated interrupt flag from software.
CC1010
executes the ISR to completion
unless another interrupt set at a higher
interrupt level occurs. Each ISR ends with
a RETI (return from interrupt) instruction.
After executing the RETI,
CC1010
returns
to the next instruction that would have
been executed if the interrupt had not
occurred.
CC1010
always completes the instruction in
progress before servicing an interrupt. If
the instruction in progress is RETI, or a
write access to any of the
IP, IE, EIP, or
EIE SFRs,
CC1010
completes one
additional instruction before servicing the
interrupt.
CC1010
SWRS047 Page 29 of 152
IE (0xA8) - Interrupt Enable Register
Bit Name R/W Reset value Description
7
EA
R/W 0 Global Interrupt enable / disable
0 : All interrupts except the Flash / debug
interrupt are disabled
1 : Each interrupt is enabled by its individual
masking bit
6
ES1
R/W 0 Serial Port 1 interrupt enable / disable
0 : Interrupt is disabled
1 : Interrupt is enabled, when also
EA is set
5
-
R/W 0 Reserved for future use
4
ES0
R/W 0 Serial Port 0 interrupt enable / disable
0 : Interrupt is disabled
1 : Interrupt is enabled, when also
EA is set
3
ET1
R/W 0 Timer 1 interrupt enable / disable
0 : Interrupt is disabled
1 : Interrupt is enabled, when also
EA is set
2
EX1
R/W 0
External interrupt 1 (from
P3.3) enable / disable
0 : Interrupt is disabled
1 : Interrupt is enabled, when also
EA is set
1
ET0
R/W 0 Timer 0 interrupt enable / disable
0 : Interrupt is disabled
1 : Interrupt is enabled, when also
EA is set
0
EX0
R/W 0
External interrupt 0 (from
P3.2) enable / disable
0 : Interrupt is disabled
1 : Interrupt is enabled, when also EA is set
EIE (0xE8) - Extended Interrupt Enable Register
Bit Name R/W Reset value Description
7
-
R1 1 Reserved, read as 1
6
-
R1 1 Reserved, read as 1
5
-
R1 1 Reserved, read as 1
4
RTCIE
R/W 0 Realtime Clock interrupt enable / disable
0 : Interrupt is disabled
1 : Interrupt is enabled, when also
EA is set
3
ET3
R/W 0 Timer 3 interrupt enable / disable
0 : Interrupt is disabled
1 : Interrupt is enabled, when also
EA is set
2
ADIE
R/W 0 ADC / DES interrupt enable / disable
0 : Interrupt is disabled
1 : Interrupt is enabled, when also
EA is set
1
ET2
R/W 0 Timer 2 interrupt enable / disable
0 : Interrupt is disabled
1 : Interrupt is enabled, when also
EA is set
0
RFIE
R/W 0 RF Interrupt enable / disable
0 : Interrupt is disabled
1 : Interrupt is enabled, when also EA is set
CC1010
SWRS047 Page 30 of 152
EICON (0xD8) - Extended Interrupt Control
Bit Name R/W Reset value Description
7
SMOD1
R/W 0 Serial Port 1 baud rate doubler enable / disable
0 : Serial Port 1 baud rate is normal
1 : Serial Port 1 baud rate is doubled
6
-
R1 1 Reserved, read as 1
5
FDIE
R/W 0 Flash / Debug interrupt enable
0 : Interrupt is disabled
1 : Interrupt is enabled (independent of
IE.EA)
4
FDIF
R/W 0 Flash / Debug interrupt flag
FDIF is set by hardware when an 8051-initiated write to
Flash program memory is completed or a TRAP instruction
is executed. FDIF may also be set by software. FDIF
must be cleared by software before exiting the ISR.
3
RTCIF
R/W 0 Real-time clock interrupt flag
RTCIF is set by hardware when an interrupt request is
generated from the real-time clock.
RTCIF may also be set
by software.
RTCIF must be cleared by software before
exiting the ISR.
2
-
R0 0 Reserved, read as 0
1
-
R0 0 Reserved, read as 0
0
-
R0 0 Reserved, read as 0
EXIF (0x91) - Extended Interrupt Flag
Bit Name R/W Reset value Description
7
TF3
R/W 0 Timer 3 interrupt flag.
TF3
is set by hardware when an interrupt request is
generated from Timer 3.
TF3 may also be set by software.
TF3 must be cleared by software before exiting the ISR.
6
ADIF
R/W 0 ADC / DES Interrupt flag.
ADIF is set by hardware when an interrupt request is
generated from the ADC block (
ADCON2.ADCIF) or by the
DES Encryption / Decryption block (
CRPCON.CRPIF).
These interrupts must also be enabled by setting
ADCON2.ADCIE and CRPCON.CRPIE. ADIF may also
be set by software.
ADIF must be cleared by software
before exiting the ISR
5
TF2
R/W 0 Timer 2 interrupt flag.
TF2
is set by hardware when an interrupt request is
generated from Timer 2.
TF2 may also be set by software.
TF2 must be cleared by software before exiting the ISR
4
RFIF
R/W 0 RF Transmit / receive interrupt flag.
RFIF is set by hardware when an interrupt request is
generated from the RF transceiver block.
RFIF may also
be set by software.
RFIF must be cleared by software
before exiting the ISR.
3
-
R1 1 Reserved, read as 1
2
-
R0 0 Reserved, read as 0
1
-
R0 0 Reserved, read as 0
0
-
R0 0 Reserved, read as 0
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