TEXAS INSTRUMENTS CC1000 Technical data

CC1000

Single Chip Very Low Power RF Transceiver

Applications

• Very low power UHF wireless data

transmitters and receivers

• 315 / 433 / 868 and 915 MHz ISM/SRD

band systems

• RKE – Two-way Remote Keyless Entry

Product Description

CC1000

ceiver designed for very low power and very low voltage wireless applications. The circuit is mainly intended for the ISM (Industrial, Scientific and Medical) and SRD (Short Range Device) frequency bands at 315, 433, 868 and 915 MHz, but can easily be programmed for operation at other frequencies in the 300-1000 MHz range.

The main operating parameters of can be programmed via a serial bus, thus making use transceiver. In a typical system

CC1000

microcontroller and a few external passive components.

is a true single-chip UHF trans-

CC1000

will be used together with a

a very flexible and easy to

• Home automation

• Wireless alarm and security systems

• AMR – Automatic Meter Reading

• Low power telemetry

• Game Controllers and advanced toys

CC1000

technology in 0.35 µm CMOS.

is based on Chipcon’s SmartRF®

Features

• True single chip UHF RF transceiver

• Very low current consumption

• Frequency range 300 – 1000 MHz

• Integrated bit synchroniser

• High sensitivity (typical -110 dBm at 2.4

kBaud)

• Programmable output power –20 to

10 dBm

• Small size (TSSOP-28 or UltraCSP™

package)

• Low supply voltage (2.1 V to 3.6 V)

• Very few external components required

• No external RF switch / IF filter

required

• RSSI output

• Single port antenna connection

• FSK data rate up to 76.8 kBaud

• Complies with EN 300 220 and FCC

CFR47 part 15

• Programmable frequency in 250 Hz

steps makes crystal temperature drift compensation possible without TCXO

• Suitable for frequency hopping

protocols

• Development kit available

• Easy-to-use software for generating the

CC1000

SWRS048 Page 1 of 53

configuration data

CC1000

Table of Contents

1. Absolute Maximum Ratings................................................................................... 4

2. Operating Conditions ............................................................................................. 4

3. Electrical Specifications......................................................................................... 4

4. Pin Assignment.......................................................................................................8

5. Circuit Description..................................................................................................9

6. Application Circuit ................................................................................................ 10

6.1 Input / output matching............................................................................................... 10

6.2 VCO inductor.............................................................................................................. 10

6.3 Additional filtering.......................................................................................................10

6.4 Power supply decoupling ........................................................................................... 10

7. Configuration Overview ....................................................................................... 12

8. Configuration Software ........................................................................................ 12

9. 3-wire Serial Configuration Interface ..................................................................13

10. Microcontroller Interface.................................................................................... 15

10.1 Connecting the microcontroller ................................................................................ 15

11. Signal interface ................................................................................................... 16

11.1 Manchester encoding and decoding ........................................................................ 16

12. Bit synchroniser and data decision ..................................................................19

13. Receiver sensitivity versus data rate and frequency separation.................... 22

14. Frequency programming.................................................................................... 23

15. Recommended RX settings for ISM frequencies .............................................24

16. VCO ...................................................................................................................... 25

17. VCO and PLL self-calibration............................................................................. 25

18. VCO and LNA current control ............................................................................ 28

19. Power management ............................................................................................ 28

20. Input / Output Matching...................................................................................... 31

21. Output power programming .............................................................................. 32

22. RSSI output ........................................................................................................33

SWRS048 Page 2 of 53

CC1000

23. IF output ............................................................................................................. 34

24. Crystal oscillator.................................................................................................35

25. Optional LC Filter................................................................................................36

26. System Considerations and Guidelines............................................................ 37

26.1 SRD regulations ....................................................................................................... 37

26.2 Low cost systems..................................................................................................... 37

26.3 Battery operated systems......................................................................................... 37

26.4 Crystal drift compensation........................................................................................ 37

26.5 High reliability systems............................................................................................. 37

26.6 Frequency hopping spread spectrum systems......................................................... 37

27. PCB Layout Recommendations......................................................................... 38

28. Antenna Considerations..................................................................................... 38

29. Configuration registers ...................................................................................... 39

30. Package Description (TSSOP-28) ...................................................................... 48

31. Package Description (UltraCSP™) .................................................................... 49

32. Plastic Tube Specification ................................................................................. 51

33. Carrier Tape and Reel Specification.................................................................. 51

34. Ordering Information .......................................................................................... 52

35. General Information............................................................................................ 52

36. Address Information........................................................................................... 53

SWRS048 Page 3 of 53

CC1000

1. Absolute Maximum Ratings

Parameter Min. Max. Units Condition

Supply voltage, VDD -0.3 5.0 V Voltage on any pin -0.3 VDD+0.3,

Input RF level 10 dBm Storage temperature range (TSSOP) Shelf life (UltraCSP™) 1 year Room temperature and oxygen

Reflow soldering temperature (TSSOP) Peak reflow soldering temperature (UltraCSP™)

-50 150

260

251

Under no circumstances the absolute maximum ratings given above should be violated. Stress exceeding one or more of

max 5.0

the limiting values may cause permanent damage to the device.

Caution! ESD sensitive device. Precaution should be used when handling the device in order to prevent permanent damage.

2. Operating Conditions

Parameter

RF Frequency Range 300

Operating ambient temperature range -40 85

Min. Typ. Max. Unit Condition / Note

1000 MHz Programmable in steps of 250 Hz

V

°C

IPC/JEDEC J-STD-020B

IPC/JEDEC J-STD-020A

free cabinet

Supply voltage

2.1 3.0 3.6 V

3. Electrical Specifications

Tc = 25°C, VDD = 3.0 V if nothing else stated

Parameter

Transmit Section

Transmit data rate

Binary FSK frequency separation

Min. Typ. Max. Unit Condition / Note

0.6 76.8 kBaud NRZ or Manchester encoding.

0 65 kHz

Note: The same supply voltage should be used for digital (DVDD) and analogue (AVDD) power.

76.8 kBaud equals 76.8 kbit/s using NRZ coding. See page 16.

The frequency separation is programmable in 250 Hz steps. 65 kHz is the maximum guaranteed separation at 1 MHz reference frequency. Larger separations can be achieved at higher reference frequencies.

SWRS048 Page 4 of 53

CC1000

Parameter

Output power 433 MHz 868 MHz

RF output impedance 433/868 MHz

Harmonics

Receive Section

Receiver Sensitivity, 433 MHz Optimum sensitivity (9.3 mA) Low current consumption (7.4 mA)

Receiver Sensitivity, 868 MHz Optimum sensitivity (11.8 mA) Low current consumption (9.6 mA)

System noise bandwidth 30 kHz 2.4 kBaud, Manchester coded

Cascaded noise figure 433/868 MHz

Saturation

Input IP3

Blocking

LO leakage -57 dBm

Input impedance

Turn on time 11 128 Baud The turn-on time is determined by

IF Section

Intermediate frequency (IF)

IF bandwidth

RSSI dynamic range

RSSI accuracy

Min. Typ. Max. Unit Condition / Note

-20

140 / 80

-20 dBc An external LC or SAW filter

12/13 dB

10 dBm 2.4 kBaud, Manchester coded

-18 dBm From LNA to IF output

40 dBc At +/- 1 MHz

150

175 kHz

-105 -50 dBm

-110

-109

-107

-105

88-j26 70-j26

52-j7 52-j4

± 6

10

5

10.7

dB See p.33 for details

dBm dBm

Ω

dBm dBm

Ω Ω Ω Ω

kHz

MHz

Delivered to 50 Ω load. The output power is programmable.

Transmit mode. For matching details see “Input/ output matching” p.31.

should be used to reduce harmonics emission to comply with SRD requirements. See p.36.

2.4 kBaud, Manchester coded data, 64 kHz frequency separation, BER = 10

See Table 6 and Table 7 page 22 for typical sensitivity figures at other data rates.

data

data, BER = 10

Receive mode, series equivalent at 315 MHz at 433 MHz at 868 MHz. At 915 MHz For matching details see “Input/ output matching” p. 31.

the demodulator settling time, which is programmable. See p. 19

Internal IF filter External IF filter

-3

SWRS048 Page 5 of 53

Parameter

RSSI linearity

Frequency Synthesiser Section

Crystal Oscillator Frequency

Crystal frequency accuracy requirement

Crystal operation

Crystal load capacitance

Crystal oscillator start-up time 5

Output signal phase noise

PLL lock time (RX / TX turn time)

PLL turn-on time, crystal oscillator on in power down mode

Min. Typ. Max. Unit Condition / Note

3 16 MHz Crystal frequency can be 3-4, 6-8

Parallel C171 and C181 are loading

12 12 12

-85 dBc/Hz At 100 kHz offset from carrier

200

250

± 2

± 50 ± 25

22 16 16

1.5 2

dB

ppm 433 MHz

30 30 16

ms

or 9-16 MHz. Recommended frequencies are 3.6864, 7.3728,

11.0592 and 14.7456. See page 35 for details.

868 MHz The crystal frequency accuracy and drift (ageing and temperature dependency) will determine the frequency accuracy of the transmitted signal.

capacitors, see page 35

pF

3-4 MHz, 22 pF recommended

pF

6-8 MHz, 16 pF recommended

pF

9-16 MHz, 16 pF recommended

3.6864 MHz, 16 pF load

ms

7.3728 MHz, 16 pF load

ms

16 MHz, 16 pF load

Up to 1 MHz frequency step

µs

Crystal oscillator running

µs

CC1000

Digital Inputs/Outputs

Logic “0” input voltage

Logic ”1” input voltage

Logic “0” output voltage

Logic “1” output voltage

Logic “0” input current

Logic “1” input current

DIO setup time

0 0.3*VDD V

0.7*VDD VDD V

0

2.5

NA -1

NA 1

20 ns TX mode, minimum time DIO

0.4 V Output current -2.5 mA,

VDD V Output current 2.5 mA,

SWRS048 Page 6 of 53

3.0 V supply voltage

Input signal equals GND

µA

Input signal equals VDD

µA

must be ready before the positive edge of DCLK

Parameter

DIO hold time

Serial interface (PCLK, PDATA and PALE) timing specification

Current Consumption

Power Down mode

Current Consumption, receive mode 433/868 MHz

Current Consumption, average in receive mode using polling 433/868 MHz

Current Consumption, transmit mode 433/868 MHz:

P=0.01mW (-20 dBm)

P=0.3 mW (-5 dBm)

P=1 mW (0 dBm)

P=3 mW (5 dBm)

P=10 mW (10 dBm)

Current Consumption, crystal osc.

Current Consumption, crystal osc. And bias

Current Consumption, crystal osc., bias and synthesiser, RX/TX

Min. Typ. Max. Unit Condition / Note

10 ns TX mode, minimum time DIO

See Table 2 page 14

0.2 1

7.4/9.6 mA Current is programmable and can

74/96

5.3/8.6

8.9/13.8

10.4/16.5

14.8/25.4

26.7/NA

30

80

105

860

4/5 5/6

must be held after the positive edge of DCLK

Oscillator core off

µA

be increased for improved sensitivity Polling controlled by micro-

µA

controller using 1:100 receive to power down ratio

mA

The ouput power is delivered to a 50Ω load, see also p. 32

mA

3-8 MHz, 16 pF load

µA

9-14 MHz, 12 pF load

µA

14-16 MHz, 16 pF load

µA

< 500 MHz

mA

> 500 MHz

mA

CC1000

SWRS048 Page 7 of 53

CC1000

4. Pin Assignment

Pin no. UltraCSP

pin no.

1 G3 AVDD Power (A) Power supply (3 V) for analog modules (mixer and IF) 2 F2 AGND Ground (A) Ground connection (0 V) for analog modules (mixer and IF) 3 G2 RF_IN RF Input RF signal input from antenna 4 G1 RF_OUT RF output RF signal output to antenna 5 F1 AVDD Power (A) Power supply (3 V) for analog modules (LNA and PA) 6 E2 AGND Ground (A) Ground connection (0 V) for analog modules (LNA and PA) 7 E1 AGND Ground (A) Ground connection (0 V) for analog modules (PA) 8 D1 AGND Ground (A) Ground connection (0 V) for analog modules (VCO and prescaler)

9 C1 AVDD Power (A) Power supply (3 V) for analog modules (VCO and prescaler) 10 B1 L1 Analog input Connection no 1 for external VCO tank inductor 11 A1 L2 Analog input Connection no 2 for external VCO tank inductor 12 B2 CHP_OUT

13 C2 R_BIAS Analog output 14 F3 AGND Ground (A) Ground connection (0 V) for analog modules (backplane) 15 A2 AVDD Power (A) Power supply (3 V) for analog modules (general) 16 B3 AGND Ground (A) Ground connection (0 V) for analog modules (general) 17 A3 XOSC_Q2 Analog output Crystal, pin 2 18 A4 XOSC_Q1 Analog input Crystal, pin 1, or external clock input 19 B4 AGND Ground (A) Ground connection (0 V) for analog modules (guard) 20 C3 DGND Ground (D) Ground connection (0 V) for digital modules (substrate) 21 C4 DVDD Power (D) Power supply (3 V) for digital modules 22 D4 DGND Ground (D) Ground connection (0 V) for digital modules 23 E4 DIO Digital

24 F4 DCLK Digital output Data clock for data in both receive and transmit mode 25 G4 PCLK Digital input Programming clock for 3-wire bus 26 D3 PDATA Digital

27 D2 PALE Digital input Programming address latch enable for 3-wire bus. Internal pull-up. 28 E3 RSSI/IF Analog output The pin can be used as RSSI or 10.7 MHz IF output to optional

A=Analog, D=Digital

Pin name Pin type Description

Analog output Charge pump current output

(LOCK)

The pin can also be used as PLL Lock indicator. Output is high when PLL is in lock.

Connection for external precision bias resistor (82 kΩ, ± 1%)

Data input/output. Data input in transmit mode. Data output in

input/output

receive mode

Programming data for 3-wire bus. Programming data input for

input/output

write operation, programming data output for read operation

external IF and demodulator. If not used, the pin should be left open (not connected).

(Top View)

1

AVDD

AGND

RF_IN

RF_OUT

AVDD

AGND

AVDD

L1

L2

CHP_OUT

R_BIAS

AGND

1

2

3

4

5

6

7

8

9

10

11

12

13

14 15

CC1000

28

27

26

25

24

23

22

21

20

19

18

17

16

RSSI/IF

PALE

PDATA

PCLK

DCLK

DIO

DGND

DVDD

DGND

AGND

XOSC_Q1

XOSC_Q2

AGND

AVDD

SWRS048 Page 8 of 53

5. Circuit Description

MIXER

RF_IN

RF_OUT

LNA

PA

VCO

RSSI/IF

DEMOD

/N

DEMOD

~

L1

L2

IF STAGE

LPF

CHP_OUT

CHARGE

PUMP

CONTROL

BIAS

PD OSC

/R

CC1000

DIO

DCLK

PDATA, PCLK, PALE

3

R_BIAS

XOSC_Q2

XOSC_Q1

Figure 1. Simplified block diagram of the

A simplified block diagram of

CC1000

is shown in Figure 1. Only signal pins are shown.

In receive mode

CC1000

is configured as a traditional superheterodyne receiver. The RF input signal is amplified by the lownoise amplifier (LNA) and converted down to the intermediate frequency (IF) by the mixer (MIXER). In the intermediate frequency stage (IF STAGE) this downconverted signal is amplified and filtered before being fed to the demodulator (DEMOD). As an option a RSSI signal, or the IF signal after the mixer is available at the RSSI/IF pin. After demodulation

CC1000

outputs the digital demodulated data on the pin DIO. Synchronisation is done on-chip providing data clock at DCLK.

CC1000

In transmit mode the voltage controlled oscillator (VCO) output signal is fed directly to the power amplifier (PA). The RF output is frequency shift keyed (FSK) by the digital bit stream fed to the pin DIO. The internal T/R switch circuitry makes the antenna interface and matching very easy.

The frequency synthesiser generates the local oscillator signal which is fed to the MIXER in receive mode and to the PA in transmit mode. The frequency synthesiser consists of a crystal oscillator (XOSC), phase detector (PD), charge pump (CHARGE PUMP), VCO, and frequency dividers (/R and /N). An external crystal must be connected to XOSC, and only an external inductor is required for the VCO.

The 3-wire digital serial interface (CONTROL) is used for configuration.

SWRS048 Page 9 of 53

6. Application Circuit

Very few external components are required for the operation of typical application circuit is shown in Figure 2. Component values are shown in Table 1.

6.1 Input / output matching

C31/L32 is the input match for the receiver. L32 is also a DC choke for biasing. C41, L41 and C42 are used to match the transmitter to 50 Ω. An internal T/R switch circuit makes it possible to connect the input and output together and match the TX mode. See “Input/output matching” p.31 for details.

6.2 VCO inductor

The VCO is completely integrated except for the inductor L101.

CC1000

to 50 Ω in both RX and

CC1000

. A

CC1000

Component values for the matching network and VCO inductor are easily calculated using the SmartRF® Studio software.

6.3 Additional filtering

Additional external components (e.g. RF LC or SAW-filter) may be used in order to improve the performance in specific applications. See also “Optional LC filter” p.36 for further information.

6.4 Power supply decoupling

Power supply decoupling and filtering must be used (not shown in the application circuit). The placement and size of the decoupling capacitors and the power supply filtering are very important to achieve the optimum performance. Chipcon provides reference designs (CC1000PP and CC1000uCSP_EM) that should be followed very closely.

Figure 2. Typical

CC1000

application circuit (power supply decoupling not shown)

SWRS048 Page 10 of 53

CC1000

CC1000 TSSOP package

Item 315 MHz 433 MHz 868 MHz 915 MHz

C31 8.2 pF, 5%, C0G, 0603 15 pF, 5%, C0G, 0603 10 pF, 5%, C0G, 0603 10 pF, 5%, C0G, 0603 C41 2.2 pF, 5%, C0G, 0603 8.2 pF, 5%, C0G, 0603 Not used Not used C42 5.6 pF, 5%, C0G, 0603 5.6 pF, 5%, C0G, 0603 4.7 pF, 5%, C0G, 0603 4.7 pF, 5%, C0G, 0603 C171 18 pF, 5%, C0G, 0603 18 pF, 5%, C0G, 0603 18 pF, 5%, C0G, 0603 18 pF, 5%, C0G, 0603 C181 18 pF, 5%, C0G, 0603 18 pF, 5%, C0G, 0603 18 pF, 5%, C0G, 0603 18 pF, 5%, C0G, 0603 L32 39 nH, 10%, 0805

L41 20 nH, 10%, 0805

L101 56 nH, 5%, 0805

R131 XTAL 14.7456 MHz crystal,

(Coilcraft 0805CS-390XKBC)

(Coilcraft 0805HQ20NXKBC)

(Koa KL732ATE56NJ) 82 kΩ, 1%, 0603 82 kΩ, 1%, 0603 82 kΩ, 1%, 0603 82 kΩ, 1%, 0603

16 pF load

Item 315 MHz 433 MHz 868 MHz 915 MHz

C31 8.2 pF, 5%, C0G, 0402 15 pF, 5%, C0G, 0402 10 pF, 5%, C0G, 0402 10 pF, 5%, C0G, 0402 C41 Not used Not used Not used Not used C42 4.7 pF, 5%, C0G, 0402 4.7 pF, 5%, C0G, 0402 6.8 pF, 5%, C0G, 0402 6.8 pF, 5%, C0G, 0402 C171 18 pF, 5%, C0G, 0402 18 pF, 5%, C0G, 0402 18 pF, 5%, C0G, 0402 18 pF, 5%, C0G, 0402 C181 18 pF, 5%, C0G, 0402 18 pF, 5%, C0G, 0402 18 pF, 5%, C0G, 0402 18 pF, 5%, C0G, 0402 L32 39 nH, 5%, 0402

L41 22 nH, 5%, 0402

L101 56 nH, 5%, 0402

R131 XTAL 14.7456 MHz crystal,

(Ceramic multilayer)

(Thin film inductor) 82 kΩ, 1%, 0402 82 kΩ, 1%, 0402 82 kΩ, 1%, 0402 82 kΩ, 1%, 0402

16 pF load

Note: Items shaded are different for different frequencies

68 nH, 10%, 0805

(Coilcraft 0805CS-680XKBC)

6.2 nH, 10%, 0805

(Coilcraft 0805HQ6N2XKBC)

33 nH, 5%, 0805 (Koa KL732ATE33NJ)

14.7456 MHz crystal, 16 pF load

120 nH, 10%, 0805

(Coilcraft 0805CS-121XKBC)

2.5 nH, 10%, 0805

(Coilcraft 0805HQ2N5XKBC)

4.7 nH, 5%, 0805 (Koa KL732ATE4N7C)

14.7456 MHz crystal, 16 pF load

CC1000 UltraCSP™ package

68 nH, 5%, 0402

(Ceramic multilayer)

15 nH, 5%, 0402

(Ceramic multilayer)

33 nH, 5%, 0402 (Thin film inductor)

14.7456 MHz crystal, 16 pF load

120 nH, 5%, 0402

(Ceramic multilayer)

2.7 nH, 5%, 0402

(Ceramic multilayer)

7.5 nH, 5%, 0402 (Thin film inductor)

14.7456 MHz crystal, 16 pF load

120 nH, 10%, 0805

(Coilcraft 0805CS-121XKBC)

2.5 nH, 10%, 0805

(Coilcraft 0805HQ2N5XKBC)

4.7 nH, 5%, 0805 (Koa KL732ATE4N7C)

14.7456 MHz crystal, 16 pF load

120 nH, 5%, 0402

(Ceramic multilayer)

2.7 nH, 5%, 0402

(Ceramic multilayer)

7.5 nH, 5%, 0402 (Thin film inductor)

14.7456 MHz crystal, 16 pF load

Table 1. Bill of materials for the application circuit

Note that the component values for 868/915 MHz can be the same. However, it is important the layout is optimised for the selected VCO inductor in order to centre the tuning range around the operating frequency to account for inductor tolerance. The VCO inductor must be placed very close and symmetrical with respect to the pins (L1 and L2).

Chipcon provide reference layouts that should be followed very closely in order to achieve the best performance. The reference design can be downloaded from the Chipcon website.

SWRS048 Page 11 of 53

7. Configuration Overview

CC1000

best performance for different applications. Through the programmable configuration registers the following key parameters can be programmed:

• Receive / transmit mode

• RF output power

• Frequency synthesiser key

8. Configuration Software

Chipcon provides users of software program, SmartRF® Studio (Windows interface) that generates all necessary based on the user’s selections of various parameters. These hexadecimal numbers will then be the necessary input to the microcontroller for the configuration of

can be configured to achieve the

parameters: RF output frequency, FSK

CC1000

configuration data

with a

CC1000

frequency separation (deviation), crystal oscillator reference frequency

• Power-down / power-up mode

• Crystal oscillator power-up / power

down

• Data rate and data format (NRZ,

Manchester coded or UART interface)

• Synthesiser lock indicator mode

• Optional RSSI or external IF

CC1000

provide the user with the component values needed for the input/output matching circuit and the VCO inductor.

Figure 3 shows the user interface of the

CC1000

. In addition the program will

configuration software.

Figure 3. SmartRF® Studio user interface

SWRS048 Page 12 of 53

9. 3-wire Serial Configuration Interface

CC1000

interface (PDATA, PCLK and PALE). There are 28 8-bit configuration registers, each addressed by a 7-bit address. A Read/Write bit initiates a read or write operation. A full configuration of requires sending 22 data frames of 16 bits each (7 address bits, R/W bit and 8 data bits). The time needed for a full configuration depend on the PCLK frequency. With a PCLK frequency of 10 MHz the full configuration is done in less than 46 µs. Setting the device in power down mode requires sending one frame only and will in this case take less than 2 µs. All registers are also readable.

In each write-cycle 16 bits are sent on the PDATA-line. The seven most significant bits of each data frame (A6:0) are the address-bits. A6 is the MSB (Most Significant Bit) of the address and is sent as the first bit. The next bit is the R/W bit (high for write, low for read). During address and R/W bit transfer the PALE (Program Address Latch Enable) must be kept low. The 8 data-bits are then transferred (D7:0). See Figure 4.

is configured via a simple 3-wire

CC1000

T

SA

CC1000

The timing for the programming is also shown in Figure 4 with reference to Table

2. The clocking of the data on PDATA is done on the negative edge of PCLK. When the last bit, D0, of the 8 data-bits has been loaded, the data word is loaded in the internal configuration register.

The configuration data is stored in internal RAM. The data is retained during powerdown mode, but not when the powersupply is turned off. The registers can be programmed in any order.

The configuration registers can also be read by the microcontroller via the same configuration interface. The seven address bits are sent first, then the R/W bit set low to initiate the data read-back.

CC1000

returns the data from the addressed register. PDATA is in this case used as an output and must be tri-stated (or set high n the case of an open collector pin) by the microcontroller during the data read-back (D7:0). The read operation is illustrated in Figure 5.

T

HA

then

PCLK

PDATA

PALE

T

CH,min

Address Write mode

6543210

T

CL,min

Figure 4. Configuration registers write operation

T

SA

W

7 6 5 4 3 2 1 0

T

HD

Data byte

T

SD

SWRS048 Page 13 of 53

CC1000

PCLK

Address Read mode

PDATA

6543210

R 7 6 5 4 3 2 1 0

PALE

Figure 5. Configuration registers read operation

Parameter Symbol Min Max Units Conditions

PCLK, clock frequency

PCLK low pulse duration

PCLK high pulse duration

PALE setup time

PALE hold time

PDATA setup time

PDATA hold time

Rise time T

Fall time T

F

CLOCK

50 ns The minimum time PCLK must be low.

T

CL,min

50 ns The minimum time PCLK must be high.

T

CH,min

T

SA

THA 10 - ns The minimum time PALE must be held low after

T

SD

10 - ns The minimum time data must be held at PDATA,

T

HD

100 ns The maximum rise time for PCLK and PALE

rise

100 ns The maximum fall time for PCLK and PALE

fall

Note: The set-up- and hold-times refer to 50% of VDD.

- 10 MHz

10 - ns The minimum time PALE must be low before

negative edge of PCLK.

the positive edge of PCLK.

10 - ns The minimum time data on PDATA must be ready

before the negative edge of PCLK.

after the negative edge of PCLK.

Data byte

Table 2. Serial interface, timing specification

SWRS048 Page 14 of 53

10. Microcontroller Interface

Used in a typical system, interface to a microcontroller. This microcontroller must be able to:

• Program

via the 3-wire serial configuration interface (PDATA, PCLK and PALE).

• Interface to the bi-directional

synchronous data signal interface (DIO and DCLK).

10.1 Connecting the microcontroller

The microcontroller uses 3 output pins for the configuration interface (PDATA, PCLK and PALE). PDATA should be a bidirectional pin for data read-back. A bidirectional pin is used for data (DIO) to be transmitted and data received. DCLK providing the data timing should be connected to a microcontroller input. Optionally another pin can be used to monitor the LOCK signal (available at the CHP_OUT pin). This signal is logic level high when the PLL is in lock. See Figure

6.

Also the RSSI signal can be connected to the microcontroller if it has an analogue ADC input.

Pin Pin state Note

PDATA Input Should be driven high or low PCLK Input Should be driven high or low PALE Input with internal pull-

DIO Input Should be driven high or low DCLK High-impedance

CC1000

up resistor

output

into different modes

CC1000

will

Should be driven high or high-impedance to minimize power consumption

• Optionally the microcontroller can do

data encoding / decoding.

• Optionally the microcontroller can

monitor the frequency lock status from pin CHP_OUT (LOCK).

• Optionally the microcontroller can

monitor the RSSI output for signal strength acquisition.

The microcontroller pins connected to PDATA and PCLK can be used for other purposes when the configuration interface is not used. PDATA and PCLK are high impedance inputs as long as PALE is high.

PALE has an internal pull-up resistor and should be left open (tri-stated by the microcontroller) or set to a high level during power down mode in order to prevent a trickle current flowing in the pullup. The pin state in power down mode is summarized in Table 3.

CC1000

Table 3. CC1000 pins in power-down mode

PDATA

CC1000

PCLK PALE

DIO DCLK

CHP_OUT (LOCK)

RSSI/IF

Figure 6. Microcontroller interface

(Optional)

SWRS048 Page 15 of 53

Microcontroller

ADC

11. Signal interface

The signal interface consists of DIO and DCLK and is used for the data to be transmitted and data received. DIO is the bi-directional data line and DCLK provides a synchronous clock both during data transmission and data reception.

CC1000

The Return-to-Zero) data or Manchester (also known as bi-phase-level) encoded data.

CC1000

the demodulator and provide the data clock at DCLK.

CC1000

different data formats:

Synchronous NRZ mode

mode DCLK, and DIO is used as data input. Data is clocked into edge of DCLK. The data is modulated at RF without encoding. configured for the data rates 0.6, 1.2, 2.4,

4.8, 9.6, 19.2, 38.4 or 76.8 kbit/s. For 38.4 and 76.8 kbit/s a crystal frequency of

14.7456 MHz must be used. In receive mode and provides received data clock at DCLK and data at DIO. The data should be clocked into the interfacing circuit at the rising edge of DCLK. See Figure 7.

Synchronous Manchester encoded mode

In transmit mode clock at DCLK, and DIO is used as data input. Data is clocked into rising edge of DCLK and should be in NRZ format. The data is modulated at RF with Manchester code. The encoding is done

CC1000

by configured for the data rates 0.3, 0.6, 1.2,

2.4, 4.8, 9.6, 19.2 or 38.4 kbit/s. The 38.4 kbit/s rate corresponds to the maximum

76.8 kBaud due to the Manchester encoding. For 38.4 and 76.8 kBaud a crystal frequency of 14.7456 MHz must be used. In receive mode synchronisation and provides received data clock at DCLK and data at DIO.

CC1000

can be used with NRZ (Non-

can also synchronise the data from

can be configured for three

. In transmit

CC1000

does the decoding and NRZ data

provides the data clock at

CC1000

does the synchronisation

CC1000

provides the data

CC1000

. In this mode

CC1000

at the rising

can be

.

at the

can be

does the

CC1000

is presented at DIO. The data should be clocked into the interfacing circuit at the rising edge of DCLK. See Figure 8.

CC1000

.

Transparent Asynchronous UART mode

In transmit mode DIO is used as data input. The data is modulated at RF without synchronisation or encoding. In receive mode the raw data signal from the demodulator is sent to the output. No synchronisation or decoding of the signal is done in the interfacing circuit. The DCLK pin is used as data output in this mode. Data rates in the range from 0.6 to 76.8 kBaud can be used. For 38.4 and 76.8 kBaud a crystal frequency of 14.7456 MHz must be used. See Figure 9.

11.1 Manchester encoding and decoding

In the Synchronous Manchester encoded mode

when modulating the data. The also performs the data decoding and synchronisation. The Manchester code is based on transitions; a “0” is encoded as a low-to-high transition, a “1” is encoded as a high-to-low transition. See Figure 10.

The decoding violation and will set a Manchester Violation Flag when such a violation is detected in the incoming signal. The threshold limit for the Manchester Violation can be set in the MODEM1 register. The Manchester Violation Flag can be monitored at the CHP_OUT (LOCK) pin, configured in the LOCK register.

The Manchester code ensures that the signal has a constant DC component, which is necessary in some FSK demodulators. Using this mode also ensures compatibility with CC400/CC900 designs.

CC1000

and should be done by

uses Manchester coding

can detect a Manchester

SWRS048 Page 16 of 53

Transmitter side:

CC1000

DIO

DCLK

“RF”

Receiver side:

“RF”

DCLK

DIO

Transmitter side:

Data provided by microcontroller

Clock provided by CC1000

FSK modulating signal (NRZ),

FSK modulating signal (NRZ), internal in CC1000

internal in CC1000

Demodulated signal (NRZ),

Demodulated signal (NRZ), internal in CC1000

internal in CC1000

Clock provided by CC1000

Data provided by CC1000

Figure 7. Synchronous NRZ mode

DIO

DCLK

“RF”

Receiver side:

“RF”

DCLK

DIO

Figure 8. Synchronous Manchester encoded mode

Data provided by microcontroller (NRZ)

Clock provided by CC1000

FSK modulating signal (Manchester encoded),

FSK modulating signal (Manchester encoded), internal in CC1000

internal in CC1000

Demodulated signal (Manchester encoded),

Demodulated signal (Manchester encoded), internal in CC1000

internal in CC1000

Clock provided by CC1000

Data provided by CC1000 (NRZ)

SWRS048 Page 17 of 53