Texas Instruments C28 Series, TMS320C28 Series Student Manual

TI

C28x DSP Design Workshop

Student Guide

C28x Revision 5.0 February 2004

Technical Training

Organization

Important Notice

Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, patent infringement, and limitation of liability.

TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements.

Customers are responsible for their applications using TI components.

In order to minimize risks associated with the customer’s applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards.

TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI’s publication of information regarding any third party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.

Copyright  2001, 2002, 2003, 2004 Texas Instruments Incorporated

Revision History

October 2001 – Revision 1.0

January 2002 – Revision 2.0

May 2002 – Revision 3.0

June 2002 – Revision 3.1

October 2002 – Revision 4.0

December 2002 – Revision 4.1

July 2003 – Revision 4.2

August 2003 – Revision 4.21

February 2004 – Revision 5.0

Mailing Address

Texas Instruments Training Technical Organization 7839 Churchill Way M/S 3984 Dallas, Texas 75251-1903

ii C28x - Introduction

C28x Workshop

C28x DSP Design Workshop

eZdsp™ F2812 Starter Kit

Texas Instruments

Technical Training

TO

TTTO

Technical Training

Organization

eZdsp

is a trademark of Spectrum Digital, Inc.

eZdsp

is a trademark of Spectrum Digital, Inc.

Introductions

Name



Name

Company



Company

Project Responsibilities



Project Responsibilities

DSP / Microcontroller Experience



DSP / Microcontroller Experience

TMS320 DSP Experience



TMS320 DSP Experience

Hardware / Software --



Hardware / Software

Interests



Interests

Introductions

Assembly / C

C28x - Introduction iii

C28x Workshop

C28x Workshop Outline

Architecture Overview

1.1.Architecture Overview

Programming Development Environment

2.2.Programming Development Environment

Peripheral Register Header Files

3.3.Peripheral Register Header Files

Reset and Interrupts

4.4.Reset and Interrupts

System Initialization

5.5.System Initialization

Analog--toto--

6.6.Analog

Event Manager

7.7.Event Manager

Numerical Concepts and IQ Math

8.8.Numerical Concepts and IQ Math

Using DSP/BIOS

9.9.Using DSP/BIOS

10.

System Design

10.

System Design

11.

Communications

11.

Communications

12.

Support Resources

12.

Support Resources

Digital Converter

eZdsp™ F2812 Hardware

JTAG Interface (P1)

Parallel Port/

JTAG

Controller

Interface (P3)

eZdsp

™ F2812 Hardware

EXPANSION

Data & Address (P2)

SRAM

64K x 16

TMS320F2812 --

Power

Connector (P6)

+5V

iv C28x - Introduction

I/O Interface (P4/P8/P7)

TMS320F2812

DSP

ANALOG

Interface (P5/P9)

Introduction

This architecture overview introduces the basic architecture of the TMS320C28x (C28x) series of Digital Signal Processors from Texas Instruments. The C28x series adds a new level of general purpose processing ability unseen in any previous DSP chips. The C28x is ideal for applications combining DSP, standard microcontroller processing, efficient C code execution, or operating system tasks.

Learning Objectives

When this module is complete, you should have a basic understanding of the C28x architecture and how all of its components work together to create a high-end, uniprocessor control system.

Learning Objectives

Identify the three main components



Identify the three main components

Architecture Overview

of the C28x

List the key features of the C28x



List the key features of the C28x

CPU

Identify the memory capabilities of



Identify the memory capabilities of

the C28x

Identify the peripherals available on



Identify the peripherals available on

the C28x

C28x - Architecture Overview 1 - 1

Module Topics

Architecture Overview.............................................................................................................................. 1-1

Module Topics......................................................................................................................................... 1-2

What is the TMS320C28x?...................................................................................................................... 1-3

C28x CPU............................................................................................................................................... 1-4

Multiplier, ALU, and Shifters............................................................................................................. 1-5

TMS320C28x Internal Bussing .......................................................................................................... 1-6

Special Instructions............................................................................................................................. 1-7

Pipeline Advantage............................................................................................................................. 1-8

Memory ................................................................................................................................................... 1-9

Memory Map...................................................................................................................................... 1-9

Code Security Module (CSM)...........................................................................................................1-10

Peripherals .........................................................................................................................................1-10

Fast Interrupt Response.........................................................................................................................1-11

C28 Mode...............................................................................................................................................1-12

Reset.......................................................................................................................................................1-13

Summary ................................................................................................................................................1-14

1 - 2 C28x - Architecture Overview

What is the TMS320C28x?

The TMS320C28x is a 32-bit fixed point DSP that specializes in high performance control applications such as, robotics, industrial automation, mass storage devices, lighting, optical networking, power supplies, and other control applications needing a single processor to solve a high performance application.

C28x Block Diagram

Program Bus

A(18--0)0)

A(18

D(15--0)0)

D(15

Realtime

JTAG

22

32

Sectored

Flash

bit

3232--bit

32-bit

Auxiliary

Registers

Program Bus

32x32 bit

Multiplier

Register Bus

CPU

RAM

RR--MM--W

R-M-W

Atomic

ALU

W

Boot

ROM

PIE

Interrupt

Manager

3

32 bit

Timers

Event

Manager A

Event

Manager B

bit ADC

1212--bit ADC

12-bit ADC

Watchdog

McBSP

CAN2.0B

SCI--AA

SCI

SCI-A

SCI--BB

SCI

SCI-B

SPI

Data Bus

The C28x architecture can be divided into 3 functional blocks:

• CPU and busing

• Memory

• Peripherals

GPIO

C28x - Architecture Overview 1 - 3

C28x CPU

The C28x is a highly integrated, high performance solution for demanding control applications. The C28x is a cross between a general microcontroller and a digital signal processor, balancing the code density of a RISC chip and the execution speed of a DSP with the architecture, firmware, and development tools of a microcontroller.

The DSP features include a modified Harvard architecture and circular addressing. The RISC features are single-cycle instruction execution, register-to-register operations, and modified Harvard architecture. The microcontroller features include ease of use through an intuitive instruction set, byte packing and unpacking, and bit manipulation.

bit

3232--bit

32-bit

Auxiliary

Registers

Realtime

JTAG

Program Bus

32x32 bit

Multiplier

Register Bus

CPU

Data Bus

W

RR--MM--W

R-M-W

Atomic

ALU

C28x CPU



MCU/DSP balancing code density



MCU/DSP balancing code density

& execution time.



PIE

Interrupt

Manager

3

32 bit

Timers

3232--bit fixed



32 x 32 bit fixed--



32 x 32 bit fixed



Dual 16 x 16 single--



Dual 16 x 16 single

point MAC (DMAC)



3232--/64



64/32 and 32/32 modulus division



64/32 and 32/32 modulus division



Fast interrupt service time



Fast interrupt service time



Single cycle read--



Single cycle read

instructions



Unique real--



Unique real

capabilities

Upward code compatibility



Upward code compatibility

Supports 32--

Supports 32

for improved execution time;

Supports 16--

Supports 16

for improved code efficiency

bit fixed--

/64--

bit saturation

bit instructions

point DSP

point MAC

cycle fixed--

cycle fixed

modify--

modify

time debugging

write

The C28x design supports an efficient C engine with hardware that allows the C compiler to generate compact code. Multiple busses and an internal register bus allow an efficient and flexible way to operate on the data. The architecture is also supported by powerful addressing modes, which allow the compiler as well as the assembly programmer to generate compact code that is almost one to one corresponded to the C code.

The C28x is as efficient in DSP math tasks as it is in system control tasks that typically are handled by microcontroller devices. This efficiency removes the need for a second processor in many systems.

The C28x is one of several members of the fixed-point generations of digital signal processors (DSPs) in the TMS320 family. The C28x is source-code and object-code compatible with the C27x. In addition, the C28x is source code compatible with the 24x/240x DSP and previously written code can be reassembled to run on a C28x device. This allows for migration of existing code onto the C28x.

1 - 4 C28x - Architecture Overview

C28x CPU

Multiplier, ALU, and Shifters

C28x Multiplier and ALU / Shifters

Program Bus

Data Bus

Shift R/L (0--

Shift R/L (0

Data Bus

32

16/32

XT (32) or T/TL

16

16)

32

AH (16)

AH.MSB AH.LSB

Shift R/L (0--

Shift R/L (0

XT (32) or T/TL

MULTIPLIER

32

Dual 16 x 16

P (32) or PH/PL

Shift R/L (0--

Shift R/L (0

ALU (32)

32

ACC (32)

AL (16)

AL.MSB AL.LSB

32

•

32

•

32

32 x 32 or

32

16)

16/32

8/16

•

32

The 32 x 32-bit MAC capabilities of the C28x and its 64-bit processing capabilities, enable the C28x to efficiently handle higher numerical resolution problems that would otherwise demand a more expensive floating-point processor solution. Along with this is the capability to perform two 16 x 16-bit multiply accumulate instructions simultaneously or Dual MACs (DMAC).

C28x

XARn

XARn →→3232--

XARn

ARn→→1616--

ARn

XAR0

XAR1

XAR2

XAR3

XAR4

XAR5

XAR6

XAR7

ARAU

bits

, DP and Memory

Data Bus

Program Bus

6 LSB

from IR

32

Data Memory

DP (16)

22

MUX

C28x - Architecture Overview 1 - 5

C28x CPU

TMS320C28x Internal Bussing

As with many DSP type devices, multiple busses are used to move data between the memories and peripherals and the CPU. The C28x memory bus architecture contains:

• A program read bus (22 bit address line and 32 bit data line)

• A data read bus (32 bit address line and 32 bit data line)

• A data write bus (32 bit address line and 32 bit data line)

C28x Internal Bus Structure

Program

PC

Decoder

Registers

ARAU

SP

DPDP@X

XAR0

to

XAR7

SP

@X

Program Address Bus (22)

Program--

Program

Data--

Data

Data--

Data

Execution

MPY32x32

ALU

XT

P

ACC

read Data Bus (32)

read Address Bus (32)

read Data Bus (32)

RR--MM--W

Atomic

ALU

W

Debug

Real--

Time

Real

Time

Emulation

&

Test

Engine

JTAG

Program

(4M* 16)

Data

(4G * 16)

Memory

Standard

Peripherals

External

Register Bus / Result Bus

Data/Program--

Data/Program

Data--

Data

write Data Bus (32)

write Address Bus (32)

External

Interfaces

The 32-bit-wide data busses enable single cycle 32-bit operations. This multiple bus architecture, known as a Harvard Bus Architecture enables the C28x to fetch an instruction, read a data value and write a data value in a single cycle. All peripherals and memories are attached to the memory bus and will prioritize memory accesses.

1 - 6 C28x - Architecture Overview

C28x CPU

Special Instructions

C28x Atomic Read/Modify/Write

Atomic Instructions Benefits:



Atomic Instructions Benefits:

LOAD

Registers

CPU

LOAD

ALU / MPY

STORE

READ

WRITE

Mem

Simpler programming

¾

Simpler programming

¾

Smaller, faster code

¾

Smaller, faster code

Uninterruptible (Atomic)

¾

Uninterruptible (Atomic)

¾

More efficient compiler

¾

More efficient compiler

Standard Load/Store

DINT

MOV

AND

MOV

EINT

AL,*XAR2

AL,#1234h

*XAR2,AL

6 words / 6 cycles

Atomic Read/Modify/Write

AND *XAR2,#1234h

2 words / 1 cycles

Atomics are small common instructions that are non-interuptable. The atomic ALU capability supports instructions and code that manages tasks and processes. These instructions usually execute several cycles faster than traditional coding.

C28x - Architecture Overview 1 - 7

C28x CPU

Pipeline Advantage

C28x Pipeline

F

D

R

F

D

2

1

D

1

F

D

F

D

2

F

1

F

1

2

1

A

F

B

C

D

E

F

G

H

F1: Instruction Address

F2: Instruction Content

D1: Decode Instruction

D2: Resolve Operand Addr

R1: Operand Address

R2: Get Operand

X: CPU doing “real” work

W: store content to memory

F

2

1

2

1

R

1

D

R

D

R

2

D

1

F

D

F

D

2

F

1

F

X

W

2

1

2

1

2

1

W

1

R

D

1

F

2

F

1

W

X

2

R

X

R

X

1

2

1

2

R

2

1

2

1

Protected Pipeline

2

1

2

D

R

D

R

2

1

2

1

D

1

2

1

2

F

D

F

D

2

1

2

1

F

1

2

1

2

Order of results are as written in

¾

Order of results are as written in

source code

¾

Programmer need not worry about

¾

Programmer need not worry about

the pipeline

stage pipeline

88--stage pipeline

W

X

W

R

X

2

1

2

1

W

X

W

R

X

2

1

2

W

X

W

R

X

R

X

W

R

XXW

R

2

1

2

1

R

W

X

2

R

1

R

D

R

D

E & G Access

same address

W

X W

W

X W

W

The C28x uses a special 8-stage protected pipeline to maximize the throughput. This protected pipeline prevents a write to and a read from the same location from occurring out of order.

This pipelining also enables the C28x to execute at high speeds without resorting to expensive high-speed memories. Special branch-look-ahead hardware minimizes the latency for conditional discontinuities. Special store conditional operations further improve performance.

1 - 8 C28x - Architecture Overview

Memory

The memory space on the C28x is divided into program and data space. There are several different types of memory available that can be used as both program or data space. They include the flash memory, single access RAM (SARAM), expanded SARAM, and Boot ROM which is factory programmed with boot software routines or standard tables used in math related algorithms.

Memory Map

The C28x CPU contains no memory, but can access memory both on and off the chip. The C28x uses 32-bit data addresses and 22-bit program addresses. This allows for a total address reach of 4G words (1 word = 16 bits) in data space and 4M words in program space. Memory blocks on all C28x designs are uniformly mapped to both program and data space.

This memory map shows the different blocks of memory available to the program and data space.

TMS320F2812 Memory Map

Data

0x00 0000

0x00 0400

0x00 0800

0x00 0D00

0x00 1000

0x00 6000

0x00 7000

0x00 8000

0x00 9000

0x00 A000

0x3D 7800

0x3D 7C00

0x3D 8000

0x3F 8000

0x3F A000

0x3F F000

0x3F FFC0

| Program

Data

| Program

MO SARAM (1K)

M1 SARAM (1K)

PF 0 (2K)

PIE vector

(256)

ENPIE=1

PF 2 (4K)

PF 1 (4K)

LO SARAM (4K)

L1 SARAM (4K)

FLASH (128K)

128--

128

HO SARAM (8K)

Boot ROM (4K)

BROM vector (32)

MP/MC=0 ENPIE=0

reserved

reserved reserved

reserved

OTP (1K)

reserved

Bit Password

reserved

MP/MC=0

Data

| Program

Data

| Program

reserved

XINT Zone 0 (8K) XINT Zone 1 (8K)

reserved

XINT Zone 2 (0.5M) XINT Zone 6 (0.5M)

reserved

XINT Zone 7 (16K)

MP/MC=1

XINT Vector-RAM (32)

MP/MC=1 ENPIE=0

0x00 2000

0x00 4000

0x08 0000

0x10 0000

0x18 0000

0x3F C000

CSM: LO, L1

OTP, FLASH

C28x - Architecture Overview 1 - 9

Memory

Code Security Module (CSM)

Code Security Module

Prevents reverse engineering and



Prevents reverse engineering and

protects valuable intellectual property

0x00 8000

0x00 9000

0x00 A000

0x3D 7800

0x3D 7C00

0x3D 8000



128--



bit user defined password is stored in Flash

128

bit user defined password is stored in Flash

128

128--

bits = 2

128

bits = 2

To try 1 password every 2 cycles at 150 MHz, it

would take at least 1.4 x 10

possible combinations!

128

LO SARAM (4K)

L1 SARAM (4K)

reserved

OTP (1K)

reserved

FLASH (128K)

128--

Bit Password

128

Bit Password

= 3.4 x 10

38

possible passwords

23

years to try all

Peripherals

The C28x comes with many built in peripherals optimized to support control applications. These peripherals vary depending on which C28x device you choose.

• Event Manager

• Analog-to-Digital Converter

• Watchdog Timer

• SPI

• SCI

• CAN

• McBSP

• GPIO

1 - 10 C28x - Architecture Overview

Fast Interrupt Response

The fast interrupt response, with automatic context save of critical registers, resulting in a device that is capable of servicing many asynchronous events with minimal latency. C28x implements a zero cycle penalty to do 14 registers context saved and restored during an interrupt. This feature helps reduces the interrupt service routine overheads.

C28x Fast Interrupt Response Manager

96 dedicated PIE

¾

96 dedicated PIE

vectors

No software decision

¾

No software decision

96

PIE module

For 96

interrupts

PIE

Register

Map

INT1 to

INT12

12 interrupts

28x CPU Interrupt logic

IFR

IER

IFR

IER

INTM

28x

CPU

making required

Direct access to RAM

¾

Direct access to RAM

vectors

Auto flags update

¾

Auto flags update

Concurrent auto

¾

Concurrent auto

context save

Auto Context Save

T

AH

PH

AR1 (L)

DP

DBSTAT

PC(msw)

ST0

AL

PL

AR0 (L)

ST1

IER

PC(lsw)

Peripheral Interrupts 12x8 = 96

C28x - Architecture Overview 1 - 11

C28 Mode

The C28x is one of several members of the fixed-point generations of digital signal processors (DSPs) in the TMS320 family. The C28x is source-code and object-code compatible with the C27x. In addition, the C28x is source code compatable with the 24x/240x DSP and previously written code can be reassembled to run on a C28x device. This allows for migration of existing code onto the C28x.

C28x / C24x Modes

Mode Type

C24x Mode

C28x Mode

Test Mode (default)

Reserved

C24x source--

¾

C24x source

Allows you to run C24x source code which has been reassembled

¾

Allows you to run C24x source code which has been reassembled

using the C28x code generation tools (need new vectors)

C28x mode:

¾

C28x mode:

Can take advantage of all the C28x native features

¾

Can take advantage of all the C28x native features

compatible mode:

Mode Bits

OBJMODE AMODE

1

0 00

0

0 11

0

1

0

Compiler

Option

v28 --

m20

--v28

m20

v28

--v28

v27

--v27

(workshop)

1 - 12 C28x - Architecture Overview

Reset

Reset ––

Reset

OBJMODE=0 AMODE=0

ENPIE=0 VMAP=1

XMPNMC=0

(microcomputer mode)

Reset vector fetched

from boot ROM

0x3F FFC0

Note:

Details of the various boot options will be

discussed in the Reset and Interrupts module

Bootloader

OBJMODE = 1

AMODE = 0

Boot determined by

state of GPIO pins

Execution

Entry Point

H0 SARAM

sets

C28x - Architecture Overview 1 - 13

Summary



High performance 32--



High performance 32



32 x 32 bit or dual 16 x 16 bit MAC



32 x 32 bit or dual 16 x 16 bit MAC

bit DSP

Atomic read--



Atomic read



stage fully protected pipeline

88--stage fully protected pipeline

Fast interrupt response manager

128Kw on--

128Kw on

Code security module (CSM)

Two event managers

bit ADC module

1212--bit ADC module

56 shared GPIO pins

Watchdog timer

Communications peripherals

modify--

modify

chip flash memory

write instructions

1 - 14 C28x - Architecture Overview

Programming Development Environment

Introduction

This module will explain how to use Code Composer Studio (CCS) integrated development environment (IDE) tools to develop a program. Creating projects and setting building options will be covered. Use and the purpose of the linker command file will be described. Additionally, the DSP/BIOS Configuration Tool will be used to handle system memory and system setup.

Learning Objectives

Use Code Composer Studio to:



Use Code Composer Studio to:



Create a



Create a



Set



Build Options

Set

Build Options

Project

Create a



Create a

Describes a system’s available memory



Describes a system’s available memory



Indicates where sections will be placed



Indicates where sections will be placed

in memory

Use



Use

DSP/BIOS Configuration Tool



Handle system memory and system setup



Handle system memory and system setup



Create a .



Create a .

user

cdb

linker command file which:

to:

and .

cmd

file

C28x - Programming Development Environment 2 - 1

Module Topics

Programming Development Environment .............................................................................................. 2-1

Module Topics......................................................................................................................................... 2-2

Code Composer Studio ........................................................................................................................... 2-3

Software Development and COFF Concepts...................................................................................... 2-3

Projects ............................................................................................................................................... 2-5

Build Options...................................................................................................................................... 2-6

Creating a Linker Command File ........................................................................................................... 2-9

Sections .............................................................................................................................................. 2-9

Linker Command Files (.cmd).........................................................................................................2-12

Memory-Map Description .................................................................................................................2-12

Section Placement..............................................................................................................................2-14

Exercise 2a.............................................................................................................................................2-15

Summary: Linker Command File......................................................................................................2-16

Lab 2a: Linker Command File...............................................................................................................2-17

DSP/BIOS Configuration Tool...............................................................................................................2-21

Lab 2b: DSP/BIOS Configuration Tool .................................................................................................2-26

Solutions.................................................................................................................................................2-30

2 - 2 C28x - Programming Development Environment

Code Composer Studio

Software Development and COFF Concepts

In an effort to standardize the software development process, TI uses the Common Object File Format (COFF). COFF has several features which make it a powerful software development system. It is most useful when the development task is split between several programmers.

Each file of code, called a module, may be written independently, including the specification of all resources necessary for the proper operation of the module. Modules can be written using Code Composer Studio (CCS) or any text editor capable of providing a simple ASCII file output. The expected extension of a source file is .ASM for assembly and .C for C programs.

Code Composer Studio

Build

Compile

Build

lnk..

lnk

cmd

Probe In

SIM

eZdsp™™

eZdsp

Asm

DSP/BIOS

Edit



Code Composer Studio includes:



Code Composer Studio includes:



DSP/BIOS

Config

Tool

Integrated Edit/Debug GUI

Code Generation Tools

DSP/BIOS

Link

DSP/BIOS

Libraries

Debug

Probe Out

Graphs

Profiling

EVM

Third

Party

XDS

DSP

Board

Code Composer Studio includes a built-in editor, compiler, assembler, linker, and an automatic build process. Additionally, tools to connect file input and output, as well as built-in graph displays for output are available. Other features can be added using the plug-ins capability

Numerous modules are joined to form a complete program by using the linker. The linker efficiently allocates the resources available on the device to each module in the system. The linker uses a command (.CMD) file to identify the memory resources and placement of where the various sections within each module are to go. Outputs of the linking process includes the linked object file (.OUT), which runs on the DSP, and can include a .MAP file which identifies where each linked section is located.

The high level of modularity and portability resulting from this system simplifies the processes of verification, debug and maintenance. The process of COFF development is presented in greater detail in the following paragraphs.

C28x - Programming Development Environment 2 - 3

Code Composer Studio

The concept of COFF tools is to allow modular development of software independent of hardware concerns. An individual assembly language file is written to perform a single task and may be linked with several other tasks to achieve a more complex total system.

Writing code in modular form permits code to be developed by several people working in parallel so the development cycle is shortened. Debugging and upgrading code is faster, since components of the system, rather than the entire system, is being operated upon. Also, new systems may be developed more rapidly if previously developed modules can be used in them.

Code developed independently of hardware concerns increases the benefits of modularity by allowing the programmer to focus on the code and not waste time managing memory and moving code as other code components grow or shrink. A linker is invoked to allocate systems hardware to the modules desired to build a system. Changes in any or all modules, when re-linked, create a new hardware allocation, avoiding the possibility of memory resource conflicts.

Code Composer Studio: IDE



Integrates



Integrates

and debug



Single--



Single



Powerful



Powerful



Automated tasks using



Automated tasks using

Built--



Built

Support TI or 3



Support TI or 3

: edit, code generation,

click access

graphing/profiling

in access to

using buttons

BIOS

rd

party

tools

GEL scripts

functions

plug--

ins

plug

ins

2 - 4 C28x - Programming Development Environment

Code Composer Studio

Projects

Code Composer works with a project paradigm. Essentially, within CCS you create a project for each executable program you wish to create. Projects store all the information required to build the executable. For example, it lists things like: the source files, the header files, the target system’s memory-map, and program build options.

The CCS Project

Project (.



Source files (by reference)



Source files (by reference)





Project settings:



Project settings:



pjt

) files contain:

pjt

) files contain:

Source (C, assembly)

Libraries

DSP/BIOS configuration

Linker command files

Build Options (compiler and

assembler)

Build configurations

DSP/BIOS

Linker

The project information is stored in a .PJT file, which is created and maintained by CCS. To create a new project, you need to select the

Project:New… menu item.

Along with the main Project menu, you can also manage open projects using the right-click popup menu. Either of these menus allows you to Add Files… to a project. Of course, you can also drag-n-drop files onto the project from Windows Explorer.

C28x - Programming Development Environment 2 - 5

Code Composer Studio

Build Options

Project options direct the code generation tools (i.e. compiler, assembler, linker) to create code according to your system’s needs. When you create a new project, CCS creates two sets of build options – called Configurations: one called Debug, the other Release (you might think of as Optimize).

To make it easier to choose build options, CCS provides a graphical user interface (GUI) for the various compiler options. Here’s a sample of the Debug configuration options.

Build Options GUI --

Build Options GUI

GUI has 8 pages of categories for code



GUI has 8 pages of categories for code

generation tools

Controls many aspects of the build process,



Controls many aspects of the build process,

such as:



Optimization level



Optimization level



Target device



Target device



Compiler/assembly/link options



Compiler/assembly/link options

Compiler

There is a one-to-one relationship between the items in the text box and the GUI check and dropdown box selections. Once you have mastered the various options, you can probably find yourself just typing in the options.

2 - 6 C28x - Programming Development Environment

Code Composer Studio

Build Options GUI --

Build Options GUI



There are many linker options but these four handle all of the basic needs.

• -o <filename> specifies the output (executable) filename.

Linker

GUI has 2 categories

for linking

Specifies various link

options

Debug\\

“.“.\\Debug

on subfolder level

below project (.

location

” indicates

pjt) )

pjt

• -m <filename> creates a map file. This file reports the linker’s results.

• -c tells the compiler to autoinitialize your global and static variables.

• -x tells the compiler to exhaustively read the libraries. Without this option libraries are

searched only once, and therefore backwards references may not be resolved.

C28x - Programming Development Environment 2 - 7

Code Composer Studio

Default Build Configurations

For new projects, CCS automatically



For new projects, CCS automatically

creates two build configurations:



Debug



Debug

Release



Release



Use the drop--



Use the drop

select the build configuration

Add/Remove your own custom



Add/Remove your own custom

build configurations using

Project Configurations

Edit a configuration:



Edit a configuration:

1.

Set it active

1.

Set it active

Modify build options

2.

Modify build options

3.

Save project

3.

Save project

unoptimized))

((unoptimized

(optimized)

down menu to quickly

To help make sense of the many compiler options, TI provides two default sets of options (configurations) in each new project you create. The Release (optimized) configuration invokes the optimizer with –o3 and disables source-level, symbolic debugging by omitting –g (which disables some optimizations to enable debug).

2 - 8 C28x - Programming Development Environment

Creating a Linker Command File

Sections

Looking at a C program, you'll notice it contains both code and different kinds of data (global, local, etc.).

Sections

Global Vars (.

int

void main(void)

{

}

Local vars (

In the TI code-generation tools (as with any toolset based on the COFF – Common Object File Format), these various parts of a program are called Sections. Breaking the program code and data into various sections provides flexibility since it allows you to place code sections in ROM and variables in RAM. The preceding diagram illustrated five sections:

• Global Variables

ebss)

ebss

x = 2;

y = 7;

long z;

z = x + y;

.stack) Code (

.stack

Init vals (..

cinit)

cinit

.text)

.text



Every C program



Every C program

consists of different

parts called



All default sections



All default sections

names begin with “.”



The compiler has



The compiler has

default sections

names for

and

uninitialized

and

uninitialized

sections

initialized

sections

• Initial Values for global variables

• Local Variables (i.e. the stack)

• Code (the actual instructions)

C28x - Programming Development Environment 2 - 9

Creating a Linker Command File

Following is a list of the sections that are created by the compiler. Along with their description, we provide the Section Name defined by the compiler.

Initialized Sections

Name

.text

cinit

..cinit

econst

..econst

.switch

pinit

..pinit

Compiler Section Names

Description

code

initialized global and static variables program

constant data (e.g. const

tables for switch statements

tables for global constructors (C++)

int

k = 3;) data

int

k = 3;) data

Link Location

program

prog

/low 64K data

prog

/low 64K data

program

Uninitialized

Name

ebss

..ebss

.stack stack space

esysmem

..esysmem

Sections

Description

global & static variables

memory for far

malloc

functions

Link Location

data

low 64K data

data

Sections of a C program must be located in different memories in your target system. This is the big advantage of creating the separate sections for code, constants, and variables. In this way, they can all be linked (located) into their proper memory locations in your target embedded system. Generally, they’re located as follows:

Program Code (.text)

Program code consists of the sequence of instructions used to manipulate data, initialize system settings, etc. Program code must be defined upon system reset (power turn-on). Due to this basic system constraint it is usually necessary to place program code into non-volatile memory, such as FLASH or EPROM.

Constants (.cinit – initialized data)

Initialized data are those data memory locations defined at reset.It contains constants or initial values for variables. Similar to program code, constant data is expected to be valid upon reset of the system. It is often found in FLASH or EPROM (non-volatile memory).

Variables (.ebss – uninitialized data)

Uninitialized data memory locations can be changed and manipulated by the program code during runtime execution. Unlike program code or constants, uninitialized data or variables must reside in volatile memory, such as RAM. These memories can be modified and updated, supporting the way variables are used in math formulas, high-level languages, etc. Each variable must be declared with a directive to reserve memory to contain its value. By their nature, no value is assigned, instead they are loaded at runtime by the program

2 - 10 C28x - Programming Development Environment

Creating a Linker Command File

Placing Sections in Memory

Memory

0x00 0000

0x00 0400

0x3D 8000

Memory

M0SARAM

(0x400)

M1SARAM

(0x400)

FLASH

(0x20000)

Sections

ebss

..ebss

.stack

cinit

..cinit

.text

Linking code is a three step process:

1. Defining the various regions of memory (on-chip SARAM vs. FLASH vs. External Memory).

2. Describing what sections go into which memory regions

3. Running the linker with “build” or “rebuild”

C28x - Programming Development Environment 2 - 11

Creating a Linker Command File

Linker Command Files (.cmd)

The linker concatenates each section from all input files, allocating memory to each section based on its length and location as specified by the MEMORY and SECTIONS commands in the linker command file.

Linking



Memory description



Memory description

 Memory description



How to place s/w into h/w



How to place s/w into h/w

 How to place s/w into h/w

obj

..obj

Link.

Linker

.map

cmd

.out

Memory-Map Description

Describe the memory configuration of your target system to the linker. Without this specification, the linker might place code or data into memory that doesn’t exist.

The format is: Name: origin = 0x????, length = 0x????

For example, if you placed a 2K EPROM starting at memory location zero, it would read:

MEMORY { EPROM: origin = 0x0000 , length = 0x0800 }

You define each memory segment using the above format. If you added a RAM and an ABT646 transceiver, it might look like:

MEMORY { EPROM: origin = 0x0000 , length = 0x0800 RAM: origin = 0x1000 , length = 0x02000 ABT646: origin = 0x8000 , length = 0x00001 }

2 - 12 C28x - Programming Development Environment

Texas Instruments C28 Series, TMS320C28 Series Student Manual

Specifications and Main Features

Frequently Asked Questions

User Manual