Texas Instruments BQ2502MA Datasheet

Features

➤ Power monitoring, backup supply,

and switching for 3V battery­backup applications

➤ Write-protect control
➤ Input decoder for control of up to

2 banksof SRAM

➤ 3-volt backup power output
➤ Internal 130mAh lithium-coin

cell

➤ Reset output for system power-on

reset

➤ Less than 10ns chip-enable

propagation delay

➤ 5% or 10% supply operation

Integrated Backup Unit

General Description

The CMOS bq2502 Integrated Backup
Unit provides all the necessary func­tions for converting one or two
banks of standard CMOS SRAM
into nonvolatile read/write memory.

A precision comparator monitors the 5V

input for an out-of-tolerance condi-

V

CC

tion. When out of tolerance is detected,
the two conditioned chip-enable outputs
are forced inactive to write-protect both
banks of SRAM.

Power for the external SRAMs is
switched from the V
internal battery-backup supply as
VCCdecays. On a subsequent
power-up, the V
matically switched from the internal
lithium supply to the VCCsupply.

supply to the

CC

supply is auto-

OUT

bq2502

The external SRAMs are write-pro­tected until a power-valid condition
exists. The reset output provides
power-fail and power-on resets for the
system.

During power-valid operation, the
input decoder selects one of two
banks of SRAM.

The internal lithium cell is initially
electrically isolated, protecting the
battery from accidental discharge.
Connection to the battery is made
only after the first application of

.

V

CC

Pin Connections

NC
NC

SS

1
2

A

3
4
5

6

V

OUT

THS
V

12-Pin 600-mil DIP Module

PN250201.eps

12
11
10

V

CC
CE
CE

CE
NC
RST

CON1
CON2

9
8

7

Functional Description

Two banks of CMOS static RAM can be battery-backed
using the V
from the bq2502. As the voltage input VCCslews down
during a power failure, the two conditioned chip-enable
outputs, CE
independent of the chip-enable input CE.

This activity unconditionally write-protects external SRAM

falls to an out-of-tolerance threshold V

as V

CC

selected by the threshold-select input pin, THS. If THS is
tied to VSS, the power-fail detection occurs at 4.62V typical
for 5% supply operation.

Apr.1991

and conditioned chip-enable output pins

OUT

CON1

and CE

, are forced inactive

CON2

PFD.VPFD

Pin Names

V

OUT

RST
THS Threshold select input
CE

CE

CON1

CE

CON2

A Bank select input
NC No connect
V

CC

V

SS

If THS is tied to V

4.37V typical for 10% supply operation. The THS pin
must be tied to VSSor V

If a memory access is in process to any of the two exter­nal banks of SRAM during power-fail detection, that
memory cycle continues to completion before the memory
is write-protected. If the memory cycle is not terminated
within time t

is

outputs are unconditionally driven high, write-protecting
the controlled SRAMs.

Supply output
Reset output

chip-enable active low input

, Conditioned chip-enable outputs

5-volt supply input
Ground

, power-fail detection occurs at

OUT

for proper operation.

OUT

(150µs maximum), the two chip-enable

WPT

1

bq2502

As the supply continues to fall past V
switching device forces V
ergy source. CE
V

energy source.

OUT

During power-up, V
ply as VCCrises above the backup cell input voltage
sourcing V
inactive for time t
power supply has reached V
input,to allow for processor stabilization.

The reset output (RST
maximum) after V
mum of 40ms (120ms maximum) after power returns
valid. The RST output can be used as the power-on re­set for a microprocessor. Access to the external RAM
may begin when RST returns inactive.

During power-valid operation, the CE
through to one of the two CE
gation delay of less than 10ns. The CE input is output on
one of the two CE
level of bank select input A, as shown in the Truth Ta­ble.

CON1

. Outputs CE

OUT

OUT

CER

PFD,

CON

to the internal backup en-

OUT

and CE

CON2

is switched back to the 5V sup-

and CE

CON1

(120ms maximum) after the

, independent of the CE

PFD

) goes active within tR(150µs

and remains active for a mini-

outputs with a propa-

CON

output pins depending on the

, an internal

PFD

are held high by the

are held

CON2

input is passed

5V

V

OUT

V

CC

bq2502

Bank select input A is usually tied to a high-order address

pin so that a large nonvolatile memory can be designed

using lower-density memory devices .Nonvolatility and de-

coding are achieved by hardware hookup, as shown in Fig-

ure 1.

The internal lithium cell is capable of supplying 3V on

V

for an extended period. The cumulative length of

OUT

time that the external SRAMs retain data in the ab-

sence of power is a function of the data-retention cur-

rent of the SRAMs used. The initial capacity of the in-

ternal lithium cell is 130mAh. Typically, if the data- re-

tention currents for two external SRAMs are 1µA per

SRAM at room temperature, nonvolatility is calculated

to be for more than 7 years. If only one external SRAM

is used, the data-retention time increases to more than

13 years.

The bq2502 battery life is a function ofthe time spent in

battery-backed mode and the data-retention current of

the external SRAM. For example, office equipment is

generally powered on for 8 hours and powered off for 16

hours. Under these conditions, a single bq2502 provides

SRAMs drawing 2µA total data-retention current with

more than 10 years of nonvolatility.

V

CC

CMOS
SRAM

V

CC

CMOS
SRAM

CE

A
CE

CE

CON1
CON2

CE

CE

THS
V

RST

SS

To Microprocessor

FG250201.eps

Figure 1. Hardware Hookup (5% Supply Operation)

2

Apr.1991

As shipped from Benchmarq, the internal lithium cell is
electrically isolated from V
Self-discharge in this condition is less than 0.5% per
year at 20°C.

Note: Following the first application of V
tion is broken, and the backup cell provides power to
V

OUT

,CE

CON1

,and CE

CON2

,CE

OUT

for the external SRAM.

CON1

, and CE

, this isola-

CC

CON2

Caution:

Take care to avoid inadvertent discharge through
V

,CE

OUT

has been broken.

This isolation can be reestablished by applying a valid
isolation signal to the bq2502. See Figure 2. This signal
requires CE
ing a power--down. Between these two points in time,
CE must be brought to (0.48 to 0.52)*VCCand held for
at least 700ns. The isolation signal is invalid if CE ex­ceeds 0.54*VCCat any point between VCCcrossing
V

and VSO.

PFD

The battery is connected to V
quent application and removal of VCC.

, and CE

CON1

low as VCCcrosses both V

after battery isolation

CON2

OUT

and VSOdur-

PFD

immediately on subse-

bq2502

.

V

PFD

V

CC

V

SO

700ns

0.5 V

TD220201.eps

CC

CE

Figure 2. Battery Isolation Signal

Truth Table

CE ACE

HXHH

LLLH
LHHL

Apr.1991

Input Output

CON1

3

CE

CON2

bq2502

Absolute Maximum Ratings

Symbol Parameter Value Unit Conditions

V

CC

V

T

T

OPR

T

STG

T

BIAS

T

SOLDER

I

OUT

Note: Permanent device damage may occur if Absolute Maximum Ratings are exceeded. Functional opera-

DC voltage applied on VCCrelative to V

SS

DC voltage applied on any pin excluding V
relative to V

SS

-0.3 to +7.0 V

CC

-0.3 to +7.0 V V

+ 0.3

V

≤

T

CC

Operating temperature 0 to 70 °C
Storage temperature -40 to +70 °C
Temperature under bias -10 to +70 °C
Soldering temperature 260 °C For 10 seconds
V

current 200 mA

OUT

tion should be limited to the Recommended DC OperatingConditions detailed in this data sheet. Expo­sure to conditions beyond the operational limits for extendedperiods of time may affect device reliability.

Recommended DC Operating Conditions (T

= 0 to 70°C)

A

Symbol Parameter Minimum Typical Maximum Unit Notes

V

CC

V

SS

V

IL

V

IH

Supply voltage

4.50 5.0 5.5 V THS= V
Supply voltage 0 0 0 V
Input low voltage -0.3 - 0.8 V
Input high voltage 2.2 - VCC+ 0.3 V

4.75 5.0 5.5 V THS= V

SS

OUT

THS Threshold select -0.3 - VCC+ 0.3 V

Note: Typical values indicate operation at TA= 25°C, VCC=5VorV

BAT

.

4

Apr.1991