Texas Instruments bq24745 Schematics

EAO

ICREF

EAI

FBO

CE

VDDP

LGATE

PGND

CSOP

CSON

bq24745

28LDQFN

TOP VIEW

ACIN

VREF

NC

VFB

1

28

7

21

15

22

2

3

4

5

6

20

19

18

17

16

27 26 25 24

8 149 10 11 12 13

23

VICM

SDA

SCL

VDDSMB

GND

ACOK

NC

CSSP

CSSN

ICOUT

BOOT

UGAT

PHAS

DCIN

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SMBus-Controlled Multi-Chemistry Battery Charger With Input

Current Detect Comparator and Charge Enable Pin

1

FEATURES

• NMOS-NMOS Synchronous Buck Converter
with 300-kHz Frequency and >95% Efficiency

• 30-ns Minimum Driver Dead-Time and 99.5%
Maximum Effective Duty Cycle

• High-Accuracy Voltage and Current Regulation
– ±0.5% Charge Voltage Accuracy
– ±3% Charge Current Accuracy
– ±3% Adapter Current Accuracy
– ±2% Input Current Sense Amp Accuracy

• Integration
– Input Current Comparator, With Adjustable

Threshold and Hysteresis

– Internal Soft-Start

• Safety
– Dynamic Power Management (DPM)

• Up to 19.2-V Battery Voltage

• 7-V–24-V AC/DC-Adapter Operating Range

• Simplified SMBus Control Interface
– Charge Voltage DAC (1.024 V–19.2 V)
– Charge Current DAC (128 mA–8.064 A)
– Adapter Current Limit DPM DAC (256

mA–11.008 A)

• Status and Monitoring Outputs
– AC/DC Adapter Present With Adjustable

Voltage Threshold

– Input Current Comparator With Adjustable

Threshold and Hysteresis

– Current Sense Amplifier for Current Drawn

From Input Source

• Charge Any Battery Chemistry: Li+, NiCd,
NiMH, Lead Acid, Etc.

• Charge Enable Pin

• < 10-μA Battery Current With Adapter

Removed

1

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.

bq24745

SLUS761D –DECEMBER 2007– REVISED OCTOBER 2011

Check for Samples: bq24745

• < 1-mA Input DCIN Current With Adapter
Present and Charge Disabled

• 28-Pin, 5-mm × 5-mm QFN Package

APPLICATIONS

• Notebook and Ultra-Mobile Computers

• Portable Data-Capture Terminals

• Portable Printers

• Medical Diagnostics Equipment

• Battery Bay Chargers

• Battery Backup Systems

DESCRIPTION

The bq24745 is a high-efficiency, synchronous
battery charger with an integrated input-current
comparator, offering low component count for
space-constrained, multi-chemistry battery-charging
applications. The input-current, charge-current, and
charge-voltage DACs allow very high regulation
accuracies that can be easily programmed by the
system power-management microcontroller using the
SMBus interface. The bq24745 charges two, three, or
four series Li+ cells, and is available in a 28-pin,
5-mm × 5 mm QFN package.

Copyright © 2007–2011, Texas Instruments Incorporated

(1) Pullup rail could be either VREF or other system rail.

RAC

0.010

RSR

0.010

Q1 (ACFET)

SI4835BDY

N

PP

CSSN

CSSP

ACIN

VREF

CE

SDA

SCL

SMBus

VICM

HOST

(EC)

UGATE

N

PHASE

BOOT

VDDP

LGATE

PGND

CSOP

CSON

PACK+

PACK-

CHRG_IN

ADAPTER +

ADAPTER -

GND

bq24745

309k
1%

49.9k
1%

R1

R2

1uFC4

C2

0.1u

C3

0.1u

100pFC5

C6
1u

Q3
FDS6680A

Q4
FDS6680A

0.1uF

C7

L1

5.6uH

D1 BAT54

C8
1u

C9

0.1uF

C10

0.1uF

C13
2x10u

C15
10uF

VFB

ICOUT

ICREF

Q2 (RBFET)

SI4835BDY

Controlled by

HOST

C14
10uF

C17

0.1uF

R10

10k

R11
10k

EAI

FBO

NC

NC

EAO

27

28

2

12

3

26

7

9

10

8

14

16

4

5

6

1

15

17

18

19

20

25

21

23

24

DCIN

VDDSMB

11

ACOK

10k

R3

13

DISCRETE

LOGIC

RC6
10Ω

Dig I/O

+3.3V_ALWAYS

OR

+5V_ALWAYS

R12

10k

22

100 Ω

R22

C1

2.2u

RC

1

2.2Ω

DISCRETE

LOGIC

R20
20k

R21

200k

R19

7.5k

C21
2000pF

C22
130pF

C23

51pF

bq24745

SLUS761D –DECEMBER 2007– REVISED OCTOBER 2011

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.

DESCRIPTION (CONTINUED)

The bq24745 features dynamic power management (DPM) and input power limiting. These features reduce
battery-charge current when the input power limit is reached to avoid overloading the ac adaptor when supplying
the load and the battery charger simultaneously. A highly accurate current-sense amplifier enables precise
measurement of input current from the ac adapter, allowing monitoring the overall system power. If the adapter
current is above the programmed low-power threshold, a signal is sent to host so that the system optimizes its
performance to the power available from the adapter. An integrated comparator monitors the input current
through the current-sense amplifier, and indicates when the input current exceeds a programmable threshold
limit.

TYPICAL APPLICATIONS

VIN= 20 V, V

= 4-cell Li-Ion, I

BAT

CHARGE

= 4.5 A

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Internal Comparator

Product Folder Link(s) :bq24745

Figure 1. Typical System Schematic Using External Input-Current Comparator (Discrete Logic) Instead of

2 Submit Documentation Feedback Copyright © 2007–2011, Texas Instruments Incorporated

RAC

0.010

RSR

0.010

(1) Pullup rail could be either VREF or other system rail.

Q1 (ACFET)

SI4435

N

PP

CSSN

CSSP

ACIN

VREF

CE

SDA

SCL

SMBus

DISCRETE

LOGIC

VICM

HOST

(EC)

UGATE

N

PHASE

BOOT

VDDP

LGATE

PGND

CSOP

CSON

PACK+

PACK-

CHRG_IN

ADAPTER +

ADAPTER -

GND

bq24745

464k
1%

33.2k
1%

R1

R2

1uFC4

0.1uFC20.1uF

C3

100pFC5

1uF

C6

Q3
FDS6680A

Q4
FDS6680A

0.1uF

C7

L1

5.6uH

D1 BAT54

1uF

C8

C9

0.1uF

C10

0.1uF

C13
2x10uF

VFB

R4

10k

ICOUT

VREF

ICREF

R22

100Ω

R8
200k

R18

1400k

Q2 (RBFET)

SI4435

Controlled by

HOST

C14
10uF

C15
10uF

C17

0.1uF

R10

10k

R11
10k

EAI

FBO

NC

NC

EAO

27

28

2

12

3

26

7

9

10

8

14

16

4

5

6

1

15

17

18

19

20

25

21

23

24

DCIN

22

VDDSMB

11

ACOK

10k

R3

13

Dig I/O

+3.3V_ALWAYS

OR

+5V_ALWAYS

R12

10k

RC6
10Ω

C16

1u

C1

2.2u

2.2Ω

1

RC

R7
200k

DISCRETE

LOGIC

R20
20k

R21

200k

R19

7.5k

C21
2000pF

C22
130pF

C23

51pF

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bq24745

SLUS761D –DECEMBER 2007– REVISED OCTOBER 2011

VIN= 20 V, V

= 4-cell Li-Ion, I

BAT

CHARGE

= 4.5 A, VICM

= 6 A, for ICOUT Input Current comparator.

er_limit

Figure 2. Typical System Schematic Using Internal Input-Current Comparator

PART NUMBER PACKAGE QUANTITY

bq24745 28-pin 5-mm × 5-mm QFN

PACKAGE THERMAL DATA

(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI

Copyright © 2007–2011, Texas Instruments Incorporated Submit Documentation Feedback 3

PACKAGE θ

(1)

QFN – RHD

Web site at www.ti.com.

JA

36°C/W 2.36 W 0.028 W/°C

ORDERING INFORMATION

ORDERING NUMBER

TA= 40°C DERATING FACTOR

POWER RATING ABOVE TA= 25°C

Product Folder Link(s) :bq24745

(Tape and Reel)

bq24745RHDR 3000
bq24745RHDT 250

bq24745

SLUS761D –DECEMBER 2007– REVISED OCTOBER 2011

Table 1. PIN FUNCTIONS – 28-PIN QFN

PIN

NO. NAME

1 ICREF Input-current comparator voltage reference input. Connect a resistor divider from VREF to ICREF and from ICREF to

GND to program the reference for the ICOUT comparator. The ICREF pin voltage is compared to the VICM pin
voltage and the logic output is given on the ICOUT open-drain pin. Connecting a positive feedback resistor from the
ICREF pin to the ICOUT pin programs the hysteresis.

2 ACIN Adapter-detected voltage-set input. Program the adapter-detect threshold by connecting a resistor divider from the

adapter input to ACIN pin to GND. Adapter voltage is detected if the ACIN-pin voltage is greater than 2.4 V. The VICM
current-sense amplifier, ICOUT comparator, and ACOK output are active when the ACIN pin voltage is greater than

0.6 V.

3 VREF 3.3-V regulated voltage output. Place a 1-μF ceramic capacitor from VREF to the GND pin close to the IC. This

voltage could be used for ratiometric programming of voltage and current regulation and for programming the ICREF
threshold.

4 EAO Error amplifier output for compensation. Connect the feedback-compensation components from EAO to EAI. Typically,

a capacitor in parallel with a series resistor and capacitor. This node is internally compared to the PWM sawtooth
oscillator signal.

5 EAI Error amplifier input for compensation. Connect the feedback compensation components from EAI to EAO. Connect

the input compensation from FBO to EAI.

6 FBO Feedback output for compensation. Connect the input compensation from FBO to EAI. Typically, a resistor in parallel

with a series resistor and capacitor.
7 CE Charge enable active-high logic input. HI enables charge. LO disables charge.
8 VICM Adapter current-sense-amplifier output. The VICM voltage is 20 times the differential voltage across CSSP-CSSN.

Place a 100-pF (max) or less ceramic decoupling capacitor from VICM to GND.
9 SDA SMBus data input. Connect to the SMBus data line from the host controller. A 10-kΩ pullup resistor to the host

controller power rail is needed.

10 SCL SMBus clock input. Connect to the SMBus clock line from the host controller. A 10-kΩ pullup resistor to the host

controller power rail is needed.

11 VDDSMB Input voltage for SMBus logic. Connect a 3.3-V supply rail or 5-V rail to the VDDSMB pin. Connect a 0.1-μF ceramic

capacitor from VDDSMB to GND for decoupling.

12 GND Analog ground. On PCB layout, connect to the analog ground plane, and only connect to PGND through the thermal

pad underneath the IC.

13 ACOK Valid adapter active-high detect logic open-drain output. Pulled HI when Input voltage is above the ACIN programmed

threshold. Connect a 10-kΩ pullup resistor from the ACOK pin to pull up the supply rail.

14 NC No connect. Pin floating internally.
15 VFB Battery-voltage remote sense. Directly connect a Kelvin sense trace from the battery-pack positive terminal to the VFB

pin to sense the battery pack voltage accurately. Place a 0.1-μF capacitor from VFB to GND close to the IC to filter

high-frequency noise.

16 NC No Connect. Pin floating internally.
17 CSON Charge-current sense resistor, negative input. An optional 0.1-μF ceramic capacitor is placed from the CSON pin to

GND for common-mode filtering. A 0.1-μF ceramic capacitor is placed from CSON to CSOP to provide

differential-mode filtering.

18 CSOP Charge-current sense resistor, positive input. A 0.1-μF ceramic capacitor is placed from CSOP pin to GND for

common-mode filtering. A 0.1-μF ceramic capacitor is placed from CSON to CSOP to provide differential-mode

filtering.

19 PGND Power ground. On PCB layout, connect directly to the source of the low-side power MOSFET, and to the to ground

connection of the input and output capacitors of the charger. Only connect to GND through the thermal pad

underneath the IC.

20 LGATE PWM low-side driver output. Connect to the gate of the low-side power MOSFET with a short trace.
21 VDDP PWM low-side driver positive 6-V supply output. Connect a 1-μF ceramic capacitor from VDDP to the PGND pin, close

to the IC. Use for high-side driver bootstrap voltage by connecting a small signal Schottky diode from VDDP to BOOT.

22 DCIN IC-power positive supply. Connect to the common-source (diode-OR) point: source of high-side P-channel MOSFET

and source of reverse blocking power P-channel MOSFET. Place a 1-μF ceramic capacitor from DCIN to the GND pin

close to the IC. Place a 10-Ω resistor from the adapter input to the DCIN pin to limit inrush current.

23 PHASE PWM high-side driver negative supply. Connect to the phase-switching node (junction of the low-side power MOSFET

drain, high-side power MOSFET source, and output inductor). Connect the 0.1-μF bootstrap capacitor from PHASE to

BOOT.

24 UGATE PWM high-side driver output. Connect to the gate of the high-side power MOSFET with a short trace.

FUNCTION

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bq24745

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Table 1. PIN FUNCTIONS – 28-PIN QFN (continued)

PIN

NO. NAME

25 BOOT PWM high-side driver positive supply. Connect a 0.1-μF bootstrap ceramic capacitor from BOOT to PHASE. Connect

a small bootstrap Schottky diode from VDDP to BOOT.

26 ICOUT Input-current comparator active-high open-drain logic output. Place a 10-kΩ pullup resistor from the ICOUT pin to the

pullup voltage rail. Place a positive-feedback resistor from the ICOUT pin to the ICREF pin for programming

hysteresis. The output is HI when the VICM pin voltage is lower than the ICREF pin voltage. The output is LO when

VICM pin voltage is higher than ICREF pin voltage.

27 CSSN Adapter current-sense resistor, negative input. An optional 0.1-μF ceramic capacitor is placed from the CSSN pin to

GND for common-mode filtering. A 0.1-μF ceramic capacitor is placed from CSSN to CSSP to provide

differential-mode filtering.

28 CSSP Adapter current-sense resistor, positive input. A 0.1-μF ceramic capacitor is placed from the CSSP pin to GND for

common-mode filtering. A 0.1-μF ceramic capacitor is placed from CSSN to CSSP to provide differential-mode

filtering.

FUNCTION

ABSOLUTE MAXIMUM RATINGS

over operating free-air temperature range (unless otherwise noted)

DCIN, CSOP, CSON, CSSP, CSSN, VFB, ACOK –0.3 to 30
PHASE –1 to 30

Voltage range V

Maximum difference voltage: CSOP–CSON, CSSP–CSSN –0.5 to 0.5
Junction temperature range –40 to 155 °C
Storage temperature range –55 to 155 °C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) All voltages are with respect to GND if not specified. Currents are positive into, and negative out of the specified terminal. Consult

Packaging Section of the data book for thermal limitations and considerations of packages.

EAI, EAO, FBO, VDDP, LGATE, ACIN, VICM, ICOUT, ICREF, CE –0.3 to 7
VDDSMB, SDA, SCL –0.3 to 6
VREF –0.3 to 3.6
BOOT, UGATE with respect to GND and PGND –0.3 to 36

(1) (2)

SLUS761D –DECEMBER 2007– REVISED OCTOBER 2011

VALUE UNIT

RECOMMENDED OPERATING CONDITIONS

over operating free-air temperature range (unless otherwise noted)

MIN NOM MAX UNIT

PHASE –0.7 24
DCIN, CSOP, CSON, CSSP, CSSN, VFB, ACOK 0 24
VDDP, LGATE 0 6.5

Voltage range VREF 3.3

EAI, EAO, FBO, ACIN, VICM, ICOUT, ICREF, CE 0 5.5
BOOT, UGATE with respect to GND and PGND 0 30

VDDSMB, SDA, SCL 0 5.5
Maximum difference voltage: CSOP–CSON, CSSP–CSSN –0.3 0.3
Junction temperature range –40 125 °C
Storage temperature range –55 150 °C

Copyright © 2007–2011, Texas Instruments Incorporated Submit Documentation Feedback 5

Product Folder Link(s) :bq24745

V

bq24745

SLUS761D –DECEMBER 2007– REVISED OCTOBER 2011

ELECTRICAL CHARACTERISTICS

7 V ≤ V

OPERATING CONDITIONS

V

DCIN_OP

CHARGE VOLTAGE REGULATION

V

VFB_OP

V

VFB_REG _ACC

V

VFB_REG_ RNG

CHARGE CURRENT REGULATION

V

IREG_CHG_RNG

I

CHRG_REG_ACC

INPUT CURRENT REGULATION

V

IREG_DPM_RNG

I

INPUT_REG_ACC

VREF REGULATOR

V

VREF_REG

I

VREF_LIM

VDDP REGULATOR

V

VDDP_REG

I

VDDP_LIM

≤ 24 V, 0°C < TJ< 125°C, typical values are at TA= 25°C, with respect to AGND (unless otherwise noted)

DCIN

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

DCIN input-voltage operating range 7 24 V

VFB input-voltage range 0 DCIN V

VFB charge-voltage regulation accuracy

Charge-voltage regulation range 1.024 19.2 V

Charge-current regulation differential-voltage V
range is 80.64 mV

Charge-current regulation accuracy

Adapter-current regulation differential-voltage V
range is 110.084 mV

Input-current regulation accuracy

VREF regulator voltage V
VREF current limit V

VDDP regulator voltage V

VDDP current limit mA

ChargeVoltage() = 0x41A0

ChargeVoltage() = 0x3130

ChargeVoltage() = 0x20D0

ChargeVoltage() = 0x1060

16.716 16.8 16.884 V
–0.5% 0.5%

12.529 12.592 12.655 V
–0.5% 0.5%

8.350 8.4 8.450 V

–0.6% 0.6%

4.154 4.192 4.230 V

–0.9% 0.9%

TJ= 0 to 125°C, 1.024 V–19.2 V, Max DAC
value is 19.2 V

= V

– V

IREG_CHG

CSOP

ChargeCurrent() = 0x0F80

ChargeCurrent() = 0x0800

ChargeCurrent() = 0x0200

ChargeCurrent() = 0x0080

= V

IREG_DPM

CSSP

InputCurrent() ≥ 0x0800

InputCurrent() = 0x0400

InputCurrent() = 0x0100

InputCurrent() = 0x0080

> 0.6 V, 0 – 30 mA 3.267 3.3 3.333 V

ACIN

= 0 V, V

V
V

VREF

ACIN
VDDP
VDDP

ACIN

> 0.6 V, 0 – 50 mA 5.7 6 6.3 V

= 0 V, V

ACIN

= 5 V, V

ACIN

, max. DAC value

CSON

0 80.64 mV

3968 mA

–3% 3%

2048 mA

–5% 5%

512 mA

–25% 25%

128 mA

–33% 33%

– V

, max. DAC value

CSSN

0 110.1 mV

4096 mA

–3% 3%

2048 mA

–5% 5%

512 mA

–25% 25%

256 mA

–33% 33%

> 0.6 V 35 80 mA

> 0.6 V 90 135
> 0.6 V 80

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ELECTRICAL CHARACTERISTICS (continued)

7 V ≤ V

ADAPTER CURRENT SENSE AMPLIFIER

V

CSSP/N_OP

V

VICM

I

VICM

A

VICM

I

VICM_LIM

C

VICM_MAX

ACIN COMPARATOR INPUT UNDERVOLTAGE)

V

DCIN_VFB_OP

V

ACIN_CHG

V

ACIN_CHG_HYS

V

ACIN_BIAS

V

ACIN_BIAS_HYS

DCIN / VFB COMPARATOR (REVERSE DISCHARGING PROTECTION)

V

DCIN-VFB_FALL

V

DCIN-VFB__HYS

VFB OVERVOLTAGE COMPARATOR

V

OV_RISE

V

OV_FALL

VFB SHORT (UNDERVOLTAGE and TRICKLE CHARGE) COMPARATOR

V

VFB_SHORT_RISE

V

VFB_SHORT_HYS

I

TRKL_REG_ACC

I

LOW_MAX_REG

CHARGE OVERCURRENT COMPARATOR

V

OC

INPUT UNDERVOLTAGE LOCK-OUT COMPARATOR (UVLO)

UVLO AC undervoltage rising threshold Measure on DCIN pin 3.5 4 4.5 V
V

UVLO_HYS

INPUT CURRENT COMPARATOR

V

ICCOMP_OFFSET

(1) Verified by design.

≤ 24 V, 0°C < TJ< 125°C, typical values are at TA= 25°C, with respect to AGND (unless otherwise noted)

DCIN

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

Input common-mode range Voltage on CSSP/CSSN 0 24 V
VICM output-voltage range 0 2.25 V
VICM output current 0 1 mA
Current-sense amplifier voltage gain A

Adapter-current sense accuracy

Output-current limit V

= V

VICM

V

IREG_DPM

V

IREG_DPM

V

IREG_DPM

V

IREG_DPM
VICM

/ V

VICM

IREG_DPM

= V(CSSP–CSSN) ≥ 40 mV –2% 2%
= V(CSSP–CSSN) = 20 mV –3% 3%
= V(CSSP–CSSN) = 5 mV –25% 25%
= V(CSSP–CSSN) = 1.5 mV –33% 33%

= 0 V 1 mA

Maximum output load capacitance For stability with 0-mA to 1-mA load 100 pF

Differential voltage from DCIN to VFB –20 24 V
ACIN rising threshold Min. voltage to enable charging, V
ACIN falling hysteresis V
ACIN rising deglitch

(1)

ACIN falling deglitch V

falling 40 mV

ACIN

V

rising 50 100 150 μs

ACIN

falling 1 μs

ACIN

Adapter present rising threshold Min voltage to enable all bias, V
Adapter present falling hysteresis V
ACIN rising deglitch

(1)

ACIN falling deglitch V

DCIN to VFB falling threshold V

falling 20 mV

ACIN

V

rising 200

ACIN

falling 1

ACIN

– V

DCIN

to turn off ACFET 140 185 240 mV

VFB

DCIN to VFB hysteresis 50 mV
DCIN to VFB rising deglitch V
DCIN to VFB falling deglitch V

Overvoltage rising threshold As percentage of V
Overvoltage falling threshold As percentage of V

DCIN
DCIN

– V
– V

VFB
VFB

> V

DCIN-VFB_RISE

< V

DCIN-VFB_FALL

VFB_REG
VFB_REG

VFB short rising threshold 2.6 2.7 2.9 V
VFB short falling hysteresis 215 mV

V

> V

VFB

VFB short rising deglitch 1.5 μs
VFB short falling deglitch V

Trickle-charge current-regulation accuracy in V
BATSHORT

Maximum charge current regulation at low V
voltage (<4 V)

VFB_SHORT

Detection delay

< V

VFB

VFB_SHORT

< V

VFB

VFB_SHORT

VFB_SHORT

Charge overcurrent falling threshold As percentage of I

+ V

VFB_SHORT_HYS

< V

< 4 3

VFB

REG_CHG

Minimum current limit (CSOP–CSON) 50 mV
Internal filter pole frequency 160 kHz

AC undervoltage hysteresis, falling 260 mV

Input current-comparator offset voltage -6.8 0.12 6.8 mV

SLUS761D –DECEMBER 2007– REVISED OCTOBER 2011

20 V/V

rising 2.376 2.4 2.424 V

ACIN

rising 0.56 0.62 0.68 V

ACIN

1 ms

3.3 μs

104
102

3.3 μs

60 200 300

145%

μs

%

mA

A

Copyright © 2007–2011, Texas Instruments Incorporated Submit Documentation Feedback 7

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bq24745

SLUS761D –DECEMBER 2007– REVISED OCTOBER 2011

ELECTRICAL CHARACTERISTICS (continued)

7 V ≤ V

THERMAL SHUTDOWN COMPARATOR

T

SHUT

T

SHUT_HYS

PWM HIGH SIDE DRIVER (UGATE)

R

DS_HI_ON

R

DS_HI_OFF

V

BOOT_REFRESH

I

BOOT_LEAK

PWM LOW SIDE DRIVER (LGATE)

R

DS_LO_ON

R

DS_LO_OFF

PWM DRIVERS TIMING

PWM OSCILLATOR

F

SW

V

RAMP_HEIGHT

QUIESCENT CURRENT

I

OFF_STATE

I

BAT_ON

I

BAT_LOAD_CD

I

BAT_LOAD_CE

I

AC

I

AC_SWITCH

INTERNAL SOFT START (8 Steps to Regulation Current ICHG)

CHARGER SECTION POWER-UP SEQUENCING

CHARGE UNDERCURRENT COMPARATOR (CYCLE-BY-CYCLE SYNCHRONOUS TO NON-SYNCHRONOUS)

V

UCP

LOGIC INPUT PIN CHARACTERISTICS (CE)

V

IN_LO

V

IN_HI

V

BIAS

OPEN-DRAIN LOGIC OUTPUT PIN CHARACTERISTICS (ACOK, ICOUT)

V

OUT_LO

VDDSMB INPUT SUPPLY FOR SMBus

V

VDDSMB_RANGE

V

VDDSMB_UVLO_

Threshold_Rising

V

VDDSMB_UVLO_

Hyst_Rising

≤ 24 V, 0°C < TJ< 125°C, typical values are at TA= 25°C, with respect to AGND (unless otherwise noted)

DCIN

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

Thermal shutdown rising temperature Temperature Increasing 155
Thermal shutdown hysteresis, falling 20

High-side driver (HSD) turnon resistance V
High-side driver turnoff resistance V
Bootstrap refresh comparator threshold V

voltage is requested

BOOT
BOOT
BOOT

– V

= 5.5 V 6 Ω

PHASE

– V

= 5.5 V 1 Ω

PHASE

– V

when low-side refresh pulse

PHASE

BOOT leakage current when charge enabled High side is on; charge enabled 200 μA

Low-side driver (LSD) turnon resistance 6 Ω
Low-side driver turnoff resistance 1 Ω

Driver dead time 30 ns

Dead time when switching between LGATE
and UGATE , no load at LGATE and UGATE

PWM switching frequency 240 360 kHz
PWM ramp height As percentage of DCIN 6.67 %DCIN

Total off-state battery current from CSOP, V
CSON, VFB, DCIN, BOOT, PHASE, etc V

Battery on-state quiescent current 0.7 1 mA

Internal battery load current, charge disabled 0.7 1 mA

Internal battery load current, charge enabled 6 10 12 mA
Adapter quiescent current Charge disabled, V
Adapter switching quiescent current 25 mA

= 16.8 V, V

VFB

> 5 V, 0°C ≤ TJ≤ 85°C

DCIN

V

= 16.8 V, 0.6V < V

VFB

V

> 5 V

DCIN

ACIN

Charge is disabled: V
V

> 2.4 V, V

ACIN

DCIN

Charge is enabled: V
V

> 2.4 V, V

ACIN

Charge enabled, V
running

DCIN

DCIN

< 0.6 V,

< 2.4 V,

ACIN

= 16.8 V,

VFB

> 5 V

= 16.8 V,

VFB

> 5 V

= 20 V 0.7 1 mA

DCIN

= 20 V, converter

Soft-start steps 8 step
Soft-start step time 1.5 ms

Charge-enable delay after power up 1.5 ms

Cycle-by-cycle synchronous to
non-synchronous transition threshold

Delay from when adapter is detected to when
the charger is allowed to turn on

Cycle-by-cycle, (CSOP-CSON) voltage,
falling, LGATE turns off and latches off until 5 10 15 mV
next cycle

Blankout time after LGATE turns on Blankout comparator after LGATE turns on 100 ns

(2)

Pull-up CE with ≥2.2 kΩ resistor or directly to VREF.

Input low-threshold voltage 0.8 V
Input high-threshold voltage 2.1
Input bias current V = 0 TO V

VDDP

Output low saturation voltage Sink current = 5 mA 0.5 V

VDDSMB input voltage range 2.7 5.5 V
VDDSMB undervoltage lockout threshold

voltage, rising
VDDSMB undervoltage lockout hysteresis

voltage, falling

V

rising 2.4 2.5 2.6 V

VDDSMB

V

falling 100 150 200 V

VDDSMB

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°C

4 V

7 10 μA

1 μA

(2) Pull up CE with ≥ 2-kΩ resistor, or connect directly to VREF.
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ELECTRICAL CHARACTERISTICS (continued)

7 V ≤ V

IVDDSMB_Iq VDDSMB quiescent current V

≤ 24 V, 0°C < TJ< 125°C, typical values are at TA= 25°C, with respect to AGND (unless otherwise noted)

DCIN

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

= SCL = SDA = 5.5 V, 0°C ≤ TJ≤ 20 27 μA

VDDSMB

85°C

ELECTRICAL CHARACTERISTICS

7 Vdc ≤ V

PARAMETER MIN TYP MAX UNIT
[SMB TIMING SPECIFICATION (VDD = 2.7 V to 5.5 V) (see Figures 4 and 5)]

SMBus TIMING CHARACTERISTICS

t

R

t

F

t

W(H)

t

W(L)

t

SU(STA)

t

H(STA)

t

SU(DAT)

t

H(DAT)

t

SU(STOP)

t

(BUF)

F

S(CL)

HOST COMMUNICATION FAILURE

t

timeout

t

WDI

OUTPUT BUFFER CHARACTERISTICS

V

(SDAL)

(1) Devices participating in a transfer time out when any clock low exceeds the 2- ms minimum time-out period. Devices that have detected

a time-out condition must reset the communication no later than the 35-ms maximum timeout period. Both a master and a slave must
adhere to the maximum value specified, as it incorporates the cumulative stretch limit for both a master (10 ms) and a slave (25 ms).

≤ 24 Vdc, –20°C<TJ<125°C, ref = AGND (unless otherwise noted)

(VCC)

SCLK/SDATA rise time 1 μs
SCLK/SDATA fall time 300 ns
SCLK pulse duration high 4 50 μs
SCLK pulse duration low 4.7 μs
Setup time for START condition 4.7 μs
START condition hold time after which first clock pulse is generated 4 μs
Data setup time 250 ns
Data hold time 300 ns
Setup time for STOP condition 4 μs
Bus free time between START and STOP condition 4.7 μs
Clock frequency 10 100 kHz

SMBus bus release timeout 22 25 35 ms
Watchdog timeout period 140 170 210 s

Output LO voltage at SDA, I

= 3 mA 0.4 V

(SDA)

SLUS761D –DECEMBER 2007– REVISED OCTOBER 2011

(1)

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-3

-2

-1

0

0 20 40 60 80 100

DCIN=10V

DCIN=20V

V -Error-%

DDP

I -LoadCurrent-mA

L

-1

-0.80

-0.60

-0.40

-0.20

0

0.20

0.40

0 5 10 15 20 25 30 35 40

I -LoadCurrent-mA

L

DCIN=10V

DCIN=20V

V -Error-%

REF

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Figure 3. SMBus Communication Timing Waveforms

VREF LOAD AND LINE REGULATION VDDP LOAD AND LINE REGULATION

LOAD CURRENT LOAD CURRENT

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Figure 4. Figure 5.

TYPICAL CHARACTERISTICS

vs vs

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-3

-2

-1

0

1

0 1 2 3 4 5 6 7 8 9

BatteryChargeCurrent- A

BatteryVoltage Accuracy-%

3CELL @12.592V,
ICHG@8.064 A,
DCIN=20V

-0.2

0

0.2

0.4

0.6

0.8

1

1.2

0 2000 4000 6000 8000 10000 12000 14000 16000 18000 20000

VFBprogrammedSetpoint-mV

BatteryVoltageRegulation Accuracy-%

DCIN=20V

3CELL @12.592V,
ICHG@4.096 A,
DCIN=20V

0

0.5

1

1.5

2

2.5

3

3.5

4

4.5

0 2 4 6 8 10 12 14

BatteryVoltage-V

BatteryChargeCurrent- A

-16

-14

-12

-10

-8

-6

-4

-2

0

0 1000 2000 3000 4000 5000 6000 7000 8000 9000

ICHGDACProgrammedSetpoint-mA

ChargeCurrent Accuracy-%

DCIN=20V,
VFB=9V

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SLUS761D –DECEMBER 2007– REVISED OCTOBER 2011

TYPICAL CHARACTERISTICS (continued)

VFB (BATTERY) VOLTAGE REGULATION ACCURACY VFB (BATTERY) VOLTAGE REGULATION ACCURACY

vs vs

CHARGE CURRENT DAC VBAT SETPOINT

Figure 6. Figure 7.

CHARGE CURRENT REGULATION ACCURACY CHARGE CURRENT REGULATION ACCURACY

vs vs

DAC ICHRG SETPOINT VFB (BATTERY) VOLTAGE

Figure 8. Figure 9.

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DCIN=20V,
VFB=9V

-2

-1.8

-1.6

-1.4

-1.2

-1

-0.8

-0.6

-0.4

-0.2

0

0 2000 4000 6000 8000 10000 12000

DPMProgramValue-mA

VICM Accuracy-%

DPMProgrammedSetpoint-mA

InputCurrentRegulation Accuracy-%

VFB=9V,
DCIN=20V

6000

-2.5

2000 120004000 8000 100000

0

-3

-2

-1.5

-1

-0.5

t − Time=1ms/div

Ch1

2 A/div

Ch2

2 A/div

I

(DCIN)

I

LOAD

I

(SYS)

VICM

Ch4

500mV/div

Ch3

2 A/div

DCIN=20V

0

1

2

3

4

5

6

0 0.5 1 1.5 2 2.5 3 3.5 4

SystemCurrent- A

ChargeCurrent- A

2.5

3

3.5

4

4.5

5

InputCurrent- A

ChargeCurrent

InputCurrent

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SLUS761D –DECEMBER 2007– REVISED OCTOBER 2011

TYPICAL CHARACTERISTICS (continued)

INPUT CURRENT REGULATION (DPM) ACCURACY

vs VICM INPUT CURRENT-SENSE AMPLIFIER ACCURACY

DAC IDPM SETPOINT INPUT CHARGE CURRENT

Figure 10. Figure 11.

INPUT CURRENT REGULATION (DPM)

AND CHARGE CURRENT

vs SYSTEM LOAD RESPONSE

SYSTEM CURRENT CCM TO CCM

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INPUT CURRENT REGULATION (DPM) TRANSIENT

Figure 12. Figure 13.

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