Texas Instruments BQ24725ARGRR Schematic [ru]

Adapter

4.5-24V

HOST

bq24725A

Hybrid Power Boost Charge

Controller

SYS

Battery Pack

N-FET Driver

1S-4S

SMBus

SMBus Controls V & I

with high accuracy

Adapter Detection

Enhanced Safety: OCP,OVP, FET Short

Integration: Loop Compensation; Soft-Start Comparator

Product Folder

Sample & Buy

Technical Documents

Tools & Software

Support & Community

bq24725A

SLUSAL0A –SEPTEMBER 2011–REVISED AUGUST 2014

bq24725A 1-4 Cell Li+ Battery SMBus Charge Controller with N-Channel Power MOSFET

Selector and Advanced Circuit Protection

1 Features 3 Description

• SMBus Host-Controlled NMOS-NMOS Synchronous Buck Converter with Programmable 615kHz, 750kHz, and 885kHz Switching Frequencies

• Automatic N-channel MOSFET Selection of System Power Source from Adapter or Battery Driven by Internal Charge Pumps

• Enhanced Safety Features for Over Voltage Protection, Over Current Protection, Battery, Inductor and MOSFET Short Circuit Protection

• Programmable Input Current, Charge Voltage, Charge Current Limits

– ±0.5% Charge Voltage Accuracy up to 19.2V – ±3% Charge Current Accuracy up to 8.128A – ±3% Input Current Accuracy up to 8.064A – ±2% 20x Adapter Current or Charge Current

Amplifier Output Accuracy

• Programmable Battery Depletion Threshold, and Battery LEARN Function

• Programmable Adapter Detection and Indicator

• Integrated Soft Start

• Integrated Loop Compensation

• Real Time System Control on ILIM pin to Limit Charge Current

• AC Adapter Operating Range 4.5V-24V

• 5µA Off-State Battery Discharge Current

• 0.65mA (0.8mA max) Adapter Standby Quiescent Current

• 20-pin 3.5 x 3.5 mm2VQFN Package

The bq24725A is a high-efficiency, synchronous battery charger, offering low component count for space-constraint, multi-chemistry battery charging applications.

The bq24725A utilizes two charge pumps to separately drive n-channel MOSFETs (ACFET, RBFET and BATFET) for automatic system power source selection.

SMBus controlled input current, charge current, and charge voltage DACs allow for very high regulation accuracies that can be easily programmed by the system power management micro-controller.

The bq24725A uses internal input current register or external ILIM pin to throttle down PWM modulation to reduce the charge current.

The bq24725A charges one, two, three or four series Li+ cells.

Device Information

PART NUMBER PACKAGE BODY SIZE (NOM)

bq24725A VQFN (20) 3.50mm x 3.50mm (1) For all available packages, see the orderable addendum at

the end of the datasheet.

(1)

2 Applications

• Portable Notebook Computers, UMPC, Ultra-Thin Notebook, and Netbook

• Handheld Terminal

• Industrial and Medical Equipment

• Portable Equipment

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA.

bq24725A

SLUSAL0A –SEPTEMBER 2011–REVISED AUGUST 2014

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1 Features.................................................................. 1

2 Applications ........................................................... 1

3 Description ............................................................. 1

4 Revision History..................................................... 2

5 Pin Configuration and Functions......................... 3

6 Specifications......................................................... 4

6.1 Absolute Maximum Ratings ...................................... 4

6.2 Handling Ratings....................................................... 5

6.3 Recommended Operating Conditions....................... 5

6.4 Thermal Information.................................................. 5

6.5 Electrical Characteristics........................................... 6

6.6 Timing Characteristics............................................. 10

6.7 Typical Characteristics............................................ 10

7 Parameter Measurement Information ................ 12

8 Detailed Description ............................................ 13

8.1 Overview................................................................. 13

8.2 Functional Block Diagram....................................... 14

8.3 Feature Description................................................. 15

8.4 Device Functional Modes........................................ 16

8.5 Register Maps......................................................... 22

9 Application and Implementation ........................ 28

9.1 Application Information............................................ 28

9.2 Typical Application .................................................. 28

9.3 Application Curves .................................................. 35

9.4 System Examples .................................................. 35

10 Power Supply Recommendations ..................... 36

11 Layout................................................................... 37

11.1 Layout Guidelines ................................................. 37

11.2 Layout Example ................................................... 38

12 Device and Documentation Support ................. 39

12.1 Third-Party Products Disclaimer ........................... 39

12.2 Trademarks........................................................... 39

12.3 Electrostatic Discharge Caution............................ 39

12.4 Glossary................................................................ 39

13 Mechanical, Packaging, and Orderable

Information........................................................... 39

4 Revision History

Changes from Original (September 2011) to Revision A Page

• Changed the format to the new TI standard .......................................................................................................................... 1

• Added the Device Information table ...................................................................................................................................... 1

• Added LODRV, HIDRV, and PHASE (2% duty cycle) to the Abs Max Table........................................................................ 4

• Added the Handling Ratings table.......................................................................................................................................... 5

Product Folder Links: bq24725A

6 7 8 9 10

20 19 18 17 16

ACN

ACP

CMSRC

ACDRV

ACOK

ACDET

IOUT

SDA

SCL

ILIM

BATDRV

SRN

SRP

GND

LODRV

REGN

BTST

HIDRV

PHASE

VCC

bq24725A

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SLUSAL0A –SEPTEMBER 2011–REVISED AUGUST 2014

5 Pin Configuration and Functions

RGR Package

Top View

Pin Functions

NO. NAME

1 ACN Input current sense resistor negative input. Place an optional 0.1µF ceramic capacitor from ACN to GND for common-

mode filtering. Place a 0.1µF ceramic capacitor from ACN to ACP to provide differential mode filtering.

2 ACP Input current sense resistor positive input. Place a 0.1µF ceramic capacitor from ACP to GND for common-mode

filtering. Place a 0.1µF ceramic capacitor from ACN to ACP to provide differential-mode filtering.

3 CMSRC ACDRV charge pump source input. Place a 4kΩ resistor from CMSRC to the common source of ACFET (Q1) and

RBFET (Q2) limits the in-rush current on CMSRC pin.

4 ACDRV Charge pump output to drive both adapter input n-channel MOSFET (ACFET) and reverse blocking n-channel MOSFET

(RBFET). ACDRV voltage is 6V above CMSRC when voltage on ACDET pin is between 2.4V to 3.15V, voltage on VCC pin is above UVLO and voltage on VCC pin is 275mV above voltage on SRN pin so that ACFET and RBFET can be turned on to power the system by AC adapter. Place a 4kΩ resistor from ACDRV to the gate of ACFET and RBFET limits the in-rush current on ACDRV pin.

5 ACOK AC adapter detection open drain output. It is pulled HIGH to external pull-up supply rail by external pull-up resistor when

voltage on ACDET pin is between 2.4V and 3.15V, and voltage on VCC is above UVLO and voltage on VCC pin is 275mV above voltage on SRN pin, indicating a valid adapter is present to start charge. If any one of the above conditions can not meet, it is pulled LOW to GND by internal MOSFET. Connect a 10kΩ pull up resistor from ACOK to the pull-up supply rail.

6 ACDET Adapter detection input. Program adapter valid input threshold by connecting a resistor divider from adapter input to

ACDET pin to GND pin. When ACDET pin is above 0.6V and VCC is above UVLO, REGN LDO is present, ACOK comparator and IOUT are both active.

7 IOUT Buffered adapter or charge current output, selectable with SMBus command ChargeOption(). IOUT voltage is 20 times

the differential voltage across sense resistor. Place a 100pF or less ceramic decoupling capacitor from IOUT pin to GND.

8 SDA SMBus open-drain data I/O. Connect to SMBus data line from the host controller or smart battery. Connect a 10kΩ pull-

up resistor according to SMBus specifications.

9 SCL SMBus open-drain clock input. Connect to SMBus clock line from the host controller or smart battery. Connect a 10kΩ

pull-up resistor according to SMBus specifications.

10 ILIM Charge current limit input. Program ILIM voltage by connecting a resistor divider from system reference 3.3V rail to ILIM

pin to GND pin. The lower of ILIM voltage or DAC limit voltage sets charge current regulation limit. To disable the control on ILIM, set ILIM above 1.6V. Once voltage on ILIM pin falls below 75mV, charge is disabled. Charge is enabled when ILIM pin rises above 105mV.

11 BATDRV Charge pump output to drive Battery to System n-channel MOSFET (BATFET). BATDRV voltage is 6V above SRN to

turn on BATFET to power the system from battery. BATDRV voltage is SRN voltage to turn off BATFET to power system from AC adapter. Place a 4kΩ resistor from BATDRV to the gate of BATFET limits the in-rush current on BATDRV pin.

Product Folder Links: bq24725A

DESCRIPTION

bq24725A

SLUSAL0A –SEPTEMBER 2011–REVISED AUGUST 2014

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Pin Functions (continued)

NO. NAME

12 SRN Charge current sense resistor negative input. SRN pin is for battery voltage sensing as well. Connect SRN pin to a 7.5

Ω resistor first then from resistor another terminal connect a 0.1µF ceramic capacitor to GND for common-mode filtering and connect to current sensing resistor. Connect a 0.1µF ceramic capacitor between current sensing resistor to provide differential mode filtering. See application information about negative output voltage protection for hard shorts on battery to ground or battery reverse connection by adding small resistor.

13 SRP Charge current sense resistor positive input. Connect SRP pin to a 10 Ω resistor first then from resistor another terminal

connect to current sensing resistor. Connect a 0.1µF ceramic capacitor between current sensing resistor to provide differential mode filtering. See application information about negative output voltage protection for hard shorts on battery to ground or battery reverse connection by adding small resistor.

14 GND IC ground. On PCB layout, connect to analog ground plane, and only connect to power ground plane through the power

pad underneath IC. 15 LODRV Low side power MOSFET driver output. Connect to low side n-channel MOSFET gate. 16 REGN Linear regulator output. REGN is the output of the 6V linear regulator supplied from VCC. The LDO is active when

voltage on ACDET pin is above 0.6V and voltage on VCC is above UVLO. Connect a 1µF ceramic capacitor from

REGN to GND. 17 BTST High side power MOSFET driver power supply. Connect a 0.047µF capacitor from BTST to PHASE, and a bootstrap

Schottky diode from REGN to BTST. 18 HIDRV High side power MOSFET driver output. Connect to the high side n-channel MOSFET gate. 19 PHASE High side power MOSFET driver source. Connect to the source of the high side n-channel MOSFET. 20 VCC Input supply, diode OR from adapter or battery voltage. Use 10Ω resistor and 1µF capacitor to ground as low pass filter

to limit inrush current.

PowerPAD™ Exposed pad beneath the IC. Analog ground and power ground star-connected only at the PowerPAD plane. Always

solder PowerPad to the board, and have vias on the PowerPAD plane connecting to analog ground and power ground

planes. It also serves as a thermal pad to dissipate the heat.

DESCRIPTION

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)

SRN, SRP, ACN, ACP, CMSRC, VCC –0.3 30 PHASE –2 30 ACDET, SDA, SCL, LODRV, REGN, IOUT, ILIM, ACOK –0.3 7

Voltage range BTST, HIDRV, ACDRV, BATDRV –0.3 36

LODRV (2% duty cycle) –4 7 HIDVR (2% duty cycle) –4 36 PHASE (2% duty cycle) –4 30

Maximum difference SRP–SRN, ACP–ACN –0.5 0.5 voltage

Junction temperature range, T

(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) All voltages are with respect to GND if not specified. Currents are positive into, negative out of the specified terminal. Consult Packaging

Section of the data book for thermal limitations and considerations of packages.

(1) (2)

VALUE UNIT

MIN MAX

–40 155 °C

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6.2 Handling Ratings

MIN MAX UNIT

stg

(ESD)

Storage temperature range –55 155 °C

Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all

(1)

Electrostatic discharge V

pins Charged device model (CDM), per JEDEC specification

JESD22-C101, all pins

(2)

–2000 2000

–500 500

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. (2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

MIN NOM MAX UNIT

SRN, SRP, ACN, ACP, CMSRC, VCC 0 24

Voltage range V

Maximum difference voltage SRP–SRN, ACP–ACN –0.2 0.2 V Junction temperature range, T

PHASE -2 24 ACDET, SDA, SCL, LODRV, REGN, IOUT, ILIM, ACOK 0 6.5 BTST, HIDRV, ACDRV, BATDRV 0 30

0 125 °C

6.4 Thermal Information

(1)

R R R

θJA θJCtop θJB

JT JB θJCbot

THERMAL METRIC

Junction-to-ambient thermal resistance 46.8 Junction-to-case (top) thermal resistance 56.9 Junction-to-board thermal resistance 46.6 Junction-to-top characterization parameter 0.6 Junction-to-board characterization parameter 15.3 Junction-to-case (bottom) thermal resistanc 4.4

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

bq24725A

RGR (20 PIN)

UNIT

°C/W

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SLUSAL0A –SEPTEMBER 2011–REVISED AUGUST 2014

6.5 Electrical Characteristics

4.5 V ≤ V

OPERATING CONDITIONS

VCC_OP

CHARGE VOLTAGE REGULATION

BAT_REG_RNG

BAT_REG_ACC

CHARGE CURRENT REGULATION

IREG_CHG_RNG

CHRG_REG_ACC

INPUT CURRENT REGULATION

IREG_DPM_RNG

DPM_REG_ACC

INPUT CURRENT OR CHARGE CURRENT SENSE AMPLIFIER

ACP/N_OP

SRP/N_OP

IOUT

IOUT_ACC

IOUT_MAX

REGN REGULATOR

REGN_REG

≤ 24 V, 0°C ≤ TJ≤ 125°C, typical values are at TA= 25°C, with respect to GND (unless otherwise noted)

VCC

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

VCC Input voltage operating range 4.5 24 V

Battery voltage range 1.024 19.2 V

Charge voltage regulation accuracy

Charge current regulation differential voltage range

Charge current regulation accuracy 10mΩ current sensing resistor

Input current regulation differential voltage range

Input current regulation accuracy 10mΩ current sensing resistor

Input common mode range Voltage on ACP/ACN 4.5 24 V Output common mode range Voltage on SRP/SRN 0 19.2 V IOUT output voltage range 0 3.3 V IOUT output current 0 1 mA Current sense amplifier gain V

Current sense output accuracy

Maximum output load capacitance For stability with 0 to 1mA load 100 pF

REGN regulator voltage V

ChargeVoltage() = 0x41A0H

ChargeVoltage() = 0x3130H

ChargeVoltage() = 0x20D0H

ChargeVoltage() = 0x1060H

IREG_CHG

= V

SRP

- V

SRN

ChargeCurrent() = 0x1000H

ChargeCurrent() = 0x0800H

ChargeCurrent() = 0x0200H

ChargeCurrent() = 0x0100H

ChargeCurrent() = 0x0080H

IREG_DPM

= V

ACP

– V

ACN

InputCurrent() = 0x1000H

InputCurrent() = 0x0800H

InputCurrent() = 0x0400H

InputCurrent() = 0x0200H

or V or V or V or V or V or V

or V

(ACP-ACN)

= 40.96mV –2% 2%

(ACP-ACN)

= 20.48mV –4% 4%

(ACP-ACN)

= 10.24mV –15% 15%

(ACP-ACN)

= 5.12mV –20% 20%

(ACP-ACN)

= 2.56mV –33% 33%

(ACP-ACN)

= 1.28mV –50% 50%

(ACP-ACN)

> 0.6V (0-45mA load) 5.5 6 6.5 V

ACDET

(ICOUT)/V(SRP-SRN)

(SRP-SRN)

> 6.5V, V

VCC

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16.716 16.8 16.884 V

-0.5% 0.5%

12.529 12.592 12.655 V –0.5% 0.5%

8.350 8.4 8.45 V

–0.6% 0.6%

4.163 4.192 4.221 V

–0.7% 0.7%

0 81.28 mV

3973 4096 4219 mA

–3% 3%

1946 2048 2150 mA

–5% 5%

410 512 614 mA

–20% 20%

172 256 340 mA

–33% 33%

64 128 192 mA

–50% 50%

0 80.64 mV

3973 4096 4219 mA

–3% 3%

1946 2048 2150 mA

–5% 5%

870 1024 1178 mA

–15% 15%

384 512 640 mA

–25% 25%

20 V/V

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Electrical Characteristics (continued)

bq24725A

SLUSAL0A –SEPTEMBER 2011–REVISED AUGUST 2014

4.5 V ≤ V

≤ 24 V, 0°C ≤ TJ≤ 125°C, typical values are at TA= 25°C, with respect to GND (unless otherwise noted)

VCC

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

REGN_LIM

REGN

REGN current limit

REGN output capacitor required for I stability

INPUT UNDERVOLTAGE LOCKOUT COMPARATOR (UVLO)

UVLO

Under voltage rising threshold V Under voltage hysteresis, falling V

FAST DPM COMPARATOR (FAST_DPM)

FAST_DPM

Fast DPM comparator stop charging rising threshold with respect to input current limit, voltage across input sense resistor rising edge

QUIESCENT CURRENT

Battery BATFET OFF STATE Current,

BAT_BATFET_OFF

BATFET off, I

+ I

SRP

SRN

+ I

PHASE

+ I

ACP

+ I

ACN

Battery BATFET ON STATE Current,

BAT_BATFET_ON

STANDBY

AC_NOSW

AC_SW

BATFET on, I

+ I

VCC

ACP

+ I

ACN

ACP

SRP

SRN

PHASE

VCC

Standby quiescent current, I I

ACN

Adapter bias current during charge, V I

+ I

ACP

+ I

ACN

VCC

Adapter bias current during charge, V I

+ I

ACP

+ I

ACN

VCC

ACOK COMPARATOR

ACOK_RISE

ACOK_FALL_HYS

ACOK_RISE_DEG

WAKEUP_RISE

WAKEUP_FALL

ACOK rising threshold V ACOK falling hysteresis V

ACOK rising deglitch (Specified by design)

WAKEUP detect rising threshold V WAKEUP detect falling threshold V

VCC to SRN COMPARATOR (VCC_SRN)

VCC-SRN_FALL

VCC-SRN _RHYS

VCC-SRN falling threshold V VCC-SRN rising hysteresis V

ACN to SRN COMPARATOR (ACN_SRN)

ACN-SRN_FALL

ACN-SRN_RHYS

HIGH SIDE IFAULT COMPARATOR (IFAULT_HI)

IFAULT_HI_RISE

LOW SIDE IFAULT COMPARATOR (IFAULT_LOW)

IFAULT_LOW_RISE

ACN to BAT falling threshold V ACN to BAT rising hysteresis V

(1)

ACP to PHASE rising threshold mV

(1)

PHASE to GND rising threshold mV

INPUT OVER-VOLTAGE COMPARATOR (ACOV)

ACOV

ACOV_HYS

INPUT OVER-CURRENT COMPARATOR (ACOC)

ACDET over voltage rising threshold V ACDET over voltage falling hysteresis V

(1)

Adapter over current rising threshold with ChargeOption() bit [1] = 1 (Default) 300% 333% 366%

ACOC

respect to input current limit, voltage across input sense resistor rising edge

= 0V, V

REGN

TSHUT V

= 0V, V

REGN

TSHUT

= 100µA to 50mA 1

LOAD

rising 3.5 3.75 4 V

VCC

falling 340 mV

VCC

> UVLO charge enabled and not in 50 75

VCC

> UVLO charge disabled or in 7 14

VCC

103% 107% 111%

= 16.8V, VCC disconnect from battery, BATFET

VBAT

charge pump off, BATFET turns off, TJ= 0 to 85°C

= 16.8V, VCC connect from battery, BATFET

VBAT

charge pump on, BATFET turns on, TJ= 0 to 85°C

+ V

> UVLO, V

VCC

TJ= 0 to 85°C

> UVLO, 2.4V < V

VCC

charge enabled, no switching, TJ= 0 to 85°C

> UVLO, 2.4V < V

VCC

charge enabled, switching, MOSFET Sis412DN

> UVLO, V

VCC

> UVLO, V

VCC

> UVLO, V

VCC

First time OR ChargeOption() bit [15] = 0 V

> UVLO, V

VCC

(NOT First time) AND ChargeOption() bit [15] = 1 0.9 1.3 1.7 s

> 0.6V, charge disabled,

ACDET

< 3.15V,

ACDET

< 3.15V,

ACDET

rising 2.376 2.4 2.424 V

ACDET

falling 35 55 75 mV

ACDET

rising above 2.4V,

ACDET

rising above 2.4V,

ACDET

0.65 0.8 mA

1.5 3 mA

10 mA

100 150 200 ms

(Default)

> UVLO, V

VCC

> UVLO, V

VCC

falling towards V

VCC

rising above V

VCC

falling towards V

ACN

rising above V

ACN

rising 0.57 0.8 V

ACDET

falling 0.3 0.51 V

ACDET

SRN

70 125 200 mV

100 150 200 mV

120 200 280 mV

40 80 120 mV

ChargeOption() bit [8] = 1 (Default) 450 750 1200 ChargeOption() bit [8] = 0 Disable function

ChargeOption() bit [7] = 0 (Default) 70 135 220 ChargeOption() bit [7] = 1 140 230 340

rising 3.05 3.15 3.25 V

ACDET

falling 50 75 100 mV

ACDET

ChargeOption() bit [1] = 0 Disable function

µF

5 µA

25 µA

(1) User can adjust threshold via SMBus ChargeOption() REG0x12.

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SLUSAL0A –SEPTEMBER 2011–REVISED AUGUST 2014

Electrical Characteristics (continued)

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4.5 V ≤ V

≤ 24 V, 0°C ≤ TJ≤ 125°C, typical values are at TA= 25°C, with respect to GND (unless otherwise noted)

VCC

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

ACOC_min

ACOC_max

ACOC_DEG

Min ACOC threshold clamp voltage 40 45 50 mV

Max ACOC threshold clamp voltage 135 150 165 mV

ACOC deglitch time (Specified by design) 2.3 4.2 6.6 ms

BAT OVER-VOLTAGE COMPARATOR (BAT_OVP)

OVP_RISE

OVP_FALL

Over voltage rising threshold as V percentage of V

BAT_REG

Over voltage falling threshold as V percentage of V

BAT_REG

CHARGE OVER-CURRENT COMPARATOR (CHG_OCP)

Charge over current rising threshold,

OCP_RISE

measure voltage drop across current ChargeCurrent()=0x1000H – 0x17C0H 80 90 100 mV sensing resistor

CHARGE UNDER-CURRENT COMPARATOR (CHG_UCP)

UCP_FALL

Charge under-current falling threshold V

LIGHT LOAD COMPARATOR (LIGHT_LOAD)

LL_FALL

LL_RISE_HYST

Light load falling threshold 1.25 mV Light load rising hysteresis 1.25 mV

BATTERY DEPLETION COMPARATOR (BAT_DEPL) [1]

Battery depletion falling threshold,

BATDEPL_FALL

BATDEPL_RHYST

BATDEPL_RDEG

percentage of voltage regulation limit, V falling

Battery depletion rising hysteresis, V rising

Battery Depletion Rising Deglitch Delay to turn off ACFET and turn on BATFET during (Specified by design) LEARN cycle

BATTERY LOWV COMPARATOR (BAT_LOWV)

BATLV_FALL

BATLV_RHYST

BATLV

Battery LOWV falling threshold V Battery LOWV rising hysteresis V Battery LOWV charge current limit 10 mΩ current sensing resistor 0.5 A

THERMAL SHUTDOWN COMPARATOR (TSHUT)

SHUT

SHUT_HYS

Thermal shutdown rising temperature Temperature rising 155 °C Thermal shutdown hysteresis, falling Temperature falling 20 °C

ILIM COMPARATOR

ILIM_FALL

ILIM_RISE

ILIM as CE falling threshold V ILIM as CE rising threshold V

LOGIC INPUT (SDA, SCL)

IN_ LO

IN_ HI

IN_ LEAK

Input low threshold 0.8 V Input high threshold 2.1 V Input bias current V = 7 V –1 1 μA

LOGIC OUTPUT OPEN DRAIN (ACOK, SDA)

OUT_ LO

OUT_ LEAK

Output saturation voltage 5 mA drain current 500 mV Leakage current V = 7 V –1 1 μA

ANALOG INPUT (ACDET, ILIM)

IN_ LEAK

Input bias current V = 7 V –1 1 μA

PWM OSCILLATOR

PWM switching frequency ChargeOption () bit [9] = 0 (Default) 600 750 900 kHz

ChargeOption() Bit [1] = 1 (333%), InputCurrent () = 0x0400H (10.24mV)

ChargeOption() Bit [1] = 1 (333%), InputCurrent () = 0x1F80H (80.64mV)

Voltage across input sense resistor rising to disable charge

rising 103% 104% 106%

SRN

falling 102%

SRN

ChargeCurrent()=0x0xxxH 54 60 66 mV

ChargeCurrent()=0x1800 H– 0x1FC0H 110 120 130 mV

falling towards V

SRP

SRN

1 5 9 mV

Measure the voltage drop across current sensing resistor

ChargeOption() bit [12:11] = 00 55.53% 59.19% 63.5% ChargeOption() bit [12:11] = 01 58.68% 62.65% 67.5%

SRN

ChargeOption() bit [12:11] = 10 62.17% 66.55% 71.5% ChargeOption() bit [12:11] = 11 (Default) 66.06% 70.97% 77% ChargeOption() bit [12:11] = 00 225 305 400 mV ChargeOption() bit [12:11] = 01 240 325 430 mV

SRN

ChargeOption() bit [12:11] = 10 255 345 450 mV ChargeOption() bit [12:11] = 11 (Default) 280 370 490 mV

600 ms

falling 2.4 2.5 2.6 V

SRN

rising 200 mV

SRN

falling 60 75 90 mV

ILIM

rising 90 105 120 mV

ILIM

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Electrical Characteristics (continued)

bq24725A

SLUSAL0A –SEPTEMBER 2011–REVISED AUGUST 2014

4.5 V ≤ V

≤ 24 V, 0°C ≤ TJ≤ 125°C, typical values are at TA= 25°C, with respect to GND (unless otherwise noted)

VCC

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

SW+

SW–

PWM increase frequency ChargeOption() bit [10:9] = 11 665 885 1100 kHz PWM decrease frequency ChargeOption() bit [10:9] = 01 465 615 765 kHz

BATFET GATE DRIVER (BATDRV)

BATFET

BATDRV_LOAD

BATDRV_OFF

BATDRV charge pump current limit 40 60 µA Gate drive voltage on BATFET V Minimum load resistance between

BATDRV and SRN

BATDRV

- V

SRN

when V

> UVLO 5.5 6.1 6.5 V

SRN

500 kΩ

BATDRV turn-off resistance I = 30 µA 5 6.2 7.4 kΩ

ACFET GATE DRIVER (ACDRV)

ACFET

ACDRV_LOAD

ACDRV_OFF

ACFET_LOW

ACDRV charge pump current limit 40 60 μA Gate drive voltage on ACFET V Minimum load resistance between ACDRV

and CMSRC

ACDRV–VCMSRC

when V

> UVLO 5.5 6.1 6.5 V

VCC

500 kΩ

ACDRV turn-off resistance I = 30 µA 5 6.2 7.4 kΩ ACDRV Turn-Off when Vgs voltage is low

(Specified by design)

5.9 V

PWM HIGH SIDE DRIVER (HIDRV)

DS_HI_ON

DS_HI_OFF

BTST_REFRESH

High side driver turn-on resistance V High side driver turn-off resistance V Bootstrap refresh comparator threshold V

voltage

– VPH= 5.5 V, I = 10 mA 6 10 Ω

BTST

– VPH= 5.5 V, I = 10 mA 0.65 1.3 Ω

BTST

– VPHwhen low side refresh pulse is requested

BTST

3.85 4.3 4.7 V

PWM LOW SIDE DRIVER (LODRV)

DS_LO_ON

DS_LO_OFF

Low side driver turn-on resistance V Low side driver turn-off resistance V

= 6 V, I = 10 mA 7.5 12 Ω

REGN

= 6 V, I = 10 mA 0.9 1.4 Ω

REGN

PWM DRIVER TIMING

LOW_HIGH

HIGH_LOW

Driver dead time from low side to high side 20 ns Driver dead time from high side to low side 20 ns

INTERNAL SOFT START

STEP

Soft start current step 64 mA Soft start current step time 240 μs

In CCM mode 10mΩ current sensing resistor

SMBus TIMING CHARACTERISTICS

W(H)

W(L)

SU(STA)

H(STA)

SU(DAT)

H(DAT)

SU(STOP)

(BUF)

S(CL)

SCLK/SDATA rise time 1 μs SCLK/SDATA fall time 300 ns SCLK pulse width high 4 50 μs SCLK Pulse Width Low 4.7 μs Setup time for START condition 4.7 μs START condition hold time after which first clock pulse is generated 4 μs Data setup time 250 ns Data hold time 300 ns Setup time for STOP condition 4 µs Bus free time between START and STOP condition 4.7 μs Clock Frequency 10 100 kHz

HOST COMMUNICATION FAILURE

timeout

BOOT

WDI

SMBus bus release timeout Deglitch for watchdog reset signal 10 ms Watchdog timeout period, ChargeOption() bit [14:13] = 01 Watchdog timeout period, ChargeOption() bit [14:13] = 10 Watchdog timeout period, ChargeOption() bit [14:13] = 11

(2)

(3) (3) (3)

(Default) 140 175 210 s

25 35 ms

35 44 53 s 70 88 105 s

(2) Devices participating in a transfer will timeout when any clock low exceeds the 25ms minimum timeout period. Devices that have

detected a timeout condition must reset the communication no later than the 35ms maximum timeout period. Both a master and a slave must adhere to the maximum value specified as it incorporates the cumulative stretch limit for both a master (10ms) and a slave (25ms).

(3) User can adjust threshold via SMBus ChargeOption() REG0x12.

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6.6 Timing Characteristics

4.5 V ≤ V

SMBus TIMING CHARACTERISTICS

W(H)

W(L)

SU(STA)

H(STA)

SU(DAT)

H(DAT)

SU(STOP)

(BUF)

S(CL)

HOST COMMUNICATION FAILURE

timeout

BOOT

WDI

(1) Devices participating in a transfer will timeout when any clock low exceeds the 25ms minimum timeout period. Devices that have

(2) User can adjust threshold via SMBus ChargeOption() REG0x12.

≤ 24 V, 0°C ≤ TJ≤ 125°C, typical values are at TA= 25°C, with respect to GND (unless otherwise noted)

VCC

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

SMBus bus release timeout

(1)

25 35 ms Deglitch for watchdog reset signal 10 ms Watchdog timeout period, ChargeOption() bit [14:13] = 01 Watchdog timeout period, ChargeOption() bit [14:13] = 10 Watchdog timeout period, ChargeOption() bit [14:13] = 11

(2) (2) (2)

(Default) 140 175 210 s

35 44 53 s

70 88 105 s

6.7 Typical Characteristics

CH1: VCC, 10V/div, CH2: ACDET 2V/div, CH3: ACOK, 5V/div CH4: REGN, 5V/div, 40ms/div

Figure 1. VCC, ACDET, REGN and ACOK Power Up

CH1: ILIM, 1V/div CH4: inductor current 1A/div, 20ms/div

Figure 2. Charge Enable by ILIM

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Typical Characteristics (continued)

bq24725A

SLUSAL0A –SEPTEMBER 2011–REVISED AUGUST 2014

CH1: Vin, 10V/div , CH2: LODRV, 5V/div, CH3: PHASE, 10V/div CH4: inductor current, 2A/div, 2ms/div

Figure 3. Current Soft-Start

CH1: PHASE, 10V/div, CH2: LODRV, 5V/div CH3: HIDRV, 10V/div CH4: inductor current, 2A/div, 400ns/div

Figure 5. Continuous Conduction Mode Switching

Waveforms

CH1: ILIM, 1V/div CH4: inductor current, 1A/div, 4us/div

Figure 4. Charge Disable by ILIM

CH1: PHASE, 10V/div, CH2: LODRV, 5V/div CH3: HIDRV, 10V/div CH4: inductor current, 1A/div, 400ns/div

Figure 6. Cycle-by-Cycle Synchronous to Non-synchronous

CH1: PHASE, 10V/div, CH2: LODRV, 5V/div CH2: battery current, 2A/div, CH3: adapter current, 2A/div CH4: inductor current, 2A/div, 4us/div CH4: system load current, 2A/div, 100us/div

Figure 7. 100% Duty and Refresh Pulse Figure 8. System Load Transient (Input DPM)

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7 Parameter Measurement Information

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Figure 9. SMBus Communication Timing Waveforms

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8 Detailed Description

8.1 Overview

The bq24725A is a 1-4 cell battery charge controller with power selection for space-constrained, multi-chemistry portable applications such as notebook and detachable ultrabook. It supports wide input range of input sources from 4.5V to 24V, and 1-4 cell battery for a versatile solution.

The bq24725A supports automatic system power source selection with separate drivers for n-channel MOSFETS on the adapter side and battery side.

The bq24725A features Dynamic Power Management (DPM) to limit the input power and avoid AC adapter overloading. During battery charging, as the system power increases, the charging current will reduce to maintain total input current below adapter rating.

The SMBus controls input current, charge current and charge voltage registers with high resolution, high accuracy regulation limits.

Product Folder Links: bq24725A

bq24725A

135mV

1.07

bq24725A

SLUSAL0A –SEPTEMBER 2011–REVISED AUGUST 2014

8.2 Functional Block Diagram

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Figure 10. Functional Block Diagram for bq24725A

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SLAVE

ADDRESS

W ACK

COMMAND

BYTE

ACK

LOW DATA

BYTE

ACK

HIGH DATA

BYTE

ACK P

7 BITS 1b 1b 8 BITS 1b 8 BITS 1b 8 BITS 1b

MSB LSB 0 0 MSB LSB 0 MSB LSB 0 MSB LSB 0

a) Write-Word Format

SLAVE

ADDRESS

W ACK

COMMAND

BYTE

ACK S

SLAVE

ADDRESS

R ACK

LOW DATA

BYTE

ACK

HIGH DATA

BYTE

NACK P

7 BITS 1b 1b 8 BITS 1b 7 BITS 1b 1b 8 BITS 1b 8 BITS 1b

MSB LSB 0 0 MSB LSB 0 MSB LSB 1 0 MSB LSB 0 MSB LSB 1

Preset to 0b0001001 DeviceID() = 0xFFH Preset to D7 D0 D15 D8

ManufactureID() = 0xFEH 0b0001001 ChargeCurrent() = 0x14H ChargeVoltage() = 0x15H InputCurrent() = 0x3FH

ChargeOption() = 0x12H LEGEND: S = START CONDITION OR REPEATED START CONDITION P = STOP CONDITION ACK = ACKNOWLEDGE (LOGIC-LOW) NACK = NOT ACKNOWLEDGE (LOGIC-HIGH) W = WRITE BIT (LOGIC-LOW) R = READ BIT (LOGIC-HIGH)

b) Read-Word Format

MASTER TO SLAVE SLAVE TO MASTER

Preset to 0b0001001

ChargeOption() = 0x12H

D0 D15 D8

ChargeCurrent() = 0x14H ChargeVoltage() = 0x15H InputCurrent() = 0x3FH

bq24725A

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SLUSAL0A –SEPTEMBER 2011–REVISED AUGUST 2014

8.3 Feature Description

8.3.1 SMBus Interface

The bq24725A operates as a slave, receiving control inputs from the embedded controller host through the SMBus interface. The bq24725A uses a simplified subset of the commands documented in System Management Bus Specification V1.1, which can be downloaded from www.smbus.org. The bq24725A uses the SMBus ReadWord and Write-Word protocols (see Figure 11) to communicate with the smart battery. The bq24725A performs only as a SMBus slave device with address 0b00010010 (0x12H) and does not initiate communication on the bus. In addition, the bq24725A has two identification registers a 16-bit device ID register (0xFFH) and a 16-bit manufacturer ID register (0xFEH).

SMBus communication is enabled with the following conditions:

• V

• V The data (SDA) and clock (SCL) pins have Schmitt-trigger inputs that can accommodate slow edges. Choose

pull-up resistors (10kΩ) for SDA and SCL to achieve rise times according to the SMBus specifications. Communication starts when the master signals a START condition, which is a high-to-low transition on SDA, while SCL is high. When the master has finished communicating, the master issues a STOP condition, which is a low-to-high transition on SDA, while SCL is high. The bus is then free for another transmission. Figure 12 and

Figure 13 show the timing diagram for signals on the SMBus interface. The address byte, command byte, and

data bytes are transmitted between the START and STOP conditions. The SDA state changes only while SCL is low, except for the START and STOP conditions. Data is transmitted in 8-bit bytes and is sampled on the rising edge of SCL. Nine clock cycles are required to transfer each byte in or out of the bq24725A because either the master or the slave acknowledges the receipt of the correct byte during the ninth clock cycle. The bq24725A supports the charger commands as described in Table 2.

is above UVLO;

VCC

is above 0.6V;

ACDET

Figure 11. SMBus Write-Word and Read-Word Protocols

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+ 33 hidden pages

Texas Instruments BQ24725ARGRR Schematic [ru]

1 Features 3 Description

2 Applications

Table of Contents

4 Revision History

5 Pin Configuration and Functions

6 Specifications

6.1 Absolute Maximum Ratings

6.2 Handling Ratings

6.3 Recommended Operating Conditions

6.4 Thermal Information

6.5 Electrical Characteristics

6.6 Timing Characteristics

6.7 Typical Characteristics

7 Parameter Measurement Information

8 Detailed Description

8.1 Overview

8.2 Functional Block Diagram

8.3 Feature Description

8.3.1 SMBus Interface