Texas Instruments BQ24725 Schematic [ru]

6 7 8 9 10

20 19 18 17 16

ACN

ACP

CMSRC

ACDRV

ACOK

ACDET

IOUT

SDA

SCL

ILIM

BATDRV

SRN

SRP

GND

LODRV

REGN

BTST

HIDRV

PHASE

VCC

bq24725

Not Recommended for New Designs

bq24725

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SLUS702A –JULY 2010–REVISED NOVEMBER 2010

2-4 Cell Li+ Battery SMBus Charge Controller with N-Channel Power MOSFET Selector

and Advanced Circuit Protection

Check for Samples: bq24725

FEATURES

• SMBus Host-Controlled NMOS-NMOS Synchronous Buck Converter with Programmable 615kHz, 750kHz, and 885kHz Switching Frequencies

• Automatic N-channel MOSFET Selection of System Power Source from Adapter or Battery Driven by Internal Charge Pumps

• Enhanced Safety Features for Over Voltage Protection, Over Current Protection, Battery, Inductor and MOSFET Short Circuit Protection

• Programmable Input Current, Charge Voltage, Charge Current Limits

– ±0.5% Charge Voltage Accuracy up to 19.2V – ±3% Charge Current Accuracy up to 8.128A – ±3% Input Current Accuracy up to 8.064A – ±2% 20x Adapter Current or Charge Current

Amplifier Output Accuracy

• Programmable Battery Depletion Threshold, and Battery LERAN Function

• Programmable Adapter Detection and Indicator

• Integrated Soft Start

• Integrated Loop Compensation

• Real Time System Control on ILIM pin to Limit Charge Current

• AC Adapter Operating Range 9V-24V

• 5µA Off-State Battery Discharge Current

• 20-pin 3.5 x 3.5 mm2QFN Package

DESCRIPTION

The bq24725 is a high-efficiency, synchronous battery charger, offering low component count for space-constraint, multi-chemistry battery charging applications.

The bq24725 uses two charge pumps to separately drive n-channel MOSFETs (ACFET, RBFET and BATFET) for automatic system power source selection.

SMBus controlled input current, charge current, and charge voltage DACs allow for high regulation accuracies that can be programmed by the system power management micro-controller.

The bq24725 uses internal input current register or external ILIM pin to throttle down PWM modulation to reduce the charge current.

The bq24725 charges two, three or four series Li+ cells, and is available in a 20-pin, 3.5 x 3.5 mm2QFN package.

APPLICATIONS

• Portable Notebook Computers, UMPC, UltraThin Notebook, and Netbook

• Personal Digital Assistant

• Handheld Terminal

• Industrial and Medical Equipment

• Portable Equipment

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2PowerPAD is a trademark of Texas Instruments.

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

VCC

BATDRV

REGN

BTST

HIDRV

PHASE

LODRV

GND

SRP

SRN

Q4 Sis412DN

4.7µH

SYSTEM

C10 10µF

RSR

10m?

R1 430k

66.5k

0.1µF

bq24725

C8 10uF

Q3 Sis412DN

Q5 (BATFET) FDS6680A

0.047µF

Adapter +

RAC 10m?

Pack +

C13

0.1µF

C6 1µF

HOST

Dig I/O

SMBus

+3.3V

C4 100p

R4 10k

R5 10k

R7 316k

ACN

ACP

CMSRC

ACDRV

ACDET

ILIM

SDA

SCL

ACOK

IOUT

2.2µF

Ri 2?

D2 BAT54C

R9 10Ω

R3 10k

R8 100k

R10

4.02k

R11

4.02k

D1 BAT54

C14

0.1µF

C9 10uF

C11 10µF

Pack -

0.1µF C5

1µF

4.02k

0.1µF

Total Csys 220µF

C15

0.01µF

C16

0.1µF

C17 2200pF

Adapter -

ADC

U2 IMD2A

Q1 (ACFET) FDS6680A

Q2 (RBFET) FDS6680A

PowerPad

R12 1M

R13

3.01M

Q6 BSS138W

Reverse Input Protection

Dig I/O

R14 10Ω

R15

7.5Ω

Not Recommended for New Designs

bq24725

SLUS702A –JULY 2010–REVISED NOVEMBER 2010

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.

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DEVICE INFORMATION

Fs= 750kHz, I

ADPT

= 4.096A, I

CHRG

= 2.944A, I

LIM

= 4A, V

= 12.592V, 90W adapter and 3S2P battery pack

CHRG

See the application information about negative output voltage protection for hard shorts on battery to ground or battery reverse connection.

Figure 1. Typical System Schematic with Two NMOS Selector

Product Folder Links :bq24725

VCC

BATDRV

REGN

BTST

HIDRV

PHASE

LODRV

GND

SRP

SRN

Q4 Sis412DN

4.7µH

SYSTEM

C10 10µF

RSR

10m?

R1 430k

66.5k

0.1µF

bq24725

C8 10uF

Q3 Sis412DN

Q5 (BATFET) FDS6680A

0.047µF

Adapter +

RAC 10m?

Pack +

C6 1µF

HOST

Dig I/O

SMBus

+3.3V

C4 100p

R4 10k

R5 10k

R7 549k

ACN

ACP

CMSRC

ACDRV

ACDET

ILIM

SDA

SCL

ACOK

IOUT

2.2µF

Ri 2?

R9 10Ω

R3 10k

R8 100k

R10

4.02k R11

4.02k

D1 BAT54

C9 10uF

C11 10µF

Pack -

0.1µF C5

1µF

4.02k

0.1µF

Total Csys 220µF

C15

0.01µF

C16

0.1µF

C17 2200pF

Adapter -

ADC

Q1 (ACFET) FDS6680A

D3 PDS1040

PowerPad

C13

0.1µF

C14

0.1µF

R14 10Ω

R15

7.5Ω

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Not Recommended for New Designs

bq24725

SLUS702A –JULY 2010–REVISED NOVEMBER 2010

Fs= 750kHz, I

ADPT

= 2.688A, I

CHRG

= 1.984A, I

= 2.54A, V

LIM

= 12.592V, 65W adapter and 3S2P battery pack

CHRG

See the application information about negative output voltage protection for hard shorts on battery to ground or battery reverse connection.

Figure 2. Typical System Schematic with One NMOS Selector and Schottky Diode

ORDERING INFORMATION

PART NUMBER IC MARKING PACKAGE QUANTITY

bq24725 BQ725 20-PIN 3.5 x 3.5mm2QFN

ORDERING NUMBER

(Tape and Reel)

bq24725RGRR 3000 bq24725RGRT 250

THERMAL INFORMATION

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. (2) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as

specified in JESD51-7, in an environment described in JESD51-2a.

(3) The junction-to-top characterization parameter, ψJT, estimates the junction temperature of a device in a real system and is extracted (4) The junction-to-board characterization parameter, ψJB, estimates the junction temperature of a device in a real system and is extracted

from the simulation data for obtaining θJA, using a procedure described in JESD51-2a (sections 6 and 7). from the simulation data for obtaining θJA, using a procedure described in JESD51-2a (sections 6 and 7).

Junction-to-ambient thermal resistance Junction-to-top characterization parameter Junction-to-board characterization parameter

THERMAL METRIC

(1)

(2)

(3)

(4)

Product Folder Links :bq24725

bq24725

RGR (20 PIN)

46.8

0.6 °C/W

15.3

UNITS

Not Recommended for New Designs

bq24725

SLUS702A –JULY 2010–REVISED NOVEMBER 2010

ABSOLUTE MAXIMUM RATINGS

over operating free-air temperature range (unless otherwise noted)

SRN, SRP, ACN, ACP, CMSRC, VCC –0.3 to 30

Voltage range

Maximum difference voltage SRP–SRN, ACP–ACN –0.5 to 0.5 Junction temperature range, T Storage temperature range, T

(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) All voltages are with respect to GND if not specified. Currents are positive into, negative out of the specified terminal. Consult Packaging

Section of the data book for thermal limitations and considerations of packages.

PHASE –2 to 30 ACDET, SDA, SCL, LODRV, REGN, IOUT, ILIM, ACOK –0.3 to 7 V BTST, HIDRV, ACDRV, BATDRV –0.3 to 36

stg

(1) (2)

VALUE UNIT

–40 to 155 °C –55 to 155 °C

RECOMMENDED OPERATING CONDITIONS

over operating free-air temperature range (unless otherwise noted)

MIN NOM MAX UNIT

SRN, SRP, ACN, ACP, CMSRC, VCC 0 24

Voltage range V

Maximum difference voltage SRP–SRN, ACP–ACN –0.2 0.2 V Junction temperature range, T Storage temperature range, T

PHASE -2 24 ACDET, SDA, SCL, LODRV, REGN, IOUT, ILIM, ACOK 0 6.5 BTST, HIDRV, ACDRV, BATDRV 0 30

stg

–55 150 °C

0 125 °C

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ELECTRICAL CHARACTERISTICS

4.5 V ≤ V

OPERATING CONDITIONS

VCC_OP

CHARGE VOLTAGE REGULATION

BAT_REG_RNG

BAT_REG_ACC

≤ 24 V, 0°C ≤ TJ≤ 125°C, typical values are at TA= 25°C, with respect to GND (unless otherwise noted)

VCC

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

VCC Input voltage operating range 4.5 24 V

BAT voltage regulation range 1.024 19.2 V

Charge Voltage Regulation Accuracy ChargeVoltage() = 0x3130H

ChargeVoltage() = 0x41A0H

ChargeVoltage() = 0x20D0H

16.716 16.8 16.884 V

-0.5% 0.5%

12.529 12.592 12.655 V –0.5% 0.5%

8.35 8.4 8.45 V

–0.6% 0.6%

Product Folder Links :bq24725

Not Recommended for New Designs

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ELECTRICAL CHARACTERISTICS (continued)

4.5 V ≤ V

CHARGE CURRENT REGULATION

IREG_CHG_RNG

CHRG_REG_ACC

INPUT CURRENT REGULATION

IREG_DPM_RNG

DPM_REG_ACC

INPUT CURRENT OR CHARGE CURRENT SENSE AMPLIFIER

ACP/N_OP

SRP/N_OP

IOUT

IOUT_ACC

IOUT_MAX

REGN REGULATOR

REGN_REG

REGN_LIM

REGN

INPUT UNDERVOLTAGE LOCK-OUT COMPARATOR (UVLO)

UVLO

Fast DPM comparator (FAST_DPM)

FAST_DPM

≤ 24 V, 0°C ≤ TJ≤ 125°C, typical values are at TA= 25°C, with respect to GND (unless otherwise noted)

VCC

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

Charge Current Regulation Differential Voltage Range

IREG_CHG

ChargeCurrent() = 0x1000H

ChargeCurrent() = 0x0800H

Charge Current Regulation Accuracy 10mΩ current sensing resistor

ChargeCurrent() = 0x0200H

ChargeCurrent() = 0x0100H

ChargeCurrent() = 0x0080H

Input current regulation differential voltage range

IREG_DPM

InputCurrent() = 0x1000H

InputCurrent() = 0x0800H Input current regulation accuracy 10mΩ current sensing resistor

InputCurrent() = 0x0400H

InputCurrent() = 0x0200H

Input common mode range Voltage on ACP/ACN 4.5 24 V Output Common Mode Range Voltage on SRP/SRN 0 19.2 V IOUT Output Voltage Range 0 1.6 V IOUT Output Current 0 1 mA Current Sense Amplifier Gain V

Current Sense Output Accuracy

(ICOUT)/V(SRP-SRN)

(SRP-SRN)

Maximum Output Load Capacitance For stability with 0 to 1mA load 100 pF

REGN regulator voltage V

REGN current limit

REGN Output Capacitor Required for I Stability

Under voltage rising threshold V Under voltage hysteresis, falling V

> 6.5V, V

VCC

= 0V, V

REGN

TSHUT

= 0V, V

REGN

TSHUT

= 100µA to 65mA 1

LOAD

rising 3.5 3.75 4 V

VCC

falling 340 mV

VCC

Fast DPM comparator stop charging rising threshold with respect to input current limit, voltage across input sense resistor rising edge (Specified by design)

SLUS702A –JULY 2010–REVISED NOVEMBER 2010

= V

- V

SRP

SRN

= V

– V

ACP

ACN

or V

(ACP-ACN)

or V or V or V or V or V or V

= 40.96mV –2% 2%

(ACP-ACN)

= 20.48mV –4% 4%

(ACP-ACN)

= 10.24mV –15% 15%

(ACP-ACN)

= 5.12mV –20% 20%

(ACP-ACN)

= 2.56mV –33% 33%

(ACP-ACN)

= 1.28mV –50% 50%

(ACP-ACN)

> 0.6V (0-55mA load) 5.5 6 6.5 V

ACDET

> UVLO charge enabled and not in 65 80

VCC

> UVLO charge disabled or in 7 16

VCC

bq24725

0 81.28 mV

3973 4096 4219 mA

–3% 3%

1946 2048 2150 mA

–5% 5%

410 512 614 mA

–20% 20%

172 256 340 mA

–33% 33%

64 128 192 mA

–50% 50%

0 80.64 mV

3973 4096 4219 mA

–3% 3%

1946 2048 2150 mA

–5% 5%

870 1024 1178 mA

–15% 15%

384 512 640 mA

–25% 25%

20 V/V

µF

108%

Product Folder Links :bq24725

Not Recommended for New Designs

bq24725

SLUS702A –JULY 2010–REVISED NOVEMBER 2010

ELECTRICAL CHARACTERISTICS (continued)

4.5 V ≤ V

QUIESCENT CURRENT

BAT_BATFET_OFF

BAT_BATFET_ON

STANDBY

AC_NOSW

AC_SW

ACOK COMPARATOR

ACOK_RISE

ACOK_FALL_HYS

ACOK_RISE_DEG

WAKEUP_RISE

WAKEUP_FALL

VCC to SRN COMPARATOR (VCC_SRN)

VCC-SRN_FALL

VCC-SRN _RHYS

ACN to SRN COMPARATOR (ACN_SRN)

ACN-SRN_FALL

ACN-SRN_RHYS

HIGH SIDE IFAULT COMPARATOR (IFAULT_HI)

IFAULT_HI_RISE

LOW SIDE IFAULT COMPARATOR (IFAULT_LOW)

IFAULT_LOW_RISE

INPUT OVER VOLTAGE COMPARATOR (ACOV)

ACOV

ACOV_HYS

INPUT OVER CURRENT COMPARATOR (ACOC)

ACOC

ACOC_min

ACOC_max

ACOC_DEG

BAT OVER VOLTAGE COMPARATOR (BAT_OVP)

OVP_RISE

OVP_FALL

(1) User can adjust threshold via SMBus ChargeOption() REG0x12.

≤ 24 V, 0°C ≤ TJ≤ 125°C, typical values are at TA= 25°C, with respect to GND (unless otherwise noted)

VCC

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

Battery BATFET OFF STATE Current, BATFET off, I I

ACN

SRP

+ I

SRN

+ I

PHASE

+ I

Battery BATFET ON STATE Current, BATFET on, I I

+ I

ACP

ACN

Standby quiescent current, I I

ACN

SRP

+ I

SRN

+ I

PHASE

VCC

+ I

ACP

Adapter bias current during charge, V I

+ I

ACP

+ I

ACN

VCC

Adapter bias current during charge, V I

+ I

ACP

+ I

ACN

VCC

ACOK rising threshold V ACOK falling hysteresis V

ACOK rising deglitch (Specified by design)

WAKEUP detect rising threshold V WAKEUP detect falling threshold V

VCC-SRN falling threshold V VCC-SRN rising hysteresis V

ACN to BAT falling threshold V ACN to BAT rising hysteresis V

(1)

= 16.8V, VCC disconnect from battery, BATFET

VBAT

+ 5 µA

ACP

charge pump off, BATFET turns off, TJ= 0 to 85°C

= 16.8V, VCC connect from battery, BATFET

VBAT

+ 20 µA

VCC

charge pump on, BATFET turns on, TJ= 0 to 85°C

+ V

> UVLO, V

VCC

TJ= 0 to 85°C

> UVLO, 2.4V < V

VCC

charge enabled, no switching, TJ= 0 to 85°C

> UVLO, 2.4V < V

VCC

charge enabled, switching, MOSFET Sis412DN

> UVLO, V

VCC

> UVLO, V

VCC

> UVLO, V

VCC

First time OR ChargeOption() bit [15] = 0 (Default)

> UVLO, V

VCC

(NOT First time) AND ChargeOption() bit [15] = 1

> UVLO, V

VCC

> UVLO, V

VCC

falling towards V

VCC

rising above V

VCC

falling towards V

ACN

rising above V

ACN

ChargeOption() bit [8:7] = 00 200 300 450

ACP to PHASE rising threshold mV

ChargeOption() bit [8:7] = 01 330 500 700

ChargeOption() bit [8:7] = 10 (Default) 450 700 1000

ChargeOption() bit [8:7] = 11 600 900 1250

PHASE to GND rising threshold 40 110 160 mV

ACDET over voltage rising threshold V ACDET over voltage falling hysteresis V

(1)

Adapter over current rising threshold with

rising 3.05 3.15 3.25 V

ACDET

falling 50 75 100 mV

ACDET

ChargeOption() bit [2:1] = 01 120% 133% 145% respect to input current limit, voltage ChargeOption() bit [2:1] = 10 (Default) 150% 166% 180%

across input sense resistor rising edge

Min ACOC threshold clamp voltage 40 45 50 mV

Max ACOC threshold clamp voltage 140 150 160 mV

ACOC deglitch time (Specified by design) 1.7 2.5 3.3 ms

Over voltage rising threshold as V percentage of V

BAT_REG

Over voltage falling threshold as V percentage of V

BAT_REG

ChargeOption() bit [2:1] = 11 200% 222% 240%

ChargeOption() Bit [2:1] = 01 (133%),

InputCurrent () = 0x0400H (10.24mV)

ChargeOption() Bit [2:1] = 11 (222%),

InputCurrent () = 0x1F80H (80.64mV)

Voltage across input sense resistor rising to disable

charge

rising 103% 104% 106%

SRN

falling 102%

SRN

> 0.6V, charge disabled,

ACDET

< 3.15V,

ACDET

< 3.15V,

ACDET

rising 2.376 2.4 2.424 V

ACDET

falling 35 55 75 mV

ACDET

rising above 2.4V,

ACDET

rising above 2.4V,

ACDET

rising 0.57 0.8 V

ACDET

falling 0.3 0.51 V

ACDET

SRN

100 150 200 ms

100 150 200 mV

120 200 280 mV

0.5 1 mA

1.5 3 mA

10 mA

0.9 1.3 1.7 s

70 125 180 mV

40 80 120 mV

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Product Folder Links :bq24725

Not Recommended for New Designs

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ELECTRICAL CHARACTERISTICS (continued)

4.5 V ≤ V

CHARGE OVER CURRENT COMPARATOR (CHG_OCP)

OCP_RISE

CHARGE UNDER CURRENT COMPARATOR (CHG_UCP)

UCP_FALL

LIGHT LOAD COMPARATOR (LIGHT_LOAD)

LL_FALL

LL_RISE_HYST

BATTERY DEPLETION COMPARATOR (BAT_DEPL) [1]

BATDEPL_FALL

BATDEPL_RHYST

BATDEPL_RDEG

BATTERY LOWV COMPARATOR (BAT_LOWV)

BATLV_FALL

BATLV_RHYST

BATLV

THERMAL SHUTDOWN COMPARATOR (TSHUT)

SHUT

SHUT_HYS

ILIM COMPARATOR

ILIM_FALL

ILIM_RISE

LOGIC INPUT (SDA, SCL)

IN_ LO

IN_ HI

IN_ LEAK

LOGIC OUTPUT OPEN DRAIN (ACOK, SDA)

OUT_ LO

OUT_ LEAK

ANALOG INPUT (ACDET, ILIM)

IN_ LEAK

PWM OSCILLATOR

SW+

SW–

BATFET GATE DRIVER (BATDRV)

BATFET

BATDRV_LOAD

BATDRV_OFF

≤ 24 V, 0°C ≤ TJ≤ 125°C, typical values are at TA= 25°C, with respect to GND (unless otherwise noted)

VCC

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

Charge over current rising threshold,

ChargeCurrent()=0x0xxxH 54 60 66 mV measure voltage drop across current ChargeCurrent()=0x1000H – 0x17C0H 80 90 100 mV

sensing resistor

Charge undercurrent falling threshold V

Light load falling threshold 1.25 mV Light load rising hysteresis 1.25 mV

ChargeCurrent()=0x1800 H– 0x1FC0H 110 120 130 mV

falling towards V

SRP

Measure the voltage drop across current sensing

resistor

ChargeOption() bit [12:11] = 00 55.53% 59.19% 62.84% Battery Depletion Falling Threshold,

percentage of voltage regulation limit, V falling

ChargeOption() bit [12:11] = 01 58.68% 62.65% 66.62%

SRN

ChargeOption() bit [12:11] = 10 62.17% 66.55% 70.93%

ChargeOption() bit [12:11] = 11 (Default) 66.06% 70.97% 75.88%

ChargeOption() bit [12:11] = 00 225 305 385 mV Battery Depletion Rising Hysteresis, V

rising

ChargeOption() bit [12:11] = 01 240 325 410 mV

SRN

ChargeOption() bit [12:11] = 10 255 345 435 mV

ChargeOption() bit [12:11] = 11 (Default) 280 370 460 mV Battery Depletion Rising Deglitch Delay to turn off ACFET and turn on BATFET during

(Specified by design) LEARN cycle

Battery LOWV falling threshold V Battery LOWV rising hysteresis V

falling 2.4 2.5 2.6 V

SRN

rising 200 mV

SRN

Battery LOWV charge current limit 10 mΩ current sensing resistor 0.5 A

Thermal shutdown rising temperature Temperature rising 155 °C Thermal shutdown hysteresis, falling Temperature falling 20 °C

ILIM as CE falling threshold V ILIM as CE rising threshold V

falling 60 75 90 mV

ILIM

rising 90 105 120 mV

ILIM

Input low threshold 0.8 V Input high threshold 2.1 V Input bias current V = 7 V –1 1 μA

Output saturation voltage 5 mA drain current 500 mV Leakage current V = 7 V –1 1 μA

Input bias current V = 7 V –1 1 μA

PWM switching frequency ChargeOption () bit [9] = 0 (Default) 600 750 900 kHz PWM increase frequency ChargeOption() bit [10:9] = 11 665 885 1100 kHz PWM decrease frequency ChargeOption() bit [10:9] = 01 465 615 765 kHz

BATDRV charge pump current limit 40 60 µA Gate drive voltage on BATFET V

BATDRV

Minimum load resistance between BATDRV and SRN

BATDRV turn-off resistance I = 30µA 5 6.2 7.4 kΩ

- V

SRN

when V

SLUS702A –JULY 2010–REVISED NOVEMBER 2010

SRN

1 5 9 mV

600 ms

> UVLO 5.5 6.1 6.5 V

SRN

500 kΩ

bq24725

Product Folder Links :bq24725

Not Recommended for New Designs

bq24725

SLUS702A –JULY 2010–REVISED NOVEMBER 2010

ELECTRICAL CHARACTERISTICS (continued)

4.5 V ≤ V

ACFET GATE DRIVER (ACDRV)

ACFET

ACDRV_LOAD

ACDRV_OFF

ACFET_LOW

PWM HIGH SIDE DRIVER (HIDRV)

DS(on)

BTST_REFRESH

PWM LOW SIDE DRIVER (LODRV)

DS(on)

PWM DRIVER TIMING

LOW_HIGH

HIGH_LOW

INTERNAL SOFT START

STEP

SMBus TIMING CHARACTERISTICS

W(H)

W(L)

SU(STA)

H(STA)

SU(DAT)

H(DAT)

SU(STOP)

(BUF)

S(CL)

HOST COMMUNICATION FAILURE

timeout

BOOT

WDI

(2) Devices participating in a transfer will timeout when any clock low exceeds the 25ms minimum timeout period. Devices that have

detected a timeout condition must reset the communication no later than the 35ms maximum timeout period. Both a master and a slave must adhere to the maximum value specified as it incorporates the cumulative stretch limit for both a master (10ms) and a slave (25ms).

(3) User can adjust threshold via SMBus ChargeOption() REG0x12.

≤ 24 V, 0°C ≤ TJ≤ 125°C, typical values are at TA= 25°C, with respect to GND (unless otherwise noted)

VCC

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

ACDRV charge pump current limit 40 60 μA Gate drive voltage on ACFET V Minimum load resistance between ACDRV

and CMSRC

ACDRV–VCMSRC

when V

> UVLO 5.5 6.1 6.5 V

VCC

500 kΩ

ACDRV turn-off resistance I = 30µA 5 6.2 7.4 kΩ ACDRV Turn-Off when Vgs voltage is low

(Specified by design)

High side driver (HSD) turn-on resistance V High side driver turn-off resistance V Bootstrap refresh comparator threshold V

voltage

Low side driver (LSD) turn-on resistance V Low side driver turn-off resistance V

– VPH= 5.5 V, I = 10mA 12 20 Ω

BTST

– VPH= 5.5 V, I = 10mA 0.65 1.3 Ω

BTST

– VPHwhen low side refresh pulse is requested

BTST

= 6 V, I = 10 mA 15 25 Ω

REGN

= 6 V, I = 10 mA 0.9 1.4 Ω

REGN

3.85 4.3 4.7 V

Driver dead time from low side to high side 20 ns Driver dead time from high side to low side 20 ns

Soft start current step 64 mA Soft start current step time 240 μs

In CCM mode 10mΩ current sensing resistor

SCLK/SDATA rise time 1 μs SCLK/SDATA fall time 300 ns SCLK pulse width high 4 50 μs SCLK Pulse Width Low 4.7 μs Setup time for START condition 4.7 μs START condition hold time after which first clock pulse is generated 4 μs Data setup time 250 ns Data hold time 300 ns Setup time for STOP condition 4 µs Bus free time between START and STOP condition 4.7 μs Clock Frequency 10 100 kHz

SMBus bus release timeout

(2)

25 35 ms Deglitch for watchdog reset signal 10 ms Watchdog timeout period, ChargeOption()

bit [14:13] = 01 Watchdog timeout period, ChargeOption()

bit [14:13] = 10 Watchdog timeout period, ChargeOption()

bit [14:13] = 11

(3)

(Default)

35 44 53 s

70 88 105 s

140 175 210 s

5.9 V

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Figure 3. SMBus Communication Timing Waveforms

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SLUS702A –JULY 2010–REVISED NOVEMBER 2010

TYPICAL CHARACTERISTICS

Table 1. Table of Graphs

FIGURE NO. VCC, ACDET, REGN and ACOK Power up Figure 4 Charge Enable by ILIM Figure 5 Current Soft-start Figure 6 Charge Disable by ILIM Figure 7 Continuous Conduction Mode Switching Waveforms Figure 8 Cycle-by-Cycle Synchronous to Non-synchronous Figure 9 100% Duty and Refresh Pulse Figure 10 System Load Transient (Input DPM) Figure 11 Battery Insertion Figure 12 Battery to Ground Short Protection Figure 13 Battery to Ground Short Transition Figure 14 Efficiency vs Output Current Figure 15

SPACER SPACER

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CH1: VCC, 10V/div, CH2: ACDET, 2V/div, CH3: ACOK, 5V/div, CH4: REGN, 5V/div, 40ms/div

Figure 4. VCC, ACDET, REGN and ACOK Power Up Figure 5. Charge Enable by ILIM

CH1: Vin, 10V/div, CH2: LODRV, 5V/div, CH3: PHASE, 10V/div, CH4: inductor current, 2A/div, 2ms/div

Figure 6. Current Soft-Start Figure 7. Charge Disable by ILIM

CH1: ILIM, 1V/div, CH4: inductor current, 1A/div, 20ms/div

CH1: ILIM, 1V/div, CH4: inductor current, 1A/div, 4us/div

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CH1: HIDRV, 10V/div, CH2: LODRV, 5V/div, CH3: PHASE, 10V/div, CH4: inductor current, 2A/div, 400ns/div

Figure 8. Continuous Conduction Mode Switching Figure 9. Cycle-by-Cycle Synchronous to Non-synchronous

CH1: PHASE, 10V/div, CH2: LODRV, 5V/div, CH4: inductor current, 2A/div, 4us/div

Figure 10. 100% Duty and Refresh Pulse Figure 11. System Load Transient (Input DPM)

Waveforms

CH1: HIDRV, 10V/div, CH2: LODRV, 5V/div, CH3: PHASE, 10V/div, CH4: inductor current, 1A/div, 400ns/div

CH2: battery current, 2A/div, CH3: adapter current, 2A/div, CH4: system load current, 2A/div, 100us/div

CH1: PHASE, 20V/div, CH2: battery voltage, 5V/div, CH3: LODRV, 10V/div, CH4: inductor current, 2A/div, 400us/div

Figure 12. Battery Insertion Figure 13. Battery to Ground Short Protection

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CH1: PHASE, 20V/div, CH2: LODRV, 10V/div, CH3: battery voltage, 5V/div, CH4: inductor current, 2A/div, 2ms/div

0 0.5 1 1.5 2 2.5 3 3.5 4 4.5

ChargeCurrent

4-cell16.8V

3-cell12.6V

2-cell8.4V

Efficiency-%

V =20V, f=750kHz,

L =4.7 HIm

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SLUS702A –JULY 2010–REVISED NOVEMBER 2010

CH1: PHASE, 20V/div, CH2: LODRV, 10V/div, CH3: battery voltage, 5V/div, CH4: inductor current, 2A/div, 4us/div

NO. NAME

1 ACN Input current sense resistor negative input. Place an optional 0.1 µF ceramic capacitor from ACN to GND for common-

2 ACP Input current sense resistor positive input. Place a 0.1µF ceramic capacitor from ACP to GND for common-mode

3 CMSRC ACDRV charge pump source input. Place a 4kΩ resistor from CMSRC to the common source of ACFET (Q1) and

4 ACDRV Charge pump output to drive both adapter input n-channel MOSFET (ACFET) and reverse blocking n-channel MOSFET

5 ACOK AC adapter detection open drain output. It is pulled HIGH to external pull-up supply rail by external pull-up resistor when

6 ACDET Adapter detection input. Program adapter valid input threshold by connecting a resistor divider from adapter input to

7 IOUT Buffered adapter or charge current output, selectable with SMBus command ChargeOption(). IOUT voltage is 20 times

8 SDA SMBus open-drain data I/O. Connect to SMBus data line from the host controller or smart battery. Connect a 10kΩ pull-

9 SCL SMBus open-drain clock input. Connect to SMBus clock line from the host controller or smart battery. Connect a 10kΩ

10 ILIM Charge current limit input. Program ILIM voltage by connecting a resistor divider from system reference 3.3V rail to ILIM

11 BATDRV Charge pump output to drive Battery to System n-channel MOSFET (BATFET). BATDRV voltage is 6V above SRN to

12 SRN Charge current sense resistor negative input. SRN pin is for battery voltage sensing as well. Connect the SRN pin to a

Figure 14. Battery to Ground Short Transition Figure 15. Efficiency vs Output Current

PIN FUNCTION DESCRIPTION

mode filtering. Place a 0.1µF ceramic capacitor from ACN to ACP to provide differential mode filtering.

filtering. Place a 0.1 µF ceramic capacitor from ACN to ACP to provide differential-mode filtering.

RBFET (Q2) limit the in-rush current on the CMSRC pin.

(RBFET). ACDRV voltage is 6V above CMSRC when voltage on ACDET pin is between 2.4V to 3.15V, voltage on VCC pin is above UVLO and voltage on VCC pin is 275mV above voltage on SRN pin so that ACFET and RBFET can be turned on to power the system by AC adapter. Place a 4kΩ resistor from ACDRV to the gate of ACFET and RBFET limits the in-rush current on ACDRV pin.

voltage on ACDET pin is between 2.4V and 3.15V, and voltage on VCC is above UVLO and voltage on VCC pin is 275mV above voltage on SRN pin, indicating a valid adapter is present to start charge. If any one of the above conditions can not meet, it is pulled LOW to GND by internal MOSFET. Connect a 10kΩ pull up resistor from ACOK to the pull-up supply rail.

ACDET pin to GND pin. When ACDET pin is above 0.6V and VCC is above UVLO, REGN LDO is present, ACOK comparator and IOUT are both active.

the differential voltage across sense resistor. Place a 100pF or less ceramic decoupling capacitor from IOUT pin to GND.

up resistor according to SMBus specifications.

pull-up resistor according to SMBus specifications.

pin to GND pin. The lower of ILIM voltage or DAC limit voltage sets charge current regulation limit. To disable the control on ILIM, set ILIM above 1.6V. Once voltage on ILIM pin falls below 75mV, charge is disabled. Charge is enabled when ILIM pin rises above 105mV.

turn on BATFET (Q5) to power the system from battery. BATDRV voltage is SRN voltage to turn off BATFET to power system from AC adapter. Place a 4kΩ resistor from BATDRV to the gate of BATFET limits the in-rush current on BATDRV pin.

7.5Ω resistor first then from resistor another terminal connect a 0.1µF ceramic capacitor to GND for common-mode filtering and connect to current sensing resistor. Connect a 0.1µF ceramic capacitor between current sensing resistor to provide differential mode filtering. See the application information about negative output voltage protection for hard shorts on battery to ground or battery reverse connection by adding small resistor.

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PIN FUNCTIONS – 20-PIN QFN

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PIN FUNCTIONS – 20-PIN QFN (continued)

PIN FUNCTION DESCRIPTION

NO. NAME

13 SRP Charge current sense resistor positive input. Connect the SRP pin to a 10Ω resistor first then from resistor another

terminal connect to current sensing resistor. Connect a 0.1µF ceramic capacitor between current sensing resistor to provide differential mode filtering. See the application information about negative output voltage protection for hard shorts on battery to ground or battery reverse connection by adding small resistor.

14 GND IC ground. On PCB layout, connect to analog ground plane, and only connect to power ground plane through the power

pad underneath IC. 15 LODRV Low side power MOSFET driver output. Connect to low side n-channel MOSFET gate. 16 REGN Linear regulator output. REGN is the output of the 6V linear regulator supplied from VCC. The LDO is active when

voltage on ACDET pin is above 0.6V and voltage on VCC is above UVLO. Connect a 1µF ceramic capacitor from

REGN to GND. 17 BTST High side power MOSFET driver power supply. Connect a 0.047µF capacitor from BTST to PHASE, and a bootstrap

Schottky diode from REGN to BTST. 18 HIDRV High side power MOSFET driver output. Connect to the high side n-channel MOSFET gate. 19 PHASE High side power MOSFET driver source. Connect to the source of the high side n-channel MOSFET. 20 VCC Input supply, diode OR from adapter or battery voltage. Use 10Ω resistor and 1µF capacitor to ground as low pass filter

to limit inrush current.

Exposed pad beneath the IC. Analog ground and power ground star-connected only at the PowerPAD plane. Always

PowerPAD™ solder PowerPAD to the board, and have vias on the PowerPAD plane connecting to analog ground and power ground

planes. It also serves as a thermal pad to dissipate the heat.

SLUS702A –JULY 2010–REVISED NOVEMBER 2010

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