TEXAS INSTRUMENTS bq2050 Technical data

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Features

Conservative and repeatable

➤

measurement of available capac ity in Lithium Ion rechargeable batteries

Designed for battery pack inte

➤

gration

120µA typical operating

current

Small size enables imple-

mentations in as little as square inch of PCB

Integrate within a system or as a

➤

stand-alone device

Display capacity via single-

wire serial communication port or direct drive of LEDs

➤ Measurements compensated for

current and temperature

➤ Self-discharge compensation us-

ing internal temperature sensor

➤ 16-pin narrow SOIC

bq2050

Lithium Ion Power Gauge™ IC

General Description

The bq2050 Lithium Ion Power Gauge™ IC is intended for battery-

pack or in-system installation to maintain an accurate record of available battery capacity. The IC

monitors a voltage drop across a

sense resistor connected in series between the negative battery termi nal and ground to determine charge and discharge activity of the battery. Compensations for bat

tery temperature and rate of charge or discharge are applied to the

charge, discharge, and self-discharge calculations to provide available ca pacity information across a wide range of operating conditions. Bat tery capacity is automatically recali brated, or “learned,” in the course of a discharge cycle from full to empty.

supports a simple single-line bidi rectional serial link to an external processor (common ground). The bq2050 outputs battery information in response to external commands over the serial link.

The bq2050 may operate directly from one cell (V REF output and an external transis

tor, a simple, inexpensive regulator

> 3V). With the

BAT

can be built for systems with more than one series cell.

Internal registers include available

capacity, temperature, scaled avail able energy, battery ID, battery

status, and programming pin set

tings. To support subassembly test

ing, the outputs may also be con

trolled. The external processor may

also overwrite some of the bq2050 power gauge data registers.

Nominal available capacity may be directly indicated using a fivesegment LED display. These segments are used to graphically indicate available capacity. The bq2050

Pin Connections Pin Names

LCOM LED common output

SEG

/PROG1LED segment 1/

/PROG2LED segment 2/

SEG

/PROG3LED segment 3/

SEG

/PROG4LED segment 4/

SEG

/PROG5LED segment 5/

SEG

PROG

9/96 C

LCOM

SEG1/PROG

SEG2/PROG

SEG3/PROG

SEG4/PROG

SEG5/PROG

PROG

16-Pin Narrow SOIC

PN205001.eps

REF

N/C

RBI

DISP

program 1 input

program 2 input

program 3 input

program 4 input

program 5 input

Program 6 input

REF Voltage reference output

N/C No connect

DQ Serial communications

input/output

RBI Register backup input

SB Battery sense input

DISP

Display control input

SR Sense resistor input

3.0–6.5V

System ground

bq2050

Pin Descriptions

LCOM

SEG SEG

PROG PROG

PROG

N/C

LED common output

Open-drain output switches V current for the LEDs. The switch is off dur ing initialization to allow reading of the soft pull-up or pull-down program resistors. LCOM is also high impedance when the dis play is off.

LED display segment outputs (dual func

–

tion with PROG

Each output may activate an LED to sink the current sourced from LCOM.

Programmed full count selection inputs

–

(dual function with SEG

These three-level input pins define the pro grammed full count (PFC) thresholds de scribed in Table 2.

Power gauge rate selection inputs (dual

–

function with SEG

These three-level input pins define the scale factor described in Table 2.

Self-discharge rate selection (dual func-

tion with SEG

This three-level input pin defines the selfdischarge and battery compensation factors as shown in Table 1.

Capacity initialization selection

This three-level pin defines the battery state of charge at reset as shown in Table 1.

No connect

–PROG6)

)

–SEG4)

–SEG2)

to source

DISP

Sense resistor input

The voltage drop (V sistor R

is monitored and integrated over

) across the sense re

time to interpret charge and discharge activ ity. The SR input is tied between the nega tive terminal of the battery and the sense re sistor. V

SR<VSS

indicates discharge, and V >VSSindicates charge. The effective voltage drop, V V

, as seen by the bq2050 is VSR+

SRO

Display control input

high disables the LED display. DISP

DISP

tied to VCCallows PROGXto connect directly to V

or VSSinstead of through a pull-up or

pull-down resistor. DISP

floating allows the LED display to be active during charge. DISP

low activates the display. See Table 1.

Secondary battery input

This input monitors the battery cell voltage potential through a high-impedance resistive divider network for end-of-discharge voltage (EDV) thresholds, and battery removed.

RBI

This pin is used to provide backup potential to the bq2050 registers during periods when V

≤ 3V. A storage capacitor or a battery

can be connected to RBI.

Serial I/O pin

This is an open-drain bidirectional pin.

REF

Voltage reference output for regulator

REF provides a voltage reference output for an optional micro-regulator.

Supply voltage input

Ground

bq2050

Functional Description

General Operation

The bq2050 determines battery capacity by monitor ing the amount of current input to or removed from a rechargeable battery. The bq2050 measures dis charge and charge currents, measures battery volt age, estimates self-discharge, monitors the battery for low battery voltage thresholds, and compensates for temperature and charge/discharge rates. The cur rent measurement is made by monitoring the voltage across a small-value series sense resistor between the negative battery terminal and ground. The estimate of scaled available energy is made using the remaining average battery voltage during the discharge cycle and the remaining nominal available charge. The

bq2050

Power Gauge IC

LCOM

SEG1/PROG

SEG2/PROG

SEG3/PROG

SEG4/PROG

SEG5/PROG

PROG

PSTAT

REF

DISP

RBI

scaled available energy measurement is corrected for the environmental and operating conditions.

Figure 1 shows a typical battery pack application of the bq2050 using the LED display capability as a chargestate indicator. The bq2050 is configured to display ca

pacity in relative display mode. The relative display mode uses the last measured discharge capacity of the

battery as the battery “full” reference. A push-button

display feature is available for momentarily enabling the LED display.

The bq2050 monitors the charge and discharge currents

as a voltage across a sense resistor (see R

in Figure 1).

A filter between the negative battery terminal and the SR pin may be required if the rate of change of the bat tery current is too great.

Q1 ZVNL110A

0.1 F V

Indicates optional.

Directly connect to VCC across 1 cell (V

Otherwise, R1, C1, and Q1 are needed for regulation of > 1 cell.

Programming resistors (6 max.) and ESD-protection diodes are not shown.

R-C on SR may be required, application-specific.

A series Zener may be used to limit discharge current at low voltages

ns using 3 or more cells.

in desi

BAT

> 3V).

Charger

Load

FG205001.eps

Figure 1. Battery Pack Application Diagram—LED Display

bq2050

Voltage Thresholds

In conjunction with monitoring VSRfor charge/discharge currents, the bq2050 monitors the battery potential through the SB pin. The voltage is determined through a resistor-divider network per the following equation:

RB1 RB2

2N=−1

where N is the number of cells, RB1 is connected to the positive battery terminal, and RB2 is connected to the negative battery terminal. The single-cell battery volt age is monitored for the end-of-discharge voltage (EDV). EDV threshold levels are used to determine when the battery has reached an “empty” state.

Two EDV thresholds for the bq2050 are programmable with the default values fixed at:

EDV1 (early warning) = 1.52V

EDVF (empty) = 1.47V

If V

is below either of the two EDV thresholds, the as

sociated flag is latched and remains latched, independent of V

, until the next valid charge. The VSBvalue is

also available over the serial port.

During discharge and charge, the bq2050 monitors V

for various thresholds used to compensate the charge and discharge rates. Refer to the count compensation section for details. EDV monitoring is disabled if the discharge rate is greater than 2C (typical) and resumes

second after the rate falls below 2C.

RBI Input

The RBI input pin is intended to be used with a storage ca pacitor or external supply to provide backup potential to the internal bq2050 registers when V

drops below 3.0V. V

is output on RBI when VCCis above 3.0V. A diode is re quired to isolate the external supply.

Reset

The bq2050 can be reset either by removing VCCand grounding the RBI pin for 15 seconds or by writing 0x80 to register 0x39.

Temperature

The bq2050 internally determines the temperature in 10°C steps centered from approximately -35°C to +85°C. The temperature steps are used to adapt charge and dis charge rate compensations, self-discharge counting, and available charge display translation. The temperature range is available over the serial port in 10°C incre ments as shown in the following table:

TMP (hex) Temperature Range

0x < -30°C

1x -30°C to -20°C

2x -20°C to -10°C

3x -10°C to 0°C

4x 0°C to 10°C

5x 10°C to 20°C

6x 20°C to 30°C

7x 30°C to 40°C

8x 40°C to 50°C

9x 50°C to 60°C

Ax 60°C to 70°C

Bx 70°C to 80°C

Cx > 80°C

Layout Considerations

The bq2050 measures the voltage differential between

the SR and V pin) is greatly affected by PC board layout. For optimal results, the PC board layout should follow the strict rule

of a single-point ground return. Sharing high-current ground with small signal ground causes undesirable noise on the small signal nodes. Additionally:

The capacitors (C1 and C2) should be placed as close as possible to the V respectively, and their paths to V short as possible. A high-quality ceramic capacitor of 0.1µf is recommended for V

The sense resistor capacitor should be placed as close as possible to the SR pin.

The sense resistor (RS) should be as close as possible to

the bq2050.

pins. VOS(the offset voltage at the SR

and SB pins,

should be as

bq2050

Gas Gauge Operation

The operational overview diagram in Figure 2 illustrates the operation of the bq2050. The bq2050 accumulates a measure of charge and discharge currents, as well as an estimation of self-discharge. Charge and discharge cur rents are temperature and rate compensated, whereas self-discharge is only temperature compensated.

The main counter, Nominal Available Capacity (NAC), represents the available battery capacity at any given time. Battery charging increments the NAC register, while battery discharging and self-discharge decrement the NAC register and increment the DCR (Discharge Count Register).

The Discharge Count Register (DCR) is used to update the Last Measured Discharge (LMD) register only if a complete battery discharge from full to empty occurs without any partial battery charges. Therefore, the bq2050 adapts its capacity determination based on the actual conditions of discharge.

Inputs

Charge Current

Rate and

Temperature

Compensation

The battery's initial capacity is equal to the Pro grammed Full Count (PFC) shown in Table 2. Until LMD is updated, NAC counts up to but not beyond this threshold during subsequent charges. This approach al lows the gas gauge to be charger-independent and com patible with any type of charge regime.

1. Last Measured Discharge (LMD) or learned battery capacity:

LMD is the last measured discharge capacity of the battery. On initialization (application of V tery replacement), LMD = PFC. During subsequent discharges, the LMD is updated with the latest measured capacity in the Discharge Count Register (DCR) representing a discharge from full to below EDV1. A qualified discharge is necessary for a capac ity transfer from the DCR to the LMD register. The LMD also serves as the 100% reference threshold used by the relative display mode.

Discharge

Current

Rate and

Temperature

Compensation

Self-Discharge

Timer

Temperature

Compensation

or bat

Main Counters

and Capacity

Reference (LMD)

Outputs

Nominal

Available

Charge

(NAC)

Temperature

Translation

Compensated Available Charge LED Display, etc.

Last

Measured

Discharged

(LMD)

Serial

Port

Figure 2. Operational Overview

Discharge

Count

Qualified

Transfer

Temperature Step, Other Data

(DCR)

FG205002.eps

bq2050

2. Programmed Full Count (PFC) or initial bat tery capacity:

The initial LMD and gas gauge rate values are pro grammed by using PROG

–PROG4. The bq2050 is

configured for a given application by selecting a PFC value from Table 2. The correct PFC may be determined by multiplying the rated battery capac ity in mAh by the sense resistor value:

Battery capacity (mAh)*sense resistor (Ω) =

PFC (mVh)

Selecting a PFC slightly less than the rated capac ity provides a conservative capacity reference until the bq2050 “learns” a new capacity reference.

Example: Selecting a PFC Value

Given:

Sense resistor = 0.05

Ω

Number of cells = 2 Capacity = 1000mAh, Li-Ion battery, coke-anode

Current range = 50mA to 1A Relative display mode Serial port only Self-discharge = Voltage drop over sense resistor = 2.5mV to 50mV

NAC

per day @ 25°C

512

Nominal discharge voltage = 3.6V

Therefore:

1000mAh*0.05Ω= 50mVh

Table 1. bq2050 Programming

Connection

H Table 4/Disabled PFC LEDs disabled

Z Table 4/

L Table 3/

Note: PROG5and PROG6states are independent.

PROG5Compensation/

Self-Discharge

NAC

512

NAC

512

PROG

NAC on Reset

Display State

0 LEDs on when charging

0 LEDs on for 4 sec.

DISP

Table 2. bq2050 Programmed Full Count mVh Selections

Pro-

grammed

PROG

Full

Count

1 2 PROG3 = H PROG3 = Z PROG3 = L PROG3 = H PROG3 = Z PROG3 = L

-- -

(PFC)

SCALE =

1/80

H H 49152 614 307 154 76.8 38.4 19.2 mVh

H Z 45056 563 282 141 70.4 35.2 17.6 mVh

H L 40960 512 256 128 64.0 32.0 16.0 mVh

Z H 36864 461 230 115 57.6 28.8 14.4 mVh

Z Z 33792 422 211 106 53.0 26.4 13.2 mVh

Z L 30720 384 192 96.0 48.0 24.0 12.0 mVh

L H 27648 346 173 86.4 43.2 21.6 10.8 mVh

L Z 25600 320 160 80.0 40.0 20.0 10.0 mVh

L L 22528 282 141 70.4 35.2 17.6 8.8 mVh

VSR equivalent to 2

counts/sec. (nom.)

90 45 22.5 11.25 5.6 2.8 mV

PROG

= L PROG4= Z

SCALE =

1/160

SCALE =

1/320

SCALE =

1/640

SCALE =

1/1280

SCALE =

1/2560

Units

mVh/ count

bq2050

Select:

PFC = 30720 counts or 48mVh

= float

PROG

= low

PROG

= high

PROG

= float

PROG

= float

PROG

= float

The initial full battery capacity is 48mVh (960mAh) until the bq2050 “learns” a new capacity with a qualified discharge from full to EDV1.

3. Nominal Available Capacity (NAC):

NAC counts up during charge to a maximum value of LMD and down during discharge and self-dis charge to 0. NAC is reset to 0 on initialization and on the first valid charge following discharge to EDV1. To prevent overstatement of charge during periods of overcharge, NAC stops incrementing when NAC = LMD.

4. Discharge Count Register (DCR):

The DCR counts up during discharge independent of NAC and could continue increasing after NAC has decremented to 0. Prior to NAC = 0 (empty battery), both discharge and self-discharge increment the DCR. After NAC = 0, only discharge increments the DCR. The DCR resets to 0 when NAC = LMD. The DCR does not roll over but stops counting when it reaches FFFFh.

The DCR value becomes the new LMD value on the first charge after a valid discharge to V

EDV1

No valid charge initiations (charges greater than 256 NAC counts, where V

SRO>VSRQ

) occurred dur ing the period between NAC = LMD and EDV1 de tected.

The self-discharge count is not more than 4096 counts (8% to 18% of PFC, specific percentage threshold determined by PFC).

The temperature is≥0°C when the EDV1 level is reached during discharge.

The valid discharge flag (VDQ) indicates whether the present discharge is valid for LMD update.

5. Scaled Available Energy (SAE):

SAE is useful in determining the available energy within the battery, and may provide a more useful capacity reference in battery chemistries with sloped voltage profiles during discharge. SAE may be converted to a mWh value using the following formula:

E(mWh) =

(* *SAEH SAEL)256 +

24.)∗∗+

SCALE (R R

B1 B2

∗

SB2

where RB1,RB2and RSare resistor values in ohms. SCALE is the selected scale from Table 2. SAEH and SAEL are digital values read via DQ.

6. Compensated Available Capacity (CAC)

CAC counts similar to NAC, but contains the avail

able capacity compensated for discharge rate and temperature.

Charge Counting

Charge activity is detected based on a positive voltage on the V bq2050 increments NAC at a rate proportional to V if enabled, activates an LED display. Charge actions in

input. If charge activity is detected, the

and,

crement the NAC after compensation for temperature.

The bq2050 determines charge activity sustained at a continuous rate equivalent to V

SRO>VSRQ

. A valid charge equates to sustained charge activity greater than 256 NAC counts. Once a valid charge is detected, charge counting continues until V below V

SRQ

is 210µV, and is described in the

SRQ

SRO(VSR+VOS

) falls

Digital Magnitude Filter section.

Discharge Counting

Discharge activity is detected based on a negative voltage on the V

if:

cause the NAC register to decrement and the DCR to increment. V

input. All discharge counts where V

is -200µV, and is described in the

SRD

SRO<VSRD

Digital Magnitude Filter section.

Self-Discharge Estimation

The bq2050 continuously decrements NAC and increments DCR for self-discharge based on time and temperature. The self-discharge count rate is programmed to be a nominal

NAC per day or disabled. This is the rate for a bat

512

tery whose temperature is between 20°–30°C. The NAC

Count Compensations

Discharge Compensation

Corrections for the rate of discharge, temperature, and anode type are made by adjusting an internal compensation factor. This factor is based on the measured rate of discharge of the battery. Tables 3A and 3B outline the correction factor typi cally used for graphite anode Li-Ion batteries, and Tables 4A and 4B outline the factors typically used for coke anode Li-Ion batteries. The compensation factor is applied to CAC and is based on discharge rate and temperature.

bq2050

Table 3A. Graphite Anode

Discharge

Approximate

Discharge Rate

0.5C 1.00 100%

0.5C 1.05 95%

≥

Compensation

Factor Efficiency

Table 3B. Graphite Anode

Temperature

Compensation

Temperature

10°C 1.00 100%

≥

Factor Efficiency

0°C to 10°C 1.10 90%

-10°C to 0°C 1.35 74%

-10°C 2.50 40%

≤

Table 4A. Coke Anode

Discharge

Approximate

Discharge Rate

0.5C 1.00 100%

0.5C 1.15 86%

≥

Compensation

Factor Efficiency

Charge Compensation

The bq2050 applies the following temperature compen sation to NAC during charge:

Temperature

Compensation

Temperature

10°C 0.95 95%

10°C 1.00 100%

≥

Factor Efficiency

This compensation applies to both types of Li-Ion cells.

Self-Discharge Compensation

The self-discharge compensation is programmed for a nominal rate of battery within the 20°C–30°C temperature range. This rate varies across 8 ranges from < 10°C to > 70°C, chang ing with each higher temperature (approximately 10°C). See Table 5 below:

NAC per day. This is the rate for a

512

Table 5. Self-Discharge Compensation

Typical Rate

Temperature Range

< 10°C

10–20°C

20–30°C

30–40°C

40–50°C

50–60°C

60–70°C

> 70°C

PROG

NAC

= Z or L

2048

1024

512

256

128

Table 4B. Coke Anode

Temperature

Compensation

Temperature

10°C 1.00 100%

≥

0°C to 10°C 1.25 80%

-10°C to 0°C 2.00 50%

-10°C 8.00 12%

≤

Factor Efficiency

Self-discharge may be disabled by connecting PROG

Digital Magnitude Filter

The bq2050 has a digital filter to eliminate charge and dis charge counting below a set threshold. The bq2050 setting is 200µV for V

and 210µV for V

SRD

SRQ

=H.

Table 6. bq2050 Current-Sensing Errors

Symbol Parameter Typical Maximum Units Notes

INL

INR

Integrated non-linearity error

Integrated nonrepeatability error

Add 0.1% per °C above or below 25°C

and 1% per volt above or below 4.25V.

Measurement repeatability given

similar operating conditions.

bq2050

Error Summary

Capacity Inaccurate

The LMD is susceptible to error on initialization or if no updates occur. On initialization, the LMD value in cludes the error between the programmed full capacity and the actual capacity. This error is present until a valid discharge occurs and LMD is updated (see the DCR description on page 7). The other cause of LMD er ror is battery wear-out. As the battery ages, the meas ured capacity must be adjusted to account for changes in actual battery capacity.

A Capacity Inaccurate counter (CPI) is maintained and incremented each time a valid charge occurs (qualified by NAC; see the CPI register description) and is reset whenever LMD is updated from the DCR. The counter does not wrap around but stops counting at 255. The capacity inaccurate flag (CI) is set if LMD has not been updated following 64 valid charges.

Current-Sensing Error

Table 5 illustrates the current-sensing error as a func tion of V charge counts to the NAC register when V V

SRQ

. A digital filter eliminates charge and dis

SRO

and V

SRD

is between

SRO

Communicating With the bq2050

The bq2050 includes a simple single-pin (DQ plus re turn) serial data interface. A host processor uses the in terface to access various bq2050 registers. Battery char acteristics may be easily monitored by adding a single contact to the battery pack. The open-drain DQ pin on the bq2050 should be pulled up by the host system, or may be left floating if the serial interface is not used.

The interface uses a command-based protocol, where the host processor sends a command byte to the bq2050. The command directs the bq2050 to either store the next eight bits of data received to a register specified by the command byte or output the eight bits of data specified by the command byte.

The communication protocol is asynchronous return-toone. Command and data bytes consist of a stream of

eight bits that have a maximum transmission rate of 333 bits/sec. The least-significant bit of a command or data byte is transmitted first. The protocol is simple enough that it can be implemented by most host proces sors using either polled or interrupt processing. Data

input from the bq2050 may be sampled using the pulsewidth capture timers available on some microcontrol lers.

If a communication error occurs, e.g. t

bq2050 should be sent a BREAK to reinitiate the serial

interface. A BREAK is detected when the DQ pin is

driven to a logic-low state for a time, t

> 6ms, the

CYCB

or greater. The

DQ pin should then be returned to its normal readyhigh logic state for a time, t

. The bq2050 is now ready

to receive a command from the host processor.

The return-to-one data bit frame consists of three distinct sections. The first section is used to start the transmission by either the host or the bq2050 taking the DQ pin to a logic-low state for a period, t

STRH,B

next section is the actual data transmission, where the data should be valid by a period, t

, after the negative

DSU

edge used to start communication. The data should be

held for a period, t

sample the data bit.

, to allow the host or bq2050 to

The final section is used to stop the transmission by re turning the DQ pin to a logic-high state by at least a pe riod, t

, after the negative edge used to start commu

SSU

nication. The final logic-high state should be held until a period, t

mission was stopped properly. The timings for data and

break communication are given in the serial communi

cation timing specification and illustration sections.

, to allow time to ensure that the bit trans

Communication with the bq2050 is always performed with the least-significant bit being transmitted first. Figure 3 shows an example of a communication sequence to read the bq2050 NAC register.

. The

bq2050

Written by Host to bq2050

CMDR = 03h

LSB MSB LSB MSB

Break 0 0 0 0 0 0 1 0 1 0 0 1

1110

Figure 3. Typical Communication With the bq2050

bq2050 Registers

The bq2050 command and status registers are listed in Table 7 and described below.

Command Register (CMDR)

The write-only CMDR register is accessed when eight valid command bits have been received by the bq2050. The CMDR register contains two fields:

W/R bit

Command address

The W/R the received command is for a read or a write function.

The W/R

Where W/R is:

The lower seven-bit field of CMDR contains the address portion of the register to be accessed. Attempts to write to invalid addresses are ignored.

bit of the command register is used to select whether

values are:

CMDR Bits

7654 3 2 1 0

W/R

- -- - - - -

0 The bq2050 outputs the requested register con

tents specified by the address portion of CMDR.

1 The following eight bits should be written

to the register specified by the address por

tion of CMDR.

Received by Host to bq2050

NAC = 65h

TD205002.eps

Primary Status Flags Register (FLGS1)

The read-only FLGS1 register (address=01h) contains the primary bq2050 flags.

The charge status flag (CHGS) is asserted when a valid charge rate is detected. Charge rate is deemed valid when V

SRO>VSRQ

discharge activity clears CHGS.

The CHGS values are:

76543 2 1 0

CHGS - -- - - - -

Where CHGS is:

0 Either discharge activity detected or V

SRQ

SRO>VSRQ

The battery replaced flag (BRP) is asserted whenever the bq2050 is reset either by application of V serial port command. BRP is reset when either a valid charge action increments NAC to be equal to LMD, or a valid charge action is detected after the EDV1 flag is as serted. BRP = 1 signifies that the device has been reset.

The BRP values are:

76543 2 1 0

- BRP - - - - - -

.AV

SRO

FLGS1 Bits

of less than V

SRO

SRQ

or by a

CMDR Bits

765 4 3 2 1 0

- AD6 AD5 AD4 AD3 AD2 AD1

AD0

(LSB)

Where BRP is:

0 Battery is charged until NAC = LMD or dis

charged until the EDV1 flag is asserted

1 bq2050 is reset

bq2050

Table 7. bq2050 Command and Status Registers

Loc.

Symbol

CMDR Command register 00h Write W/R

FLGS1

TMP Temperature register 02h Read TMP3 TMP2 TMP1 TMP0 GG3 GG2 GG1 GG0

NACH

NACL

BATID

LMD

FLGS2

PPD

PPU

CPI

VSB

VTS

CACH

CACL

SAEH

SAEL

RST Reset register 39h Write RST 0 0 0 0 0 0 0

Note: n/u = not used

Primary status flags register

Nominal available ca pacity high byte reg ister

Nominal available capacity low byte register

Battery identification register

Last measured dis charge register

Secondary status flags register

Program pin pulldown register

Program pin pull-up register

Capacity inaccurate count register

Battery voltage register

End-of-discharge thresh

old select register Compensated avail

able capacity high byte register

Compensated available capacity low byte register

Scaled available energy high byte reg ister

Scaled available energy low byte regis ter

Read/

(hex)

Write

01h Read CHGS BRP n/u CI VDQ n/u EDV1 EDVF

03h R/W NACH7 NACH6 NACH5 NACH4 NACH3 NACH2 NACH1 NACH0

17h Read NACL7 NACL6 NACL5 NACL4 NACL3 NACL2 NACL1 NACL0

04h R/W BATID7 BATID6 BATID5 BATID4 BATID3 BATID2 BATID1 BATID0

05h R/W LMD7 LMD6 LMD5 LMD4 LMD3 LMD2 LMD1 LMD0

06h Read n/u DR2 DR1 DR0 n/u n/u n/u OVLD

07h Read n/u n/u PPD6 PPD5 PPD4 PPD3 PPD2 PPD1

08h Read n/u n/u PPU6 PPU5 PPU4 PPU3 PPU2 PPU1

09h Read CPI7 CPI6 CPI5 CPI4 CPI3 CPI2 CPI1 CPI0

0Bh Read VSB7 VSB6 VSB5 VSB4 VSB3 VSB2 VSB1 VSB0

0Ch R/W VTS7 VTS6 VTS5 VTS4 VTS3 VTS2 VTS1 VTS0

0Dh Read CACH7 CACH6 CACH5 CACH4 CACH3 CACH2 CACH1 CACH0

0Eh Read CACL7 CACL6 CACL5 CACL4 CACL3 CACL2 CACL1 CACL0

0Fh Read SAEH7 SAEH6 SAEH5 SAEH4 SAEH3 SAEH2 SAEH1 SAEH0

10h Read SAEL7 SAEL6 SAEL5 SAEL4 SAEL3 SAEL2 SAEL1 SAEL0

Control Field

7(MSB) 6 5 4 3 2 1 0(LSB)

AD6 AD5 AD4 AD3 AD2 AD1 AD0

bq2050

The capacity inaccurate flag (CI) is used to warn the user that the battery has been charged a substantial number of times since LMD has been updated. The CI flag is asserted on the 64th charge after the last LMD update or when the bq2050 is reset. The flag is cleared after an LMD update.

The CI values are:

FLGS1 Bits

76543 2 1 0

---CI- - - -

Where CI is:

0 When LMD is updated with a valid full dis

charge

1 After the 64th valid charge action with no

LMD updates or the bq2050 is reset

The valid discharge flag (VDQ) is asserted when the bq2050 is discharged from NAC=LMD. The flag remains set until either LMD is updated or one of three actions that can clear VDQ occurs:

The self-discharge count register (SDCR) has

exceeded the maximum acceptable value (4096 counts) for an LMD update.

A valid charge action sustained at V

SRO

> V

SRQ

for at

least 256 NAC counts.

The EDV1 flag was set at a temperature below 0°C

The VDQ values are:

FLGS1 Bits

76543 2 1 0

- - - - VDQ - - -

Where VDQ is:

0 SDCR≥4096, subsequent valid charge ac

tion detected, or EDV1 is asserted with the temperature less than 0°C

1 On first discharge after NAC = LMD

The first end-of-discharge warning flag (EDV1) warns the user that the battery is almost empty. The first segment pin, SEG

, is modulated at a 4Hz rate if

the display is enabled once EDV1 is asserted, which should warn the user that loss of battery power is immi nent. The EDV1 flag is latched until a valid charge has been detected. The EDV1 threshold is externally con trolled via the VTS register (see Voltage Threshold Reg ister on this page).

The EDV1 values are:

FLGS1 Bits

7654 3 2 1 0

- - - - - - EDV1 -

Where EDV1 is:

0 Valid charge action detected, V

≥

1VSB<VTSproviding that the discharge rate is

<2C

The final end-of-discharge warning flag (EDVF) flag is used to warn that battery power is at a failure condi tion. All segment drivers are turned off. The EDVF flag is latched until a valid charge has been detected. The EDVF threshold is set 50mV below the EDV1 threshold.

The EDVF values are:

FLGS1 Bits

7654 3 2 1 0

---- - - -EDVF

Where EDVF is:

0 Valid charge action detected, V

≥

50mV)

< (VTS- 50mV) providing the discharge

rate is < 2C

Temperature Register (TMP)

The read-only TMP register (address=02h) contains the battery temperature.

TMP Temperature Bits

76543210

TMP4 TMP3 TMP2 TMP1 - - - -

The bq2050 contains an internal temperature sensor. The temperature is used to set charge and discharge ef ficiency factors as well as to adjust the self-discharge co efficient. The temperature register contents may be translated as shown in Table 7.

The bq2050 calculates the gas gauge bits, GG3-GG0 as a function of CACH and LMD. The results of the calculation

give available capacity in

increments from 0 to

bq2050

Table 7. Temperature Register

TMP3 TMP2 TMP1 TMP0 Temperature

0000 T < -30°C

0001-30°C < T < -20°C

0010-20°C < T < -10°C

0011-10°C < T < 0°C

01000°C < T < 10°C

010110°C < T < 20°C

011020°C < T < 30°C

011130°C < T < 40°C

100040°C < T < 50°C

100150°C < T < 60°C

101060°C < T < 70°C

101170°C < T < 80°C

1100 T > 80°C

TMPGG Gas Gauge Bits

76 5 4 321 0

- - - - GG3 GG2 GG1 GG0

Nominal Available Charge Registers (NACH/NACL)

The read/write NACH high-byte register (address=03h) and the read-only NACL low-byte register (address=17h) are the main gas gauging register for the bq2050. The NAC registers are incremented during charge actions and decre mented during discharge and self-discharge actions. The correction factors for charge/discharge efficiency are applied automatically to NAC. NACH and NACL are set to 0 dur ing a bq2050 reset.

Writing to the NAC registers affects the available charge

counts and, therefore, affects the bq2050 gas gauge opera tion. Do not write the NAC registers to a value greater than LMD.

Battery Identification Register (BATID)

The read/write BATID register (address=04h) is avail able for use by the system to determine the type of bat tery pack. The BATID contents are retained as long as V

is greater than 2V. The contents of BATID have no

effect on the operation of the bq2050. There is no de fault setting for this register.

Last Measured Discharge Register (LMD)

LMD is a read/write register (address=05h) that the bq2050 uses as a measured full reference. The bq2050 adjusts LMD based on the measured discharge capacity of the battery from full to empty. In this way the bq2050 updates the capacity of the battery. LMD is set to PFC during a bq2050 reset.

Secondary Status Flags Register (FLGS2)

The read-only FLGS2 register (address=06h) contains the secondary bq2050 flags.

FLGS2 Bits

7 6 5 4 3210

- DR2 DR1 DR0 - - -

The discharge rate flags, DR2–0,are bits 6–4.

DR2 DR1 DR0 Discharge Rate

0 0 0 DRATE<0.5C 0 0 1 0.5C≤DRATE<2C 0 1 0 DRATE≥2C (OVLD = 1)

They are used to determine the current discharge regime as follows:

FLGS2 Bits

76543 2 1 0

- - - - - - - OVLD

The overload flag (OVLD) is asserted when a discharge rate in excess of 2C is detected. OVLD remains asserted as long as the condition persists and is cleared 0.5 sec

onds after the rate drops below 2C. The overload condi

tion is used to stop sampling of the battery terminal char acteristics for end-of-discharge determination.

Program Pin Pull-Down Register (PPD)

The read-only PPD register (address=07h) contains some

of the programming pin information for the bq2050. The segment drivers, SEG ter location, PPD resistor has been detected on its corresponding segment driver. For example, if SEG

resistors, the contents of PPD are xx001001.

, have a corresponding PPD regis

1–6

. A given location is set if a pull-down

1–6

and SEG4have pull-down

Program Pin Pull-Up Register (PPU)

The read-only PPU register (address=08h) contains the rest

of the programming pin information for the bq2050. The

segment drivers, SEG ter location, PPU sistor has been detected on its corresponding segment

, have a corresponding PPU regis

1–6

. A given location is set if a pull-up re

1–6

bq2050

driver. For example, if SEG3and SEG6have pull-up resis tors, the contents of PPU are xx100100.

PPD/PPU Bits

76543210

- - PPU

- - PPD6PPD5PPD4PPD3PPD2PPD

PPU5PPU4PPU3PPU2PPU

Capacity Inaccurate Count Register (CPI)

The read-only CPI register (address=09h) is used to in dicate the number of times a battery has been charged without an LMD update. Because the capacity of a re chargeable battery varies with age and operating condi tions, the bq2050 adapts to the changing capacity over time. A complete discharge from full (NAC=LMD) to empty (EDV1=1) is required to perform an LMD update assuming there have been no intervening valid charges, the temperature is greater than or equal to 0°C, and the self-discharge counter is less than 4096 counts.

The CPI register is incremented every time a valid charge is detected. When NAC > 0.94*LMD, however, the CPI register increments on the first valid charge; CPI does not increment again for a valid charge until NAC < 0.94*LMC. This prevents continuous trickle charging from incrementing CPI if self-discharge decrements NAC. The CPI register increments to 255 without rolling over. When the contents of CPI are incremented to 64, the capacity inaccurate flag, CI, is asserted in the FLGS1 register. The CPI register is reset whenever an update of the LMD register is performed, and the CI flag is also cleared.

Battery Voltage Register (VSB)

The read-only battery voltage register is used to read the single-cell battery voltage on the SB pin. The VSB regis ter (address = 0Bh) is updated approximately once per sec ond with the present value of the battery voltage. V

2.4V*(VSB/256).

VSB Register Bits

76543210

VSB7 VSB6 VSB5 VSB4 VSB3 VSB2 VSB1 VSB0

Voltage Threshold Register (VTS)

The end-of-discharge threshold voltages (EDV1 and EDVF) can be set using the VTS register (address = 0Ch). The read/write VTS register sets the EDV1 trip point. EDVF is set 50mV below EDV1. The default value in the VTS register is A2h, representing EDV1 =

1.52V and EDVF = 1.47V. EDV1 = 2.4V*(VTS/256).

76543210

VTS7 VTS6 VTS5 VTS4 VTS3 VTS2 VTS1 VTS0

Compensated Available Charge Registers

(CACH/CACL)

The read-only CACH high-byte register (address = 0Dh) and the read-only CACL low-byte register (address = 0Eh) represent the available charge compensated for discharge rate and temperature. CACH and CACL use

piece-wise corrections as outlined in Tables 3A, 3B, 4A,

and 4B, and will vary as conditions change. The NAC

and LMD registers are not affected by the discharge

rate and temperature.

VTS Register Bits

Scaled Available Energy Registers (SAEH/SAEL)

The read-only SAEH high-byte register (address = 0Fh) and the read only SAEL low-byte register (address = 10h) are used to scale battery voltage and CAC to a value which can be translated to watt-hours remaining under the present conditions. SAEL and SAEH may be converted to mWh using the formula on page 7.

Reset Register (RST)

The reset register (address = 39h) enables a softwarecontrolled reset of the device. By writing the RST register contents from 00h to 80h, a bq2050 reset is performed. Setting any bit other than the most-significant

bit of the RST register is not allowed and results in im proper operation of the bq2050.

Resetting the bq2050 sets the following:

LMD = PFC

CPI, VDQ, NACH, and NACL = 0

CI and BRP = 1

Note: Self-discharge is disabled when PROG

Display

The bq2050 can directly display capacity information using low-power LEDs. If LEDs are used, the program pins should be resistively tied to V gram high or program low, respectively.

The bq2050 displays the battery charge state in relative mode. In relative mode, the battery charge is represented as a percentage of the LMD. Each LED segment repre sents 20% of the LMD.

The capacity display is also adjusted for the present bat tery temperature. The temperature adjustment reflects the available capacity at a given temperature but does

or VSSfor a pro

=H.

bq2050

not affect the NAC register. The temperature adjust ments are detailed in the CACH and CACL register de scriptions.

When DISP tive. When DISP

is tied to VCC, the SEG

outputs are inac

1–5

is left floating, the display becomes ac tive whenever the bq2050 detects a charge in progress V

SRO>VSRQ

. When pulled low, the segment outputs be

come active for a period of four seconds,±0.5 seconds.

The segment outputs are modulated as two banks, with segments 1, 3, and 5 alternating with segments 2 and 4. The segment outputs are modulated at approximately 100Hz with each segment bank active for 30% of the pe riod.

SEG

blinks at a 4Hz rate whenever VSBhas been de

tected to be below V battery condition. V

(EDV1 = 1), indicating a low-

EDV1

below V

(EDVF = 1) disables

EDVF

the display output.

Microregulator

The bq2050 can operate directly from one cell. A micro power source for the bq2050 can be inexpensively built using the FET and an external resistor to accommodate a greater number of cells; see Figure 1.

bq2050

Absolute Maximum Ratings

Symbol Parameter Minimum Maximum Unit Notes

Relative to V

All other pins Relative to V

REF Relative to V

OPR

Relative to V

Operating tempera ture

-0.3 7.0 V

-0.3 8.5 V Current limited by R1 (see Figure 1)

Minimum 100Ωseries resistor should

-0.3 7.0 V

be used to protect SR in case of a shorted battery (see the bq2050 appli cation note for details).

0 70 °C Commercial

-40 85 °C Industrial

Note: Permanent device damage may occur if Absolute Maximum Ratings are exceeded. Functional operation

should be limited to the Recommended DC Operating Conditions detailed in this data sheet. Exposure to con ditions beyond the operational limits for extended periods of time may affect device reliability.

DC Voltage Thresholds (T

= T

; V = 3.0 to 6.5V)

OPR

Symbol Parameter Minimum Typical Maximum Unit Notes

EDVF

EDV1

SRO

SRQ

SRD

MCV

Final empty warning 1.44 1.47 1.50 V SB

First empty warning 1.49 1.52 1.55 V SB

SR sense range -300 - 2000 mV SR, VSR+ V

Valid charge 210 - -

Valid discharge - - -200

VVSR+ VOS(see note)

Maximum single-cell voltage 2.20 2.25 2.30 V SB

Note: VOSis affected by PC board layout. Proper layout guidelines should be followed for optimal performance.

See “Layout Considerations.”

bq2050

DC Electrical Characteristics (T

= T

OPR

)

Symbol Parameter Minimum Typical Maximum Unit Notes

excursion from < 2.0V to

REF

SBmax

DISP

LCOM

RBI

OLSL

OLSH

OHLCL

OHLCH

OHLCOM

OLS

IHDQ

ILDQ

PROG

FLOAT

Supply voltage 3.0 4.25 6.5 V

Offset referred to V

±50 ±150 µV

Reference at 25°C 5.7 6.0 6.3 V I

Reference at -40°C to +85°C 4.5 - 7.5 V I

Reference input impedance 2.0 5.0 - MΩV

- 90 135

Normal operation

- 120 180

- 170 250

Battery input 0 - V

SB input impedance 10 - - MΩ0 < VSB< V

DISP input leakage - - 5

LCOM input leakage -0.2 - 0.2

RBI data retention current - - 100 nA V

Internal pulldown 500 - - K

Sense resistor input -0.3 - 2.0 V

SR input impedance 10 - - MΩ-200mV < VSR< V

Logic input high VCC- 0.2 - - V PROG1–PROG

Logic input low - - VSS+ 0.2 V PROG1–PROG

Logic input Z float - float V PROG1–PROG

SEGXoutput low, low V

SEGXoutput low, high V

LCOM output high, low V

LCOM output high, high V

PROG

input high current - 1.2 -

1-6

input low current - 1.2 -

1-6

- 0.1 - V

- 0.4 - V

VCC- 0.3 - - V VCC= 3V, I

VCC- 0.6 - - V VCC= 6.5V, I

LCOM source current -33 - - mA At V

SEG

sink current - - 11.0 mA At V

1-5

Open-drain sink current - - 5.0 mA

Open-drain output low - - 0.5 V I

DQ input high 2.5 - - V DQ

DQ input low - - 0.8 V DQ

Soft pull-up or pull-down resis tor value (for programming)

- - 200

Float state external impedance - 5 - MΩPROG1–PROG

3.0V initializes the unit.

= V

DISP

= 5µA

REF

= 5µA

REF

= 3V

REF

= 3.0V, DQ = 0

= 4.25V, DQ = 0

= 6.5V, DQ = 0

A DISP = V

= V

DISP

> VCC< 3V

RBI

Ω

SR<VSS

> VSS= charge

= 3V, I

–SEG

SEG

= 6.5V, I

SEG

–SEG

PROG

At V

= VCC/2

OHLCH

OLSH

= VSS+ 0.3V

5mA, DQ

≤

–PROG

PROG

Ω

= discharge;

OLS

OHLCOM

= VCC- 0.6V

= 0.4V

Note: All voltages relative to VSS.

1.75mA

≤

11.0mA

≥

= -5.25mA

= -33.0mA

bq2050

Serial Communication Timing Specification (T

OPR

)

Symbol Parameter Minimum Typical Maximum Unit Notes

CYCH

CYCB

STRH

STRB

DSU

SSU

Cycle time, host to bq2050 3 - - ms See note

Cycle time, bq2050 to host 3 - 6 ms

Start hold, host to bq2050 5 - - ns

Start hold, bq2050 to host 500 - -

Data setup - - 750

Data hold 750 - -

Data valid 1.50 - - ms

Stop setup - - 2.25 ms

Stop hold 700 - -

Stop valid 2.95 - - ms

Break 3 - - ms

Break recovery 1 - - ms

Notes: The open-drain DQ pin should be pulled to at least VCCby the host system for proper DQ operation.

DQ may be left floating if the serial interface is not used.

Serial Communication Timing

(R/W "1")

(R/W "0")

(BREAK)

STRH

STRB

DSU

SSU

CYCH, tCYCB, tB

TD201002.eps

16-Pin SOIC Narrow (SN)

bq2050

16-Pin SN(0.150" SOIC

Dimension

A 0.060 0.070 1.52 1.78

A1 0.004 0.010 0.10 0.25

B 0.013 0.020 0.33 0.51

C 0.007 0.010 0.18 0.25

D 0.385 0.400 9.78 10.16

E 0.150 0.160 3.81 4.06

e 0.045 0.055 1.14 1.40

H 0.225 0.245 5.72 6.22

L 0.015 0.035 0.38 0.89

Inches Millimeters

Min. Max. Min. Max.

)

.004

Data Sheet Revision History

Change No. Page No. Description Nature of Change

1 4 Changed reset procedure Was: Reset by issuing command over serial port

1 11, 14 Deleted reset register 2 16 Changed values V

2 17 Changed values V 2 4, 11, 13, 14 Reinserted reset register 2 9 Maximum offset V

Notes: Change 1 = June 1995 B changes from Dec. 1994.

Change 2 = Sept. 1996 C changes from June 1995 B.

Is: Reset by removing V

EDVF

EDV1

15 s.

: Min. was 1.45; Max. was 1.49

Min. now is 1.44; Max. now is 1.50

: Min. was 1.50; Min. now is 1.49

: Min. was 2.5; Min. now is 3.0

: Max. was 150

Max. now is 180

and grounding RBI for

bq2050

Ordering Information

bq2050

* Contact factory for availability.

Temperature Range:

blank = Commercial (-20 to +70°C) N = Industrial (-40 to +85°C)*

Package Option:

SN = 16-pin narrow SOIC

Device:

bq2040 Gas Gauge IC With SMB Interface

17919 Waterview Parkway

Dallas, Texas 75252

Fax: (972) 437-9198

Tel: (972) 437-9195

www.benchmarq.com or www.unitrode.com

Copyright © 1996, Unitrode Corporation All rights reserved. No part of this data sheet may be reproduced in any form or means, without express permission from Unitrode. Unitrode reserves the right to make changes in its prod ucts without notice.

Unitrode assumes no responsibility for use of any products or circuitry described within. No license for use of intel lectual property (patents, copyrights, or other rights) owned by Unitrode or other parties is granted or implied.

Unitrode does not authorize the use of its components in life-support systems where failure or malfunction may cause injury to the user. If Unitrode components are used in life-support systems, the user assumes all responsibili ties and indemnifies Unitrode from all liability or damages.

Benchmarq is a registered trademark of Unitrode Corporation. Printed in U.S.A.

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TEXAS INSTRUMENTS bq2050 Technical data

Specifications and Main Features

Frequently Asked Questions

User Manual