TEXAS INSTRUMENTS bq2022 Technical data
T
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments
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FEATURES
D 1024 bits of One-Time Programmable (OTP)
EPROM For Storage Of User-Programmable
Configuration Data
D Factory-Programmed Unique 64-Bit
Identification Number
D Bus-Interface Architecture Allowing Multiple
bq2022s Attached to a Single Host
D Single-Wire Interface to Reduce Circuit
Board Routing
D Synchronous Communication Reduces Host
Interrupt Overhead
D No Standby Power Required
D Available in a 3-Pin SOT23 Package
APPLICATIONS
D Security Encoding
D Inventory Tracking
D Product-Revision Maintenance
D Battery-Pack Identification
SLUS526B − OCTOBER 2002 − REVISED OCTOBER 2003
DESCRIPTION
The bq2022 is a 1K-bit serial EPROM containing a factory
programmed unique 48-bit identification number, 8-bit
CRC generation, and the 8-bit family code (09h). A 64-bit
status register controls write protection and page
redirection.
The bq2022 SDQ interface (TI’s proprietary serial
communications protocol) requires only a single
connection and a ground return. The DATA pin is also the
sole power source for the bq2022. The bus architecture
allows multiple SDQ devices to be connected to a single
host.
The small surface-mount package options saves
printed-circuit-board space, while the low cost makes it
ideal for applications such as battery pack configuration
parameters, record maintenance, asset tracking, productrevision status, and access-code security.
ORDERING INFORMATION
A
−20°C to 70°C bq2022DBZR
(1)
Device assured to communicate at −40°C to 85°C.
(2)
The device is available only in tape and reel with a base quantity of
3000 units.
PACKAGED DEVICES
SOT23−3
BLOCK DIAGRAM
DBZR P ACKAGE
ID ROM
SDQ 1
2VSS 3 VSS
semiconductor products and disclaimers thereto appears at the end of this data sheet.
!"# $ %&'# "$ (&)%"# *"#'+ *&%#$
%! # $('%%"#$ (' #,' #'!$ '-"$ $#&!'#$ $#"*"* .""#/+
*&%# (%'$$0 *'$ # '%'$$")/ %)&*' #'$#0 ")) (""!'#'$+
SDQ Communications
Controller and 8-Bit CRC
Generation Circuit
Internal
Bus
RAM
Buffer
(8 bytes)
(64 bits)
EPROM
MEMORY
(1024 bits)
EPROM
STATUS
(64 bits)
UDG−02054
Copyright 2003, Texas Instruments Incorporated
(TOP VIEW)
SDQ
VSS
1
VSS
3
2
VOLLow-level output voltage
V
t
Recovery time
(1)
s
SLUS526B − OCTOBER 2002 − REVISED OCTOBER 2003
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during
storage or handling to prevent electrostatic damage to the MOS gates.
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ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range unless otherwise noted
DC voltage applied to data, V
Low-level output current, I
ESD human body model Data to V
Operating free-air temperature range, T
Communication free-air temperature range, T
Storage temperature range, T
Lead temperature (soldering, 10 s) 260°C
(1)
Stresses beyond those listed under “absolute maximum ratings may cause permanent damage to the device. These are stress ratings only , a nd
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions is not implied.
Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
PU
OL
A
A(Comm)
stg
(1)
UNIT
−0.3 V to 7 V
40 mA
SS, VSS
Communication is specified by design −40°C to 85°C
to data 15 kV
−20°C to 70°C
−55°C to 125°C
DC ELECTRICAL CHARACTERISTICS
TA = −20°C to 70°C; V
PARAMETER TEST CONDITION MIN TYP MAX UNIT
I
DATA
V
OH
I
OL
V
IL
V
IH
V
PP
Supply current VPU = 5.5 V 20 µA
High-level output voltage Logic 1 V
Low-level output current (sink) VOL = 0.4 V , SDQ pin 4 mA
Low-level input voltage Logic 0 0.8 V
High-level input voltage Logic 1 2.2 V
Programming voltage 11.5 12 V
= 2.65 VDC to 5.5 VDC, all voltages relative to VSS
PU(min)
Logic 0, VPU = 5.5 V , IOL = 4 mA, SDQ pin 0.4
Logic 0, VPU = 2.65 V , IOL = 2 mA 0.4
PU
5.5
AC ELECTRICAL CHARACTERISTICS
TA = −20°C to 70°C; V
t
c
t
WSTRB
t
WDSU
t
WDH
rec
t
RSTRB
t
ODD
t
ODHO
t
RST
t
PPD
t
PP
t
EPROG
t
PSU
t
PREC
t
PRE
t
PFE
t
RSTREC
(1)
5-kΩ series resistor between SDQ pin and VPU. (See Figure 1)
(2)
t
WDH
Bit cycle time
Write start cycle
Write data setup
Write data hold
Read start cycle
Output data delay
Output data hold
Reset time
Presence pulse delay
Presence pulse
EPROM programming time 2500 µs
Program setup time 5 µs
Program recovery time 5 µs
Program rising-edge time 5 µs
Program falling-edge time 5 µs
must be less than tc to account for recovery.
= 2.65 VDC to 5.5 VDC, all voltages relative to VSS
PU(min)
PARAMETER TEST CONDITION MIN TYP MAX UNIT
(1)
(1)
(1)
(1) (2)
(1)
(1)
(1)
(1)
(1)
(1)
60 120 µs
t
WSTRB
60 t
For memory command only 5
t
RSTRB
17 60 µs
480 µs
15 60 µs
60 240 µs
480 µs
1 15 µs
15 µs
µs
c
1
1 13 µs
µ
13 µs
2
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I/O
DESCRIPTION
SLUS526B − OCTOBER 2002 − REVISED OCTOBER 2003
Terminal Functions
TERMINAL
NAME NO.
SDQ 1 I Data
VSS 2, 3 − Ground
FUNCTIONAL DESCRIPTION
General Operation
The block diagram on page 1 shows the relationships among the major control and memory sections of the
bq2022. The bq2022 has three main data components: a 64-bit factory programmed ROM, including 8-bit family
code, 48-bit identification number and 8-bit CRC value, 1024-bit EPROM, and EPROM STATUS bytes. Power
for read and write operations is derived from the DA TA pin. An internal capacitor stores energy while the signal
line is high and releases energy during the low times of the DA TA pin, until the pin returns high to replenish the
charge on the capacitor. A special manufacturer’s PROGRAM PROFILE BYTE can be read to determine the
programming profile required to program the part.
1024-Bits EPROM
Table 1 is a memory map of the 1024-bit EPROM section of the bq2022, configured as four pages of 32 bytes
each. The 8-byte RAM buffer are additional registers used when programming the memory. Data are first written
to the RAM buffer and then verified by reading an 8-bit CRC from the bq2022 that confirms proper receipt of
the data. If the buffer contents are correct, a programming command is issued and an 8-byte segment of data
is written into the selected address in memory. This process ensures data integrity when programming the
memory. The details for reading and programming the 1024-bit EPROM portion of the bq2022 are in the
Memory Function Commands section of this data sheet.
Table 1. 1024-Bit EPROM Data Memory Map
ADDRESS
(HEX)
0060−007F Page 3
0040−005F Page 2
0020−003F Page 1
0000−001F Page 0
PAGE
EPROM STATUS Memory
In addition to the programmable 1024-bits of memory, are 64 bits of status information contained in the EPROM
STATUS memory. The STATUS memory is accessible with separate commands. The STA TUS bits are EPROM
and are read or programmed to indicate various conditions to the software interrogating the bq2022. The first
byte of the STA TUS memory contains the write protect page bits, that inhibit programming of the corresponding
page in the 1024-bit main memory area if the appropriate write-protection bit is programmed. Once a bit has
been programmed in the write protect page byte, the entire 32-byte page that corresponds to that bit can no
longer be altered but may still be read. The write protect bits may be cleared by using the WRITE STATUS
command.
The next four bytes of the EPROM STATUS memory contain the page address redirection bytes. Bits in the
EPROM status bytes can indicate to the host what page is substituted for the page by the appropriate redirection
byte. The hardware of the bq2022 makes no decisions based on the contents of the page address redirection
bytes. This feature allows the user’s software to make a data patch to the EPROM by indicating that a particular
page or pages should be replaced with those indicated in the page address redirection bytes. The ones
complement of the new page address is written into the page address redirection byte that corresponds to the
original (replaced) page. If a page address redirection byte has an FFh value, the data in the main memory that
corresponds to that page are valid. If a page address redirection byte has some other hex value, the data in
the page corresponding to that redirection byte are invalid, and the valid data can now be found at the ones
3
SLUS526B − OCTOBER 2002 − REVISED OCTOBER 2003
complement of the page address indicated by the hex value stored in the associated page address redirection
byte. A value of FDh in the redirection byte for page 1, for example, indicates that the updated data are now
in page 2. The details for reading and programming the EPROM status memory portion of the bq2022 are given
in the Memory Function Commands section.
Table 2. EPROM Status Bytes
ADDRESS
(HEX)
Write protection bits
BIT0 − write protect page 0
00h
01h Redirection byte for page 0
02h Redirection byte for page 1
03h Redirection byte for page 2
04h Redirection byte for page 3
05h Reserved
06h Reserved
07h Factory programmed 00h
BIT1 − write protect page 1
BIT2 − write protect page 2
BIT3 − write protect page 3
BIT4 to 7 − bitmap of used pages
PAGE
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Error Checking
To validate the data transmitted from the bq2022, the host generates a CRC value from the data as they are
received. This generated value is compared to the CRC value transmitted by the bq2022. If the two CRC values
match, the transmission is error-free. The equivalent polynomial function of this CRC is X8 + X5 + X4 + 1. Details
are found in the CRC Generation Section of this data sheet.
Customizing the bq2022
The 64-bit ID identifies each bq2022. The 48-bit serial number is unique and programmed by Texas
Instruments. The default 8-bit family code is 09h; however, a different value can be reserved on an individual
customer basis. Contact your Texas Instruments sales representative for more information.
Bus Termination
Because the drive output of the bq2022 is an open-drain N-channel MOSFET, the host must provide a source
current or a 5-kΩ external pullup, as shown in the typical application circuit in Figure 1.
V
PU
1
SDQ
Communications
Controller
3 VSS VSS
2
CPU
HOSTbq2022
UDG−02055
Figure 1. Typical Applications Circuit
4
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SLUS526B − OCTOBER 2002 − REVISED OCTOBER 2003
Serial Communication
A host reads, programs, or checks the status of the bq2022 through the hierarchical command structure of the
SDQ interface. Figure 2 shows that the host must first issue a ROM command before the EPROM memory or
status can be read or modified. The ROM command either selects a specific device when multiple devices are
on the SDQ bus, or skips the selection process in single SDQ device applications.
Initialization ROM Command Sequence Memory/Status Command Sequence
Figure 2. General Command Sequence
Initialization
Initialization consists of two pulses, the RESET and the PRESENCE pulses. The host generates the RESET
pulse, while the bq2022 responds with the PRESENCE pulse. The host resets the bq2022 by driving the DATA
bus low for at least 480 µs. For more details, see the RESET section under SDQ Signaling.
ROM Commands
READ ROM
The READ ROM command sequence is the fastest sequence that allows the host to read the 8-bit family code
and 48-bit identification number. It is used if only one SDQ slave device is attached to the bus. The READ ROM
sequence starts with the host generating the RESET pulse of at least 480 µs. The bq2022 responds with a
PRESENCE pulse. Next, the host continues by issuing the READ ROM command, 33h, and then reads the
ROM and CRC byte using the READ signaling (see the READ and WRITE signals section) during the data
frame.
Reset
and
Presence
Signals
Read ROM (33h)
1100011
0
Family Code and Identification
Number (7 BYTES)
CRC (1 BYTE)
Figure 3. READ ROM Sequence
MATCH ROM
The MATCH ROM command, 55h, is used by the host to select a specific SDQ device when the family code
and identification number is known. The host issues the MATCH ROM command followed by the family code,
ROM number and the CRC byte. Only the device that matches the 64-bit ROM sequence is selected and
available to perform subsequent Memory/Status Function commands.
Reset
and
Presence
Signals
Match ROM (55h)
1100011
0
Family Code and Identification
Number (7 BYTES)
CRC (1 BYTE)
Figure 4. MATCH ROM Sequence
SEARCH ROM
The SEARCH ROM command, F0h, is used to obtain the 8-bit family code and the 48-bit identification number
and 8-bit CRC of any SDQ device when it is unknown. All devices on the bus are read under the SEARCH ROM
command with the use of a collision-detect and device-decode method. Figure 5 shows the SEARCH ROM
sequence started by the host, generating the RESET pulse of at least 480 µs. The bq2022 responds with a
PRESENCE pulse. The host then issues the command in the command frame by writing an F0h. During the
DATA READ of the SEARCH ROM sequence, each bit is transmitted three times. The bq2022 transmits the
bit followed by the complement of the bit. The host in turn retransmits the bit just read. Collision detection if
5
SLUS526B − OCTOBER 2002 − REVISED OCTOBER 2003
performed by comparing the bit and bit complement time-slots. If they are both zero, this indicates that a collision
has occurred, indicating multiple devices on the bus. The device decode is achieved in the third transmission
of the bit from the host back to the bq2022. If the bit transmitted by the host does not match the bit transmitted
by the bq2022, then the device with mismatch stops transmitting. Devices that did match, continue transmitting.
This process is continued until all bits of a single device are read. The SEARCH ROM command is reissued
and the process is repeated to read additional devices.
NOTE: If the number of devices on the bus is unknown, the SEARCH ROM command should
be used.
Reset
and
Presence
Signals
B = bit(n): nth bit transmitted by bq2022
C = bit(n): complement of nth bit transmitted by bq2022
H = bit(n): nth bit transmitted by host
00001111
Search ROM (F0h)
BIT0
Figure 5. SEARCH ROM Sequence
SKIP ROM
This SKIP ROM command, CCh, allows the host to access the memory/status functions without issuing the
64-bit ROM code sequence. The SKIP ROM command is directly followed by a memory/status functions
command. Because this command can cause bus collisions when multiple SDQ devices are on the same bus,
this command should be issued in single device applications.
Reset
and
Presence
Signals
1000110
Skip ROM (CCh)
Data Read
BITn BIT63
1
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Figure 6. SKIP ROM Sequence
Memory/Status Function Commands
Six memory/status function commands allow read and modification of the 1024-bit EPROM data memory or
the 64-bit EPROM status memory. There are two types of READ MEMORY command, plus the WRITE
MEMORY, READ STATUS and WRITE STATUS commands. Additionally, the part responds to a PROGRAM
PROFILE byte command. The bq2022 responds to memory/status function commands only after a part is
selected by a ROM command.
READ DATA MEMORY Commands
Two READ MEMORY commands are available on the bq2022. Both commands are used to read data from
the 1024-bit EPROM data field. They are the READ MEMORY/Page CRC and the READ MEMORY/Field CRC
commands. The READ MEMORY/Page CRC generates CRC at the end any 32 byte page boundary while the
READ MEMORY/Field CRC generates CRC when the end of the 1024-bit data memory is reached.
READ MEMORY/Page CRC
To read memory and generate the CRC at the 32-byte page boundaries of the bq2022, the ROM command is
followed by the READ MEMORY/Generate CRC command, C3h, followed by the address low byte and then
the address high byte.
6
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