1 Introduction
The LM5009AEVAL evaluation board provides the design engineer with a fully functional buck regulator,
employing the constant on-time (COT) operating principle. This evaluation board provides a 5V output
over an input range of 8V to 75V. The circuit delivers load currents to 150 mA, with current limit set at a
nominal 260 mA.
The board’s specification are:
• Input Voltage: 8V to 75V
• Output Voltage: 5V
• Maximum load current: 150 mA
• Minimum load current: 0A
• Current Limit: 260 mA (nominal)
• Measured Efficiency: 90.6% (VIN= 8V, I
• Nominal Switching Frequency: 130 kHz
• Size: 2.6 in. x 1.6 in.
User's Guide
SNVA392A–June 2009–Revised April 2013
AN-1955 LM5009A Evaluation Board
= 100 mA)
OUT
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Figure 1. Evaluation Board - Top Side
1
Copyright © 2009–2013, Texas Instruments Incorporated
tON =
V
IN
1.385 x 10
-10
x
R1
Theory of Operation
2 Theory of Operation
Refer to the evaluation board schematic in Figure 5. When the circuit is in regulation, the buck switch is on
each cycle for a time determined by R1 and VIN according to the equation:
The on-time of this evaluation board ranges from ≊4.85 µs at VIN = 8V, to ≊517 ns at VIN = 75V. The ontime varies inversely with VIN to maintain a nearly constant switching frequency. At the end of each ontime the Minimum Off-Timer ensures the buck switch is off for at least 300 ns. In normal operation, the offtime is much longer. During the off-time, the load current is supplied by the output capacitor (C2). When
the output voltage falls sufficiently that the voltage at FB is below 2.5V, the regulation comparator initiates
a new on-time period. For stable, fixed frequency operation, a minimum of 25 mV of ripple is required at
FB to switch the regulation comparator. The current limit threshold is ≊255 mA at Vin = 8V, and ≊286 mA
at Vin = 75V. Refer to the LM5009A 100V, 150 mA Constant On-Time Buck Switching Regulator
(SNVS608) data sheet for a more detailed block diagram, and a complete description of the various
functional blocks.
3 Board Layout and Probing
The pictorial in Figure 1 shows the placement of the circuit components. The following should be kept in
mind when the board is powered:
• When operating at high input voltage and high load current, forced air flow may be necessary.
• The LM5009A, and diode D1 may be hot to the touch when operating at high input voltage and high
load current.
• Use CAUTION when probing the circuit at high input voltages to prevent injury, as well as possible
damage to the circuit.
• At maximum load current, the wire size and length used to connect the load becomes important.
Ensure there is not a significant drop in the wires between this evaluation board and the load.
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(1)
4 Board Connection/Start-up
The input connections are made to the J1 connector. The load is connected to the J2 (OUT) and J3
(GND) terminals. Ensure the wires are adequately sized for the intended load current. Before start-up a
voltmeter should be connected to the input terminals, and to the output terminals. The load current should
be monitored with an ammeter or a current probe. It is recommended that the input voltage be increased
gradually to 8V, at which time the output voltage should be 5V. If the output voltage is correct with 8V at
VIN, then increase the input voltage as desired and proceed with evaluating the circuit. DO NOT EXCEED
75V AT VIN.
5 Output Ripple Control
The LM5009A requires a minimum of 25 mVp-p ripple at the FB pin, in phase with the switching waveform
at the SW pin, for proper operation. The required ripple can be supplied from ripple at V
feedback resistors as described in Option A below. Options B and C provide lower output ripple with one
or two additional components.
Option A) Lowest Cost Configuration: In this configuration R5 is installed in series with the output
capacitance (C2). Since ≥25 mVp-p are required at the FB pin, R5 must be chosen to generate ≥50 mVpp at V
for R5, the ripple at V
application can accept this ripple level, this is the most economical solution. The circuit is shown in
Figure 2 and Figure 8.
, knowing that the minimum ripple current in this circuit is ≊44 mAp-p at minimum VIN. Using 1.2Ω
OUT
ranges from ≊53 mVp-p to ≊132 mVp-p over the input voltage range. If the
OUT
, through the
OUT
2
AN-1955 LM5009A Evaluation Board SNVA392A–June 2009–Revised April 2013
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Cff
3 x t
ON (max)
(R3//R4)
t
R1
280k
0.1 PF
C5
LM5009A
C4
D1
L1
330 PH
V
OUT
GND
VIN
RT/SD
RCL
VCC
BST
SW
FB
RTN
V
IN
GND
SHUTDOWN
(TP1SD)
R6
8V to 75V
Input
0:
1 PF
C1
R2
715k
0.1 PF
C3
0.47 PF
R3
3.01k
R4
3.01k
R5
0.6:
C2
22 PF
5V
Cff
0.01 PF
R1
280k
0.1 PF
C5
LM5009A
C4
D1
L1
330 PH
V
OUT
GND
VIN
RT/SD
RCL
VCC
BST
SW
FB
RTN
V
IN
GND
SHUTDOWN
(TP1SD)
R6
8V to 75V
Input
0:
1 PF
C1
R2
715k
0.1 PF
C3
0.47 PF
R3
3.01k
R4
3.01k
R5
1.2:
C2
22 PF
5V
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Output Ripple Control
Figure 2. Lowest Cost Configuration
Option B) Intermediate Ripple Configuration: This configuration generates less ripple at V
option A above by the addition of one capacitor (Cff) across R3, as shown in Figure 3.
Figure 3. Intermediate Ripple Configuration
Since the output ripple is passed by Cff to the FB pin with little or no attenuation, R5 can be reduced so
the minimum ripple at V
where t
feedback resistors. The ripple at V
See Figure 8.
Option C) Minimum Ripple Configuration: To obtain minimum ripple at V
CA, and CB are added to generate the required ripple for the FB pin. In this configuration, the output ripple
is determined primarily by the characteristics of the output capacitance and the inductor’s ripple current.
See Figure 4.
The ripple voltage required by the FB pin is generated by RA, and CA since the SW pin switches from -1V
to VIN, and the right end of CA is a virtual ground. The values for RA and CA are chosen to generate a 50100 mVp-p triangle waveform at their junction. That triangle wave is then coupled to the FB pin through
CB. The following procedure is used to calculate values for RA, CA and CB:
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is the maximum on-time (at minimum VIN), and R3//R4 is the parallel equivalent of the
ON(max)
OUT
is ≊25 mVp-p. The minimum value for Cff is calculated from:
ranges from 26 mVp-p to 66 mVp-p over the input voltage range.
OUT
Copyright © 2009–2013, Texas Instruments Incorporated
, R5 is set to 0Ω, and RA,
OUT
OUT
than
(2)
3
R1
280k
0.1 PF
C5
LM5009A
C4
D1
L1
330 PH
V
OUT
GND
VIN
RT/SD
RCL
VCC
BST
SW
FB
RTN
V
IN
GND
SHUTDOWN
(TP1SD)
R6
8V to 75V
Input
0:
1 PF
C1
R2
715k
0.1 PF
C3
0.47 PF
R3
3.01k
RA
64.9k
R5
0:
C2
22 PF
5V
R4
3.01k
CA 4700 pF
CB
0.1 PF
RA x CA =
(8V - 4.78V) x 4.85 Ps
0.05V
= 3.12 x 10
-4
RA x CA =
(VIN ± VA) x t
ON
'V
Current Limit Off-Time
1) Calculate the voltage VA:
VA= V
OUT
where VSWis the absolute value of the voltage at the SW pin during the off-time (typically 0.6V), and VINis
the minimum input voltage. For this circuit, VAcalculates to 4.78V. This is the approximate DC voltage at
the RA/CA junction, and is used in the next equation.
2) Calculate the RA x CA product:
where tONis the maximum on-time (≊4.85 µs), VINis the minimum input voltage, and ΔV is the desired
ripple amplitude at the RA/CA junction, 50 mVp-p for this example.
RA and CA are then chosen from standard value components to satisfy the above product. Typically CA is
3000 to 10000 pF, and RA is 10 kΩ to 300 kΩ. CB is chosen large compared to CA, typically 0.1 µF. The
ripple at V
OUT
– (VSWx (1 – (V
))) (3)
OUT/VIN
is typically less than 10 mVp-p. See Figure 4 and Figure 8.
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(4)
(5)
Figure 4. Minimum Output Ripple Configuration
6 Current Limit Off-Time
When current limit is detected the on-time period is immediately terminated, and the off-time forced by the
LM5009A must be greater than the maximum normal off-time, which occurs at maximum input voltage.
The longer-than-normal off-time is necessary to allow the inductor current to decrease at least as much, if
not more, than the current increase which occurred during the on-time leading to the current limit
detection. The forced off-time is determined by the resistor at the RCL pin (R2), and is calculated from the
following:
T
= 10-5/(0.285 + (VFB/6.35 x 10-6x R2)) (6)
OFF
4
where VFBis the voltage at the FB pin at the time of the current limit detection. In this evaluation board, the
maximum normal off-time is approximately 7.2 µs (at 75V). Due to the 25% tolerance of the on-time, the
off-time tolerance is also 25%, yielding a maximum possible off-time of 9 µs. Allowing for the response
time of the current limit detection circuit (350 ns) the maximum off-time, for the purpose of this calculation,
is increased to 9.35 µs. This is increased an additional 25% to 11.7 µs to allow for the tolerances of the
above equation. Using the above equation, R2 calculates to 691 kΩ at VFB= 2.5V. A standard value 715
kΩ resistor is used.
AN-1955 LM5009A Evaluation Board SNVA392A–June 2009–Revised April 2013
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R1
280k
0.1 PF
C5
LM5009A
C4
D1
L1
330 PH
V
OUT
GND
VIN
RT/SD
RCL
VCC
BST
SW
FB
RTN
V
IN
GND
SHUTDOWN
(TP1SD)
R6
8V to 75V
Input
0:
1 PF
C1
R2
715k
0.1 PF
C3
0.47 PF
R3
3.01k
R4
3.01k
R5
1.2:
C2
22 PF
5V
V
OUT
SW
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7 Monitor The Inductor Current
The inductor’s current can be monitored or viewed on a scope with a current probe. Remove R6, and
install an appropriate current loop across the two large pads where R6 was located. In this way the
inductor’s ripple current and peak current can be accurately determined.
8 Scope Probe Adapters
Scope probe adapters are provided on this evaluation board for monitoring the waveform at the SW pin,
and at the circuit’s output (V
switching waveforms. The probe adapters are suitable for Tektronix P6137 or similar probes, with a 0.135”
diameter.
), without using the probe’s ground lead which can pick up noise from the
OUT
Monitor The Inductor Current
Figure 5. Complete Evaluation Board Schematic (As Supplied)
Item Description Mfg., Part Number Package Value
C1 Ceramic Capacitor TDK C3216X7R2A105M or Murata GRM31CR72A105KA01L 1206 1 µF, 100V
C2 Ceramic Capacitor TDK C3225X7R1C226M or Murata GRM32ER71C226KE18L 1210 22 µF, 16V
C3 Ceramic Capacitor TDK C1608X7R1C474M or TDK C1608X7R1C474K 0603 0.47 µF, 16V
C4 Ceramic Capacitor TDK C1608X7R1H103M 0603 0.01 µF, 50V
C5 Ceramic Capacitor TDK C2012X7R2A104M or Murata GRM188R72A104KA35D 0805 0.1 µF, 100V
D1 Schottky Diode Diodes Inc. DFLS1100 or Central Semi CMMSH1-100 Power DI123 100V, 1A
L1 Power Inductor Coiltronics DR73–331–R or TDK SLF10145T-331–MR54 10mm x 10mm 330 µH
R1 Resistor Vishay CRCW06032803F 0603 280k
R2 Resistor Vishay CRCW06037153F 0603 715k
R3, R4 Resistor Vishay CRCW06033011F 0603 3.01k
R5 Resistor Panasonic ERJ-3RQFIR2V 0603 1.2 ohms
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R6 Resistor Vishay CRCW08050000Z 0805 0Ω Jumper
U1 Switching Texas Instruments LM5009A VSSOP-8,
Regulator WSON-8
Table 1. Bill of Materials
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5
Circuit Performance
9 Circuit Performance
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Figure 6. Efficiency vs Load Current
Figure 7. Efficiency vs Input Voltage
Figure 8. Output Voltage Ripple
6
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Circuit Performance
Figure 9. Switching Frequency vs. Input Voltage
Figure 10. Current Limit vs Input Voltage
Figure 11. Line Regulation
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Circuit Performance
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Figure 12. Load Regulation
8
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10 Typical Waveforms
Trace 1 = SW Pin
Trace 3 = V
Trace 4 = Inductor Current
Vin = 12V, Iout = 100 mA
OUT
Typical Waveforms
Figure 13. Continuous Conduction Mode
Trace 1 = SW Pin
Trace 3 = V
Trace 4 = Inductor Current
Vin = 12V, Iout = 0 mA
Trace 1 = SW Pin
Trace 3 = V
Trace 4 = Inductor Current
Vin = 12V, Iout = 0 mA
OUT
OUT
Figure 14. Discontinuous Conduction Mode
Figure 15. Discontinuous Conduction Mode
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PC Board Layout
11 PC Board Layout
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Figure 16. Board Silkscreen
10
AN-1955 LM5009A Evaluation Board SNVA392A–June 2009–Revised April 2013
Figure 17. Board Top Layer
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PC Board Layout
Figure 18. Board Bottom Layer (Viewed from Top)
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11
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