This board is designed to allow the evaluation of the LP38853S-ADJ Voltage Regulator. Each board is
assembled and tested in the factory. This evaluation board has the TO-263 7-lead package mounted, and
the output voltage is set to 1.20V.
2General Description
The LP38853 is a dual-rail adjustable LDO linear regulator capable of suppling up to 3A of output current,
and incorporates an Enable function as well as a Soft-Start function.
The device has been designed to work with 10 µF input and output ceramic capacitors, and 1µF bias
capacitor. Footprints areas for CINand C
3Operation
User's Guide
SNVA178C–November 2006–Revised April 2013
AN-1504 LP38853S-ADJ Evaluation Board
will allow for a variety of sizes.
OUT
The input voltage, applied between VINand GND, should be at least 1.0V greater than V
than the applied V
The bias voltage, applied between V
no more than the maximum of 5.5V.
Loads can be connected to V
V
and VINtest points are provided on the board to allow accurate measurements directly onto the input
OUT
and output pins of the device, eliminating any voltage drop on the PCB traces or connecting wires to the
load.
4Setting V
OUT
The output voltage is set using the external resistive divider R1 and R2. The output voltage is given by the
formula:
V
= V
OUT
It is recommended that the values selected for R1 and R2 are such that the parallel value is less than 10
kΩ. This is to prevent internal parasitic capacitances on the ADJ pin from interfering with the FZpole set
by R1 and CFF.
The LP38853S-ADJ Evaluation board is assembled with a 1.40 kΩ ±1% resistor for R1, and a 1.00 kΩ
±1% resistor for R2. This sets V
5Selecting C
A capacitor placed across the gain resistor R1 will provide additional phase margin to improve load
transient response of the device. This capacitor, CFF, in parallel with R1, will form a zero in the loop
response given by the formula:
FZ= (1 / (2 × π × CFF× R1) )(2)
The value for CFFshould be selected to set a zero frequency (FZ) between 10 kHz and 15 kHz using the
formula:
CFF= 1 / (2 × π × FZ× R1)(3)
and no greater
voltage.
BIAS
and GND should be above the minimum bias voltage of 3.0V, and
BIAS
with reference to GND.
OUT
× (1 + (R1 / R2))(1)
ADJ
to 1.20V.
OUT
FF
OUT
All trademarks are the property of their respective owners.
SNVA178C–November 2006–Revised April 2013AN-1504 LP38853S-ADJ Evaluation Board
The closest standard 10% value is usually adequate for CFF.
The LP38853-ADJ Evaluation board is assembled with a 0.01 μF capacitor for CFF. This sets FZto
approximately 11.4 kHz.
Figure 1. 10mA to 3A Load Transient ResponseFigure 2. 1A to 3A Load Transient Response
www.ti.com
6Enable Function
ON/OFF control is provided by supplying a logic level signal to the Enable pin. A minimum VENvalue of
1.3V is typically required at this pin to enable the LDO output. The LDO output will be shutdown when the
VENvalue is typically 1.0V or less. The VENthreshold incorporates approximately 100mV of hysteresis.
In applications where the LP38853 is operated continuously the Enable pin can be connected directly to
V
, or left open. The Enable pin has a 200 kΩ internal resistor to V
BIAS
care should be taken to minimize any capacitance on the Enable pin, as any capacitance will introduce an
RC delay time on the Enable function.
. If the Enable pin is left open,
BIAS
2
AN-1504 LP38853S-ADJ Evaluation BoardSNVA178C–November 2006–Revised April 2013
will rise at an RC rate defined by the internal resistance of the SS pin (rSS), and the external capacitor
REF
(CSS) connected to the SS pin. This allows the output voltage to rise in a controlled manner until steadystate regulation is achieved. Typically, five time constants are recommended to assure that the output
voltage is sufficiently close to the final steady-state value. During the soft-start time the output current can
rise to the built-in current limit.
The LP38853S-ADJ Evaluation board is assembled with a 0.01 μF capacitor for CSS. This sets the softstart time to approximately 750 μs.
Soft-Start Function
8Power Dissipation
The TO-263 package alone has a junction to ambient thermal resistance (θJA) rating of 60°C/W. When
mounted on the LP38853S evaluation board the θJArating is approximately 40°C/W.
Although there is only approximately 0.30 square inches of 1 ounce copper area immediately under the
tab, the top copper surface area is extended to additional copper area on the bottom of the board by nine
thermal vias.
With the 40°C/W thermal rating the LP38853S-ADJ evaluation board will dissipate a maximum of 2.5W
with TA= 25°C.
Figure 4. V
Soft-Start
OUT
Figure 5. Maximum Power Dissipation vs Ambient Temperature
SNVA178C–November 2006–Revised April 2013AN-1504 LP38853S-ADJ Evaluation Board
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