Texas instruments AM3517, AM3505 User Manual
AM3517, AM3505
www.ti.com
SPRS550B–OCTOBER 2009–REVISED JULY 2010
AM3517/05 ARM Microprocessor
Check for Samples: AM3517, AM3505
1 AM3517/05 ARM Microprocessor
1.1 Features
1234
• AM3517/05 ARM Microprocessor:
– Software Compatible with OMAPTM3
Processors
– MPU Subsystem
• 600-MHz ARM CortexTM-A8 Core
• NEONTMSIMD Coprocessor and Vector
floating point (FP) co-processor
– Memory Interfaces:
• 16/32- bit mDDR/DDR2 Interface with 1
GByte total addressable space
• General Purpose Memory Interface
supporting 16-bit Wide Multiplexed
Address/Data bus
• 64 K-Byte SRAM
• 3 Removable Media Interfaces
[MMC/SD/SDIO]
– IO Voltage:
• mDDR/DDR2 IOs: 1.8V
• Other IOs: 1.8V and 3.3V
– Core Voltage: 1.2V
– Commercial and Industrial Temperature
Grade
• Display subsystem
– Parallel Digital Output
– Up to 24-Bit RGB
– Supports Up to 2 LCD Panels
(operating restrictions apply) – Support for Remote Frame Buffer Interface
– 16-bit Video Input Port capable of capturing
HD video – Two 10-bit Digital-to-Analog Converters
– HD resolution Display Subsystem
– Serial Communication
• High-End CAN Controller
• 10/100 Mbit Ethernet MAC
• USB OTG subsystem with standard
– Rotation 90, 180, and 270 degrees
– Resize Images From 1/4x to 8x
DP/DM interface [HS/FS/LS] – Color Space Converter
• Multiport USB Host Subsystem – 8-bit Alpha Blending
[HS/FS/LS]
• Video Processing Front End (VPFE) 16-bit
– 12-pin ULPI or 6/4/3-pin Serial Video Input Port
Interface
• Four Master/Slave Multichannel Serial
Port Interface (McSPI) Ports
• Five Multichannel Buffered Serial Ports
– RAW Data Interface
– 75-MHz Maximum Pixel Clock
– Supports REC656/CCIR656 Standard
– Supports YCbCr422 Format (8-bit or 16-bit
– 512-Byte Transmit/Receive Buffer
(McBSP1/3/4/5)
– 5K-Byte Transmit/Receive Buffer
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2POWERVR SGX is a trademark of Imagination Technologies Ltd.
3 is a registered trademark of ~#IMPLIED.
4All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testingof all parameters.
– Generates Optical Black Clamping Signals
(McBSP2)
– SIDETONE Core Support (McBSP2 and
3 Only) For Filter, Gain, and Mix
Operations
– 128-Channel Transmit/Receive Mode
– Direct Interface to I2S and PCM Device
and TDM Buses
• HDQ/1-Wire Interface
• 4 UARTs (One with Infrared Data
Association [IrDA] and Consumer Infrared
[CIR] Modes)
• 3 Master/Slave High-Speed
Inter-Integrated Circuit (I2C) Controllers
• 12 32-bit General Purpose Timers
• 1 32-bit Watchdog Timer
• 1 32-bit 32-kHz Sync Timer
• Up to 186 General-Purpose I/O (GPIO)
Pins
(RFBI) LCD Panels
(DACs) Supporting
• Composite NTSC/PAL Video
• Luma/Chroma Separate Video (S-Video)
With Discrete Horizontal and Vertical Sync
Signals)
Copyright © 2009–2010, Texas Instruments Incorporated
AM3517, AM3505
SPRS550B–OCTOBER 2009–REVISED JULY 2010
– Built-in Digital Clamping and Black Level – ARM Instructions - Little Endian
Compensation
– 10-bit to 8-bit A-law Compression Hardware
– Supports up to 16K Pixels (Image Size) in
Horizontal and Vertical Directions
• System Direct Memory Access (sDMA)
Controller (32 Logical Channels With
Configurable Priority)
• Comprehensive Power, Reset and Clock
Management
• ARM CortexTM-A8 Memory Architecture
– ARMv7 Architecture
• TrustZone
®
• Thumb®-2
– ARM Data – Configurable
• SDRC Memory Controller
– 16/32-bit Memory Controller With 1G-Byte
Total Address Space
– Double Data Rate (DDR2) SDRAM, mobile
Double Data Rate (mDDR)SDRAM
– SDRAM Memory Scheduler (SMS) and
Rotation Engine
• General Purpose Memory Controller (GPMC)
– 16-bit Wide Multiplexed Address/Data Bus
– Up to 8 Chip Select Pins With 128M-Byte
Address Space per Chip Select Pin
– Glueless Interface to NOR Flash, NAND
• MMU Enhancements Flash (With ECC Hamming Code
– In-Order, Dual-Issue, Superscalar
Calculation), SRAM and Pseudo-SRAM
Microprocessor Core – Flexible Asynchronous Protocol Control for
– NEONTMMultimedia Architecture
– Over 2x Performance of ARMv6 SIMD
– Supports Both Integer and Floating Point
SIMD
– Jazelle®RCT Execution Environment
Architecture
– Dynamic Branch Prediction with Branch
Target Address Cache, Global history buffer
Interface to Custom Logic (FPGA, CPLD,
ASICs, etc.)
– Nonmultiplexed Address/Data Mode (Limited
2K-Byte Address Space)
• Test Interfaces
– IEEE-1149.1 (JTAG) Boundary-Scan
Compatible
– Embedded Trace Macro Interface (ETM)
and 8 entry return stack • 65-nm CMOS technology
– Embedded Trace Macrocell [ETM] support • Packages:
for Non_invasive Debug
– 491-pin BGA (17x17, 0.65mm pitch)
– 16K-Byte instruction Cache (4-Way set- [ZCN suffix]
associative) with via channel array technology
– 16K-Byte Data Cache (4-Way – 484-pin PBGA (23x23, 1mm pitch)
Set-Associative) [ZER suffix]
– 256K-Byte L2 Cache • Applications:
• POWERVR SGX™ Graphics Accelerator – Single Board Computers
– Tile Based Architecture Delivering up to 10 – Industrial and Home Automation
MPoly/sec
– Universal Scalable Shader Engine:
Multi-threaded Engine Incorporating Pixel
and Vertex Shader Functionality
– Industry Standard API Support: OpenGLES
1.1 and 2.0, OpenVG1.0
– Fine Grained Task Switching, Load
Balancing, and Power Management
– Programmable, High-Quality Image
Anti-Aliasing
• Endianess
– Digital Signage
– Point of Service
– Portable Media Player
– Portable Industrial
– Transportation
– Navigation
– Smart White Goods
– Digital TV
– Digital Video Camera
– Gaming
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1.2 Description
AM3517/05 high-performance, industrial applications processors with video, image, and graphics
processing sufficient to support the following:
• Single Board Computers
• Home and Industrial automation
• Digital Signage
The device supports high-level operating systems (OSs), such as:
• Linux
• Windows CE
The following subsystems are part of the device:
• Microprocessor unit (MPU) subsystem based on the ARM Cortex-A8 microprocessor
• POWERVR SGX™ Graphics Accelerator (AM3517 Device only) Subsystem for 3D graphics
acceleration to support display and gaming effects (AM3517 only)
• Display subsystem with several features for multiple concurrent image manipulation, and a
programmable interface supporting a wide variety of displays. The display subsystem also supports
NTSC/PAL video out.
• High performance interconnects provide high-bandwidth data transfers for multiple initiators to the
internal and external memory controllers and to on-chip peripherals. The device also offers a
comprehensive clock-management scheme.
SPRS550B–OCTOBER 2009–REVISED JULY 2010
AM3517/05 devices are available in a 491-pin BGA package and a 484-pin PBGA package.
This AM3517/05 data manual presents the electrical and mechanical specifications for the AM3517/05
ARM Microprocessor.
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64
64
Async
64
64
L2$
256K
MPU
Subsystem
ARM Cortex-
A8
TM
Core
16K/16K L1$
POWERVR
SGX
Graphics
Accelerator
( only)
TM
AM3517
32
32
32
Channel
System
DMA
3232
Analog
DAC
LCD Panel
CVBS
or
S-Video
Dual Output 3-Layer
Display Processor
(1xGraphics, 2xVideo)
Temporal Dithering
SDTV → QCIF Support
32
HS/FS/
LS
USB
Host
32
L3 Interconnect Network-Hierarchial, Performance, and Power Driven
64K
On-Chip
RAM
32
132K
On-Chip
BOOT
ROM
SMS:
SDRAM
Memory
Scheduler/
Rotation
64
EMIF
Controller
L4 Interconnect
32
System
Controls
PRCM
External
Peripherals
Interfaces
Peripherals:
4xUART, 3xHigh-Speed I2C,
5xMcBSP
(2x with Sidetone/Audio Buffer)
4xMcSPI, 186xGPIO,
3xHigh-Speed MMC/SDIO,
HDQ/1 Wire,
12xGPTimers, 1xWDT,
32K Sync Timer
GPMC:
General
Purpose
Memory
Controller
32
Emulation
Debug: ETM, JTAG
External
DDR2/
mDDR
32
SPRS550-006
Parallel
HECC
EMAC
VPFE
USB PHY
USB OTG
Controller
DDR PHY
NAND/NOR/
FLASH,
SRAM
USB transceivers /
device ports [3]
AM3517, AM3505
SPRS550B–OCTOBER 2009–REVISED JULY 2010
1.3 Functional Block Diagram
Figure 1-1 shows the functional block diagram of the AM3517/05 ARM Microprocessor.
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4 AM3517/05 ARM Microprocessor Copyright © 2009–2010, Texas Instruments Incorporated
Figure 1-1. AM3517/05 Functional Block Diagram
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1.4 ZCN and ZER Package Differences
Table 1-1 shows the ZER and ZCN package differences on the device.
Table 1-1. ZCN and ZER Package Differences
FEATURE ZCN PACKAGE ZER PACKAGE
Pin Assignments For ZCN package pin assignments, see For ZER package pin assignments, see
Video Interfaces TV signals available TV signals not available
SPRS550B–OCTOBER 2009–REVISED JULY 2010
Terminal Description Terminal Description
Copyright © 2009–2010, Texas Instruments Incorporated AM3517/05 ARM Microprocessor 5
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SPRS550B–OCTOBER 2009–REVISED JULY 2010
1 AM3517/05 ARM Microprocessor .................... 1
1.1 Features .............................................. 1 4.4 DPLL Specifications ................................ 97
1.2 Description ........................................... 3
1.3 Functional Block Diagram ............................ 4
1.4 ZCN and ZER Package Differences ................. 5
Revision History .............................................. 7
2 TERMINAL DESCRIPTION ............................. 9
2.1 Pin Assignments ..................................... 9
2.2 Ball Characteristics ................................. 18
2.3 Multiplexing Characteristics ........................ 52
2.4 Signal Description .................................. 58
3 ELECTRICAL CHARACTERISTICS ................. 81
3.1 Absolute Maximum Ratings ........................ 81
3.2 Recommended Operating Conditions .............. 83
3.3 DC Electrical Characteristics ....................... 85
3.4 Core Voltage Decoupling ........................... 86
3.5 Power-up and Power-down ......................... 88
4 CLOCK SPECIFICATIONS ........................... 91
4.1 Oscillator ............................................ 93
4.2 Input Clock Specifications .......................... 93
4.3 Output Clock Specifications ........................ 95
5 VIDEO DAC SPECIFICATIONS .................... 100
5.1 Interface Description .............................. 101
5.2 Electrical Specifications Over Recommended
Operating Conditions .............................. 102
5.3 Analog Supply (vdda_dac) Noise Requirements
..................................................... 104
5.4 External Component Value Choice ............... 105
6 TIMING REQUIREMENTS AND SWITCHING
CHARACTERISTICS ................................. 106
6.1 Timing Test Conditions ............................ 106
6.2 Interface Clock Specifications ..................... 106
6.3 Timing Parameters ................................ 107
6.4 External Memory Interfaces ....................... 108
6.5 Video Interfaces ................................... 150
6.6 Serial Communications Interfaces ................ 155
6.7 Removable Media Interfaces ...................... 196
6.8 Test Interfaces .................................... 210
7 PACKAGE CHARACTERISTICS ................... 214
7.1 Package Thermal Resistance ..................... 214
7.2 Device Support .................................... 214
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This data manual revision history table highlights the technical changes made to the SPRS550A
device-specific data manual to make it an SPRS550B revision.
Scope: Applicable updates to the AM35x device family, which is now in the Production Data (PD) stage
of development, have been incorporated.
SPRS550B–OCTOBER 2009–REVISED JULY 2010
Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
SEE ADDITIONS/MODIFICATIONS/DELETIONS
Global
Section 2 Updated/Changed the following:
• Changed all fsusb1x_x signals to mm_fsusbx_x
• Removed all instances of dssvenc656_datax
• Changed ARM11 to ARM CortexTM-A8
• Changed all instances of "trunk" to "trunc"
• Added following signals to Ball Characteristics (ZER Package)
– hw_dbg[17:0]
– i2c3_scl
– i2c3_sda
– uart1_cts
– uart1_rts
– dss_data4
– dss_data3
– dss_data2
– dss_data1
– dss_data5
– uart3_rx_irrx
– uart3_tx_irtx
– uart1_tx
– uart1_rx
– uart3_rts_sd
– uart1_cts
– mcbsp3_clkx
– mcbsp3_dr
– mcbsp3_dx
– mcbsp3_fsx
– mmc2_dir_dat0
– mmc2_dir_dat1
– mmc2_dir_cmd
– mmc2_clkin
– sdrc_cke0_safe
– mmc2_dir_dat2
– mmc2_dir_dat3
– mcspi4_clk
– mcbsp3_dx
– mcbsp3_dr
– mcbsp3_fsx
– uart2_tx
– mcbsp3_clkx
– gpt11_pwm_evt
– gpio_146
– uart3_tx_irtx
• Table 2-3, Multiplexing Characteristics
– Added note to the usb0_dm and usb0_dp signals
– Updated uart3_cts_crtx to uart3_cts_rctx
– Added safe mode to uart3_rx_irrx signal
Copyright © 2009–2010, Texas Instruments Incorporated Contents 7
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SEE ADDITIONS/MODIFICATIONS/DELETIONS
Section 3 Updated/Changed the following:
• Deleted "Minimum pass level for HBM is 2 kV"
• Absolute Maximum Ratings Over Operating Junction Temperature Range
– Updated footnotes 2 and 3. Deleted footnote 5.
• Table 3-4, DC Electrical Characteristics
– Changed VHHSHV to VDDSHV.
– Updated VILVDDSHV = 3.3V value from 0.6 to 0.8
– Updated VILVDDSHV = 1.8V value from .3 x VDDSHV to .35 x VDDSHV
– Removed II(Input current)
– Added "Normal Mode" and High-Speed Mode" values to Transition Time (tT) parameter
Section 6 Added RMII Timing Conditions table to EMAC Electrical Data section.
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2 TERMINAL DESCRIPTION
2.1 Pin Assignments
2.1.1 Pin Map (Top View)
The following illustrations show the top and bottom views of the 484-pin [ZER] and 491-pin [ZCN] package
pin assignments in four quadrants (A, B, C, and D).
Note: A pin with an "NC" designator indicates No Connection. For proper device operation, these pins
must be left unconnected.
SPRS550B–OCTOBER 2009–REVISED JULY 2010
Copyright © 2009–2010, Texas Instruments Incorporated TERMINAL DESCRIPTION 9
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N
P
R
T
U
V
1415162223
N
P
W
Y
2425
AA
AB
T
U
R
21 17181920
NC
VDDS
VSS
VSS
NC
SYS_
CLKOUT1
VDDS_
DPLL_MPU
_USBHOST
VDDSHV
1516
17
181920
2122
23
AC
24
25
AD
AE VSS
V
W
Y
AA
AB
VSS
14
AC
AD
AE
VDDSHV
VDDSHV VDDSHV
VSS VSSVSS
VDDS_DPLL_
PER_CORE
VDDSHV VSS
VDDSHV VDDSHV VSSVSS VSSVSS VSS
VDD_CORE VDD_CORE
VSSVSS VSS
VDD_CORE
VSS
VDD_COREVDD_CORE
VSS
VDD_CORE
VSSVSS
VDD_COREVDD_CORE
VDDSHV
VDDSHVVDDSHV
VDDS
DSS_ACBIAS DSS_PCLK
ETK_D15 ETK_D12 ETK_D8
ETK_D5 ETK_CTL
MCSPI2_
CS1
MCSPI1_
CS3
MCSPI1_
CS2
MCSPI1_
CLK
DSS_DATA1 DSS_DATA0
DSS_VSYNC DSS_HSYNC
ETK_D13 ETK_D9 ETK_D6 ETK_D0
ETK_CLK
MCSPI2_
CLK
MCSPI1_
SIMO
MCSPI1_
CS1
DSS_DATA4 DSS_DATA3
DSS_DATA2
ETK_D14 ETK_D10 ETK_D1
MCSPI2_
SIMO
MCSPI1_
SOMI
DSS_DATA6
DSS_DATA5
ETK_D11
ETK_D7
ETK_D2 MCSPI2_
SOMI
MCSPI1_CS0
DSS_DATA9 DSS_DATA8
DSS_DATA7
UART1_TX ETK_D3 MCSPI2_
CS0
DSS_DATA13 DSS_DATA12
DSS_DATA11
DSS_DATA10 UART1_CTS UART1_RTS
ETK_D4
DSS_DATA18 DSS_DATA17 DSS_DATA16
DSS_DATA15 DSS_DATA14
UART1_RX
DSS_DATA20 DSS_DATA19
JTAG_TCK JTAG_NTRST
DSS_
DATA23
DSS_
DATA22
DSS_
DATA21
JTAG_EMU0
JTAG_TDO JTAG_TDI
JTAG_TMS
_TMSC
JTAG_RTCK
MCBSP1_
CLKR
JTAG_
EMU1
MCBSP_
CLKS
MCBSP1_
FSX
MCBSP1_DRMCBSP1_
DX
MCBSP1_
FSR
MCBSP1_
CLKX
M
M
SYS_
CLKOUT2
VSS VSSVDD_CORE
SYS_
CLKREQ
VSS VSS
AM3517, AM3505
SPRS550B–OCTOBER 2009–REVISED JULY 2010
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Figure 2-1. ZCN Pin Map [Quadrant A]
10 TERMINAL DESCRIPTION Copyright © 2009–2010, Texas Instruments Incorporated
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P
R
Y
AA
AB
AC
AD
U
V
W
T
10 9 8
P
R
T
U
V
W
Y
AA
AB
AC
AD
CCDC_
PCLK
13
12 11
6 5
M
N
4
3
7
M
N
2 1
CCDC_
FIELD
CCDC_
VD
CCDC_
DATA0
CCDC_
DATA3
RMII_MDIO
_CLK
RMII_TXD0
RMII_TXEN
MMC1_
DAT1
MMC1_
DAT6
MMC2_CLK
MMC2_
DAT2
MMC2_
DAT6
VSS
VSS VSS
VSS
VSS
VSS
VSS
VSS
VDDSHV
VSS
VSS
VSS
VSS
VSS
VSS VSS VSS VSS VSS VDDSHV
VDDSHV
VDDSHV
VDDSHV
VDDSHV
GPMC_
NCS5
GPMC_
NCS4
GPMC_
NCS3
GPMC_
NCS2
GPMC_
NCS7
GPMC_
NCS6
GPMC_CLK
UART3_CTS
_RCTX
UART3_RTS
_SD
UART3_RX
_IRRX
UART3_TX
_IRTX
GPMC_NADV
_ALE
GPMC_
NBE1
GPMC_
WAIT3
I2C2_SCL
SYS_NIRQ
SYS_
BOOT1
SYS_
BOOT4
SYS_
BOOT6
SYS_
BOOT7
SYS_
BOOT5
SYS_
BOOT2
SYS
_NRES
PWRON
SYS_
BOOT8
13
12 11
10 9 8
7
6 5
4
3
AE
2 1
AE
CCDC_
HD
VSS
CCDC_
WEN
CCDC_
DATA1
CCDC_
DATA4
RMII_MDIO
_DATA
RMII_TXD1
RMII_50MHZ
_CLK
MMC1_
DAT2
MMC1_
DAT7
MMC2_
CMD
MMC2_
DAT3
MMC2_
DAT7
MMC2_
DAT1
MMC2_
DAT5
MMC2_
DAT0
MMC2_
DAT4
VDDS_SRAM
_MPU
CAP_VDD_
SRAM_MPU
VDDSHV
VDDSHV
VDDSHV
MMC1_
DAT0
MMC1_
DAT5
MMC1_
CMD
MMC1_
DAT4
MMC1_CLK
MMC1_
DAT3
VDDSHV
VDDSHV
VDDSHV
VDDS
VDD_CORE VDD_CORE
VDD_CORE
VDD_CORE
VSS
VSS
VSS
VSS
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VSS VSS
VSS VSSVSS VSS
VSS VSS
CCDC_
DATA2
CCDC_
DATA7
CCDC_
DATA6
CCDC_
DATA5
VDDSHV
VDDSHV
VDDSHV
VDDSHV
RMII_RXER
RMII_CRS_
DV
RMII_RXD1
RMII_RXD0
VDDSHV
VDDSHV
VDDSHV
I2C3_SDA
I2C1_SDA
I2C3_SCL
I2C1_SCL
SYS_
BOOT3
SYS
_NRES
WARM
SYS_
BOOT0
I2C2_SDA
HECC1_
TXD
HECC1_
RXD
GPMC_
NWP
GPMC_
WAIT0
GPMC_
WAIT1
GPMC_
WAIT2
VDDS
GPMC_NBE0
_CLE
GPMC_
NWE
GPMC_
NOE
RESERVED
RESERVED
AM3517, AM3505
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SPRS550B–OCTOBER 2009–REVISED JULY 2010
Figure 2-2. ZCN Pin Map [Quadrant B]
Copyright © 2009–2010, Texas Instruments Incorporated TERMINAL DESCRIPTION 11
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L
K
J
H
G
F
E
22
23
15
16
1718
19
2021
22
23
E
D
D
C
C
24
25
2425
B B
A
A
15
16
17
181920
L
K
J
H
G
F
21
14
14
VSS
HDQ_
SIO
NC
NC
NC
VDDSHV
VDD_CORE
VSS
VSS
VSS
NC
NC
TV_
OUT1
VSS
VSS
VSS
VDD_CORE
VDD_CORE
VDD_CORE
VDD_COREVDD_CORE
VDDSHV
VSS VSS
VDDSHV
VDDS
VDDS
VDDS
VDDS VDDS
NC
UART2_RTS
SYS_
XTALIN
SYS_32K
VSSOSC
SYS_
XTALOUT
TV_
OUT2
TV_VFB2
VSSA_DAC VDDA_DAC
TV_VFB1
VSS
VSS
USB0_ID
USB0_DP
USB0_
DRVVBUS
MCBSP2_
FSX
MCBSP2_
CLKX
MCBSP2_DR
VSS
MCBSP3_
CLKX
MCBSP3_DX
MCBSP3_
DR
MCBSP2_
DX
UART2
_TX
MCBSP4_
DR
MCBSP4_
CLKX
MCBSP3_
FSX
UART2_RX
VDDA3P3V
_USBPHY
VDDA1P8V
_USBPHY
CAP_
VDDA1P2LDO
_USBPHY
MCBSP4_
FSX
SDRC_
D1
SDRC_
DQS0N
SDRC_
STRBEN0
SDRC_
STRBEN
_DLY0
SDRC_
DQS1N
SDRC_
D14
SDRC_
D15
SDRC_
NCS1
SDRC_
NWE
SDRC_
DM1
SDRC_
D13
SDRC_
DQS1P
SDRC_
D8
SDRC_
D7
SDRC_
DQS0P
SDRC_
D0
MCBSP4_
DX
SDRC_DM0 SDRC_D3 SDRC_D6
SDRC_D10
SDRC_D12 SDRC_NRAS
SDRC_CKE0
SDRC_NCAS
VREFSSTL
SDRC_D2 SDRC_D5
SDRC_D9
SDRC_D11
SDRC_D4
VDDS_SRAM
_CORE_BG
CAP_VDD_
SRAM_CORE
USB0_DM
UART2_CTS
USB0_
VBUS
VDDSHV
VDDSOSC
NC
NC
TV_VREF
AM3517, AM3505
SPRS550B–OCTOBER 2009–REVISED JULY 2010
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Figure 2-3. ZCN Pin Map [Quadrant C]
12 TERMINAL DESCRIPTION Copyright © 2009–2010, Texas Instruments Incorporated
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L
K
J
H
G
F
E
13
12 11
6 5
13
12 11
10 9 8
7
6 5
L
K
E
D
D
CC
4
3
4
3
BB
10 9 8
H
G
F
J
7
2 1
2 1
VSS
VSS
VSS
AA
VSS
VSS
VSS VSS
VDD_CORE VDD_CORE
VDD_CORE
VDD_CORE
VDDSHV VDDSHV VDDSHV
VDDSHVVSSVSS
VDDSVSS
VDDS
VDDS
GPMC_
NCS0
GPMC_
NCS1
GPMC_D12
GPMC_D13 GPMC_D14
GPMC_D15
GPMC_D11GPMC_D10
GPMC_D8 GPMC_D9
GPMC_D7
GPMC_D6
GPMC_D5
GPMC_D4
GPMC_D3GPMC_D1 GPMC_D2GPMC_D0
GPMC_A9GPMC_A8
GPMC_A7
GPMC_A6
GPMC_A5
GPMC_A4
GPMC_A3GPMC_A2
GPMC_A1
SDRC_DM3
VSS
VSS
VDD_CORE VDD_CORE
VSS
VSS
VDD_CORE VDD_CORE
VDDSVDDS
VDDS VDDS
VDDS
VDDS
SDRC_BA0
SDRC_CLK
SDRC_
NCLK
SDRC_BA1
SDRC_BA2
SDRC_
NCS0
DDR_
PADREF
SDRC_A0
SDRC_A1
SDRC_A2
SDRC_A3
SDRC_
A4
SDRC_
A9
SDRC_A8
SDRC_A7
SDRC_A6
SDRC_A5
SDRC_A11
SDRC_
A10
SDRC_
A12
SDRC_
A13
SDRC_
ODT
SDRC_A14
SDRC_DM2
SDRC_D19
SDRC_D18
SDRC_
D17
SDRC_
D16
GPMC_A10
SDRC_D21
SDRC_D20
SDRC_
DQS2N
SDRC_
DQS2P
SDRC_
STRBEN1
SDRC_D22
SDRC_D23
SDRC_24
SDRC_
STRBEN
_DLY1
SDRC_D25
SDRC_D26
SDRC_D27
SCRC_D29
SDRC_D28
SDRC_
DQS3N
SDRC_
DQS3P
SDRC_D30
SDRC_D31
AM3517, AM3505
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SPRS550B–OCTOBER 2009–REVISED JULY 2010
Figure 2-4. ZCN Pin Map [Quadrant D]
Copyright © 2009–2010, Texas Instruments Incorporated TERMINAL DESCRIPTION 13
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12
13
14
15
16
17
18
19
VSS
VSS
MMC2_DAT4
VDDS_DPLL_
MPU_
USBHOST
LK
J
HGF
ED
C
20
B
A
21
22
VSS
VDDS_
SRAM_MPU
VSS VDDS
VSS
VDD_CORE
VSS
VDD_CORE
VSS
VSS
VDD_CORE
VSS
VDD_COREVDD_CORE
VSS
VSSVSS
VSS
VDDSHVVSS
VDDSHV
DSS_PCLK
UART1_TX ETK_D8 ETK_D10 ETK_D1
ETK_CLK
MCSPI2_
SOMI
MCSPI2_CLK MCSPI1_CLK
VDDSHV
VDDSHV
DSS_HSYNC UART1_RTS
ETK_D9
ETK_D7 ETK_D5
ETK_CTL MCSPI2_CS0 MCSPI1_CS3 MMC2_DAT3 MMC2_DAT6
DSS_DATA0 DSS_VSYNC
UART1_RX ETK_D11 ETK_D2
MCSPI2_
SIMO
MMC2_DAT0 MMC2_DAT5
DSS_DATA1 DSS_ACBIAS
ETK_D6 ETK_D3
MCSPI2_CS1
MCSPI1_SIMO
MMC2_DAT1
DSS_DATA2 DSS_DATA3 DSS_DATA5
VSS VDDSHV
MCSPI1_CS0
DSS_DATA4 DSS_DATA8 DSS_DATA9 DSS_DATA6
VSS VDDSHV VSS
DSS_DATA13 DSS_DATA7 DSS_DATA10 DSS_DATA11
VSS VDDS
DSS_DATA16 DSS_DATA15
DSS_DATA17 DSS_DATA23 DSS_DATA22 DSS_DATA12 JTAG_TCK
DSS_DATA20 DSS_DATA21 DSS_DATA18 JTAG_NTRST JTAG_EMU0
JTAG_TMS_
TMSC
JTAG_TDI
LK
J
HGF
ED
C
B
A
12
13
14
15
16
17
18
19
20
21
22
ETK_D13 ETK_D0
MCSPI1_CS1
UART1_CTS
ETK_D14
ETK_D4
MCSPI1_CS2
ETK_D15 ETK_D12
VDDSHV
MCSPI1_
SOMI
VDDSHV VDDSHV
VSS
VDD_CORE
DSS_DATA19 DSS_DATA14
VDDSHV VSS VDDS
VDD_CORE
VSS
JTAG_RTCK
JTAG_TDO
JTAG_EMU1
VDDSHV VDDSHV
AM3517, AM3505
SPRS550B–OCTOBER 2009–REVISED JULY 2010
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Figure 2-5. ZER Pin Map [Quadrant A]
14 TERMINAL DESCRIPTION Copyright © 2009–2010, Texas Instruments Incorporated
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12
17
18
19
20
21
14
15
16
13
CCDC_FIELD
CCDC_
PCLK
CCDC_HDCCDC_WEN
CCDC_
DATA2
RMII_
MDIO_DATA
RMII_
CRS_DV
RMII_
50MHZ_CLK
MMC1_DAT0MMC1_CMDMMC2_CLK
VSS
GPMC_CLK
GPMC_NOE
HECC1_TXD
HECC1_RXD
I2C1_SDA
SYS_NIRQ
SYS_BOOT0
SYS_BOOT1SYS_BOOT7
SYS_BOOT3
SYS_NRES
PWRON
I2C1_SCL
SYS_BOOT8
M
N P R
T
U V
W
Y
22
AA AB
VDDSHV VSS
CCDC_VD
CCDC_
DATA0
CCDC_
DATA4
RMII_
MDIO_CLK
RMII_TXD0
RMII_RXER
MMC1_CLKMMC1_DAT4
VSS
MMC1_DAT3MMC1_DAT1
MMC1_DAT2MMC1_DAT5
MMC1_DAT7
MMC1_DAT6
VSS
VDDSHV VSS
VDDSHV
VDD_CORE VDD_CORE
VSS
VDD_CORE
VSS
VSS
VDD_CORE
VSS
VDD_CORE
VSS
VDD_CORE VDD_CORE
VSS VSS
CCDC_
DATA6
CCDC_
DATA5
CCDC_
DATA7
VSS
VDDSHV
VSS
VSS
VDDSHV
RMII_RXD1
RMII_RXD0
VSS
VDDSHV
VDDS
VDDSHV
VSS
RESERVED
RESERVED
I2C3_SCL
UART3_CTS
_RCTX
SYS_NRE
SWARM
I2C2_SCLI2C3_SDA
GPMC_
WAIT1
GPMC_NWEGPMC_NBE1
GPMC_
NADV_ALE
UART3_RX
_IRRX
UART3_TX
_IRTX
UART3_RTS
_SD
GPMC_
WAIT0
GPMC_NCS3 GPMC_NCS5 GPMC_NCS2 GPMC_NCS6
M
N P R
T
U V
W
Y
AA AB
12
17
18
19
20
21
14
15
16
13
22
MMC2_CMD
RMII_TXD1
CCDC_
DATA1
MMC2_DAT7
RMII_TXEN
CCDC_
DATA3
SYS_BOOT6 SYS_BOOT5
MMC2_DAT2
VDDSHV VDDSHV
SYS_BOOT4 SYS_BOOT2
CAP_VDD
_SRAM_MPU
VSS VDDSHV
VSS VDDSHV VSS
I2C2_SDA
VSS VDDSHV
GPMC_
WAIT3
GPMC_NWP
GPMC_
WAIT2
VDD_CORE
VSS
AM3517, AM3505
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SPRS550B–OCTOBER 2009–REVISED JULY 2010
Figure 2-6. ZER Pin Map [Quadrant B]
Copyright © 2009–2010, Texas Instruments Incorporated TERMINAL DESCRIPTION 15
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D
C
5
4
3
B
A
2
1
L
K
J
HGF
11
10
9
8
7
6
E
VSS
MCBSP1
_CLKR
MCBSP1_FSX MCBSP1_FSR MCBSP_CLKS
VSS VSS
VSS
VDD_CORE
VSS
MCBSP1_DX
NC
SYS_
CLKOUT2
VSS
VDD_CORE
VDD_CORE
VDD_CORE
VSSVDDSHV
VSS VSS
VDD_CORE
VSS
VDDS
VDDS
NC
VDDS_SRAM
_CORE_BG
NC
SYS_XTALIN
VSSOSC
SYS_
XTALOUT
SYS_32K
SYS_CLKREQ
MCBSP1
_CLKX
NC NC NC
NC
VDDA3P3V
_USBPHY
CAP_VDDA1
P2LDO_
USBPHY
USB0_
DRVVBUS
USB0_DP
UART2_CTS
MCBSP3_FSX
MCBSP4
_CLKX
MCBSP4_DX
VSS VDDSHV
MCBSP4_FSX
MCBSP4_DR
MCBSP3_DR
UART2_RTS
SDRC_D6
SDRC_D3
SDRC_D2
MCBSP2_DR
UART2_RX
VDDA1P8V
_USBPHY
UART2_TX
SDRC_D7
SDRC_DQS0N
SDRC_
STRBEN
_DLY0
SDRC_D13
SDRC_DQS1N
SDRC_D15
SDRC_NRAS SDRC_CLK
SDRC_NCLK
SDRC_NWE
SDRC_DM1
SDRC_DQS1P
SDRC_D8
SDRC_
STRBEN0
SDRC_DQS0P
SDRC_D5
SDRC_D0
SDRC_D4
SDRC_D9 SDRC_D14
SDRC_CKE0
SDRC_DM0 SDRC_D11
SDRC_NCS0 SDRC_NCS1
VSS
SDRC_BA2
SDRC_BA1
USB0_DM
VSS
USB0_ID
VSS
D
C
B
A
L
K
J
HGF
E
5
4
3
2
1
11
10
9
8
7
6
VDDS_
DPLL_PER
_CORE
VSS
VDD_CORE
HDQ_SIO
MCBSP1_DR
NC
SYS_
CLKOUT1
NC
VDDSOSC
VSS
VDDSHV
USB0_VBUS
VSS
VSS
VSS
VSS
CAP_VDD_
SRAM_CORE
MCBSP2
_CLKX
MCBSP2_FSX
VDDS
VDDS
VREFSSTL
MCBSP3_DX
MCBSP3
_CLKX
MCBSP2_DX
SDRC_D12 SDRC_BA0
SDRC_D1 SDRC_D10
SDRC_NCAS
AM3517, AM3505
SPRS550B–OCTOBER 2009–REVISED JULY 2010
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Figure 2-7. ZER Pin Map [Quadrant C]
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M
N P
W Y
11
10
5
4
3
AA
AB
2
R T U
8
7
6
9
V
VDD_CORE
VSS
VDD_CORE
1
VSS
VSS
VDD_CORE
VDDSHV
VSS
VSS VDDSHV
GPMC_D14 GPMC_D8
GPMC_NCS0
GPMC_D15VSSVDDSHV
VDDSHVVSS
VDDS
VDDS
GPMC_D12
GPMC_D10
GPMC_D3 GPMC_D9
GPMC_D13
GPMC_D0 GPMC_A9GPMC_D1
GPMC_A6GPMC_A7GPMC_A8
VSS
GPMC_A5
VSS
VDD_CORE
VDD_CORE VSS
VSS
VDD_CORE
VSS VDD_CORE
VDD_COREVDD_CORE
VDDS VSS
VSS
VDDS
VDDSVSS
DDR_
PADREF
SDRC_A0
SDRC_A1
SDRC_A2
SDRC_A4
SDRC_A8
SDRC_A7
SDRC_A6
SDRC_A9
VDDS VSS
SDRC_A13
SDRC_A12
SDRC_A11
SDRC_A10
SDRC_A14
SDRC_
ODT
SDRC_
DQS2P
SDRC_
DQS2N
SDRC_D17
SDRC_D18
VSS
SDRC_D22
SDRC_D19
SDRC_D21
SDRC_
D20
GPMC_D2
SDRC_D25
SDRC_D24
SDRC_
STRBEN
_DLY1
SDRC_
STRBEN1
SDRC_
DQS3P
SDRC_
DQS3N
SDRC_D26
SDRC_D28
VDDS VSS
SDRC_D31
SDRC_DM3
M
N P
W Y
AA
ABR T U
V
11
10
5
4
3
2
8
7
6
9
1
GPMC_NCS7
GPMC_
NBE0_CLE
GPMC_NCS1 GPMC_NCS4
VDDSHV
VDD_CORE
VSS
GPMC_D11
VDDSHV
GPMC_D5 GPMC_D6
GPMC_D4
GPMC_D7
VSS
VSS
VDDSHV
GPMC_A10
VSSVSS
VDDS VDDS
GPMC_A1 GPMC_A2 GPMC_A4
GPMC_A3
SDRC_D27 SDRC_D30SDRC_DM2
SDRC_A5
SDRC_A3
SDRC_D16
SDRC_D23
SDRC_D29
AM3517, AM3505
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SPRS550B–OCTOBER 2009–REVISED JULY 2010
Figure 2-8. ZER Pin Map [Quadrant D]
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SPRS550B–OCTOBER 2009–REVISED JULY 2010
2.2 Ball Characteristics
Table 2-1 describes the terminal characteristics and the signals multiplexed on each pin for the ZCN/ZER
package. The following list describes the table column headers.
1. BALL LOCATION: Ball number(s) on the bottom side associated with each signal(s) on the bottom.
2. PIN NAME: Names of signals multiplexed on each ball (also notice that the name of the pin is the
signal name in mode 0).
Note: The Ball Characteristics table does not take into account subsystem pin multiplexing options.
Subsystem pin multiplexing options are described in Section 2.4, Signal Descriptions.
3. MODE: Multiplexing mode number.
(a) Mode 0 is the primary mode; this means that when mode 0 is set, the function mapped on the pin
corresponds to the name of the pin. There is always a function mapped on the primary mode.
Notice that primary mode is not necessarily the default mode.
Note: The default mode is the mode which is automatically configured on release of the internal
GLOBAL_PWRON reset; also see the RESET REL. MODE column.
(b) Modes 1 to 7 are possible modes for alternate functions. On each pin, some modes are effectively
used for alternate functions, while some modes are not used and do not correspond to a functional
configuration.
4. TYPE: Signal direction
– I = Input
– O = Output
– I/O = Input/Output
– D = Open drain
– DS = Differential
– A = Analog
Note: In the safe_mode, the buffer is configured in high-impedance.
5. BALL RESET STATE: The state of the terminal at reset (power up).
– 0: The buffer drives VOL(pulldown/pullup resistor not activated)
0(PD): The buffer drives VOLwith an active pulldown resistor.
– 1: The buffer drives VOH(pulldown/pullup resistor not activated)
1(PU): The buffer drives VOHwith an active pullup resistor.
– Z: High-impedance
– L: High-impedance with an active pulldown resistor
– H : High-impedance with an active pullup resistor
6. BALL RESET REL. STATE: The state of the terminal at reset release.
– 0: The buffer drives VOL(pulldown/pullup resistor not activated)
0(PD): The buffer drives VOLwith an active pulldown resistor.
– 1: The buffer drives VOH(pulldown/pullup resistor not activated)
1(PU): The buffer drives VOHwith an active pullup resistor.
– Z: High-impedance
– L: High-impedance with an active pulldown resistor
– H : High-impedance with an active pullup resistor
7. RESET REL. MODE: This mode is automatically configured on release of the internal
GLOBAL_PWRON reset.
8. POWER: The voltage supply that powers the terminal’s I/O buffers.
9. VOLTAGE: Supply voltage for associated pin.
10. HYS: Indicates if the input buffer is with hysteresis.
11. LOAD: Load capacitance of the associated output buffer.
12. PULL U/D - TYPE: Denotes the presence of an internal pullup or pulldown resistor. Pullup and
pulldown resistors can be enabled or disabled via software.
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SPRS550B–OCTOBER 2009–REVISED JULY 2010
13. IO CELL: IO cell information.
Note: Configuring two pins to the same input signal is not supported as it can yield unexpected results.
This can be easily prevented with the proper software configuration.
Table 2-1. Ball Characteristics (ZCN Pkg.)
BALL PIN NAME MODE [3] TYPE [4] BALL BALL RESET REL. POWER [8] VOLTAGE HYS [10] LOAD (pF) PULL U/D IO CELL [13]
LOCATION [2] RESET RESET REL. MODE [7] [9] [11] TYPE [12]
[1] STATE [5] STATE [6]
B21 sdrc_d0 0 IO L Z 0 VDDS 1.8V Yes 4 PU/PD LVCMOS
A21 sdrc_d1 0 IO L Z 0 VDDS 1.8V Yes 4 PU/PD LVCMOS
D20 sdrc_d2 0 IO L Z 0 VDDS 1.8V Yes 4 PU/ PD LVCMOS
C20 sdrc_d3 0 IO L Z 0 VDDS 1.8V Yes 4 PU/ PD LVCMOS
E19 sdrc_d4 0 IO L Z 0 VDDS 1.8V Yes 4 PU/ PD LVCMOS
D19 sdrc_d5 0 IO L Z 0 VDDS 1.8V Yes 4 PU/ PD LVCMOS
C19 sdrc_d6 0 IO L Z 0 VDDS 1.8V Yes 4 PU/ PD LVCMOS
B19 sdrc_d7 0 IO L Z 0 VDDS 1.8V Yes 4 PU/ PD LVCMOS
B18 sdrc_d8 0 IO L Z 0 VDDS 1.8V Yes 4 PU/ PD LVCMOS
D17 sdrc_d9 0 IO L Z 0 VDDS 1.8V Yes 4 PU/ PD LVCMOS
C17 sdrc_d10 0 IO L Z 0 VDDS 1.8V Yes 4 PU/ PD LVCMOS
D16 sdrc_d11 0 IO L Z 0 VDDS 1.8V Yes 4 PU/ PD LVCMOS
C16 sdrc_d12 0 IO L Z 0 VDDS 1.8V Yes 4 PU/ PD LVCMOS
B16 sdrc_d13 0 IO L Z 0 VDDS 1.8V Yes 4 PU/ PD LVCMOS
A16 sdrc_d14 0 IO L Z 0 VDDS 1.8V Yes 4 PU/ PD LVCMOS
A15 sdrc_d15 0 IO L Z 0 VDDS 1.8V Yes 4 PU/ PD LVCMOS
A7 sdrc_d16 0 IO L Z 0 VDDS 1.8V Yes 4 PU/ PD LVCMOS
B7 sdrc_d17 0 IO L Z 0 VDDS 1.8V Yes 4 PU/ PD LVCMOS
D7 sdrc_d18 0 IO L Z 0 VDDS 1.8V Yes 4 PU/ PD LVCMOS
E7 sdrc_d19 0 IO L Z 0 VDDS 1.8V Yes 4 PU/ PD LVCMOS
C6 sdrc_d20 0 IO L Z 0 VDDS 1.8V Yes 4 PU/ PD LVCMOS
D6 sdrc_d21 0 IO L Z 0 VDDS 1.8V Yes 4 PU/ PD LVCMOS
B5 sdrc_d22 0 IO L Z 0 VDDS 1.8V Yes 4 PU/ PD LVCMOS
C5 sdrc_d23 0 IO L Z 0 VDDS 1.8V Yes 4 PU/ PD LVCMOS
B4 sdrc_d24 0 IO L Z 0 VDDS 1.8V Yes 4 PU/ PD LVCMOS
A3 sdrc_d25 0 IO L Z 0 VDDS 1.8V Yes 4 PU/ PD LVCMOS
B3 sdrc_d26 0 IO L Z 0 VDDS 1.8V Yes 4 PU/ PD LVCMOS
C3 sdrc_d27 0 IO L Z 0 VDDS 1.8V Yes 4 PU/ PD LVCMOS
C2 sdrc_d28 0 IO L Z 0 VDDS 1.8V Yes 4 PU/ PD LVCMOS
D2 sdrc_d29 0 IO L Z 0 VDDS 1.8V Yes 4 PU/ PD LVCMOS
B1 sdrc_d30 0 IO L Z 0 VDDS 1.8V Yes 4 PU/ PD LVCMOS
C1 sdrc_d31 0 IO L Z 0 VDDS 1.8V Yes 4 PU/ PD LVCMOS
A12 sdrc_ba0 0 O L Z 0 VDDS 1.8V No 8 PU/ PD LVCMOS
C13 sdrc_ba1 0 O L Z 0 VDDS 1.8V No 8 PU/ PD LVCMOS
D13 sdrc_ba2 0 O L Z 0 VDDS 1.8V No 8 PU/ PD LVCMOS
A11 sdrc_a0 0 O L Z 0 VDDS 1.8V No 8 PU/ PD LVCMOS
B11 sdrc_a1 0 O L Z 0 VDDS 1.8V No 8 PU/ PD LVCMOS
C11 sdrc_a2 0 O L Z 0 VDDS 1.8V No 8 PU/ PD LVCMOS
D11 sdrc_a3 0 O L Z 0 VDDS 1.8V No 8 PU/ PD LVCMOS
E11 sdrc_a4 0 O L Z 0 VDDS 1.8V No 8 PU/ PD LVCMOS
A10 sdrc_a5 0 O L Z 0 VDDS 1.8V No 8 PU/ PD LVCMOS
B10 sdrc_a6 0 O L Z 0 VDDS 1.8V No 8 PU/ PD LVCMOS
C10 sdrc_a7 0 O L Z 0 VDDS 1.8V No 8 PU/ PD LVCMOS
D10 sdrc_a8 0 O L Z 0 VDDS 1.8V No 8 PU/ PD LVCMOS
E10 sdrc_a9 0 O L Z 0 VDDS 1.8V No 8 PU/ PD LVCMOS
A9 sdrc_a10 0 O L Z 0 VDDS 1.8V No 8 PU/ PD LVCMOS
B9 sdrc_a11 0 O L Z 0 VDDS 1.8V No 8 PU/ PD LVCMOS
A8 sdrc_a12 0 O L Z 0 VDDS 1.8V No 8 PU/ PD LVCMOS
B8 sdrc_a13 0 O L Z 0 VDDS 1.8V No 8 PU/ PD LVCMOS
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Table 2-1. Ball Characteristics (ZCN Pkg.) (continued)
BALL PIN NAME MODE [3] TYPE [4] BALL BALL RESET REL. POWER [8] VOLTAGE HYS [10] LOAD (pF) PULL U/D IO CELL [13]
LOCATION [2] RESET RESET REL. MODE [7] [9] [11] TYPE [12]
[1] STATE [5] STATE [6]
D8 sdrc_a14 0 O L Z 0 VDDS 1.8V No 8 PU/ PD LVCMOS
E13 sdrc_ncs0 0 O L Z 0 VDDS 1.8V No 8 PU/ PD LVCMOS
A14 sdrc_ncs1 0 O L Z 0 VDDS 1.8V No 8 PU/ PD LVCMOS
A13 sdrc_clk 0 O L Z 0 VDDS 1.8V Yes 8 PU/ PD LVCMOS
B13 sdrc_nclk 0 O L Z 0 VDDS 1.8V No 8 PU/ PD LVCMOS
D14 sdrc_cke0 0 O L PD 7 VDDS 1.8V Yes 8 PU/PD LVCMOS
sdrc_cke0_s 7 L
afe
C14 sdrc_nras 0 O L Z 0 VDDS 1.8V No 8 PU/ PD LVCMOS
E14 sdrc_ncas 0 O L Z 0 VDDS 1.8V No 8 PU/ PD LVCMOS
B14 sdrc_nwe 0 O L Z 0 VDDS 1.8V No 8 PU/ PD LVCMOS
C21 sdrc_dm0 0 O L Z 0 VDDS 1.8V No 8 PU/ PD LVCMOS
B15 sdrc_dm1 0 O L Z 0 VDDS 1.8V No 8 PU/ PD LVCMOS
E8 sdrc_dm2 0 O L Z 0 VDDS 1.8V No 8 PU/ PD LVCMOS
D1 sdrc_dm3 0 O L Z 0 VDDS 1.8V No 8 PU/ PD LVCMOS
B20 sdrc_dqs0p 0 IO L Z 0 VDDS 1.8V Yes 8 PU/ PD LVCMOS
B17 sdrc_dqs1p 0 IO L Z 0 VDDS 1.8V Yes 8 PU/ PD LVCMOS
A6 sdrc_dqs2p 0 IO L Z 0 VDDS 1.8V Yes 8 PU/ PD LVCMOS
A2 sdrc_dqs3p 0 IO L Z 0 VDDS 1.8V Yes 8 PU/ PD LVCMOS
A20 sdrc_dqs0n 0 IO L Z 0 VDDS 1.8V 8 PU/ PD LVCMOS
A17 sdrc_dqs1n 0 IO L Z 0 VDDS 1.8V 8 PU/ PD LVCMOS
B6 sdrc_dqs2n 0 IO L Z 0 VDDS 1.8V 8 PU/ PD LVCMOS
B2 sdrc_dqs3n 0 IO L Z 0 VDDS 1.8V 8 PU/ PD LVCMOS
C8 sdrc_odt 0 L Z 0 VDDS 1.8V 8 PU/ PD LVCMOS
A19 sdrc_strben0 0 L Z 0 VDDS 1.8V 8 PU/ PD LVCMOS
A18 sdrc_strben_ 0 L Z 0 VDDS 1.8V 8 PU/ PD LVCMOS
A5 sdrc_strben1 0 L Z 0 VDDS 1.8V 8 PU/ PD LVCMOS
A4 sdrc_strben_ 0 L Z 0 VDDS 1.8V 8 PU/ PD LVCMOS
B12 ddr_padref 0 A VDDS 1.8V
E3 gpmc_a1 0 O L PD 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS
E2 gpmc_a2 0 O L PD 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS
E1 gpmc_a3 0 O L PD 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS
F7 gpmc_a4 0 O L PD 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS
F6 gpmc_a5 0 O L PD 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS
F4 gpmc_a6 0 O H PU 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS
F3 gpmc_a7 0 O H PU 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS
F2 gpmc_a8 0 O H PU 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS
F1 gpmc_a9 0 O H PU 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS
dly0
dly1
gpio_34 4 IO
safe_mode 7
gpio_35 4 IO
safe_mode 7
gpio_36 4 IO
safe_mode 7
gpio_37 4 IO
safe_mode 7
gpio_38 4 IO
safe_mode 7
gpio_39 4 IO
safe_mode 7
gpio_40 4 IO
safe_mode 7
gpio_41 4 IO
safe_mode 7
20 TERMINAL DESCRIPTION Copyright © 2009–2010, Texas Instruments Incorporated
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SPRS550B–OCTOBER 2009–REVISED JULY 2010
Table 2-1. Ball Characteristics (ZCN Pkg.) (continued)
BALL PIN NAME MODE [3] TYPE [4] BALL BALL RESET REL. POWER [8] VOLTAGE HYS [10] LOAD (pF) PULL U/D IO CELL [13]
LOCATION [2] RESET RESET REL. MODE [7] [9] [11] TYPE [12]
[1] STATE [5] STATE [6]
sys_ 1 I
ndmareq2
gpio_42 4 IO
safe_mode 7
G6 gpmc_a10 0 O H PU 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS
sys_ 1 I
ndmareq3
gpio_43 4 IO
safe_mode 7
G5 gpmc_d0 0 IO H PU 0 VDDSHV 1.8V/3.3V 30 PU/ PD LVCMOS
G4 gpmc_d1 0 IO H PU 0 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS
G3 gpmc_d2 0 IO H PU 0 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS
G2 gpmc_d3 0 IO H PU 0 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS
G1 gpmc_d4 0 IO H PU 0 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS
H2 gpmc_d5 0 IO H PU 0 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS
H1 gpmc_d6 0 IO H PU 0 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS
J5 gpmc_d7 0 IO H PU 0 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS
J4 gpmc_d8 0 IO H PU 0 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS
gpio_44 4 IO
J3 gpmc_d9 0 IO H PU 0 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS
gpio_45 4 IO
J2 gpmc_d10 0 IO H PU 0 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS
gpio_46 4 IO
J1 gpmc_d11 0 IO H PU 0 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS
gpio_47 4 IO
K4 gpmc_d12 0 IO H PU 0 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS
gpio_48 4 IO
K3 gpmc_d13 0 IO H PU 0 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS
gpio_49 4 IO
K2 gpmc_d14 0 IO H PU 0 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS
gpio_50 4 IO
K1 gpmc_d15 0 IO H PU 0 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS
gpio_51 4 IO
L2 gpmc_ncs0 0 O H Z 0 VDDSHV 1.8V/3.3V No 30 NA LVCMOS
L1 gpmc_ncs1 0 O H Z 0 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS
gpio_52 4 IO
M4 gpmc_ncs2 0 O H PU 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS
gpt9_pwm_e 2 IO
vt
gpio_53 4 IO
safe_mode 7
M3 gpmc_ncs3 0 O H PU 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS
sys_ 1 I
ndmareq0
gpt10_pwm_ 2 IO
evt
gpio_54 4 IO
safe_mode 7
M2 gpmc_ncs4 0 O H PU 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS
sys_ 1 I
ndmareq1
gpt9_pwm_e 3 IO
vt
gpio_55 4 IO
safe_mode 7
Copyright © 2009–2010, Texas Instruments Incorporated TERMINAL DESCRIPTION 21
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SPRS550B–OCTOBER 2009–REVISED JULY 2010
www.ti.com
Table 2-1. Ball Characteristics (ZCN Pkg.) (continued)
BALL PIN NAME MODE [3] TYPE [4] BALL BALL RESET REL. POWER [8] VOLTAGE HYS [10] LOAD (pF) PULL U/D IO CELL [13]
LOCATION [2] RESET RESET REL. MODE [7] [9] [11] TYPE [12]
[1] STATE [5] STATE [6]
M1 gpmc_ncs5 0 O H PU 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS
sys_ 1 I
ndmareq2
gpt10_pwm_ 3 IO
evt
gpio_56 4 IO
safe_mode 7
N5 gpmc_ncs6 0 O H PU 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS
sys_ 1 I
ndmareq3
gpt11_pwm_ 3 IO
evt
gpio_57 4 IO
safe_mode 7
N4 gpmc_ncs7 0 O H PU 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS
gpmc_io_dir 1 O
gpt8_pwm_e 3 IO
vt
gpio_58 4 IO
safe_mode 7
N1 gpmc_clk 0 O L Z 0 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS
gpio_59 4 IO
R1 gpmc_nadv_ 0 O L Z 0 VDDSHV 1.8V/3.3V No 30 PU/ PD LVCMOS
R2 gpmc_noe 0 O H Z 0 VDDSHV 1.8V/3.3V No 30 PU/ PD LVCMOS
R3 gpmc_nwe 0 O H Z 0 VDDSHV 1.8V/3.3V No 30 PU/ PD LVCMOS
R4 gpmc_nbe0_ 0 O L Z 0 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS
T1 gpmc_nbe1 0 O L PD 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS
T2 gpmc_nwp 0 O L Z 0 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS
T3 gpmc_wait0 0 I H PU 0 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS
T4 gpmc_wait1 0 I H PU 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS
T5 gpmc_wait2 0 I H PU 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS
U1 gpmc_wait3 0 I H PU 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS
AE23 dss_pclk 0 O H PU 7 VDDSHV 1.8V/3.3V Yes 20 PU/ PD LVCMOS
AD22 dss_hsync 0 O H PU 7 VDDSHV 1.8V/3.3V Yes 20 PU/ PD LVCMOS
ale
cle
gpio_60 4 IO
gpio_61 4 IO
safe_mode 7
gpio_62 4 IO
uart4_tx 1 O
gpio_63 4 IO
safe_mode 7
uart4_rx 1 I
gpio_64 4 IO
safe_mode 7
sys_ 1 I
ndmareq1
uart3_cts_rct 2 I
x
gpio_65 4 IO
safe_mode 7
gpio_66 4 IO
hw_dbg12 5 O
safe_mode 7
gpio_67 4 IO
hw_dbg13 5 O
safe_mode 7
22 TERMINAL DESCRIPTION Copyright © 2009–2010, Texas Instruments Incorporated
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SPRS550B–OCTOBER 2009–REVISED JULY 2010
Table 2-1. Ball Characteristics (ZCN Pkg.) (continued)
BALL PIN NAME MODE [3] TYPE [4] BALL BALL RESET REL. POWER [8] VOLTAGE HYS [10] LOAD (pF) PULL U/D IO CELL [13]
LOCATION [2] RESET RESET REL. MODE [7] [9] [11] TYPE [12]
[1] STATE [5] STATE [6]
AD23 dss_vsync 0 O H PU 7 VDDSHV 1.8V/3.3V Yes 20 PU/ PD LVCMOS
gpio_68 4 IO
safe_mode 7
AE24 dss_acbias 0 O L PD 7 VDDSHV 1.8V/3.3V Yes 20 PU/ PD LVCMOS
gpio_69 4 IO
safe_mode 7
AD24 dss_data0 0 O L PD 7 VDDSHV 1.8V/3.3V Yes 20 PU/ PD LVCMOS
uart1_cts 2 I
gpio_70 4 IO
safe_mode 7
AD25 dss_data1 0 O L PD 7 VDDSHV 1.8V/3.3V Yes 20 PU/ PD LVCMOS
uart1_rts 2 O
gpio_71 4 IO
safe_mode 7
AC23 dss_data2 0 O L PD 7 VDDSHV 1.8V/3.3V Yes 20 PU/ PD LVCMOS
gpio_72 4 IO
safe_mode 7
AC24 dss_data3 0 O L PD 7 VDDSHV 1.8V/3.3V Yes 20 PU/ PD LVCMOS
gpio_73 4 IO
safe_mode 7
AC25 dss_data4 0 O L PD 7 VDDSHV 1.8V/3.3V Yes 20 PU/ PD LVCMOS
uart3_rx_ irrx 2 I
gpio_74 4 IO
safe_mode 7
AB24 dss_data5 0 O L PD 7 VDDSHV 1.8V/3.3V Yes 20 PU/ PD LVCMOS
uart3_tx_ irtx 2 O
gpio_75 4 IO
safe_mode 7
AB25 dss_data6 0 O L PD 7 VDDSHV 1.8V/3.3V Yes 20 PU/ PD LVCMOS
uart1_tx 2 O
gpio_76 4 IO
hw_dbg14 5 O
safe_mode 7
AA23 dss_data7 0 O L PD 7 VDDSHV 1.8V/3.3V Yes 20 PU/ PD LVCMOS
uart1_rx 2 I
gpio_77 4 IO
hw_dbg15 5 O
safe_mode 7
AA24 dss_data8 0 O L PD 7 VDDSHV 1.8V/3.3V Yes 20 PU/ PD LVCMOS
gpio_78 4 IO
hw_dbg16 5 O
safe_mode 7
AA25 dss_data9 0 O L PD 7 VDDSHV 1.8V/3.3V Yes 20 PU/ PD LVCMOS
gpio_79 4 IO
hw_dbg17 5 O
safe_mode 7
Y22 dss_data10 0 O L PD 7 VDDSHV 1.8V/3.3V Yes 20 PU/ PD LVCMOS
gpio_80 4 IO
safe_mode 7
Y23 dss_data11 0 O L PD 7 VDDSHV 1.8V/3.3V Yes 20 PU/ PD LVCMOS
gpio_81 4 IO
safe_mode 7
Y24 dss_data12 0 O L PD 7 VDDSHV 1.8V/3.3V Yes 20 PU/ PD LVCMOS
gpio_82 4 IO
safe_mode 7
Copyright © 2009–2010, Texas Instruments Incorporated TERMINAL DESCRIPTION 23
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SPRS550B–OCTOBER 2009–REVISED JULY 2010
www.ti.com
Table 2-1. Ball Characteristics (ZCN Pkg.) (continued)
BALL PIN NAME MODE [3] TYPE [4] BALL BALL RESET REL. POWER [8] VOLTAGE HYS [10] LOAD (pF) PULL U/D IO CELL [13]
LOCATION [2] RESET RESET REL. MODE [7] [9] [11] TYPE [12]
[1] STATE [5] STATE [6]
Y25 dss_data13 0 O L PD 7 VDDSHV 1.8V/3.3V Yes 20 PU/ PD LVCMOS
gpio_83 4 IO
safe_mode 7
W21 dss_data14 0 O L PD 7 VDDSHV 1.8V/3.3V Yes 20 PU/ PD LVCMOS
gpio_84 4 IO
safe_mode 7
W22 dss_data15 0 O L PD 7 VDDSHV 1.8V/3.3V Yes 20 PU/ PD LVCMOS
gpio_85 4 IO
safe_mode 7
W23 dss_data16 0 O L PD 7 VDDSHV 1.8V/3.3V Yes 20 PU/ PD LVCMOS
gpio_86 4 IO
safe_mode 7
W24 dss_data17 0 O L PD 7 VDDSHV 1.8V/3.3V Yes 20 PU/ PD LVCMOS
gpio_87 4 IO
safe_mode 7
W25 dss_data18 0 O L PD 7 VDDSHV 1.8V/3.3V Yes 20 PU/ PD LVCMOS
mcspi3_clk 2 IO
dss_data4 3 O
gpio_88 4 IO
safe_mode 7
V24 dss_data19 0 O L PD 7 VDDSHV 1.8V/3.3V Yes 20 PU/ PD LVCMOS
mcspi3_ 2 IO
simo
dss_data3 3 O
gpio_89 4 IO
safe_mode 7
V25 dss_data20 0 O L PD 7 VDDSHV 1.8V/3.3V Yes 20 PU/ PD LVCMOS
mcspi3_ 2 IO
somi
dss_data2 3 O
gpio_90 4 IO
safe_mode 7
U21 dss_data21 0 O L PD 7 VDDSHV 1.8V/3.3V Yes 20 PU/ PD LVCMOS
mcspi3_cs0 2 IO
dss_data1 3 O
gpio_91 4 IO
safe_mode 7
U22 dss_data22 0 O L PD 7 VDDSHV 1.8V/3.3V Yes 20 PU/ PD LVCMOS
mcspi3_cs1 2 O
dss_data0 3 O
gpio_92 4 IO
safe_mode 7
U23 dss_data23 0 O L PD 7 VDDSHV 1.8V/3.3V Yes 20 PU/ PD LVCMOS
dss_data5 3 O
gpio_93 4 IO
safe_mode 7
H24 tv_out2 0 O 0 VDDA_DAC 1.8V NA 10-bit DAC
K21 tv_out1 0 O 0 VDDA_DAC 1.8V NA 10-bit DAC
K20 tv_vfb1 0 O Z NA 0 VDDA_DAC 1.8V NA 10-bit DAC
H23 tv_vfb2 0 O Z NA 0 VDDA_DAC 1.8V NA 10-bit DAC
H20 tv_vref 0 I Z NA 0 VDDA_DAC 1.8V NA 10-bit DAC
AD2 ccdc_pclk 0 IO L PD 7 VDDSHV 1.8V/3.3V Yes 15 PU/ PD LVCMOS
gpio_94 4 IO
hw_dbg0 5 O
safe_mode 7
24 TERMINAL DESCRIPTION Copyright © 2009–2010, Texas Instruments Incorporated
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www.ti.com
SPRS550B–OCTOBER 2009–REVISED JULY 2010
Table 2-1. Ball Characteristics (ZCN Pkg.) (continued)
BALL PIN NAME MODE [3] TYPE [4] BALL BALL RESET REL. POWER [8] VOLTAGE HYS [10] LOAD (pF) PULL U/D IO CELL [13]
LOCATION [2] RESET RESET REL. MODE [7] [9] [11] TYPE [12]
[1] STATE [5] STATE [6]
AD1 ccdc_field 0 IO L PD 7 VDDSHV 1.8V/3.3V Yes 15 PU/ PD LVCMOS
ccdc_data8 1 I
uart4_tx 2 O
i2c3_scl 3 IOD
gpio_95 4 IO
hw_dbg1 5 O
safe_mode 7
AE2 ccdc_ hd 0 IO L PD 7 VDDSHV 1.8V/3.3V Yes 15 PU/ PD LVCMOS
uart4_rts 2 O
gpio_96 4 IO
safe_mode 7
AD3 ccdc_vd 0 IO L PD 7 VDDSHV 1.8V/3.3V Yes 15 PU/ PD LVCMOS
uart4_cts 2 I
gpio_97 4 IO
hw_dbg2 5 O
safe_mode 7
AE3 ccdc_wen 0 IO L PD 7 VDDSHV 1.8V/3.3V Yes 15 PU/PD LVCMOS
ccdc_data9 1 I
uart4_rx 2 I
gpio_98 4 IO
hw_dbg3 5 O
safe_mode 7
AD4 ccdc_data0 0 I L PD 7 VDDSHV 1.8V/3.3V Yes 15 PU/PD LVCMOS
i2c3_sda 3 IOD
gpio_99 4 I
safe_mode 7
AE4 ccdc_data1 0 I L PD 7 VDDSHV 1.8V/3.3V Yes 15 PU/PD LVCMOS
gpio_100 4 I
safe_mode 7
AC5 ccdc_data2 0 I L PD 7 VDDSHV 1.8V/3.3V Yes 15 PU/ PD LVCMOS
gpio_101 4 IO
hw_dbg4 5 O
safe_mode 7
AD5 ccdc_data3 0 I L PD 7 VDDSHV 1.8V/3.3V Yes 15 PU/ PD LVCMOS
gpio_102 4 IO
hw_dbg5 5 O
safe_mode 7
AE5 ccdc_data4 0 I L PD 7 VDDSHV 1.8V/3.3V Yes 15 PU/ PD LVCMOS
gpio_103 4 IO
hw_dbg6 5 O
safe_mode 7
Y6 ccdc_data5 0 I L PD 7 VDDSHV 1.8V/3.3V Yes 15 PU/ PD LVCMOS
gpio_104 4 IO
hw_dbg7 5 O
safe_mode 7
AB6 ccdc_data6 0 I L PD 7 VDDSHV 1.8V/3.3V Yes 15 PU/PD LVCMOS
gpio_105 4 IO
safe_mode 7
AC6 ccdc_data7 0 I L PD 7 VDDSHV 1.8V/3.3V Yes 15 PU/PD LVCMOS
gpio_106 4 IO
safe_mode 7
AE6 rmii_mdio_da 0 IO H PU 7 VDDSHV 1.8V/3.3V Yes 25 PU/PD LVCMOS
ta
ccdc_data8 1 I
gpio_107 4 IO
Copyright © 2009–2010, Texas Instruments Incorporated TERMINAL DESCRIPTION 25
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SPRS550B–OCTOBER 2009–REVISED JULY 2010
www.ti.com
Table 2-1. Ball Characteristics (ZCN Pkg.) (continued)
BALL PIN NAME MODE [3] TYPE [4] BALL BALL RESET REL. POWER [8] VOLTAGE HYS [10] LOAD (pF) PULL U/D IO CELL [13]
LOCATION [2] RESET RESET REL. MODE [7] [9] [11] TYPE [12]
[1] STATE [5] STATE [6]
safe_mode 7
AD6 rmii_mdio_cl 0 O H PU 7 VDDSHV 1.8V/3.3V Yes 25 PU/PD LVCMOS
Y7 rmii_rxd0 0 I H PU 7 VDDSHV 1.8V/3.3V Yes 25 PU/ PD LVCMOS
AA7 rmii_rxd1 0 I H PU 7 VDDSHV 1.8V/3.3V Yes 25 PU/ PD LVCMOS
AB7 rmii_crs_dv 0 I H PU 7 VDDSHV 1.8V/3.3V Yes 25 PU/ PD LVCMOS
AC7 rmii_rxer 0 I H PU 7 VDDSHV 1.8V/3.3V Yes 25 PU/ PD LVCMOS
AD7 rmii_txd0 0 O H PU 7 VDDSHV 1.8V/3.3V Yes 25 PU/ PD LVCMOS
AE7 rmii_txd1 0 O H PU 7 VDDSHV 1.8V/3.3V Yes 25 PU/PD LVCMOS
AD8 rmii_txen 0 O H PU 7 VDDSHV 1.8V/3.3V 25 PU/PD LVCMOS
AE8 rmii_50mhz_ 0 I H PU 7 VDDSHV 1.8V/3.3V 25 PU/ PD LVCMOS
D25 mcbsp2_fsx 0 IO L PD 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS
C25 mcbsp2_ 0 IO L PD 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS
B25 mcbsp2_dr 0 I L PD 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS
D24 mcbsp2_dx 0 IO L PD 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS
AA9 mmc1_clk 0 O L PD 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS
k
ccdc_data9 1 I
gpio_108 4 IO
safe_mode 7
ccdc_data10 1 I
gpio_109 4 IO
hw_dbg8 5 O
safe_mode 7
ccdc_data11 1 I
gpio_110 4 IO
hw_dbg9 5 O
safe_mode 7
ccdc_data12 1 I
gpio_111 4 IO
safe_mode 7
ccdc_data13 1 I
gpio_167 4 IO
hw_dbg10 5 O
safe_mode 7
ccdc_ data14 1 I
gpio_126 4 IO
hw_dbg11 5 O
safe_mode 7
ccdc_data15 1 I
gpio_112 4 I
safe_mode 7
gpio_113 4 I NA
safe_mode 7
clk
gpio_114 4 I NA
safe_mode 7
gpio_116 4 IO
safe_mode 7
clkx
gpio_117 4 IO
safe_mode 7
gpio_118 4 IO
safe_mode 7
gpio_119 4 IO
safe_mode 7
gpio_120 4 IO
26 TERMINAL DESCRIPTION Copyright © 2009–2010, Texas Instruments Incorporated
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Product Folder Link(s): AM3517 AM3505
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www.ti.com
SPRS550B–OCTOBER 2009–REVISED JULY 2010
Table 2-1. Ball Characteristics (ZCN Pkg.) (continued)
BALL PIN NAME MODE [3] TYPE [4] BALL BALL RESET REL. POWER [8] VOLTAGE HYS [10] LOAD (pF) PULL U/D IO CELL [13]
LOCATION [2] RESET RESET REL. MODE [7] [9] [11] TYPE [12]
[1] STATE [5] STATE [6]
safe_mode 7
AB9 mmc1_cmd 0 IO L PD 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS
gpio_121 4 IO
safe_mode 7
AC9 mmc1_dat0 0 IO L PD 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS
mcspi2_clk 1 IO
gpio_122 4 IO
safe_mode 7
AD9 mmc1_dat1 0 IO L PD 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS
mcspi2_simo 1 IO
gpio_123 4 IO
safe_mode 7
AE9 mmc1_dat2 0 IO L PD 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS
mcspi2_somi 1 IO
gpio_124 4 IO
safe_mode 7
AA10 mmc1_dat3 0 IO L PD 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS
mcspi2_cs0 1 O
gpio_125 4 IO
safe_mode 7
AB10 mmc1_dat4 0 IO L PD 7 VDDSHV 1.8V/3.3V No 30 PU/ PD LVCMOS
gpio_126 4 IO
safe_mode 7
AC10 mmc1_dat5 0 IO L PD 7 VDDSHV 1.8V/3.3V No 30 PU/ PD LVCMOS
gpio_127 4 IO
safe_mode 7
AD10 mmc1_dat6 0 IO L PD 7 VDDSHV 1.8V/3.3V No 30 PU/ PD LVCMOS
gpio_128 4 IO
safe_mode 7
AE10 mmc1_dat7 0 IO L PD 7 VDDSHV 1.8V/3.3V No 30 PU/ PD LVCMOS
gpio_129 4 IO
safe_mode 7
AD11 mmc2_clk 0 O L PD 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS
mcspi3_clk 1 IO
uart4_cts 2 I
gpio_130 4 IO
safe_mode 7
AE11 mmc2_ cmd 0 IO H PU 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS
mcspi3_ 1 IO
simo
uart4_rts 2 O
gpio_131 4 IO
safe_mode 7
AB12 mmc2_ dat0 0 IO H PU 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS
mcspi3_ 1 IO
somi
uart4_tx 2 O
gpio_132 4 IO
safe_mode 7
AC12 mmc2_ dat1 0 IO H PU 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS
uart4_rx 2 I
gpio_133 4 IO
safe_mode 7
AD12 mmc2_ dat2 0 IO H PU 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS
mcspi3_cs1 1 O
Copyright © 2009–2010, Texas Instruments Incorporated TERMINAL DESCRIPTION 27
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Product Folder Link(s): AM3517 AM3505
AM3517, AM3505
SPRS550B–OCTOBER 2009–REVISED JULY 2010
www.ti.com
Table 2-1. Ball Characteristics (ZCN Pkg.) (continued)
BALL PIN NAME MODE [3] TYPE [4] BALL BALL RESET REL. POWER [8] VOLTAGE HYS [10] LOAD (pF) PULL U/D IO CELL [13]
LOCATION [2] RESET RESET REL. MODE [7] [9] [11] TYPE [12]
[1] STATE [5] STATE [6]
gpio_134 4 IO
safe_mode 7
AE12 mmc2_ dat3 0 IO H PU 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS
mcspi3_cs0 1 IO
gpio_135 4 IO
safe_mode 7
AB13 mmc2_ dat4 0 IO L PD 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS
mmc2_dir_da 1 O
t0
mmc3_dat0 3 IO
gpio_136 4 IO
safe_mode 7
AC13 mmc2_ dat5 0 IO L PD 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS
mmc2_dir_da 1 O
t1
mmc3_dat1 3 IO
gpio_137 4 IO
mm_fsusb3_r 6 IO
xdp
safe_mode 7
AD13 mmc2_ dat6 0 IO L PD 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS
mmc2_dir_ 1 O
cmd
mmc3_dat2 3 IO
gpio_138 4 IO
safe_mode 7
AE13 mmc2_ dat7 0 IO L PD 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS
mmc2_ clkin 1 I
mmc3_dat3 3 IO
gpio_139 4 IO
mm_fsusb3_r 6 IO
xdm
safe_mode 7
B24 mcbsp3_dx 0 IO L PD 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS
uart2_cts 1 I
gpio_140 4 IO
safe_mode 7
C24 mcbsp3_dr 0 I L PD 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS
uart2_rts 1 O
gpio_141 4 IO
safe_mode 7
A24 mcbsp3_ 0 IO L PD 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS
C23 mcbsp3_fsx 0 IO L PD 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS
F20 uart2_cts 0 I H PU 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS
F19 uart2_rts 0 O H PU 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS
clkx
uart2_tx 1 O
gpio_142 4 IO
safe_mode 7
uart2_rx 1 I
gpio_143 4 IO
safe_mode 7
mcbsp3_dx 1 IO
gpt9_pwm_e 2 IO
vt
gpio_144 4 IO
safe_mode 7
28 TERMINAL DESCRIPTION Copyright © 2009–2010, Texas Instruments Incorporated
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SPRS550B–OCTOBER 2009–REVISED JULY 2010
Table 2-1. Ball Characteristics (ZCN Pkg.) (continued)
BALL PIN NAME MODE [3] TYPE [4] BALL BALL RESET REL. POWER [8] VOLTAGE HYS [10] LOAD (pF) PULL U/D IO CELL [13]
LOCATION [2] RESET RESET REL. MODE [7] [9] [11] TYPE [12]
[1] STATE [5] STATE [6]
mcbsp3_dr 1 I
gpt10_pwm_ 2 IO
evt
gpio_145 4 IO
safe_mode 7
E24 uart2_tx 0 O H PU 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS
mcbsp3_ 1 IO
clkx
gpt11_pwm 2 IO
_evt
gpio_146 4 IO
safe_mode 7
E23 uart2_rx 0 I H PU 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS
mcbsp3_fsx 1 IO
gpt8_pwm_e 2 IO
vt
gpio_147 4 IO
safe_mode 7
AA19 uart1_tx 0 O L PD 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS
gpio_148 4 IO
safe_mode 7
Y19 uart1_rts 0 O L PD 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS
gpio_149 4 IO
safe_mode 7
Y20 uart1_cts 0 I L PD 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS
gpio_150 4 IO
safe_mode 7
W20 uart1_rx 0 I L PD 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS
mcbsp1_ clkr 2 I
mcspi4_clk 3 IO
gpio_151 4 IO
safe_mode 7
B23 mcbsp4_ 0 IO L PD 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS
A23 mcbsp4_dr 0 I L PD 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS
B22 mcbsp4_dx 0 IO L PD 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS
A22 mcbsp4_fsx 0 IO L PD 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS
R25 mcbsp1_ clkr 0 IO L PD 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS
P21 mcbsp1_fsr 0 IO L PD 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS
clkx
gpio_152 4 IO
mm_fsusb3_t 6 IO
xse0
safe_mode 7
gpio_153 4 IO
mm_fsusb3_r 6 IO
xrcv
safe_mode 7
gpio_154 4 IO
mm_fsusb3_t 6 IO
xdat
safe_mode 7
gpio_155 4 IO
mm_fsusb3_t 6 IO
xen_ n
safe_mode 7
mcspi4_clk 1 IO
gpio_156 4 IO
safe_mode 7
Copyright © 2009–2010, Texas Instruments Incorporated TERMINAL DESCRIPTION 29
Submit Documentation Feedback
Product Folder Link(s): AM3517 AM3505
AM3517, AM3505
SPRS550B–OCTOBER 2009–REVISED JULY 2010
www.ti.com
Table 2-1. Ball Characteristics (ZCN Pkg.) (continued)
BALL PIN NAME MODE [3] TYPE [4] BALL BALL RESET REL. POWER [8] VOLTAGE HYS [10] LOAD (pF) PULL U/D IO CELL [13]
LOCATION [2] RESET RESET REL. MODE [7] [9] [11] TYPE [12]
[1] STATE [5] STATE [6]
gpio_157 4 IO
safe_mode 7
P22 mcbsp1_dx 0 IO L PD 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS
mcspi4_ 1 IO
simo
mcbsp3_dx 2 IO
gpio_158 4 IO
safe_mode 7
P23 mcbsp1_dr 0 I L PD 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS
mcspi4_ 1 IO
somi
mcbsp3_dr 2 I
gpio_159 4 IO
safe_mode 7
P25 mcbsp_clks 0 I L PD 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS
gpio_160 4 IO
uart1_cts 5 I
safe_mode 7
P24 mcbsp1_fsx 0 IO L PD 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS
mcspi4_cs0 1 IO
mcbsp3_fsx 2 IO
gpio_161 4 IO
safe_mode 7
N24 mcbsp1_ 0 IO L PD 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS
N2 uart3_cts_ 0 IO H PU 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS
N3 uart3_rts_ sd 0 O H PU 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS
P1 uart3_rx_ irrx 0 I H PU 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS
P2 uart3_tx_ irtx 0 O H PU 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS
F25 usb0_dp 0 IO 5.0V Yes PU/ PD LVCMOS
F24 usb0_dm 0 IO 5.0V Yes PU/ PD LVCMOS
G24 usb0_vbus 0 A VDDA3P3V_ 5.0V Yes PU/ PD LVCMOS
G25 usb0_id 0 A VDDA3P3V_ 3.3V Yes PU/ PD LVCMOS
E25 usb0_drvvbu 0 O L PD 7 VDDSHV 1.8V/3.3V 30
V2 hecc1_ txd 0 O H PU 7 VDDSHV 1.8V/3.3V Yes 24 PU/ PD LVCMOS
clkx
mcbsp3_ 2 IO
clkx
gpio_162 4 IO
safe_mode 7
rctx
gpio_163 4 IO
safe_mode 7
gpio_164 4 IO
safe_mode 7
gpio_165 4 IO
safe_mode 7
gpio_166 4 IO
safe_mode 7
uart3_tx_ irtx 1 O
uart3_rx_ irrx 1 I
s
uart3_tx_ irtx 2 O
gpio_125 4 IO
safe_mode 7
uart3_rx_ irrx 2 I
gpio_130 4 IO
USBPHY
USBPHY
30 TERMINAL DESCRIPTION Copyright © 2009–2010, Texas Instruments Incorporated
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Product Folder Link(s): AM3517 AM3505
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