Texas Instruments 74AC11032DBLE, 74AC11032D, 74AC11032N, 74AC11032DR, 74AC11032DBR Datasheet
74AC11032
QUADRUPLE 2-INPUT POSITIVE-OR GATE
SCAS007C – JULY 1987 – REVISED APRIL 1996
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
D
Center-Pin VCC and GND Configurations
Minimize High-Speed Switching Noise
D
EPIC
(Enhanced-Performance Implanted
CMOS) 1-µm Process
D
500-mA Typical Latch-Up Immunity at
125°C
D
Package Options Include Plastic
Small-Outline (D) and Shrink Small-Outline
(DB) Packages, and Standard Plastic
300-mil DIPs (N)
description
This device contains four independent 2-input OR gates. It performs the Boolean function
Y+A)BorY+A
• B in positive logic.
The 74AC11032 is characterized for operation from –40°C to 85°C.
FUNCTION TABLE
(each gate)
INPUTS
OUTPUT
A B
Y
H X H
X HH
L L L
logic symbol
†
1
1A
16
1B
1Y
2
15
2A
14
2B
2Y
3
11
3A
10
3B
3Y
6
9
4A
8
4B
4Y
7
≥1
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Copyright 1996, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC is a trademark of Texas Instruments Incorporated.
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
1A
1Y
2Y
GND
GND
3Y
4Y
4B
1B
2A
2B
V
CC
V
CC
3A
3B
4A
D, DB, OR N PACKAGE
(TOP VIEW)
74AC11032
QUADRUPLE 2-INPUT POSITIVE-OR GATE
SCAS007C – JULY 1987 – REVISED APRIL 1996
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
logic diagram (positive logic)
1Y
1A
1B
1
16
2
2Y
2A
2B
15
14
3
3Y
3A
3B
11
10
6
4Y
4A
4B
9
8
7
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
†
Supply voltage range, VCC –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, VI (see Note 1) –0.5 V to VCC + 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output voltage range, VO (see Note 1) –0.5 V to VCC + 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, IIK (VI < 0 or VI > VCC) ±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, I
OK
(VO < 0 or VO > VCC) ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous output current, IO (VO = 0 to VCC) ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous current through VCC or GND ±100 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Maximum power dissipation at TA = 55°C (in still air) (see Note 2):D package 1.3 W. . . . . . . . . . . . . . . . . . . .
DB package 0.55 W. . . . . . . . . . . . . . . . . .
N package 1.1 W. . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
stg
–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The maximum package power dissipation is calculated using a junction temperature of 150_C and a board trace length of 750 mils,
except for the N package, which has a trace length of zero.
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