Texas Instruments 5962-9677001QXA Datasheet

TSB12C01A

Data Manual

IEEE 1394-1995

High-Speed Serial-Bus

Link-Layer Controller

SLLS219B

November 1998

Printed on Recycled Paper

IMPORTANT NOTICE

T exas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue
any product or service without notice, and advise customers to obtain the latest version of relevant information
to verify, before placing orders, that information being relied on is current and complete. All products are sold
subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those
pertaining to warranty, patent infringement, and limitation of liability.

TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.

CERT AIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MA Y INVOLVE POTENTIAL RISKS OF
DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR
WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER
CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICA TIONS IS UNDERST OOD TO
BE FULLY AT THE CUSTOMER’S RISK.

In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.

TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent
that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other
intellectual property right of TI covering or relating to any combination, machine, or process in which such
semiconductor products or services might be or are used. TI’s publication of information regarding any third
party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.

Copyright  1998, Texas Instruments Incorporated

iii

Contents

Section Title Page

1 Overview 1–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.1 Description 1–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.2 Features 1–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.2.1 Link 1–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.2.2 Physical-Link Interface 1–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.2.3 Host Bus Interface 1–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.2.4 General 1–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.3 Terminal Assignments 1–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.4 Terminal Functions 1–4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2 Architecture 2–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.1 Functional Block Diagram 2–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.1.1 Physical Interface 2–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.1.2 Transmitter 2–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.1.3 Receiver 2–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.1.4 Transmit and Receive FIFOs 2–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.1.5 Cycle Timer 2–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.1.6 Cycle Monitor 2–3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.1.7 Cyclic Redundancy Check (CRC) 2–3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.1.8 Internal Registers 2–3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.1.9 Host Bus Interface 2–3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3 Internal Registers 3–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.1 General 3–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.2 Internal Register Definitions 3–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.2.1 Version/Revision Register 3–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.2.2 Node-Address/Transmitter Acknowledge Register 3–3. . . . . . . . . . . . . . . . . . . .

3.2.3 Control Register 3–3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.2.4 Interrupt and Interrupt-Mask Registers 3–5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.2.5 Cycle-Timer Register 3–7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.2.6 Isochronous Receive-Port Number Register 3–8. . . . . . . . . . . . . . . . . . . . . . . . .

3.2.7 Diagnostic Control and Status Register 3–8. . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.2.8 Phy-Chip Access Register 3–8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.2.9 Asynchronous Transmit-FIFO (ATF) Status Register 3–9. . . . . . . . . . . . . . . . . .

3.2.10 ITF Status Register 3–10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.2.11 GRF Status Register 3–10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.3 FIFO Access 3–1 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.3.1 General 3–1 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.3.2 A TF Access 3–12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.3.3 ITF Access 3–12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.3.4 General-Receive-FIFO (GRF) 3–12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.3.5 RAM Test Mode 3–13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

iv

4 TSB12C01A Data Formats 4–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.1 Asynchronous Transmit (Host Bus to TSB12C01A) 4–1. . . . . . . . . . . . . . . . . . . . . . . . .

4.1.1 Quadlet Transmit 4–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.1.2 Block Transmit 4–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.1.3 Quadlet Receive 4–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.1.4 Block Receive 4–3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.2 Isochronous Transmit (Host Bus to TSB12C01A) 4–5. . . . . . . . . . . . . . . . . . . . . . . . . .

4.3 Isochronous Receive (TSB12C01A to Host Bus) 4–5. . . . . . . . . . . . . . . . . . . . . . . . . . .

4.4 Snoop 4–6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.5 CycleMark 4–7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.6 Phy Configuration 4–7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.7 Link-On 4–8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.8 Receive Self-ID 4–9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5 Electrical Characteristics 5–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.1 Absolute Maximum Ratings Over Free-Air Temperature Range 5–1. . . . . . . . . . . . . .

5.2 Recommended Operating Conditions 5–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.3 Electrical Characteristics Over Recommended Ranges of Supply Voltage

and Operating Free-Air Temperature 5–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.4 Host-Interface Timing Requirements 5–3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.5 Host-Interface Switching Characteristics Over Operating Free-Air

Temperature Range 5–3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.6 Phy-Interface Timing Requirements Over Operating Free-Air

Temperature Range 5–3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.7 Phy-Interface Switching Characteristics Over Operating Free-Air

Temperature Range 5–4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.8 Miscellaneous Timing Requirements Over Operating Free-Air

Temperature Range 5–4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.9 Miscellaneous Signal Switching Characteristics Over Operating Free-Air

Temperature Range 5–4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6 Parameter Measurement Information 6–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7 TSB12C01A to 1394 Phy Interface Specification 7–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7.1 Introduction 7–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7.2 Assumptions 7–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7.3 Block Diagram 7–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7.4 Operational Overview 7–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7.4.1 Phy Interface Has Control of the Bus 7–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7.4.2 TSB12C01A Has Control of the Bus 7–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7.5 Request 7–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7.5.1 LREQ Transfer 7–3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7.5.2 Bus Request 7–4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7.5.3 Read/Write Requests 7–4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7.6 Status 7–4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7.6.1 Status Request 7–5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7.6.2 Transmit 7–5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7.6.3 Receive 7–6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7.7 TSB12C01A to Phy Bus Timing 7–6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8 Mechanical Data 8–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

v

List of Illustrations

Figure Title Page

1–1 TSB12C01A Terminal Functions 1–4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2–1 TSB12C01A Block Diagram 2–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3–1 Internal Register Map 3–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3–2 Interrupt Logic Diagram Example 3–6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3–3 TSB12C01A Controller-FIFO-Access Address Map 3–11. . . . . . . . . . . . . . . . . . . . . . . . .

4–1 Quadlet-Transmit Format 4–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4–2 Block-Transmit Format 4–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4–3 Quadlet-Receive Format 4–3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4–4 Block-Receive Format 4–4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4–5 Isochronous-Transmit Format 4–5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4–6 Isochronous-Receive Format 4–5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4–7 Snoop Format 4–6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4–8 CycleMark Format 4–7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4–9 Phy Configuration Format 4–7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4–10 Link-On Format 4–8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4–11 Receive Self-ID Format 4–9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6–1 BCLK Waveform 6–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6–2 Host-Interface Write-Cycle Waveforms 6–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6–3 Host-Interface Read-Cycle Waveforms 6–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6–4 SCLK Waveform 6–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6–5 TSB12C01A-to-Phy-Layer Transfer Waveforms 6–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6–6 Phy Layer-to-TSB12C01A Transfer Waveforms 6–3. . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6–7 TSB12C01A Link-Request-to-Phy-Layer Waveforms 6–3. . . . . . . . . . . . . . . . . . . . . . . . .

6–8 Interrupt Waveform 6–3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6–9 CYCLEIN Waveform 6–4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6–10 CYCLEIN and CYCLEOUT Waveforms 6–4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7–1 Functional Block Diagram of the TSB12C01A to Phy Layer 7–1. . . . . . . . . . . . . . . . . . .

7–2 LREQ Timing 7–6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7–3 Status-Transfer Timing 7–6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7–4 Transmit Timing 7–7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7–5 Receiver Timing 7–7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

vi

List of Tables

Table Title Page

1–1 Terminal Functions 1–4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3–1 Version/Revision Register Field Descriptions 3–3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3–2 Node-Address/Transmitter Acknowledge Register Field Descriptions 3–3. . . . . . . . . .

3–3 Control-Register Field Descriptions 3–3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3–4 Interrupt- and Mask-Register Field Descriptions 3–6. . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3–5 Cycle-Timer Register Field Descriptions 3–8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3–6 Isochronous Receive-Port Number Register Field Descriptions 3–8. . . . . . . . . . . . . . . .

3–7 Diagnostic Control and Status-Register Field Descriptions 3–8. . . . . . . . . . . . . . . . . . . .

3–8 Phy-Chip Access Register 3–9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3–9 ATF Status Register 3–9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3–10 ITF Status Register 3–10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3–11 GRF Status Register 3–10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4–1 Quadlet-Transmit Format 4–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4–2 Block-Transmit Format Functions 4–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4–3 Quadlet-Receive Format Functions 4–3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4–4 Block-Receive Format Functions 4–4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4–5 Isochronous-Transmit Functions 4–5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4–6 Isochronous-Receive Functions 4–6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4–7 Snoop Functions 4–6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4–8 CycleMark Functions 4–7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4–9 Phy Configuration Functions 4–8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4–10 Link-On Functions 4–8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4–11 Isochronous-Receive Functions 4–9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7–1 Phy Interface Control of Bus Functions 7–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7–2 TSB12C01A Control of Bus Functions 7–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7–3 Request Functions 7–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7–4 Bus-Request Functions (Length of Stream: 7 Bits) 7–2. . . . . . . . . . . . . . . . . . . . . . . . . . .

7–5 Read-Register Request Functions (Length of Stream: 9 Bits) 7–3. . . . . . . . . . . . . . . . .

7–6 Write-Register Request (Length of Stream: 17 Bits) 7–3. . . . . . . . . . . . . . . . . . . . . . . . . .

7–7 TSB12C01A Request Functions 7–3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7–8 TSB12C01A Request-Speed Functions 7–3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7–9 Status-Request Functions (Length of Stream: 16 Bits) 7–5. . . . . . . . . . . . . . . . . . . . . . .

7–10 Speed Code for Receive 7–6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1–1

1 Overview

1.1 Description

The TSB12C01A is an IEEE 1394-1995 standard (from now on referred to only as 1394) high-speed
serial-bus link-layer controller that allows for easy integration into an I/O subsystem. The TSB12C01A
transmits and receives correctly formatted 1394 packets and generates and inspects the 32-bit cyclic
redundancy check (CRC). The TSB12C01A is capable of being a cycle master and supports reception of
isochronous data on two channels. It interfaces directly to the TSB11C01, TSB11LV01, and TSB21LV03
physical-layer chips and can support bus speeds of 100, 200, and 400 Mb/s. The TSB12C01A has a generic
32-bit host bus interface, which makes connection to most 32-bit host buses very simple. The TSB12C01A
has software-adjustable FIFOs for optimal FIFO size and performance characterization and allows for
variable-size asynchronous-transmit FIFO (ATF), isochronous-transmit FIFO (ITF), and general-receive
FIFO (GRF).

This document is not intended to serve as a tutorial on 1394; users should refer to the IEEE 1394-1995 serial
bus for detailed information regarding the 1394 high-speed serial bus.

1.2 Features

The following are features of the TSB12C01A.

1.2.1 Link

• Complies With IEEE-1394-1995 Standard

• Transmits and Receives Correctly Formatted 1394 Packets

• Supports Isochronous Data Transfer

• Performs Function of Cycle Master

• Generates and Checks 32-Bit CRC

• Detects Lost Cycle-Start Messages

• Contains Asynchronous, Isochronous, and General-Receive FIFOs

1.2.2 Physical-Link Interface

• Interfaces Directly to the TSB11C01, TSB11LV01, TSB14C01, and TSB21LV03 Phy Chips

• Supports Speeds of 100, 200, and 400 Mb/s

• Implements the Physical-Link Interface Described in Annex J of the IEEE 1394-1995 Standard

• Supports TI Bus Holder Isolation External Implementation

1.2.3 Host Bus Interface

• Provides Chip Control With Directly Addressable Registers

• Is Interrupt Driven to Minimize Host Polling

• Has a Generic 32-Bit Host Bus Interface

1.2.4 General

•

Requires a Single 5-V ±5% Power Supply

• Manufactured with Low-Power CMOS Technology

• Packaged in a 100-Pin Thin Quad Flat Package (TQFP) (PZ Package) for 0°C to 70°C and –40°C

to 85°C Operation

• Packaged in a 100-Pin Ceramic Quad Flat Package (WN Package) for –55°C to 125°C Operation

1–2

1.3 Terminal Assignments

76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100

50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26

12345678910111213141516171819202122232425

75747372717069686766656463626160595857565554535251

GND

DATA16

DATA17

DATA18

DATA19

DATA20

DATA21

DATA22

DATA23

GND

DATA24

DATA25

DATA26

DATA27

DATA28

DATA29

DATA30

DATA31

GND

ADDR0

ADDR1

ADDR2

ADDR3

Reserved

NTCLK

NTOUT

NTBIHIZ

GND

ISO

GND

LREQ

GND

SCLK

CTL0

CTL1

GNDD0D1D2D3D4D5D6D7

GND

CYST
CYDNE
GRFEMP
GND
GND
GND
CYCLEOUT
V

CC

CYCLEIN
GND
GND
RESET
GND
INT
WR
CA
CS
V

CC

BCLK
GND
ADDR7
ADDR6
ADDR5
ADDR4
V

CC

POWERON

RAMEz

GND
GND
GND

GND
DATA0
DATA1
DATA2
DATA3

V

CC

DATA4
DATA5
DATA6
DATA7

GND
DATA8
DATA9

DATA10
DATA11

V

CC

DATA12
DATA13
DATA14
DATA15

V

V

CC

CC

V

V

V

CC

CC

CC

To Host

To Phy Layer

NOTES: A. Tie reserved terminals to GND.

TSB12C01A

PZ PACKAGE

(TOP VIEW)

B. Bit 0 is the most significant bit (MSB).

1–3

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25

75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51

GND
DATA16
DATA17
DATA18
DATA19

DATA20
DATA21
DATA22
DATA23

GND
DATA24
DATA25
DATA26
DATA27

DATA28
DATA29
DATA30
DATA31

GND

ADDR0
ADDR1
ADDR2
ADDR3

Reserved
NTCLK

NTOUT
NTBIHIZ
GND
ISO
GND
LREQ
GND
SCLK

CTL0
CTL1
GND
D0
D1
D2
D3

D4
D5
D6
D7
GND

V

V

CC

CC

V

V

V

CC

CC

CC

NOTES: A. Tie reserved terminals to GND.

TSB12C01AM

WN PACKAGE

(TOP VIEW)

B. Bit 0 is the most significant bit (MSB).

DATA15

DATA13

DATA12

DATA11

DATA10

DATA8

GND

DATA7

DATA5

DATA0

GND

GND

GND

RAMEz

DATA14

GND

DATA1

DATA9

DATA6

DATA4

DATA3

DATA2

ADDR4

ADDR5

ADDR6

ADDR7

BCLK

CS

CA

INT

GND

RESET

GND

CYCLEIN

CYCLEOUT

GND

GND

GRFEMP

CYDNE

CYST

GND

GND

V

CC

GND

V

CC

V

CC

WR

V

CC

POWERON

V

CC

76

77

78

79

80

81

82

83

84

85

86

87

88

89

90

91

92

93

94

95

96

97

98

99

100

50

49

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

1–4

1.4 Terminal Functions

Phy Interface

D0 – D7
CTL0
CTL1
LREQ
ISO
SCLK

DATA0 – DATA31
ADDR0 – ADDR7

CS

CA
WR
INT

CYCLEIN

CYCLEOUT

BCLK
RESET
RAMEz

V

CC

GND

Host
Bus

10

20

TSB12C01A

NTCLK
NTOUT

NTBIHIZ

CYST
CYDNE
GRFEMP

POWERON

Figure 1–1. TSB12C01A Terminal Functions

Table 1–1. Terminal Functions

TERMINAL

NAME NO.

I/O

DESCRIPTION

Host Bus Interface

ADDR0 –
ADDR7

22–25
27–30

I Address 0 through address 7. Host bus address bus bits 0 through 7 that address

the quadlet-aligned FIFOs and configuration registers. The two least significant
address lines, 6 and 7, must be grounded.

CA 35 O Cycle acknowledge (active low). CA is a TSB12C01A control signal to the host bus.

When asserted (low), access to the configuration registers or FIFO is complete.

CS 34 I

Cycle start (active low). CS is a host bus control signal to enable access to the
configuration registers or FIFO.

DATA0 –
DATA31

2–5

7–10
12–15
17–20
82–85
87–90
92–95

97–100

I/O Data 0 through 31. DATA is a host bus data bus bits 0 through 31.

INT 37 O

Interrupt (active low). When INT is asserted (low), the TSB12C01A notifies the host
bus that an interrupt has occurred.

WR 36 I

Read/write enable. When WR is deasserted (high) in conjunction with CS, a read
from the TSB12C01A is requested. When WR

is asserted (low) in conjunction with

CS

, a write to the TSB12C01A is requested.

1–5

Table 1–1. Terminal Functions (Continued)

TERMINAL

NAME NO.

I/O

DESCRIPTION

Phy Interface

CTL1, CTL0 62, 63 I/O Control 1 and control 0 of the phy-link control bus. CTL1 and CTL0 indicate the four

operations that can occur in this interface (see Section 7 of this document or Annex
J of the IEEE 1394-1995 standard for more information about the four operations).

D0 – D7 52–55

57–60

I/O Data 0 through data 7 of the phy-link data bus. Data is expected on D0 – D1 for

100 Mb/s packets, D0 – D3 for 200 Mb/s, and D0 – D7 for 400 Mb/s.

ISO 69 I

Isolation barrier (active low). This ISO is asserted (low) when an isolation barrier is
present.

LREQ 67 O Link request. LREQ is a TSB12C01A output that makes bus requests and accesses

the phy layer.

POWERON 76 O Power on indicator to phy interface. When active, POWERON has a clock output with

1/32 of the BCLK frequency and indicates to the phy interface that the TSB12C01A
is powered. This terminal can be connected to the link power status (LPS) terminal
on the TI phy devices to provide an indication of the LLC power condition.

SCLK 65 I System clock. SCLK is a 49.152-MHz clock from the phy, that generates the

24.576-MHz clock.

Miscellaneous Signals

BCLK 32 I Bus clock. BCLK is the host bus clock used in the host-interface module of the

TSB12C01A. It is asynchronous to SCLK.

CYCLEIN 42 I Cycle in. CYCLEIN is an optional external 8,000-Hz clock used as the cycle clock,

and it should only be used when attached to the cycle-master node. It is enabled by
the cycle source bit and should be tied high when not used.

CYCLEOUT 44 O Cycle out. CYCLEOUT is the TSB12C01A version of the cycle clock. It is based on

the timer controls and received cycle-start messages.

CYDNE 49 O Status of CyDne bit. When the RevAEn bit of the control register is set, CYDNE

indicates the value of the CyDne bit of the interrupt register. When RevAEn is cleared,
CYDNE is a 3-state output.

CYST 50 O Status of CySt bit. When the RevAEn bit of the control register is set, CYST indicates

the value of the CySt bit of the interrupt register. When RevAEn is cleared, CYST is
a 3-state output.

GND 1, 11,

21, 31,
38, 40,

41,
45–47,
51, 61,
66, 68,

70,
78–81,

91

Ground reference

GRFEMP 48 O Status of Empty bit. When the RevAEn bit of the control register is set, GRFEMP

indicates the value of the Empty bit of the GRF status register. When RevAEn is
cleared, GRFEMP is a 3-state output.

RAMEz 77 I RAM 3-state enable. When RAMEz is deasserted (low), FIFOs are enabled. When

RAMEz is asserted, the FIFOs are 3-state outputs. (This is a manufacturing
test-mode condition and should be grounded under normal operating conditions.)

1–6

Table 1–1. Terminal Functions (Continued)

TERMINAL

NAME NO.

I/O

DESCRIPTION

NTBIHIZ 71 I NAND-tree bidirectional 3-state output. When NTBIHIZ is deasserted (low), the

bidirectional I/Os operate in a normal state. When NTBIHZ is asserted (high), the
bidirectional I/Os are in the 3-state output mode. (This is a manufacturing
test-mode condition and should be grounded under normal operating conditions.)

NTCLK 73 I NAND clock input. The NAND-tree clock is used for VIH and VIL manufacturing

tests. (This input should be grounded under normal operating conditions.)

NTOUT 72 O NAND-tree output. This output should remain open under normal operating

conditions.
RESET 39 I Reset (active low). RESET is the asynchronous reset to the TSB12C01A.
V

CC

6, 16, 26,
33, 43, 56,
64, 74, 86,

96

5-V ±5% power supplies

2–1

2 Architecture

2.1 Functional Block Diagram

The functional block architecture of the TSB12C01A is shown in Figure 2–1.

Transmitter

Cycle Timer

Cycle Monitor

CRC

Receiver

Configuration Registers

GRF

ITF

ATF

P
h
y
s

i
c
a

l

I
n

t
e

r

f
a
c
e

H

o
s

t

I

n

t

e

r

f
a
c
e

Figure 2–1. TSB12C01A Block Diagram

2.1.1 Physical Interface

The physical (phy) interface provides phy-level services to the transmitter and receiver. This includes
gaining access to the serial bus, sending packets, receiving packets, and sending and receiving
acknowledge packets.

The phy interface module also interfaces to the phy chip and conforms to the phy-link interface specification
described in Annex J of the IEEE 1394-1995 standard (refer to Section 7 of this document for more
information).

2.1.2 Transmitter

The transmitter retrieves data from either the ATF or the ITF and creates correctly formatted serial-bus
packets to be transmitted through the phy interface. When data is present at the ATF interface to the
transmitter, the TSB12C01A phy interface arbitrates for the serial bus and sends a packet. When data is
present at the ITF interface to the transmitter, the TSB12C01A arbitrates for the serial bus during the next
isochronous cycle. The transmitter autonomously sends the cycle-start packets when the chip is a cycle
master.

2–2

2.1.3 Receiver

The receiver takes incoming data from the phy interface and determines if the incoming data is addressed
to this node. If the incoming packet is addressed to this node, the CRC of the packet is checked. If the header
CRC is good, the header is confirmed in the GRF . For block and isochronous packets, the remainder of the
packet is confirmed one quadlet at a time. The receiver places a status quadlet in the GRF after the last
quadlet of the packet is confirmed in the GRF . The status quadlet contains the error code for the packet. The
error code is the acknowledge code that is sent for that packet. For broadcast packets that do not need
acknowledge packets, the error code is the acknowledge code that would have been sent. This
acknowledge code tells the transaction layer whether or not the data CRC is good or bad. When the header
CRC is bad, the header is flushed and the rest of the packet is ignored.

When a cycle-start message is received, it is detected and the cycle-start message data is sent to the cycle
timer. The cycle-start messages are not placed in the GRF like other quadlet packets. At the end of an
isochronous cycle and if the cycle mark enable (CyMrkEn) bit of the control register is set , the receiver
inserts a cycle-mark packet in the GRF to indicate the end of the isochronous cycle.

2.1.4 Transmit and Receive FIFOs

The TSB12C01A contains two transmit FIFOs (asynchronous and isochronous) and one receive FIFO
(general receive). Each of these FIFOs is one quadlet wide and their length is software adjustable. These
software-adjustable FIFOs allow customization of the size of each FIFO for individual applications. The sum
of all FIFOs cannot be larger than 509 quadlets. To understand how to set the size of the FIFOs, see
subsections 3.2.11 through 3.2.13. The transmit FIFOs are write only from the host bus interface, and the
receive FIFO is read only from the host bus interface.

An example of how to use software-adjustable FIFOs follows:
In applications where isochronous packets are large and asynchronous packets are small, the implementer

can set the ITF and GRF to a large size (200 quadlets each) and set the ATF to a smaller size (100 quadlets).
Notice that the sum of all FIFOs is less than or equal to 509 quadlets.

2.1.5 Cycle Timer

The cycle timer is used by nodes that support isochronous data transfer. The cycle timer is a 32-bit
cycle-timer register. Each node with isochronous data-transfer capability has a cycle-timer register as
defined in the IEEE 1394-1995 standard. In the TSB12C01A, the cycle-timer register is implemented in the
cycle timer and is located in IEEE-1212 initial register space at location 200h and can also be accessed
through the local bus at address 14h. The low-order 12 bits of the timer are a modulo 3072 counter, which
increments once every 24.576-MHz clock periods (or 40.69 ns). The next 13 higher-order bits are a count
of 8, 000-Hz (or 125 µs)cycles, and the highest 7 bits count seconds.

The cycle timer contains the cycle-timer register. The cycle-timer register consists of three fields: cycle
offset, cycle count, and seconds count. The cycle timer has two possible sources. First, if the cycle source
(CySrc) bit in the configuration register is set, then the CYCLEIN input causes the cycle count field to
increment for each positive transition of the CYCLEIN input (8 kHz) and the cycle offset resets to all zeros.
CYCLEIN should only be the source when the node is cycle master. When the cycle-count field increments,
CYCLEOUT is generated. The timer can also be disabled using the cycle-timer-enable bit in the control
register. See subsection 3.2.5 for more information.

The second cycle-source option is when the CySrc bit is cleared. In this state, the cycle-offset field of the
cycle-timer register is incremented by the internal 24.576-MHz clock. The cycle timer is updated by the
reception of the cycle-start packet for the noncycle master nodes. Each time the cycle-offset field rolls over ,
the cycle-count field is incremented and the CYCLEOUT signal is generated. The cycle-offset field in the
cycle-start packet is used by the cycle-master node to keep all nodes in phase and running with a nominal
isochronous cycle of 125 µs.

2–3

CYCLEOUT indicates to the cyclemaster node that it is time to send a cycle-start packet. And, on
noncyclemaster nodes, CYCLEOUT indicates that it is time to expect a cycle-start packet. The cycle-start
bit is set when the cycle-start packet is sent from the cyclemaster node or received by a noncyclemaster
node.

2.1.6 Cycle Monitor

The cycle monitor is only used by nodes that support isochronous data transfer. The cycle monitor observes
chip activity and handles scheduling of isochronous activity. When a cycle-start message is received or sent,
the cycle monitor sets the cycle-started interrupt bit. It also detects missing cycle-start packets and sets the
cycle-lost interrupt bit when this occurs. When the isochronous cycle is complete, the cycle monitor sets the
cycle-done-interrupt bit. The cycle monitor instructs the transmitter to send a cycle-start message when the
cycle-master bit is set in the control register.

2.1.7 Cyclic Redundancy Check (CRC)

The CRC module generates a 32-bit CRC for error detection. This is done for both the header and data. The
CRC module generates the header and data CRC for transmitting packets and checks the header and data
CRC for received packets. See the IEEE 1394-1995 standard for details on the generation of the CRC

†

.

2.1.8 Internal Registers

The internal registers control the operation of the TSB12C01A. The register definitions are specified in
Section 3.

2.1.9 Host Bus Interface

The host bus interface allows the TSB12C01A to be easily connected to most host processors. This host
bus interface consists of a 32-bit data bus and an 8-bit address bus. The TSB12C01A utilizes cycle-start
and cycle-acknowledge handshake signals to allow the local bus clock and the 1394 clock to be
asynchronous to one another. The TSB12C01A is interrupt driven to reduce polling.

†

This is the same CRC used by the IEEE802 LANs and the X3T9.5 FDDI.

2–4

3–1

3 Internal Registers

3.1 General

The host-bus processor directs the operation of the TSB12C01A through a set of registers internal to the
TSB12C01A itself. These registers are read or written by asserting CS

with the proper address on ADDR0

– ADDR7 and asserting or deasserting WR

depending on whether a read or write is needed. Figure 3–1 lists

the register addresses; subsequent sections describe the function of the various registers.

3.2 Internal Register Definitions

The TSB12C01A internal registers control the operation of the TSB12C01A. The bit definitions of the internal
registers are shown in Figure 3–1 and are described in subsections 3.2.1 through 3.2.13.

3–2

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 29 30 31

00h

Interrupt

CmdRstCmdRst

ENSpRdPhy

PSBz

ATAck

IntInt IdVal

PhIntPhInt RxSId

PhRRxPhRRx

TxRdyTxRdy

RxDtaRxDta

PhRstPhRst

BsyFlWrPhy

ArbGp

FrGp

regRW

TxEn

RxEn

RstRx

PSOn

PSRO

RstTx

ITStk

ATStk

SntRj

HdrEr

TCErr

ITStk

ATStk

SntRj

HdrEr

TCErr

CyDne

CySec

CySt

CyPnd

CyLst

CArbFl

CyDne

CySec

CySt

CyPnd

CyLst

CArbFl

IArbFl IArbFl

Full

AlF

Full

AlF

Full

AlF

4AV4AV

AIEAIEAIE

EmptyEmptyEmpty

ClrClrClr

cd

4Th

PhyRgAd PhyRxAd

Version
Node

Address

Control

Reserved

Cycle
Timer

Interrupt
Mask

Isoch Port
Number

Diagnostics

Phy Chip
Access

Reserved
Reserved

ATF Status

ITF Status

Reserved

GRF Status

Reserved

BlkBusDep

ATRC

CyTEn

CyMas

CySrc

IRP1En

IRP2En

04h

08h

0Ch

10h

14h

18h

1Ch

20h

24h

28h

2Ch

30h

34h

38h

3Ch

40h

28

CyMrkEn

RevAEn

7 Bits

Adr_clr

Control_bit1

Control_bit_err

RAM Test

IR Port1

Seconds Count

BsyCtrl

Bus Number

TAGTAG

Rollover @ 8000

Cycle Count

13 Bits Rollover @ 3072 12 Bits

IR Port2

Node Number

Version

PhyRgData

Revision

Cycle Offset

PhyRxData

Size

Size

Size

NOTE A: All gray areas (bits) are reserved bits.

Figure 3–1. Internal Register Map

3.2.1 Version/Revision Register

The version/revision register allows software to be written that supports multiple versions of the high-speed
serial-bus link-layer controllers. This register is at address 00h and is read only. The initial value is
3031_3041h.