Texas Instruments CY74FCT574TSOCT, CY74FCT574TSOC, CY74FCT574TQCT, CY74FCT574TQC, CY74FCT574CTSOCT Datasheet
...
8-Bit Registers
CY54/74FCT374T
CY54/74FCT574T
SCCS022 - May 1994 - Revised February 2000
Data sheet acquired from Cypress Semiconductor Corporation.
Data sheet modified to remove devices not offered.
Copyright © 2000, Texas Instruments Incorporated
Features
• Function, pinout, and drive compatible with FCT and
F logic
• FCT-C speed at 5.2 ns max. (Com’l)
FCT-A speed at 6.5 ns max. (Com’l)
• Reduced V
OH
(typically = 3.3V) versions of equivalent
FCT functions
• Edge-rate control circuitry for significantly improved
noise characteristics
• Power-off disable feature
• Matched rise and fall times
• Fully compatible with TTL input and output logic levels
• ESD > 2000V
• Extended commercial range of −40˚C to +85˚C
• Sink Current 64 mA (Com’l), 32 mA (Mil)
Source Current 32 mA (Com’l), 12 mA (Mil)
• Edge-triggered D-type inputs
• 250 MHz typical toggle rate
1CY54/74FCT574T
Logic Block Diagram
Pin Configurations
FCT374T–1
4
8
9
10
11
12
765
1516 17 18
3
2
1
20
13
14
19
D3D2O
1
D
6
D
5
D
7
CP
V
CC
GND
O
5
Top View
D
1
LCC
OE
O
0
D
0
O
3
D
4
O
4
1
2
3
4
5
6
7
8
9
10
11
12
16
17
18
19
20
13
14
V
CC
FCT374T–2
15
DIP/SOIC/QSOP
Top View
O
6
O
2
O
7
O
0
D
0
D
1
O
2
D
2
D
3
O
3
D
7
D
6
O
6
O
5
D
5
D
4
O
4
CP
OE
GND
O
7
O
1
FCT374T–3
4
8
9
10
11
12
765
1516 17 18
3
2
1
20
13
14
19
D6D5D
3
O
2
O
5
O
1
CP
V
CC
GND
O
4
Top View
D
2
LCC
OE
D
0
D
1
D
7
O
6
O
7
1
2
3
4
5
6
7
8
9
10
11
12
16
17
18
19
20
13
14
V
CC
FCT374T–4
15
DIP/SOIC/QSOP
Top View
O
3
D
4
O
0
D
0
D
1
D
2
D
4
D
5
D
6
D
7
O
1
O
2
O
3
O
4
O
5
O
6
O
7
CP
OE
GND
O
0
D
3
FCT374T
FCT374T–5
CP
OE
D
0
O
0
D
1
O
1
D
2
O
2
D
3
O
3
D
4
O
4
D
5
O
5
D
6
O
6
D
7
O
7
FCT374T–6
CP
D
O
0
D
0
CP
OE
CP D
O
1
D
1
CP D
O
2
D
2
CP D
O
3
D
3
CP D
O
4
D
4
CP D
O
5
D
5
CP D
O
6
D
6
CP D
O
7
D
7
QQQQQQQQ
Logic Symbol
FCT374T
FCT574T
FCT574T
CY54/74FCT374T
CY54/74FCT574T
2
Functional Description
The FCT374T and FCT574T are high-speed low-power octal
D-type flip-flops featuring separate D-type inputs for each
flip-flop.Bothdeviceshavethree-stateoutputs for busoriented
applications.A buffered clock(CP)and output enable (
OE)are
common to all flip-flops. The FCT574T is identical to FCT374T
except for flow-through pinout to simplify board design. The
eight flip-flops contained in the FCT374T and FCT574T will
store the state of their individual D inputs that meet the set-up
and hold time requirements on the LOW-to-HIGH clock (CP)
transition.When
OE is LOW, the contents of the eight flip-flops
areavailableat the outputs.When
OEisHIGH,theoutputs will
be in the high-impedance state. The state of output enable
does not affect the state of the flip-flops.
The outputs are designed with a power-off disable feature to
allow for liv e insertion of boards.
Maximum Ratings
[2, 3]
(Above which the useful life may be impaired. For user guidelines, not tested.)
Storage Temperature ..................................-65°C to +150°C
Ambient Temperature with
Power Applied.............................................–65°C to +135°C
Supply Voltage to Ground Potential............... –0.5V to +7.0V
DC Input Voltage ........................................... –0.5V to +7.0V
DC Output Voltage......................................... –0.5V to +7.0V
DC Output Current (Maximum Sink Current/Pin) ......120 mA
Power Dissipation..........................................................0.5W
Static Discharge Voltage............................................>2001V
(per MIL-STD-883, Method 3015)
Function Table
[1]
Inputs Outputs
D CP OE O
H L H
L L L
X X H Z
Operating Range
Range Range
Ambient
Temperature V
CC
Commercial T, AT, CT –40°C to +85°C 5V ± 5%
Military
[4]
All –55°C to +125°C 5V ± 10%
Electrical Characteristics Over the Operating Range
Parameter Description Test Conditions Min. Typ.
[5]
Max. Unit
V
OH
Output HIGH Voltage VCC=Min., IOH=–32 mA Com’l 2.0 V
VCC=Min., IOH=–15 mA Com’l 2.4 3.3 V
VCC=Min., IOH=–12 mA Mil 2.4 3.3 V
V
OL
Output LOW Voltage VCC=Min., IOL=64 mA Com’l 0.3 0.55 V
VCC=Min., IOL=32 mA Mil 0.3 0.55 V
V
IH
Input HIGH Voltage 2.0 V
V
IL
Input LOW Voltage 0.8 V
V
H
Hysteresis
[6]
All inputs 0.2 V
V
IK
Input Clamp Diode Voltage VCC=Min., IIN=–18 mA –0.7 –1.2 V
I
I
Input HIGH Current VCC=Max., VIN=V
CC
5 µA
I
IH
Input HIGH Current VCC=Max., VIN=2.7V ±1 µA
I
IL
Input LOW Current VCC=Max., VIN=0.5V ±1 µA
I
OZH
Off State HIGH-Level Output
Current
VCC= Max., V
OUT
= 2.7V 10 µA
I
OZL
Off State LOW-Level
Output Current
VCC = Max., V
OUT
= 0.5V –10 µA
I
OS
Output Short Circuit Current
[7]
VCC=Max., V
OUT
=0.0V –60 –120 –225 mA
I
OFF
Power-Off Disable VCC=0V, V
OUT
=4.5V ±1 µA
Notes:
1. H = HIGH Voltage Level. L = LOW Voltage Level X = Don’t Care Z = HIGH Impedance = LOW-to-HIGH clock transition
2. Unless otherwise noted, these limits are over the operating free-air temperature range.
3. Unused inputs must always be connected to an appropriate logic voltage level, preferably either V
CC
or ground.
4. T
A
is the “instant on” case temperature.
5. Typical values are at V
CC
=5.0V, TA=+25˚C ambient.
6. This parameter is specified but not tested.
7. Not more than one output should be shorted at a time. Duration of short should not exceedone second. The use of high-speed test apparatus and/or sample
and hold techniques are preferablein order to minimize internal chip heating and more accurately reflect operational values. Otherwise prolonged shortingof
a high output may raise the chip temperature well above normal and thereby cause invalidreadings in other parameters tests. In any sequence of parameter
tests, I
OS
tests should be performed last.
CY54/74FCT374T
CY54/74FCT574T
3
Capacitance
[2]
Parameter Description Typ.
[5]
Max. Unit
C
IN
Input Capacitance 5 10 pF
C
OUT
Output Capacitance 9 12 pF
Power Supply Characteristics
Parameter Description Test Conditions Typ.
[5]
Max. Unit
I
CC
Quiescent Power Supply Current VCC=Max., VIN≤0.2V, VIN≥VCC–0.2V 0.1 0.2 mA
∆I
CC
Quiescent Power Supply Current
(TTL inputs HIGH)
VCC=Max., VIN=3.4V,
[8]
f1=0, Outputs Open
0.5 2.0 mA
I
CCD
Dynamic Power Supply Current
[9]
VCC=Max., One Bit Toggling,
50% Duty Cycle, Outputs Open,
OE=GND, VIN≤0.2V or VIN≥VCC–0.2V
0.06 0.12 mA/MHz
I
C
Total Power Supply Current
[10]
VCC=Max., f0=10 MHz,
50% Duty Cycle, Outputs Open,
One Bit Toggling at f
1
=5 MHz,
OE=GND, VIN≤0.2V or VIN≥VCC–0.2V
0.7 1.4 mA
VCC=Max., f0=10 MHz,
50% Duty Cycle, Outputs Open,
One Bit Toggling at f
1
=5 MHz,
OE=GND, VIN=3.4V or VIN=GND
1.2 3.4 mA
VCC=Max., f0=10 MHz,
50% Duty Cycle, Outputs Open,
Eight Bits Toggling at f
1
=2.5 MHz,
OE=GND, VIN≤0.2V or VIN≥VCC–0.2V
1.6 3.2
[11]
mA
VCC=Max., f0=10 MHz,
50% Duty Cycle, Outputs Open,
Eight Bits Toggling at f
1
=2.5 MHz,
OE=GND, VIN=3.4V or VIN=GND
3.9 12.2
[11]
mA
Notes:
8. Per TTL driven input (V
IN
=3.4V); all other inputs at VCC or GND.
9. This parameter is not directly testable, but is derived for use in Total Power Supply calculations.
10. I
C
=I
QUIESCENT
+ I
INPUTS
+ I
DYNAMIC
IC=ICC+∆ICCDHNT+I
CCD(f0
/2 + f1N1)
I
CC
= Quiescent Current with CMOS input levels
∆I
CC
= Power Supply Current for a TTL HIGH input (VIN=3.4V)
D
H
= Duty Cycle for TTL inputs HIGH
N
T
= Number of TTL inputs at D
H
I
CCD
= Dynamic Current caused by an input transition pair (HLH or LHL)
f
0
= Clock frequency for registered devices, otherwise zero
f
1
= Input signal frequency
N
1
= Number of inputs changing at f
1
All currents are in milliamps and all frequencies are in megahertz.
11. Values for these conditions are examples of the ICC formula. These limits are specified but not tested.
Loading...