Texas Instruments CY74FCT573CTQC, CY74FCT573ATSOCT, CY74FCT573ATSOC, CY74FCT573ATQC, CY74FCT573ATPC Datasheet
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8-Bit Latches
CY54/74FCT373T
CY54/74FCT573T
SCCS021 - May 1994 - Revised February 2000
Data sheet acquired from Cypress Semiconductor Corporation.
Data sheet modified to remove devices not offered.
Copyright © 2000, Texas Instruments Incorporated
Features
• Function and pinout compatible with FCT, and F logic
• FCT-C speed at 4.2 ns max. (Com’l),
FCT-A speed at 5.2 ns max. (Com’l)
• Reduced V
OH
(typically = 3.3V) versions of equivalent
FCT functions
• Edge-rate control circuitry for significantly improved
noise characteristics
• Power-off disable feature
• ESD > 2000V
• Matched rise and fall times
• Extended commercial range of −40˚C to +85˚C
• Fully compatiblewith TTL input and output logic levels
• Sink current 64 mA (Com’l), 32 mA (Mil)
Source current 32 mA (Com’l), 12 mA (Mil)
Functional Description
The FCT373T and FCT573T consist of eight latches with
three-state outputs for bus organizedapplications. Whenlatch
enable (LE) is HIGH, the flip-flops appear transparent to the
data. Data that meets the required set-up times are latched
when LE transitions from HIGH to LOW.Data appears on the
bus when the (
OE) is LOW. When output enable is HIGH, the
bus output is in the impedance state. In this mode, data may
be entered into the latches. The FCT573T is identical to the
FCT373T except for the flow-through pinout, which simplifies
board design.
The outputs are designed with a power-off disable feature to
allow for live insertion of boards.
Logic Block Diagram
Pin Configurations
1
2
3
4
5
6
7
8
9
10 11
12
16
17
18
19
20
13
14
V
CC
15
DIP/SOIC/QSOP
Top View
O
0
D
0
D
1
O
2
D
2
D
3
O
3
D
7
D
6
O
6
O
5
D
5
D
4
O
4
LE
OE
GND
O
7
O
1
1
2
3
4
5
6
7
8
9
10 11
12
16
17
18
19
20
13
14
V
CC
15
DIP/SOIC/QSOP
Top View
D
0
D
1
D
2
D
4
D
5
D
6
D
7
O
1
O
2
O
3
O
4
O
5
O
6
O
7
LE
OE
GND
O
0
D
3
LE
OE
D
0
O
0
D
1
O
1
D
2
O
2
D
3
O
3
D
4
O
4
D
5
O
5
D
6
O
6
D
7
O
7
CP D
Q
O
0
D
0
LE
OE
CP D
Q
O
1
D
1
CP D
Q
O
2
D
2
CP D
Q
O
3
D
3
CP D
Q
O
4
D
4
CP D
Q
O
5
D
5
CP D
Q
O
6
D
6
CP D
Q
O
7
D
7
FCT373T
FCT573T
Logic Symbol
CY54/74FCT373T
CY54/74FCT573T
2
Maximum Ratings
[2, 3]
(Above which the useful life may be impaired. For user guidelines, not tested.)
Storage Temperature .................................–65°C to +150°C
Ambient Temperature with
Power Applied.............................................–65°C to +135°C
Supply Voltage to Ground Potential............... –0.5V to +7.0V
DC Input Voltage ........................................... –0.5V to +7.0V
DC Output Voltage......................................... –0.5V to +7.0V
DC Output Current (Maximum Sink Current/Pin) ......120 mA
Power Dissipation..........................................................0.5W
Static Discharge Voltage............................................>2001V
(per MIL-STD-883, Method 3015)
Function Table
[1]
Inputs Outputs
OE LE D O
L H H H
L H L L
L L X Q
0
H X X Z
Operating Range
Range Range
Ambient
Temperature V
CC
Commercial T, AT, CT –40°C to +85°C 5V ± 5%
Military
[4]
All –55°C to +125°C 5V ± 10%
Electrical Characteristics Over the Operating Range
Parameter Description Test Conditions Min. Typ.
[5]
Max. Unit
V
OH
Output HIGH Voltage VCC=Min., IOH=–32 mA Com’l 2.0 V
VCC=Min., IOH=–15 mA Com’l 2.4 3.3 V
VCC=Min., IOH=–12 mA Mil 2.4 3.3 V
V
OL
Output LOW Voltage VCC=Min., IOL=64 mA Com’l 0.3 0.55 V
VCC=Min., IOL=32 mA Mil 0.3 0.55 V
V
IH
Input HIGH Voltage 2.0 V
V
IL
Input LOW Voltage 0.8 V
V
H
Hysteresis
[6]
All inputs 0.2 V
V
IK
Input Clamp Diode Voltage VCC=Min., IIN=–18 mA –0.7 –1.2 V
I
I
Input HIGH Current VCC=Max., VIN=V
CC
5 µA
I
IH
Input HIGH Current VCC=Max., VIN=2.7V ±1 µA
I
IL
Input LOW Current VCC=Max., VIN=0.5V ±1 µA
I
OZH
Off State HIGH-Level Output
Current
VCC=Max., V
OUT
=2.7V 10 µA
I
OZL
Off State LOW-Level
Output Current
VCC=Max., V
OUT
=0.5V –10 µA
I
OS
Output Short Circuit Current
[7]
VCC=Max., V
OUT=
0.0V –60 –120 –225 mA
I
OFF
Power-Off Disable VCC=0V, V
OUT
=4.5V ±1 µA
Notes:
1. H = HIGH Voltage Level
L = LOW Voltage Level
X = Don’t Care
Z = HIGH Impedance
Q
n
= Previous state of flip flops (Q
n-1
)
2. Unless otherwise noted, these limits are over the operating free-air temperature range.
3. Unused inputs must always be connected to an appropriate logic voltage level, preferably either V
CC
or ground.
4. T
A
is the “instant on” case temperature.
5. Typical values are at V
CC
=5.0V, TA=+25˚C ambient.
6. This parameter is specified but not tested.
7. Not more thanone output shouldbe shorted at a time. Durationof short should not exceed onesecond. The useof high-speed testapparatus and/or sample
and hold techniquesare preferablein order to minimize internal chip heating and more accurately reflect operational values. Otherwise prolonged shorting of
a high output may raise the chip temperature well above normal and thereby cause invalid readings in other parametric tests. In any sequence of parameter
tests, I
OS
tests should be performed last.
CY54/74FCT373T
CY54/74FCT573T
3
Capacitance
[6]
Parameter Description Typ.
[5]
Max. Unit
C
IN
Input Capacitance 6 10 pF
C
OUT
Output Capacitance 8 12 pF
Power Supply Characteristics
Parameter Description Test Conditions Typ.
[5]
Max. Unit
I
CC
Quiescent Power Supply Current VCC=Max., VIN ≤ 0.2V, VIN ≥ VCC– 0.2V 0.1 0.2 mA
∆I
CC
Quiescent Power Supply Current
(TTL inputs HIGH)
VCC=Max.,VIN=3.4V, f1=0,Outputs Open
[8]
0.5 2.0 mA
I
CCD
Dynamic Power Supply Current
[9]
VCC=Max., One Input Toggling,
50% Duty Cycle, Outputs Open,
OE=GND, VIN ≤ 0.2V or VIN ≥ VCC – 0.2V
0.6 0.12 mA/MHz
I
C
Total Power Supply Current
[10]
VCC=Max.,50%DutyCycle, Outputs Open,
One Bit Toggling at f
1
=10 MHz,
OE=GND, LE=V
CC
VIN ≤ 0.2V or VIN ≥ VCC – 0.2V
0.7 1.4 mA
VCC=Max.,50%DutyCycle, Outputs Open,
One Bit Toggling at f
1
=10 MHz,
OE=GND, LE=VCC, VIN=3.4V or VIN=GND
1.0 2.4 mA
VCC=Max.,50%DutyCycle, Outputs Open,
Eight Bits Toggling at f
1
=2.5 MHz,
OE=GND, LE=VCC,
V
IN
≤ 0.2V or VIN ≥ VCC – 0.2V
1.3 2.6
[11]
mA
VCC=Max.,50%DutyCycle, Outputs Open,
Eight Bits Toggling at f
1
=2.5 MHz,
OE=GND, LE=VCCVIN=3.4V or VIN=GND
3.3 10.6
[11]
mA
Notes:
8. Per TTL driven input (V
IN
=3.4V); all other inputs at VCC or GND.
9. This parameter is not directly testable, but is derived for use in Total Power Supply calculations.
10. I
C
=I
QUIESCENT
+ I
INPUTS
+ I
DYNAMIC
IC=ICC+∆ICCDHNT+I
CCD(f0
/2 + f1N1)
I
CC
= Quiescent Current with CMOS input levels
∆I
CC
= Power Supply Current for a TTL HIGH input (VIN=3.4V)
D
H
= Duty Cycle for TTL inputs HIGH
N
T
= Number of TTL inputs at D
H
I
CCD
= Dynamic Current caused by an input transition pair (HLH or LHL)
f
0
= Clock frequency for registered devices, otherwise zero
f
1
= Input signal frequency
N
1
= Number of inputs changing at f
1
All currents are in milliamps and all frequencies are in megahertz.
11. Values for these conditions are examples of the ICC formula. These limits are specified but not tested.
CY54/74FCT373T
CY54/74FCT573T
4
e
Switching Characteristics Over the Operating Range
[12]
Parameter Description
FCT373T/FCT573T FCT373AT/FCT573AT
Unit
Fig.
No.
[13]
Military Commercial Military Commercial
Min. Max. Min. Max. Min. Max. Min. Max.
t
PLH
t
PHL
Propagation Delay
D to O
1.5 8.5 1.5 8.0 1.5 5.6 1.5 5.2 ns 1, 3
t
PLH
t
PHL
Propagation Delay
LE to O
2.0 15.0 2.0 13.0 2.0 9.8 2.0 8.5 ns 1, 5
t
PZH
t
PZL
Output Enable Time 1.5 13.5 1.5 12.0 1.5 7.5 1.5 6.5 ns 1, 7, 8
t
PHZ
t
PLZ
Output Disable Time 1.5 10.0 1.5 7.5 1.5 6.5 1.5 5.5 ns 1, 7, 8
t
S
Set-Up Time
HIGH to LOW
D to LE
2.0 2.0 2.0 2.0 ns 9
t
H
Set-Up Time
HIGH to LOW
D to LE
1.5 1.5 1.5 1.5 ns 9
t
W
LE Pulse
Width HIGH
6.0 6.0 6.0 5.0 ns 5
Parameter Description
FCT373CT/
FCT573CT
Unit Fig. No.
[13]
Commercial
Min. Max.
t
PLH
t
PHL
Propagation Delay D to O 1.5 4.2 ns 1, 3
t
PLH
t
PHL
Propagation Delay LE to O 2.0 5.5 ns 1, 5
t
PZH
t
PZL
Output Enable Time 1.5 5.5 ns 1, 7, 8
t
PHZ
t
PLZ
Output Disable Time 1.5 5.0 ns 1, 7, 8
t
S
Set-Up Time, HIGH to LOW D to LE 2.0 ns 9
t
H
Set-Up Time, HIGH to LOW D to LE 1.5 ns 9
t
W
LE Pulse Width HIGH 5.0 ns 5
Note:
12. Minimum limits are specified but not tested on Propagation Delays.
13. See “Parameter Measurement Information” in the General Information section.
CY54/74FCT373T
CY54/74FCT573T
5
Ordering Information–FCT373T
Speed
(ns) Ordering Code
Package
Name Package Type
Operating
Range
4.2 CY74FCT373CTQCT Q5 20-Lead (150-Mil) QSOP Commercial
CY74FCT373CTSOC/SOCT S5 20-Lead (300-Mil) Molded SOIC
5.2 CY74FCT373ATQCT Q5 20-Lead (150-Mil) QSOP Commercial
CY74FCT373ATSOC/SOCT S5 20-Lead (300-Mil) Molded SOIC
5.6 CY54FCT373ATDMB D6 20-Lead (300-Mil) CerDIP Military
8.0 CY74FCT373TSOC/SOCT S5 20-Lead (300-Mil) Molded SOIC Commercial
8.5 CY54FCT373TDMB D6 20-Lead (300-Mil) CerDIP Military
Ordering Information—FCT573T
Speed
(ns) Ordering Code
Package
Name Package Type
Operating
Range
4.2 CY74FCT573CTQCT Q5 20-Lead (150-Mil) QSOP Commercial
CY74FCT573CTSOC/SOCT S5 20-Lead (300-Mil) Molded SOIC
5.2 CY74FCT573ATPC P5 20-Lead (300-Mil) Molded DIP Commercial
CY74FCT573ATQCT Q5 20-Lead (150-Mil) QSOP
CY74FCT573ATSOC/SOCT S5 20-Lead (300-Mil) Molded SOIC
8.0 CY74FCT573TQCT Q5 20-Lead (150-Mil) QSOP Commercial
CY74FCT573TSOC/SOCT S5 20-Lead (300-Mil) Molded SOIC
8.5 CY54FCT573TDMB D6 20-Lead (300-Mil) CerDIP Military
Document #: 38-00272-B
CY54/74FCT373T
CY54/74FCT573T
6
Package Diagrams
20-Lead (300-Mil) CerDIP D6
MIL-STD-1835 D-8 Config.A
20-Lead (300-Mil) Molded DIP P5
CY54/74FCT373T
CY54/74FCT573T
7
Package Diagrams (continued)
20-Lead Quarter Size Outline
Q5
20-Lead (300-Mil) Molded SOIC
S5
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