Texas Instruments 5962-9172701Q3A Datasheet

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SN54BCT8374A, SN74BCT8374A

SCAN TEST DEVICES

WITH OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS

SCBS045E – JUNE 1990 – REVISED JUL Y 1996

Members of the Texas Instruments

SCOPE

Octal Test-Integrated Circuits

Functionally Equivalent to ’F374 and

 Family of Testability Products

’BCT374 in the Normal-Function Mode

Compatible With the IEEE Standard

1149.1-1990 (JTAG) Test Access Port and Boundary-Scan Architecture

Test Operation Synchronous to Test Access Port (TAP)

Implement Optional Test Reset Signal by Recognizing a Double-High-Level Voltage (10 V) on TMS Pin

SCOPE

 Instruction Set

– IEEE Standard 1149.1-1990 Required

Instructions, Optional INTEST, CLAMP,

and HIGHZ – Parallel-Signature Analysis at Inputs – Pseudo-Random Pattern Generation

From Outputs – Sample Inputs/Toggle Outputs

Package Options Include Plastic Small-Outline (DW) Packages, Ceramic Chip Carriers (FK), and Standard Plastic (NT) and Ceramic (JT) 300-mil DIPs

description

The ’BCT8374A scan test devices with octal edge-triggered D-type flip-flops are members of the Texas Instruments SCOPE testability integrated-circuit family. This family of devices supports IEEE Standard 1149.1-1990 boundary scan to facilitate testing of complex circuit-board assemblies. Scan access to the test circuitry is accomplished via the 4-wire test access port (TAP) interface.

SN54BCT8374A ...JT PACKAGE

SN74BCT8374A . . . DW OR NT PACKAGE

SN54BCT8374A . . . FK PACKAGE

1D OE NC

CLK

NC – No internal connection

(TOP VIEW)

CLK

GND

TDO

TMS

(TOP VIEW)

3D4D5DNCV6D7D

3212827

426

5 6 7 8 9 10 11

12 13

14 15 16 17

GND

24 23 22 21 20 19 18 17 16 15 14 13

5Q6Q7Q

OE 1D 2D 3D 4D 5D V

6D 7D 8D TDI TCK

25 24 23 22 21 20 19

8D TDI TCK NC TMS TDO 8Q

In the normal mode, these devices are functionally equivalent to the ’F374 and ’BCT374 octal D-type flip-flops. The test circuitry can be activated by the TAP to take snapshot samples of the data appearing at the device terminals or to perform a self test on the boundary-test cells. Activating the TAP in normal mode does not af fect the functional operation of the SCOPE octal flip-flops.

In the test mode, the normal operation of the SCOPE octal flip-flops is inhibited and the test circuitry is enabled to observe and control the I/O boundary of the device. When enabled, the test circuitry can perform boundary-scan test operations as described in IEEE Standard 1149.1-1990.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

SCOPE is a trademark of Texas Instruments Incorporated.

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

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On products compliant to MIL-PRF-38535, all parameters are tested unless otherwise noted. On all other products, production processing does not necessarily include testing of all parameters.

SN54BCT8374A, SN74BCT8374A SCAN TEST DEVICES WITH OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS

SCBS045E – JUNE 1990 – REVISED JUL Y 1996

description (continued)

Four dedicated test terminals control the operation of the test circuitry: test data input (TDI), test data output (TDO), test mode select (TMS), and test clock (TCK). Additionally, the test circuitry performs other testing functions such as parallel-signature analysis (PSA) on data inputs and pseudo-random pattern generation (PRPG) from data outputs. All testing and scan operations are synchronized to the TAP interface.

The SN54BCT8374A is characterized for operation over the full military temperature range of –55°C to 125°C. The SN74BCT8374A is characterized for operation from 0°C to 70°C.

FUNCTION TABLE

(normal mode, each flip-flop)

INPUTS

OE CLK D

L ↑ H H L ↑ LL L H or L X Q

H X X Z

OUTPUT

logic symbol

†

This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.

Pin numbers shown are for the DW, JT, and NT packages.

†

SCAN

TDI

TMS

TCK

CLK

1D 1Q

3D 3Q

4D 4Q

5D 5Q

6D 6Q

7D 7Q

8D 8Q

TDI TMS

TCK-IN TCK-OUT

’BCT8374A

TDO

2 3

4 5 7 8 9

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functional block diagram

CLK

SN54BCT8374A, SN74BCT8374A

SCAN TEST DEVICES

WITH OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS

SCBS045E – JUNE 1990 – REVISED JUL Y 1996

Boundary-Scan Register

TDI

TMS

TCK

One of Eight Channels

Bypass Register

Boundary-Control

Instruction Register

TAP

Controller

TDO

Pin numbers shown are for the DW, JT, and NT packages.

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SN54BCT8374A, SN74BCT8374A SCAN TEST DEVICES WITH OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS

SCBS045E – JUNE 1990 – REVISED JUL Y 1996

Terminal Functions

TERMINAL

NAME

CLK

1D–8D

GND Ground

1Q–8Q Normal-function data outputs. See function table for normal-mode logic.

TCK

TDI

TDO

TMS

Normal-function clock input. See function table for normal-mode logic. An internal pullup forces CLK to a high level if left unconnected.

Normal-function data inputs. See function table for normal-mode logic. Internal pullups force these inputs to a high level if left unconnected.

Normal-function output-enable input. See function table for normal-mode logic. An internal pullup forces OE to a high level if left unconnected.

T est clock. One of four terminals required by IEEE Standard 1149.1-1990. Test operations of the device are synchronous to TCK. Data is captured on the rising edge of TCK and outputs change on the falling edge of TCK. An internal pullup forces TCK to a high level if left unconnected.

T est data input. One of four terminals required by IEEE Standard 1 149.1-1990. TDI is the serial input for shifting data through the instruction register or selected data register. An internal pullup forces TDI to a high level if left unconnected.

Test data output. One of four terminals required by IEEE Standard 1149.1-1990. TDO is the serial output for shifting data through the instruction register or selected data register. An internal pullup forces TDO to a high level when it is not active and is not driven from an external source.

Test mode select. One of four terminals required by IEEE Standard 1149.1-1990. TMS directs the device through its TAP controller states. An internal pullup forces TMS to a high level if left unconnected. TMS also provides the optional test reset signal of IEEE Standard 1149.1-1990. This is implemented by recognizing a third logic level, double high (V

Supply voltage

DESCRIPTION

IHH

), at TMS.

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SN54BCT8374A, SN74BCT8374A

SCAN TEST DEVICES

WITH OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS

SCBS045E – JUNE 1990 – REVISED JUL Y 1996

test architecture

Serial-test information is conveyed by means of a 4-wire test bus, or TAP, that conforms to IEEE Standard 1 149.1-1990. Test instructions, test data, and test control signals all are passed along this serial-test bus. The TAP controller monitors two signals from the test bus, TCK and TMS. The TAP controller extracts the synchronization (TCK) and state control (TMS) signals from the test bus and generates the appropriate on-chip control signals for the test structures in the device. Figure 1 shows the TAP-controller state diagram.

The T AP controller is fully synchronous to the TCK signal. Input data is captured on the rising edge of TCK, and output data changes on the falling edge of TCK. This scheme ensures that data to be captured is valid for fully one-half of the TCK cycle.

The functional block diagram shows the IEEE Standard 1149.1-1990 4-wire test bus and boundary-scan architecture and the relationship among the test bus, the T AP controller, and the test registers. As shown, the device contains an 8-bit instruction register and three test-data registers: an 18-bit boundary-scan register, a 2-bit boundary-control register, and a 1-bit bypass register.

Test-Logic-Reset

TMS = H

TMS = L

Run-Test/Idle Select-DR-Scan

TMS = L

Capture-DR

TMS = L

Shift-DR

TMS = L

TMS = H

Exit1-DR

TMS = L

Pause-DR

TMS = L

TMS = H

Exit2-DR

TMS = H

TMS = HTMS = H

TMS = H TMS = H

TMS = L

Select-IR-Scan

TMS = H

TMS = L

Capture-IR

TMS = L

Shift-IR

TMS = L

TMS = H

Exit1-IR

TMS = L

Pause-IR

TMS = L

TMS = H

Exit2-IR

TMS = H

Update-DR

TMS = LTMS = H

Figure 1. TAP-Controller State Diagram

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Update-IR

TMS = LTMS = H

SN54BCT8374A, SN74BCT8374A SCAN TEST DEVICES WITH OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS

SCBS045E – JUNE 1990 – REVISED JUL Y 1996

state diagram description

The T AP controller is a synchronous finite state machine that provides test control signals throughout the device. The state diagram shown in Figure 1 is in accordance with IEEE Standard 1149.1-1990. The TAP controller proceeds through its states based on the level of TMS at the rising edge of TCK.

As shown, the T AP controller consists of 16 states. There are six stable states (indicated by a looping arrow in the state diagram) and ten unstable states. A stable state is a state the T AP controller can retain for consecutive TCK cycles. Any state that does not meet this criterion is an unstable state.

There are two main paths through the state diagram: one to access and control the selected data register and one to access and control the instruction register. Only one register can be accessed at a time.

Test-Logic-Reset

The device powers up in the T est-Logic-Reset state. In the stable Test-Logic-Reset state, the test logic is reset and is disabled so that the normal logic function of the device is performed. The instruction register is reset to an opcode that selects the optional IDCODE instruction, if supported, or the BYP ASS instruction. Certain data registers also can be reset to their power-up values.

The state machine is constructed such that the T AP controller returns to the Test-Logic-Reset state in no more than five TCK cycles if TMS is left high. The TMS pin has an internal pullup resistor that forces it high if left unconnected or if a board defect causes it to be open circuited.

For the ’BCT8374A, the instruction register is reset to the binary value 11111111, which selects the BYPASS instruction. The boundary-control register is reset to the binary value 10, which selects the PSA test operation.

Run-T est/Idle

The T AP controller must pass through the Run-T est/Idle state (from T est-Logic-Reset) before executing any test operations. The Run-Test/Idle state also can be entered following data-register or instruction-register scans. Run-Test/Idle is a stable state in which the test logic may be actively running a test or may be idle.

The test operations selected by the boundary-control register are performed while the T AP controller is in the Run-Test/Idle state.

Select-DR-Scan, Select-lR-Scan

No specific function is performed in the Select-DR-Scan and Select-lR-Scan states, and the T AP controller exits either of these states on the next TCK cycle. These states allow the selection of either data-register scan or instruction-register scan.

Capture-DR

When a data register scan is selected, the TAP controller must pass through the Capture-DR state. In the Capture-DR state, the selected data register may capture a data value as specified by the current instruction. Such capture operations occur on the rising edge of TCK, upon which the TAP controller exits the Capture-DR state.

Shift-DR

Upon entry to the Shift-DR state, the data register is placed in the scan path between TDI and TDO and, on the first falling edge of TCK, TDO goes from the high-impedance state to an active state. TDO enables to the logic level present in the least-significant bit of the selected data register.

While in the stable Shift-DR state, data is serially shifted through the selected data register on each TCK cycle. The first shift occurs on the first rising edge of TCK after entry to the Shift-DR state (i.e., no shifting occurs during the TCK cycle in which the T AP controller changes from Capture-DR to Shift-DR or from Exit2-DR to Shift-DR). The last shift occurs on the rising edge of TCK, upon which the TAP controller exits the Shift-DR state.

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SN54BCT8374A, SN74BCT8374A

SCAN TEST DEVICES

WITH OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS

SCBS045E – JUNE 1990 – REVISED JUL Y 1996

Exit1-DR, Exit2-DR

The Exit1-DR and Exit2-DR states are temporary states that end a data-register scan. It is possible to return to the Shift-DR state from either Exit1-DR or Exit2-DR without recapturing the data register.

On the first falling edge of TCK after entry to Exit1-DR, TDO goes from the active state to the high-impedance state.

Pause-DR

No specific function is performed in the stable Pause-DR state, in which the TAP controller can remain indefinitely. The Pause-DR state suspends and resumes data-register scan operations without loss of data.

Update-DR

If the current instruction calls for the selected data register to be updated with current data, then such update occurs on the falling edge of TCK, following entry to the Update-DR state.

Capture-IR

When an instruction register scan is selected, the TAP controller must pass through the Capture-IR state. In the Capture-IR state, the instruction register captures its current status value. This capture operation occurs on the rising edge of TCK, upon which the TAP controller exits the Capture-IR state.

For the ’BCT8374A, the status value loaded in the Capture-IR state is the fixed binary value 10000001.

Shift-IR

Upon entry to the Shift-IR state, the instruction register is placed in the scan path between TDI and TDO and, on the first falling edge of TCK, TDO goes from the high-impedance state to an active state. TDO enables to the logic level present in the least-significant bit of the instruction register.

While in the stable Shift-IR state, instruction data is serially shifted through the instruction register on each TCK cycle. The first shift occurs on the first rising edge of TCK after entry to the Shift-IR state (i.e., no shifting occurs during the TCK cycle in which the TAP controller changes from Capture-IR to Shift-IR or from Exit2-IR to Shift-IR). The last shift occurs on the rising edge of TCK, upon which the T AP controller exits the Shift-IR state.

Exit1-IR, Exit2-IR

The Exit1-IR and Exit2-IR states are temporary states that end an instruction-register scan. It is possible to return to the Shift-IR state from either Exit1-IR or Exit2-IR without recapturing the instruction register.

On the first falling edge of TCK after entry to Exit1-IR, TDO goes from the active state to the high-impedance state.

Pause-IR

No specific function is performed in the stable Pause-IR state, in which the TAP controller can remain indefinitely. The Pause-IR state suspends and resumes instruction-register scan operations without loss of data.

Update-IR

The current instruction is updated and takes effect on the falling edge of TCK following entry to the Update-IR state.

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SN54BCT8374A, SN74BCT8374A SCAN TEST DEVICES WITH OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS

SCBS045E – JUNE 1990 – REVISED JUL Y 1996

With the exception of the bypass register, any test register may be thought of as a serial-shift register with a shadow latch on each bit. The bypass register differs in that it contains only a shift register. During the appropriate capture state (Capture-IR for instruction register, Capture-DR for data registers), the shift register may be parallel loaded from a source specified by the current instruction. During the appropriate shift state (Shift-IR or Shift-DR), the contents of the shift register are shifted out from TDO while new contents are shifted in at TDI. During the appropriate update state (Update-IR or Update-DR), the shadow latches are updated from the shift register.

instruction register description

The instruction register (IR) is eight bits long and tells the device what instruction is to be executed. Information contained in the instruction includes the mode of operation (either normal mode, in which the device performs its normal logic function, or test mode, in which the normal logic function is inhibited or altered), the test operation to be performed, which of the three data registers is to be selected for inclusion in the scan path during data-register scans, and the source of data to be captured into the selected data register during Capture-DR.

Table 2 lists the instructions supported by the ’BCT8374A. The even-parity feature specified for SCOPE devices is not supported in this device. Bit 7 of the instruction opcode is a don’t-care bit. Any instructions that are defined for SCOPE devices but are not supported by this device default to BYPASS.

During Capture-IR, the IR captures the binary value 10000001. As an instruction is shifted in, this value is shifted out via TDO and can be inspected as verification that the IR is in the scan path. During Update-IR, the value that has been shifted into the IR is loaded into shadow latches. At this time, the current instruction is updated and any specified mode change takes effect. At power up or in the Test-Logic-Reset state, the IR is reset to the binary value 11111111, which selects the BYPASS instruction. The IR order of scan is shown in Figure 2.

Bit 7

(MSB)

Don’t

Care

Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1

Bit 0

(LSB)

TDOTDI

Figure 2. Instruction Register Order of Scan

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SN54BCT8374A, SN74BCT8374A

SCAN TEST DEVICES

WITH OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS

SCBS045E – JUNE 1990 – REVISED JUL Y 1996

data register description

boundary-scan register

The boundary-scan register (BSR) is 18 bits long. It contains one boundary-scan cell (BSC) for each normal-function input pin and one BSC for each normal-function output pin. The BSR is used to 1) store test data that is to be applied internally to the inputs of the normal on-chip logic and/or externally to the device output terminals, and/or 2) to capture data that appears internally at the outputs of the normal on-chip logic and/or externally at the device input terminals.

The source of data to be captured into the BSR during Capture-DR is determined by the current instruction. The contents of the BSR may change during Run-Test/Idle as determined by the current instruction. The contents of the BSR are not changed in Test-Logic-Reset.

The BSR order of scan is from TDI through bits 17–0 to TDO. T able 1 shows the BSR bits and their associated device pin signals.

Table 1. Boundary-Scan Register Configuration

BSR BIT

NUMBER

17 CLK 15 1D 7 1Q 16 OE 14 2D 6 2Q

– – 13 3D 5 3Q – – 12 4D 4 4Q – – 11 5D 3 5Q – – 10 6D 2 6Q – – 9 7D 1 7Q – – 8 8D 0 8Q

DEVICE SIGNAL

BSR BIT

NUMBER

DEVICE SIGNAL

BSR BIT

NUMBER

DEVICE SIGNAL

boundary-control register

The boundary-control register (BCR) is two bits long. The BCR is used in the context of the RUNT instruction to implement additional test operations not included in the basic SCOPE instruction set. Such operations include PRPG and PSA. Table 3 shows the test operations that are decoded by the BCR.

During Capture-DR, the contents of the BCR are not changed. At power up or in Test-Logic-Reset, the BCR is reset to the binary value 10, which selects the PSA test operation. The BCR order of scan is shown in Figure 3.

Bit 1

(MSB)

Bit 0

(LSB)

TDOTDI

Figure 3. Boundary-Control Register Order of Scan

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SN54BCT8374A, SN74BCT8374A SCAN TEST DEVICES WITH OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS

SCBS045E – JUNE 1990 – REVISED JUL Y 1996

bypass register

The bypass register is a 1-bit scan path that can be selected to shorten the length of the system scan path, thereby reducing the number of bits per test pattern that must be applied to complete a test operation.

During Capture-DR, the bypass register captures a logic 0. The bypass register order of scan is shown in Figure 4.

Bit 0

TDOTDI

Figure 4. Bypass Register Order of Scan

instruction-register opcode description

The instruction-register opcodes are shown in Table 2. The following descriptions detail the operation of each instruction.

Table 2. Instruction-Register Opcodes

BINARY CODE

BIT 7 → BIT 0

MSB → LSB

X0000000 EXTEST/INTEST Boundary scan Boundary scan Test X0000001 BYPASS X0000010 SAMPLE/PRELOAD Sample boundary Boundary scan Normal X000001 1 INTEST/EXTEST Boundary scan Boundary scan Test X0000100 BYPASS X0000101 BYPASS X0000110 HIGHZ (TRIBYP) Control boundary to high impedance Bypass Modified test X00001 11 CLAMP (SETBYP) Control boundary to 1/0 Bypass Test X0001000 BYPASS X0001001 RUNT Boundary run test Bypass Test X0001010 READBN Boundary read Boundary scan Normal X000101 1 READBT Boundary read Boundary scan Test X0001 100 CELLTST Boundary self test Boundary scan Normal X0001 101 TOPHIP Boundary toggle outputs Bypass Test X0001 110 SCANCN Boundary-control register scan Boundary control Normal X0001 111 SCANCT Boundary-control register scan Boundary control Test

All others BYPASS Bypass scan Bypass Normal

†

Bit 7 is a don’t-care bit; X = don’t care.

‡

The BYPASS instruction is executed in lieu of a SCOPE instruction that is not supported in the ’BCT8374A.

†

SCOPE OPCODE DESCRIPTION

‡

‡ ‡

‡

SELECTED DATA

Bypass scan Bypass Normal

Bypass scan Bypass Normal Bypass scan Bypass Normal

Bypass scan Bypass Normal

MODE

boundary scan

This instruction conforms to the IEEE Standard 1149.1-1990 EXTEST and INTEST instructions. The BSR is selected in the scan path. Data appearing at the device input terminals is captured in the input BSCs, while data appearing at the outputs of the normal on-chip logic is captured in the output BSCs. Data that has been scanned into the input BSCs is applied to the inputs of the normal on-chip logic, while data that has been scanned into the output BSCs is applied to the device output terminals. The device operates in the test mode.

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SN54BCT8374A, SN74BCT8374A

SCAN TEST DEVICES

WITH OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS

SCBS045E – JUNE 1990 – REVISED JUL Y 1996

bypass scan

This instruction conforms to the IEEE Standard 1149.1-1990 BYPASS instruction. The bypass register is selected in the scan path. A logic 0 value is captured in the bypass register during Capture-DR. The device operates in the normal mode.

sample boundary

This instruction conforms to the IEEE Standard 1149.1-1990 SAMPLE/PRELOAD instruction. The BSR is selected in the scan path. Data appearing at the device input terminals is captured in the input BSCs, while data appearing at the outputs of the normal on-chip logic is captured in the output BSCs. The device operates in the normal mode.

control boundary to high impedance

This instruction conforms to the IEEE Standard 1149.1a-1993 HIGHZ instruction. The bypass register is selected in the scan path. A logic 0 value is captured in the bypass register during Capture-DR. The device operates in a modified test mode in which all device output terminals are placed in the high-impedance state, the device input terminals remain operational, and the normal on-chip logic function is performed.

control boundary to 1/0

This instruction conforms to the IEEE Standard 1149.1a-1993 CLAMP instruction. The bypass register is selected in the scan path. A logic 0 value is captured in the bypass register during Capture-DR. Data in the input BSCs is applied to the inputs of the normal on-chip logic, while data in the output BSCs is applied to the device output terminals. The device operates in the test mode.

boundary run test

The bypass register is selected in the scan path. A logic 0 value is captured in the bypass register during Capture-DR. The device operates in the test mode. The test operation specified in the BCR is executed during Run-Test/Idle. The four test operations decoded by the BCR are: sample inputs/toggle outputs (TOPSIP), PRPG, PSA, and simultaneous PSA and PRPG (PSA/PRPG).

boundary read

The BSR is selected in the scan path. The value in the BSR remains unchanged during Capture-DR. This instruction is useful for inspecting data after a PSA operation.

boundary self test

The BSR is selected in the scan path. All BSCs capture the inverse of their current values during Capture-DR. In this way , the contents of the shadow latches may be read out to verify the integrity of both shift-register and shadow-latch elements of the BSR. The device operates in the normal mode.

boundary toggle outputs

The bypass register is selected in the scan path. A logic 0 value is captured in the bypass register during Capture-DR. Data in the shift register elements of the selected output BSCs is toggled on each rising edge of TCK in Run-Test/Idle and is then updated in the shadow latches and applied to the associated device output terminals on each falling edge of TCK in Run-Test/Idle. Data in the selected input BSCs remains constant and is applied to the inputs of the normal on-chip logic. Data appearing at the device input terminals is not captured in the input BSCs. The device operates in the test mode.

boundary-control-register scan

The BCR is selected in the scan path. The value in the BCR remains unchanged during Capture-DR. This operation must be performed before a boundary-run test operation to specify which test operation is to be executed.

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SCBS045E – JUNE 1990 – REVISED JUL Y 1996

boundary-control-register opcode description

The BCR opcodes are decoded from BCR bits 1–0 as shown in T able 3. The selected test operation is performed while the RUNT instruction is executed in the Run-T est/Idle state. The following descriptions detail the operation of each BCR instruction and illustrate the associated PSA and PRPG algorithms.

Table 3. Boundary-Control Register Opcodes

BINARY CODE

BIT 1 → BIT 0

MSB → LSB

00 Sample inputs/toggle outputs (TOPSIP) 01 Pseudo-random pattern generation/16-bit mode (PRPG) 10 Parallel-signature analysis/16-bit mode (PSA) 11 Simultaneous PSA and PRPG/8-bit mode (PSA/PRPG)

It should be noted, in general, that while the control input BSCs (bits 17–16) are not included in the sample, toggle, PSA, or PRPG algorithms, the output-enable BSC (bit 16 of the BSR) does control the drive state (active or high impedance) of the device output terminals.

DESCRIPTION

sample inputs/toggle outputs (TOPSIP)

Data appearing at the device input terminals is captured in the shift-register elements of the input BSCs on each rising edge of TCK. This data is then updated in the shadow latches of the input BSCs and applied to the inputs of the normal on-chip logic. Data in the shift register elements of the output BSCs is toggled on each rising edge of TCK, updated in the shadow latches, and applied to the device output terminals on each falling edge of TCK.

pseudo-random pattern generation (PRPG)

A pseudo-random pattern is generated in the shift-register elements of the BSCs on each rising edge of TCK and then updated in the shadow latches and applied to the device output terminals on each falling edge of TCK. This data also is updated in the shadow latches of the input BSCs and applied to the inputs of the normal on-chip logic. Figure 5 shows the 16-bit linear-feedback shift-register algorithm through which the patterns are generated. An initial seed value should be scanned into the BSR before performing this operation. A seed value of all zeroes will not produce additional patterns.

2D 3D 4D 5D 6D 7D 8D

2Q 3Q 4Q 5Q 6Q 7Q 8Q

Figure 5. 16-Bit PRPG Configuration

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SCAN TEST DEVICES

WITH OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS

SCBS045E – JUNE 1990 – REVISED JUL Y 1996

parallel-signature analysis (PSA)

Data appearing at the device input terminals is compressed into a 16-bit parallel signature in the shift-register elements of the BSCs on each rising edge of TCK. This data is then updated in the shadow latches of the input BSCs and applied to the inputs of the normal on-chip logic. Data in the shadow latches of the output BSCs remains constant and is applied to the device outputs. Figure 6 shows the 16-bit linear-feedback shift-register algorithm through which the signature is generated. An initial seed value should be scanned into the BSR before performing this operation.

2D 3D 4D 5D 6D 7D 8D

2Q 3Q 4Q 5Q 6Q 7Q 8Q

Figure 6. 16-Bit PSA Configuration

simultaneous PSA and PRPG (PSA/PRPG)

Data appearing at the device input terminals is compressed into an 8-bit parallel signature in the shift-register elements of the input BSCs on each rising edge of TCK. This data is then updated in the shadow latches of the input BSCs and applied to the inputs of the normal on-chip logic. At the same time, an 8-bit pseudo-random pattern is generated in the shift-register elements of the output BSCs on each rising edge of TCK, updated in the shadow latches, and applied to the device output terminals on each falling edge of TCK. Figure 7 shows the 8-bit linear-feedback shift-register algorithm through which the signature and patterns are generated. An initial seed value should be scanned into the BSR before performing this operation. A seed value of all zeroes will not produce additional patterns.

2D 3D 4D 5D 6D 7D 8D

2Q 3Q 4Q 5Q 6Q 7Q 8Q

Figure 7. 8-Bit PSA/PRPG Configuration

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SN54BCT8374A, SN74BCT8374A SCAN TEST DEVICES WITH OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS

SCBS045E – JUNE 1990 – REVISED JUL Y 1996

timing description

All test operations of the ’BCT8374A are synchronous to TCK. Data on the TDI, TMS, and normal-function inputs is captured on the rising edge of TCK. Data appears on the TDO and normal-function output terminals on the falling edge of TCK. The T AP controller is advanced through its states (as shown in Figure 1) by changing the value of TMS on the falling edge of TCK and then applying a rising edge to TCK.

A simple timing example is shown in Figure 8. In this example, the T AP controller begins in the T est-Logic-Reset state and is advanced through its states as necessary to perform one instruction-register scan and one data-register scan. While in the Shift-IR and Shift-DR states, TDI is used to input serial data and TDO is used to output serial data. The TAP controller is then returned to the Test-Logic-Reset state. Table 4 explains the operation of the test circuitry during each TCK cycle.

Table 4. Explanation of Timing Example

TCK

CYCLE(S)

1 Test-Logic-Reset 2 Run-Test/Idle

3 Select-DR-Scan 4 Select-IR-Scan

5 Capture-IR

6 Shift-IR

7–13 Shift-IR

14 Exit1-IR TDO becomes inactive (goes to the high-impedance state) on the falling edge of TCK. 15 Update-IR The IR is updated with the new instruction (BYPASS) on the falling edge of TCK. 16 Select-DR-Scan

17 Capture-DR

18 Shift-DR

19–20 Shift-DR The binary value 101 is shifted in via TDI, while the binary value 010 is shifted out via TDO.

21 Exit1-DR TDO becomes inactive (goes to the high-impedance state) on the falling edge of TCK. 22 Update-DR In general, the selected data register is updated with the new data on the falling edge of TCK. 23 Select-DR-Scan 24 Select-IR-Scan 25 Test-Logic-Reset Test operation completed

TAP STATE

AFTER TCK

DESCRIPTION

TMS is changed to a logic 0 value on the falling edge of TCK to begin advancing the TAP controller toward the desired state.

The IR captures the 8-bit binary value 10000001 on the rising edge of TCK as the TAP controller exits the Capture-IR state.

TDO becomes active and TDI is made valid on the falling edge of TCK. The first bit is shifted into the TAP on the rising edge of TCK as the TAP controller advances to the next state.

One bit is shifted into the IR on each TCK rising edge. With TDI held at a logic 1 value, the 8-bit binary value 11111111 is serially scanned into the IR. At the same time, the 8-bit binary value 10000001 is serially scanned out of the IR via TDO. In TCK cycle 13, TMS is changed to a logic 1 value to end the IR scan on the next TCK cycle. The last bit of the instruction is shifted as the TAP controller advances from Shift-IR to Exit1-IR.

The bypass register captures a logic 0 value on the rising edge of TCK as the TAP controller exits the Capture-DR state.

TDO becomes active and TDI is made valid on the falling edge of TCK. The first bit is shifted into the TAP on the rising edge of TCK as the TAP controller advances to the next state.

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ООООО

TCK

TMS

TDO

SN54BCT8374A, SN74BCT8374A

SCAN TEST DEVICES

WITH OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS

SCBS045E – JUNE 1990 – REVISED JUL Y 1996

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25

TDI

TAP

Controller

State

Run-Test/Idle

Test-Logic-Reset

Select-DR-Scan

Capture-IR

Select-IR-Scan

Shift-IR

3-State (TDO) or Don’t Care (TDI)

Exit1-IR

Update-IR

Capture-DR

Select-DR-Scan

Shift-DR

Exit1-DR

Update-DR

Select-IR-Scan

Select-DR-Scan

Figure 8. Timing Example

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

Supply voltage range, VCC –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input voltage range, VI: except TMS (see Note 1) –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

TMS (see Note 1) –0.5 V to 12 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Voltage range applied to any output in the disabled or power-off state –0.5 V to 5.5 V. . . . . . . . . . . . . . . . . . . .

Voltage range applied to any output in the high state –0.5 V to V

Input clamp current, IIK –30 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Current into any output in the low state: SN54BCT8374A (TDO) 40 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

SN54BCT8374A (any Q) 96 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

SN74BCT8374A (TDO) 48 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

SN74BCT8374A (any Q) 128 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Maximum power dissipation at T Storage temperature range, T

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES: 1. The input voltage rating may be exceeded if the input clamp-current rating is observed.

2. The maximum package power dissipation is calculated using a junction temperature of 150°C and a board trace length of 750 mils, except for the NT package, which has a trace length of zero. For more information, refer to the application note in the

ABT Advanced BiCMOS Technology Data Book

= 55°C (in still air) (see Note 2): DW package 1.7 W. . . . . . . . . . . . . . . . . .

–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

stg

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

NT package 1.3 W. . . . . . . . . . . . . . . . . . .

Package Thermal Considerations

, literature number SCBD002.

Test-Logic-Reset

†

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SN54BCT8374A, SN74BCT8374A

UNIT

IOHHigh-level output current

IOLLow-level output current

SCAN TEST DEVICES WITH OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS

SCBS045E – JUNE 1990 – REVISED JUL Y 1996

recommended operating conditions

V V V V I

Supply voltage 4.5 5 5.5 4.5 5 5.5 V

High-level input voltage 2 2 V

Double-high-level input voltage TMS 10 12 10 12 V

IHH

Low-level input voltage 0.8 0.8 V

Input clamp current –18 –18 mA

Operating free-air temperature –55 125 0 70 °C

TDO –3 –3 Any Q –12 –15 TDO 20 24 Any Q 48 64

SN54BCT8374A SN74BCT8374A

MIN NOM MAX MIN NOM MAX

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PARAMETER

TEST CONDITIONS

UNIT

Any Q

TDO

SN54BCT8374A, SN74BCT8374A

SCAN TEST DEVICES

WITH OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS

SCBS045E – JUNE 1990 – REVISED JUL Y 1996

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)

SN54BCT8374A SN74BCT8374A

MIN TYP†MAX MIN TYP†MAX

TDO

IHH

OZH

OZL

OZPU

OZPD

off

C C

†

All typical values are at VCC = 5 V, TA = 25°C.

‡

Not more than one output should be shorted at a time, and the duration of the short circuit should not exceed one second.

TMS VCC = 5.5 V, VI = 10 V 1 1 mA

Any Q TDO Any Q TDO

‡

i o

VCC = 4.5 V, II = –18 mA –1.2 –1.2 V VCC = 4.75 V, IOH = –3 mA 2.7 3.4 2.7 3.4

IOH = –3 mA 2.4 3.4 2.4 3.4

VCC = 4.5 V

VCC = 4.75 V, IOH = –1 mA 2.7 3.4 2.7 3.4

= 4.5

VCC = 5.5 V, VI = 5.5 V 0.1 0.1 mA VCC = 5.5 V, VI = 2.7 V –1 –35 –100 –1 –35 –100 µA

VCC = 5.5 V, VI = 0.5 V –30 –70 –200 –30 –70 –200 µA

= 5.5 V,

VCC = 0 to 2 V, VO = 0.5 V or 2.7 V ±250 ±250 µA VCC = 2 V to 0, VO = 0.5 V or 2.7 V ±250 ±250 µA VCC = 0, VI or VO ≤ 4.5 V ±250 ±250 µA VCC = 5.5 V, VO = 0 –100 –225 –100 –225 mA

VCC = 5.5 V, Outputs open

VCC = 5 V, VI = 2.5 V or 0.5 V 10 10 pF VCC = 5 V, VO = 2.5 V or 0.5 V 14 14 pF

IOH = –12 mA 2 3.2 IOH = –15 mA 2 3.1

IOH = –1 mA 2.5 3.4 2.5 3.4 IOH = –3 mA 2.4 3.3 2.4 3.3 IOL = 48 mA 0.38 0.55 IOL = 64 mA 0.42 0.55 IOL = 20 mA 0.3 0.5 IOL = 24 mA 0.35 0.5

= 2.7

= 0.5

–1 –35 –100 –1 –35 –100

–30 –70 –200 –30 –70 –200

Outputs high 3.5 7 3.5 7 Outputs low Outputs disabled 1.5 3.5 1.5 3.5

50 50

–50 –50

35 52 35 52

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SN54BCT8374A, SN74BCT8374A

twPulse duration

tsuSetup time

thHold time

SCAN TEST DEVICES WITH OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS

SCBS045E – JUNE 1990 – REVISED JUL Y 1996

timing requirements over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (normal mode) (see Figure 9)

VCC = 5 V,

TA = 25°C MIN MAX MIN MAX MIN MAX

clock

Clock frequency CLK 0 70 0 70 0 70 MHz Pulse duration CLK high or low 5 5 5 ns Setup time Data before CLK↑ 3 3 3 ns Hold time Data after CLK↑ 2 2 2 ns

timing requirements over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (test mode) (see Figure 9)

VCC = 5 V,

TA = 25°C MIN MAX MIN MAX MIN MAX

clock

* On products compliant to MIL-PRF-38535, this parameter is not production tested.

Clock frequency TCK 0 20 0 20 0 20 MHz

TCK high or low 25 25 25 TMS double high 50* 50* 50 Any D before TCK↑ 6 6 6

Delay time Power up to TCK↑ 100* 100* 100 ns

CLK or OE before TCK↑ 6 6 6 TDI before TCK↑ 6 6 6 TMS before TCK↑ 12 12 12 Any D after TCK↑ 4.5 4.5 4.5 CLK or OE after TCK↑ 4.5 4.5 4.5 TDI after TCK↑ 4.5 4.5 4.5 TMS after TCK↑ 0 0 0

SN54BCT8374A SN74BCT8374A

UNIT

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(INPUT)

(OUTPUT)

CLK

(INPUT)

(OUTPUT)

TCK↓

TDO

TCK↑

TCK↓

TDO

TCK↑

TCK↓

TDO

TCK↑

SN54BCT8374A, SN74BCT8374A

SCAN TEST DEVICES

WITH OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS

SCBS045E – JUNE 1990 – REVISED JUL Y 1996

switching characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (normal mode) (see Figure 9)

VCC = 5 V,

TA = 25°C

MIN TYP MAX MIN MAX MIN MAX

3 6.7 8.5 3 10.5 3 10 3 6.4 8 3 10 3 9.5 3 6.5 8.5 3 10.5 3 10

3.5 7.5 9.5 3.5 12.5 3.5 11 3 6.1 8 3 10 3 9

2.5 5.8 7.5 2.5 9.5 2.5 8.5

PARAMETER

max

PLH

PHL

PZH

PZL

PHZ

PLZ

FROM

CLK 70 70 70 MHz

switching characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (test mode) (see Figure 9)

VCC = 5 V,

TA = 25°C

MIN TYP MAX MIN MAX MIN MAX

6 13 15.5 6 21.5 6 20 6 12.5 15.5 6 21.5 6 20

3.5 7.6 10.5 3.5 14 3.5 13

3.5 8 10.5 3.5 13 3.5 12

7.5 16.5 20 7.5 28 7.5 24

7.5 17 21 7.5 29 7.5 25

6.5 14 17 6.5 24 6.5 21 7 15 20 7 26 7 23

3.5 7.6 10.5 3.5 11.5 3.5 11 4 8.5 11 4 13.5 4 12.5 8 18 22 8 30 8 27 8 19 25 8 32 8 29 6 14 18 6 24 6 22 6 14 17 6 23 6 21 3 8 11.5 3 13 3 12.5 3 7.5 10 3 13 3 12 8 18.5 22 8 31 8 27 8 18.5 22 8 31 8 27

PARAMETER

max

PLH

PHL

PLH

PHL

PLH

PHL

PZH

PZL

PZH

PZL

PZH

PZL

PHZ

PLZ

PHZ

PLZ

PHZ

PLZ

FROM

TCK 20 20 20 MHz

SN54BCT8374A SN74BCT8374A

UNIT

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SN54BCT8374A, SN74BCT8374A SCAN TEST DEVICES WITH OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS

SCBS045E – JUNE 1990 – REVISED JUL Y 1996

PARAMETER MEASUREMENT INFORMATION

7 V (t

From Output

Under Test

Timing Input

Data Input

, t

PZL

(see Note A)

3-STATE AND OPEN-COLLECTOR OUTPUTS

, O.C.)

PLZ

LOAD CIRCUIT FOR

VOLTAGE WAVEFORMS

SETUP AND HOLD TIMES

1.5 V

Open (all others)

1.5 V

Test Point

RL = R1 = R2

1.5 V

3 V

0 V

3 V

0 V

From Output

Under Test

(see Note A)

High-Level

Pulse

Low-Level

Pulse

LOAD CIRCUIT FOR

TOTEM-POLE OUTPUTS

1.5 V

VOLTAGE WAVEFORMS

PULSE DURATION

Test Point

3 V

1.5 V 0 V

3 V

1.5 V 0 V

Input

In-Phase

Out-of-Phase

NOTES: A. CL includes probe and jig capacitance.

PLH

Output

PHL

Output

PROPAGATION DELAY TIMES (see Note D)

B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.

Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, tr = tf≤ 2.5 ns, duty cycle = 50%. D. The outputs are measured one at a time with one transition per measurement. E. When measuring propagation delay times of 3-state outputs, switch S1 is open.

1.5 V 1.5 V

1.5 V1.5 V

1.5 V 1.5 V

VOLTAGE WAVEFORMS

Figure 9. Load Circuits and Voltage Waveforms

PHL

PLH

3 V

0 V

Output

Control

(low-level enable)

Waveform 1

(see Note B)

Waveform 2

(see Note B)

ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS

PZL

1.5 V

PZH

1.5 V

VOLTAGE WAVEFORMS

PHZ

3 V

1.5 V1.5 V 0 V

PLZ

3.5 V

0.3 V

0.3 V 0 V

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