Texas Instruments 5962-9172501M3A Datasheet

SN54BCT8373A, SN74BCT8373A

SCAN TEST DEVICES

WITH OCTAL D-TYPE LATCHES

SCBS044F – JUNE 1990 – REVISED JUL Y 1996

Members of the Texas Instruments

SCOPE

Octal Test-Integrated Circuits

Functionally Equivalent to ’F373 and

 Family of Testability Products

’BCT373 in the Normal-Function Mode

Compatible With the IEEE Standard

1149.1-1990 (JTAG) Test Access Port and Boundary-Scan Architecture

Test Operation Synchronous to Test Access Port (TAP)

Implement Optional Test Reset Signal by Recognizing a Double-High-Level Voltage (10 V) on TMS Pin

SCOPE

 Instruction Set

– IEEE Standard 1149.1-1990 Required

Instructions, Optional INTEST, CLAMP,

and HIGHZ – Parallel Signature Analysis at Inputs – Pseudo-Random Pattern Generation

From Outputs – Sample Inputs/Toggle Outputs

Package Options Include Plastic Small-Outline (DW) Packages, Ceramic Chip Carriers (FK), and Standard Plastic and Ceramic 300-mil DIPs (JT, NT)

description

The ’BCT8373A scan test devices with octal D-type latches are members of the Texas Instruments SCOPE testability integrated- circuit family . This family of devices supports IEEE Standard 1 149.1-1990 boundary scan to facilitate testing of complex circuit board assemblies. Scan access to the test circuitry is accomplished via the 4-wire test access port (TAP) interface.

SN54BCT8373A . . . JT PACKAGE

SN74BCT8373A ... DW OR NT PACKAGE

SN54BCT8373A . . . FK PACKAGE

1D OE NC

NC – No internal connection

(TOP VIEW)

GND

TDO

TMS

(TOP VIEW)

3D4D5DNCV6D7D

3212827

426

5 6 7 8 9 10 11

12 13

14 15 16 17

GND

24 23 22 21 20 19 18 17 16 15 14 13

5Q6Q7Q

OE 1D 2D 3D 4D 5D V

6D 7D 8D TDI TCK

25 24 23 22 21 20 19

8D TDI TCK NC TMS TDO 8Q

In the normal mode, these devices are functionally equivalent to the ’F373 and ’BCT373 octal D-type latches. The test circuitry can be activated by the TAP to take snapshot samples of the data appearing at the device terminals or to perform a self test on the boundary test cells. Activating the TAP in normal mode does not affect the functional operation of the SCOPE octal latches.

In the test mode, the normal operation of the SCOPE octal latches is inhibited and the test circuitry is enabled to observe and control the I/O boundary of the device. When enabled, the test circuitry can perform boundary scan test operations, as described in IEEE Standard 1149.1-1990.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

SCOPE is a trademark of Texas Instruments Incorporated.

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

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On products compliant to MIL-PRF-38535, all parameters are tested unless otherwise noted. On all other products, production processing does not necessarily include testing of all parameters.

SN54BCT8373A, SN74BCT8373A SCAN TEST DEVICES WITH OCTAL D-TYPE LATCHES

SCBS044F – JUNE 1990 – REVISED JUL Y 1996

description (continued)

Four dedicated test terminals are used to control the operation of the test circuitry: test data input (TDI), test data output (TDO), test mode select (TMS), and test clock (TCK). Additionally, the test circuitry can perform other testing functions such as parallel signature analysis (PSA) on data inputs and pseudo-random pattern generation (PRPG) from data outputs. All testing and scan operations are synchronized to the T AP interface.

The SN54BCT8373A is characterized for operation over the full military temperature range of –55°C to 125°C. The SN74BCT8373A is characterized for operation from 0°C to 70°C.

FUNCTION TABLE

(normal mode, each latch)

INPUTS

OE LE D

L H H H L HL L L LX Q

H X X Z

OUTPUT

logic symbol

†

This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.

Pin numbers shown are for the DW, JT, and NT packages.

†

SCAN

TDI

TMS

TCK

1D 1Q

3D 3Q

4D 4Q

5D 5Q

6D 6Q

7D 7Q

8D 8Q

TDI TMS

TCK-IN

TCK-OUT EN C1

’BCT8373A

TDO

2 3

4 5 7 8 9

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functional block diagram

SN54BCT8373A, SN74BCT8373A

SCAN TEST DEVICES

WITH OCTAL D-TYPE LATCHES

SCBS044F – JUNE 1990 – REVISED JUL Y 1996

Boundary-Scan Register

TDI

TMS

TCK

Boundary-Control

Instruction Register

TAP

Controller

One of Eight Channels

Bypass Register

TDO

Pin numbers shown are for the DW, JT, and NT packages.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

SN54BCT8373A, SN74BCT8373A SCAN TEST DEVICES WITH OCTAL D-TYPE LATCHES

SCBS044F – JUNE 1990 – REVISED JUL Y 1996

Terminal Functions

TERMINAL

NAME

1D–8D

GND Ground

1Q–8Q Normal-function data outputs. See function table for normal-mode logic.

TCK

TDI

TDO

TMS

Normal-function data inputs. See function table for normal-mode logic. Internal pullups force these inputs to a high level if left unconnected.

Normal-function latch-enable input. See function table for normal-mode logic. An internal pullup forces LE to a high level if left unconnected.

Normal-function output-enable input. See function table for normal-mode logic. An internal pullup forces OE to a high level if left unconnected.

T est clock. One of four terminals required by IEEE Standard 1149.1-1990. Test operations of the device are synchronous to TCK. Data is captured on the rising edge of TCK and outputs change on the falling edge of TCK. An internal pullup forces TCK to a high level if left unconnected.

T est data input. One of four terminals required by IEEE Standard 1 149.1-1990. TDI is the serial input for shifting data through the instruction register or selected data register. An internal pullup forces TDI to a high level if left unconnected.

Test data output. One of four terminals required by IEEE Standard 1149.1-1990. TDO is the serial output for shifting data through the instruction register or selected data register. An internal pullup forces TDO to a high level when it is not active and is not driven from an external source.

Test mode select. One of four terminals required by IEEE Standard 1149.1-1990. TMS directs the device through its TAP controller states. An internal pullup forces TMS to a high level if left unconnected. The TMS pin also provides the optional test reset signal of IEEE Standard 1149.1-1990. This is implemented by recognizing a third logic level, double-high (V at TMS.

Supply voltage

DESCRIPTION

IHH

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

SN54BCT8373A, SN74BCT8373A

SCAN TEST DEVICES

WITH OCTAL D-TYPE LATCHES

SCBS044F – JUNE 1990 – REVISED JUL Y 1996

test architecture

Serial test information is conveyed by means of a 4-wire test bus, or TAP, that conforms to IEEE Standard 1 149.1-1990. Test instructions, test data, and test control signals all are passed along this serial test bus. The TAP controller monitors two signals from the test bus, TCK and TMS. The TAP controller extracts the synchronization (TCK) and state control (TMS) signals from the test bus and generates the appropriate on-chip control signals for the test structures in the device. Figure 1 shows the TAP-controller state diagram.

The T AP controller is fully synchronous to the TCK signal. Input data is captured on the rising edge of TCK, and output data changes on the falling edge of TCK. This scheme ensures that data to be captured is valid for fully one-half of the TCK cycle.

The functional block diagram shows the IEEE Standard 1149.1-1990 4-wire test bus and boundary-scan architecture and the relationship between the test bus, the T AP controller , and the test registers. As shown, the device contains an 8-bit instruction register and three test data registers: an 18-bit boundary-scan register, a 2-bit boundary-control register, and a 1-bit bypass register.

Test-Logic-Reset

TMS = H

TMS = L

Run-Test/Idle Select-DR-Scan

TMS = L

Capture-DR

TMS = L

Shift-DR

TMS = L

TMS = H

Exit1-DR

TMS = L

Pause-DR

TMS = L

TMS = H

Exit2-DR

TMS = H

TMS = HTMS = H

TMS = H TMS = H

TMS = L

Select-IR-Scan

TMS = H

TMS = L

Capture-IR

TMS = L

Shift-IR

TMS = L

TMS = H

Exit1-IR

TMS = L

Pause-IR

TMS = L

TMS = H

Exit2-IR

TMS = H

Update-DR

TMS = LTMS = H

Figure 1. TAP-Controller State Diagram

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Update-IR

TMS = LTMS = H

SN54BCT8373A, SN74BCT8373A SCAN TEST DEVICES WITH OCTAL D-TYPE LATCHES

SCBS044F – JUNE 1990 – REVISED JUL Y 1996

state diagram description

The T AP controller is a synchronous finite state machine that provides test control signals throughout the device. The state diagram shown in Figure 1 is in accordance with IEEE Standard 1149.1-1990. The TAP controller proceeds through its states based on the level of TMS at the rising edge of TCK.

As shown, the T AP controller consists of 16 states. There are six stable states (indicated by a looping arrow in the state diagram) and ten unstable states. A stable state is a state the T AP controller can retain for consecutive TCK cycles. Any state that does not meet this criterion is an unstable state.

There are two main paths though the state diagram: one to access and control the selected data register and one to access and control the instruction register. Only one register can be accessed at a time.

Test-Logic-Reset

The device powers up in the T est-Logic-Reset state. In the stable Test-Logic-Reset state, the test logic is reset and is disabled so that the normal logic function of the device is performed. The instruction register is reset to an opcode that selects the optional IDCODE instruction, if supported, or the BYP ASS instruction. Certain data registers also can be reset to their power-up values.

The state machine is constructed such that the T AP controller returns to the Test-Logic-Reset state in no more than five TCK cycles if TMS is left high. The TMS pin has an internal pullup resistor that forces it high if left unconnected or if a board defect causes is to be open circuited.

For the ′BCT8373A, the instruction register is reset to the binary value 11111111, which selects the BYPASS instruction. The boundary-control register is reset to the binary value 10, which selects the PSA test operation.

Run-T est/Idle

The T AP controller must pass through the Run-T est/Idle state (from T est-Logic-Reset) before executing any test operations. The Run-Test/Idle state also can be entered, following data-register or instruction-register scans. Run-Test/Idle is a stable state in which the test logic may be actively running a test or may be idle.

The test operations selected by the boundary-control register are performed while the T AP controller is in the Run-Test/Idle state.

Select-DR-Scan, Select-lR-Scan

No specific function is performed in the Select-DR-Scan and Select-lR-Scan states, and the T AP controller exits either of these states on the next TCK cycle. These states allow the selection of either data-register scan or instruction-register scan.

Capture-DR

When a data-register scan is selected, the TAP controller must pass through the Capture-DR state. In the Capture-DR state, the selected data register may capture a data value, as specified by the current instruction. Such capture operations occur on the rising edge of TCK, upon which the T AP controller exits the Capture-DR state.

Shift-DR

Upon entry to the Shift-DR state, the data register is placed in the scan path between TDI and TDO and, on the first falling edge of TCK, TDO goes from the high-impedance state to an active state. TDO enables to the logic level present in the least-significant bit of the selected data register.

While in the stable Shift-DR state, data is serially shifted through the selected data register on each TCK cycle. The first shift occurs on the first rising edge of TCK after entry to the Shift-DR state (i.e., no shifting occurs during the TCK cycle, in which the T AP controller changes from Capture-DR to Shift-DR or from Exit2-DR to Shift-DR). The last shift occurs on the rising edge of TCK, upon which the TAP controller exits the Shift-DR state.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

SN54BCT8373A, SN74BCT8373A

SCAN TEST DEVICES

WITH OCTAL D-TYPE LATCHES

SCBS044F – JUNE 1990 – REVISED JUL Y 1996

Exit1-DR, Exit2-DR

The Exit1-DR and Exit2-DR states are temporary states that end a data register scan. It is possible to return to the Shift-DR state from either Exit1-DR or Exit2-DR without recapturing the data register.

On the first falling edge of TCK after entry to Exit1-DR, TDO goes from the active state to the high-impedance state.

Pause-DR

No specific function is performed in the stable Pause-DR state, in which the TAP controller can remain indefinitely. The Pause-DR state suspends and resumes data-register scan operations without loss of data.

Update-DR

If the current instruction calls for the selected data register to be updated with current data, then such update occurs on the falling edge of TCK, following entry to the Update-DR state.

Capture-IR

When an instruction-register scan is selected, the TAP controller must pass through the Capture-IR state. In the Capture-IR state, the instruction register captures its current status value. This capture operation occurs on the rising edge of TCK, upon which the TAP controller exits the Capture-IR state.

For the ′BCT8373A, the status value loaded in the Capture-IR state is the fixed binary value 10000001.

Shift-IR

Upon entry to the Shift-IR state, the instruction register is placed in the scan path between TDI and TDO and, on the first falling edge of TCK, TDO goes from the high-impedance state to an active state. TDO enables to the logic level present in the least-significant bit of the instruction register.

While in the stable Shift-IR state, instruction data is serially shifted through the instruction register on each TCK cycle. The first shift occurs on the first rising edge of TCK after entry to the Shift-IR state (i.e., no shifting occurs during the TCK cycle, in which the TAP controller changes from Capture-IR to Shift-IR or from Exit2-IR to Shift-IR). The last shift occurs on the rising edge of TCK, upon which the T AP controller exits the Shift-IR state.

Exit1-IR, Exit2-IR

The Exit1-IR and Exit2-IR states are temporary states used to end an instruction-register scan. It is possible to return to the Shift-IR state from either Exit1-IR or Exit2-IR without recapturing the instruction register.

On the first falling edge of TCK after entry to Exit1-IR, TDO goes from the active state to the high-impedance state.

Pause-IR

No specific function is performed in the stable Pause-IR state, in which the TAP controller can remain indefinitely. The Pause-IR state suspends and resumes instruction-register scan operations without loss of data.

Update-IR

The current instruction is updated and takes effect on the falling edge of TCK, following entry to the Update-IR state.

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