Datasheet 73S8024C Datasheet (TERIDIAN Semiconductor)

73S8024C

Smart Card Interface

Simplifying System Integration™

DATA SHEET

April 2009

DESCRIPTION

The Teridian 73S8024C is a single smart card
interface IC. It provides full electrical compliance
with ISO-7816-3, EMV 4.0 and NDS specifications

1

Interfacing with the system controller is done through
the control bus, composed of digital inputs to control
the interface, and one interrupt output to inform the
system controller of the card presence and faults.
Data exchange with the card is managed from the
system controller using the I/O line (and eventually
the auxiliary I/O lines). Hardware support for
auxiliary I/O lines, C4 / C8 contacts, is provided.

The card clock signal can be generated by an on-chip
oscillator using an external crystal or by connection to
a clock signal coming from the sy stem co ntrolle r.

The Teridian 73S8024C device incorporates an
ISO-7816-3 activation/deactivation sequencer that
controls the card signals. Level shifters drive the
card signals with the selected card voltage (3 V or
5 V), coming from an internal DC-DC converter.

With its high-efficiency DC-DC converter, the
Teridian 73S8024C is a cost-effective solution for
any smart card reader application to be powered
from a single 2.7 V to 3.6 V power supply.

Emergency card deactivation is initiated upon card
extraction or upon any fault generated by the
protection circuitry. The fault can be a V
power supply) or a V
a card over-current,

(card power supply) failure,

CC

an over-heating fault.

or

(digital

DD

ADVANTAGES

• The only smart card interface IC firmwar e
compatible with the TDA8004 operating with a
single 2.7 V to 3.6 V power supply (allows
removal of 5 V from the system)

• The inductor-based DC-DC converter provides
higher current and efficiency than the usual
charge-pump capacitor-based converters

 Ideal for battery-powered applications
 Suitable for high current cards and SAMs:

(100 mA max)

• Power down mode: 2 µA typical

FEATURES

• Card Interface:

 Complies with ISO-7816-3, EMV 4.0 and NDS

.

 A DC-DC Converter provides 3V / 5V to the

card from an external power supply input

 High-efficiency converter: > 80% @

=3.3 V, VCC=5 V and I

V

DD

CC

 Up to 100 mA supplied to the card
 ISO-7816-3 Activation / Deactivation

sequencer with emergency automated
deactivation on card removal or fault
detected by the protection circuitry

 Protection includes 2 voltage supervisors

which detect voltage drops on card V
on V

 The V

power supplies

DD

voltage supervisor threshold value

DD

can be externally adjusted

 True over-current detection (150 mA max.)
 2 card detection inputs, 1 for each possible

user polarity

 Auxiliary I/O lines, for C4/C8 contact signals
 Card clock up to 20 MHz

• System Controller Interface:

 3 Digital inputs control the card activ ation /

deactivation, card reset and card voltage

 4 Digital inputs control the card clock

(division rate and card clock stop modes)

 1 Digital output, interrupt to the syst em

controller, allows the system controller to
monitor the card presence and faults.

 Crystal oscillator or host clock, up to 27 MHz

• Power Supply: V

2.7 V to 3.6 V

DD

• Power Down mode

• 6 kV ESD Protection on the card interface

• Package: SO28

APPLICATIONS

• Set-Top-Boxes , DVD / HDD Recorders

• Point of Sales and Transaction Terminals

• Control Access and Identification

1

Pending NDS approval.

= 65 mA

CC

and

1

Rev. 1.3 © 2009 Teridian Semiconductor Corporation 1

73S8024C Data Sheet DS_8024C_023

ICC I/O BUFFERS

VDD VOLTAGE SUPERVISOR

VOLTAGE REFERENCE

XTAL

OSC

CLOCK

GENERATION

DIGITAL

CIRCUITRY

&

FAULT LOGIC

VDD FAULT

V

CC

FAULT

Int_Clk

VDD VDD

VCC

RST

CLK

PRES

PRES

XTALIN

XTALOUT

CLKDIV1

CLKDIV2

GND

TEMP FAULT

NC

1

2

3

5

6

7

9

10

11

12

13

14

15

17

16

21

20

19

18

26

25

24

23

28

27

ISO-7816-3

SEQUENCER

R-C

OSC.

DC-DC

CONVERTER

ICC RESET

BUFFER

ICC CLOCK

BUFFER

OVER
TEMP

PWRDN

I/O

AUX1

AUX2

IOUC

AUX1UC

AUX2UC

VDDF_ADJ

RSTIN

CMDVCC

5V/#V

OFF

8

GND

4

6

LIN

6

22

GND

ICC FAULT

FUNCTIONAL DIAGRAM

Pin number reference to SO28 Package

Figure 1: 73S8024C Block Diagram

2 Rev. 1.3

DS_8024C_023 73S8024C Data Sheet

Table of Contents

1 Pin Description .................................................................................................................................... 4

1.1

Card Interface ............................................................................................................................... 4

Miscellaneous Inputs and Outputs ................................................................................................ 4

1.2

Power supply and ground ............................................................................................................. 4

1.3

Microcontroller Interface ............................................................................................................... 5

1.4

System Controller Interface ............................................................................................................... 6

2

Oscillator .............................................................................................................................................. 6

3

DC-DC Converter – Card Power Supply ........................................................................................... 7

4

Over-temperature Monitor .................................................................................................................. 7

5

Voltage Supervision ........................................................................................................................... 8

6

Power Down ......................................................................................................................................... 8

7

Activation Sequence ........................................................................................................................... 9

8

Deactivation Sequence ..................................................................................................................... 10

9

OFF and Fault Detection .................................................................................................................. 11

10

I/O Circuitry and Timing ................................................................................................................... 12

11

Typical Application Schematic ........................................................................................................ 13

12

Electrical Specification ..................................................................................................................... 14

13

13.1

Absolute Maximum Ratings ........................................................................................................ 14

Recommended Operating Conditions ......................................................................................... 14

13.2

Card Interface Characteristics .................................................................................................... 15

13.3

Digital Signals ............................................................................................................................. 18

13.4

DC Characteristics ...................................................................................................................... 18

13.5

Voltage / Temperature Fault Detection Circuits .......................................................................... 18

13.6

Mechanical Drawings (28-SO) .......................................................................................................... 19

14

Package Pin Designation (28-SO) ................................................................................................... 20

15

Ordering Information ........................................................................................................................ 21

16

Related Documentation .................................................................................................................... 21

17

Contact Information .......................................................................................................................... 21

18
Revision History

Figures

........................................................................................................................................ 22

Figure 1: 73S8024C Block Diagram ............................................................................................................. 2

Figure 2: Power Down Mode Operation
Figure 3: Activation Sequence – RSTIN low when CMDVCC goes low
Figure 4: Activation Sequence – RSTIN high when CMDVCC goes low

Figure 5: Deactivation Sequence ............................................................................................................... 11

Figure 6: Timing Diagram – Management of the Interrupt Line OFF
Figure 7: I/O and I/OUC State Diagram
Figure 8: I/O – I/OUC Delays: Timing Diagram
Figure 9: 73S8024C Typical Application Schematic
Figure 10: DC – DC Converter efficiency (V
Figure 11: DC – DC Converter Efficiency (V
Figure 12: 28 Lead SO

= 5 V) ................................................................................ 16

CC

= 3 V) ................................................................................ 16

CC

........................................................................................................ 9

....................................................... 9

................................................... 10

.......................................................... 11

...................................................................................................... 12

........................................................................................... 12

................................................................................... 13

................................................................................................................................ 19

Table

Table 1: Choice of VCC Pin Capacitor .......................................................................................................... 7

Rev. 1.3 3

73S8024C Data Sheet DS_8024C_023

1 Pin Description

1.1 Card Interface

Name

IO 11 Card I/O: Data signal to/from card. Includes a pull-up resistor to V

Pin

(SO)

Description

CC.

AUX1 13 AUX1: Auxiliary data signal to/from card. Includes a pull-up resistor to V
AUX2 12 AUX2: Auxiliary data signal to/from card. Includes a pull-up resistor to V
RST 16 Card reset: provides reset (RST) signal t o card.
CLK 15

Card clock: provides clock (CLK) signal to card. The rate of this clock is
determined by crystal oscillator frequency and CLKDIV selections.

PRES 10

Card Presence switch: active high indicates card is present. Includes a pull­down current source.

PRES 9

Card Presence switch: active low indicates c ard is present. Includes a pull-up
current source.

VCC 17

Card power supply: logically controlled by t he sequencer, output of DC-DC
converter. Requires an external filter capacitor to the card GND.

GND 14 Card ground.

1.2 Miscellaneous Inputs and Outputs

Name

XTALIN

XTALOUT

VDDF_ADJ

NC

Pin

(SO)

24

25

18

7

Description

Crystal oscillator input: can either be conne ct ed to crystal or driven as a source
for the card clock.

Crystal oscillator output: connected to crystal. Left open if XTALIN is being
used as an external clock input.

VDD fault threshold adjustment input: this pin can be used to adjust the V
value (that controls deactivation of the card). Must be left open if unused.

Non-connected pin.

1.3 Power supply and ground

CC.

CC.

DDF

Name

VDD 6, 21

Pin

(SO)

Description

System controller interface supply volt age, supply voltage for internal power

supply and DC-DC converter power supply source.
GND 4 DC-DC converter ground.
GND 22 Digital ground.
LIN 5 External inductor. Connect external inductor from pin 5 to VDD. Keep the

inductor close to pin 5.

4 Rev. 1.3

DS_8024C_023 73S8024C Data Sheet

1.4 Microcontroller Interface

Name

CMDVCC 19

5V/#V

Pin

(SO)

3

Description

Command V
converter to ramp the V

(negative assertion): Logic low on this pin causes the DC-DC

CC

supply to the card and initiates a card activation sequence.

CC

5 volt / 3 volt card sel ecti on: Logi c one select s 5 volt s fo r V

and card interface, logic

CC

low selects 3 volt operation. Whe n the part i s to be use d wit h a sin gle c ard voltage,
this pin should be tie d to e ither GND o r V

. However, it includes a high impedance

DD

pull-up resistor to default this pin hig h (sele ction of 5 V card) when unconnected.

PWRDN 8

Power Down control input (active high): When Power Down (PD) mode is
activated; all internal analog functions are disabled to place the 73S8024C in its
lowest power consumption mode. The PD mode is allowed only out of a card
session (= PWRDN high is not taken into account when CMDVCC = 0). Must be
tied to ground when the power down function is not used.

CLKDIV1
CLKDIV2

Sets the divide ratio from the XTALIN oscillator (or external clock input) to the card

1

clock. These pins include pull-down resistors.

2

CLKDIV1 CLKDIV2 Clock Rate

0 0 XTALIN/8
0 1 XTALIN/4
1 1 XTALIN/2
1 0 XTALIN

OFF 23

Interrupt signal to the processor (active low): Multi-function indicating fault
conditions and card presence. Open drain output configuration; it includes an
internal 20 kΩ pull-up to V

DD.

RSTIN 20 Reset Input: This signal is the res et command to the card.
I/OUC 26 System controller data I/O to/from the card. Includes internal pull-up resistor to V
AUX1UC 27

AUX2UC 28

System controller auxiliary data I/O to/from the card. Includes internal pull-up
resistor to V

DD.

System controller auxiliary data I/O to/from the card. Includes internal pull-up
resistor to V

DD.

DD.

Rev. 1.3 5

73S8024C Data Sheet DS_8024C_023

2 System Controller Interface

• 2 digital inputs allow direct control of the card int erface from the host as follows:

 Pin CMDVCC: When low, starts an activation sequence if a card is present.
 Pin 5V/#V: Defines the card voltage.

• The card I/O and Reset signals have their corresponding controller I/Os to be connected directly to
the host:

 Pin RSTIN: controls the card reset signal (when enabled by the sequencer).
 Pin I/OUC: data transfer to card I/O contact.
 Pins AUX1UC and AUX2UC (auxiliary I/O l i nes as sociated to the auxiliary I/O lines to be

connected to the C4 and C8 card connector contact s).

• 2 digital inputs control the card clock frequen cy di vision rate: CLKDIV1 and CLKDIV2 define the card
clock frequency, from the input clock fre quency (crystal or external clock). The division rate is defined
as follows:

CLKDIV2 CLKDIV1 CLK

0 0
0 1 XTAL

1 0 ¼ XTAL
1 1 ½ XTAL

When the division rate is equal to 1 (CLKDIV2 =0 and CLKDIV 1 = 1), the duty-cycle of the
card clock depends on the duty-cycle and wavefor m of the signal applied on the pin XTALIN.
When other division rates are used, the 73S8024C circuitry guarantees a duty-cycle in the
range 45% to 55%, conforming to ISO-7816-3, E M V 4.0 and NDS specifications.

• Interrupt output to the host: As long as the car d i s not activated, the OFF pin informs the host about
the card presence only (low = no card in the reader). When CMDVCC is set low (Card activation
sequence requested from the host), a low level on OFF means a fault has been detected (e.g. card
removed during a card session, or voltage fault , or thermal / over-current fault) that automatically
initiates a deactivation sequence.

• Power Down: The PWRDN pin is a digit al input that allows the host controller to put the 73S8024C in
its Power Down state. This pin can only be activated out of a card session.

⅛ XTAL

3 Oscillator

The 73S8024C device has an on-chip oscillator that c an generate the smart card clock using an external
crystal (connected between the pins XTALI N and XTALOUT) to set the oscillator frequency. When the
card clock signal is available from another source, i t can be connected to the pin XTALIN, and the pin
XTALOUT should be left unconnected.

6 Rev. 1.3

DS_8024C_023 73S8024C Data Sheet

4 DC-DC Converter – Card Power Supply

An internal DC-DC converter provides the card powe r supply. This converter is able to provide either 3 V
or 5 V card voltage from the power supply applied on the V
controls the converter. Card voltage selection is carried out by the digital input 5V/#V.

The circuit is an inductive step-up converter/regulator. The external components required are 2 filter
capacitors on the power-supply input V
output filter capacitor on the card power supply V
step-up operation when V
and the input supply V

= 3.6 V, VCC =3 V) the circuit operates as a linear regulator.

(V

DD

is below a set point of 5.0 or 3.0 volts minus a comparator hysteresis voltage

CC

is less than the set point for VCC. When VDD is greater than the set point for VCC

DD

(next to the LIN pin, 100 nF + 10 µF), an inductor, and an

DD

. The circuit performs regulation by activat ing the

CC

Depending on the inductor values, the voltage converter can provide current on V
The circuit provides over-current protect i on and l im i ts I
sensed, the circuit initiates a deactivation sequence from the control logic and reports back to the host
controller a fault on the interrupt output OFF.

Choice of the inductor

The nominal inductor value is 10 µH, rated for 400 mA. The inductor is connected between LIN (pin 5 in
the SO package, pin 2 in the QFN package) and the V
meet a particular configuration (I

). The inductor should be located on the PCB as close as possible

CC_MAX

DD

to the LIN pin of the IC.

Choice of the V

capacitor

CC

Depending on the applications, the requirements in terms of both the V
transient currents that the interface must provide to the card are different. shows the
recommended capacitors for each V

power supply configuration and applicabl e specification.

CC

Table 1: Choice of VCC Pin Capaci to r

pin. The digital ISO-7816-3 sequencer

DD

as high as 100 mA.

to 150 mA. When an over-current condition is

CC

CC

voltage. The inductor value can be optimized to

minimum voltage and the

CC

Table 1

Specification Requirement Application

Min V

Specification

Allowed During

Transient Current

EMV 4.0 4.6 V 30 nAs
ISO-7816-3 4.5 V 20 nAs

Voltage

CC

Max Transient

Current Charge

Capacitor

Type

X5R/X7R w/

ESR < 100 mΩ

Capacitor

Value

3.3 µF
1 µF

Table 1: Choice of VCC Pin Capacitor

5 Over-temperature Monitor

A built-in detector monitors die temperature. When an over-temperature condition occurs, a card
deactivation sequence is initiated, and an error or fault condition is reported to the system controller.

Rev. 1.3 7

73S8024C Data Sheet DS_8024C_023

6 Voltage Supervision

Two voltage supervisors constantly check the level of the voltages VDD and VCC. A card deactivation
sequence is triggered upon a fault of any of these voltage supervisors.

The digital circuitry is powered by the power supply appli ed on the VDD pin. VDD also defines the voltage
range for the interface with the system controller. The V

Voltage supervisor is also used to initialize the

DD

ISO-7816-3 sequencer at power-on, and also to deactivate the card at power-off or upon a fault. The
voltage threshold of the V

voltage supervisor is internally set by default to 2.3 V nominal. However, it

DD

may be desirable, in some applications, to m odi fy this threshold value. The pin VDDF_ADJ (pin 18 in the
SO package, pin 17 in the QFN package) is used to connect an external resistor R
the V

fault voltage to another value, V

DD

R

= 180 kΩ / (V

EXT

- 2.33)

DDF

An alternative (more accurate) method of adjusting t he V
R3 from the pin to supply and R1 from the pin to ground (see ). In order to set the new threshold

. The resistor value is defined as follows:

DDF

fault voltage is to use a resistive network of

DD

Figure 9

to ground to raise

EXT

voltage, the equivalent resistance must be determined. This resistance value will be designat ed Kx. Kx
is defined as R1/(R1+R3) and is calculated as:

Kx = (2.649 / VTH) - 0.6042 where VTH is the desired new threshold voltage.

To determine the values of R1 and R3, use the following formulas:

R3 = 72000 / Kx R1 = R3*(Kx / (1 – Kx))

Taking the example above, where a V

fault threshold voltage of 2.7 V is desired, solving for Kx gives:

DD

 Kx = (2.649 / 2.7) - 0.6042 = 0.377.

Solving for R3 gives:  R3 = 72000 / 0.377 = 191 kΩ.
Solving for R1 gives:  R1 = 191000 *(0.377 / (1 – 0.377)) = 115.6 kΩ.

Using standard 1% resistor values gives R3 = 191 kΩ and R1 = 1 15 kΩ. These values give an equivalent
resistance of Kx = 0.376, a 0.3% error.

If the 2.3 V default threshold is used, this pin must be left unconnected.

7 Power Down

A power down function is provided via the PWRDN pin (active high). When activated, the Power Down
(PD) mode disables all the internal analog functions, including the card analog interface, the oscillators
and the DC-DC converter, to put the 73S8024C in i ts lowest power consumption mode. PD mode is o nl y
allowed in the deactivated condition (out of a card session, when the CMDVCC signal is driven high from
the host controller).

The host controller invokes the power down state when it is desirable to save power. The signals PRES
and PRES remain functional in PD mode such that a card ins ertion sets OFF high. The micro-controller
must then set PWRDN low and wait for the internal stabilization time prior to starting any card sessi on
(prior to turning CMDVCC low).

Resumption of the normal mode occurs at approxi mately 10 ms (stabilization of the internal oscillat ors
and reset of the circuitry) after PWRDN is set low. No card activation shoul d be invoked during this 10 ms
time period. If a card is present, OFF can be used as an i ndication that the circuit has completed its
recovery from the power down state. OFF will go high at the end of t he st abi lization period. Should
CMDVCC go low during PWRDN = 1, or wi thin the 10 ms internal stabilization / reset tim e, it will not be
taken into account and the card interface will remain inactive. Since CMDVCC is take n i nto account on
its edges, it should be toggled high and low again after the 10 ms to activate a card.

Figure 2 illustrates the sequencing of the P D and Normal modes. PWRDN must be connected to GND if

the power down function is not used.
8 Rev. 1.3

DS_8024C_023 73S8024C Data Sheet

t1 = 0.510 ms (timing by 1.5 MHz internal Oscillator)
t4 ≥ 42000 card clock cycles (time for RST to become the copy of RSTIN)

CMDVCC

VCC

IO

CLK

RSTIN

t

1

t

2

t

3

t

4

RST

PRES

OFF

PWRDN

Internal RC OSC

CMDVCC

OFF follows PRES regardless of PWRDN

PWRDN during a card

session has no effect

After setting PWRDN = 0,
the controller must wait at

least 10ms before setting

CMDVCC=0

EMV / ISO deactivation

time ~= 100 uS

~10ms

PWRDN has effect when

the cardi s deactivated

Figure 2: Power Down Mode Operation

8 Activation Sequence

The 73S8024C smart card interface IC has an internal 10 ms delay at power-on reset or upon application

> V

of V

DD

high which indicates a card is present. No activation is allowed at this time. CMDVCC (edge trigge red )
must then be set low to activate the card.

The following steps and
when the system controller sets CMDVCC low while the RSTIN is low:

1. CMDVCC is set low.

2. Next, the internal V
the voltage V
low to report a fault to the system controller, and t he power V

3. Turn I/O (AUX1, AUX2) to reception mode at the end of t

4. Due to the fall of RSTIN, CLK is applied to the card at the end of t

5. RST is a copy of RSTIN after t
RST high until 42000 clock cycles after the start of CLK.

or upon exit of Power-Down mode. The card interface may only be activated when OFF is

DDF

Figure 3 show the activation sequence and the timing of the card control signals

control circuit checks the presence of VCC at the end of t1. In normal operation,

CC

to the card becomes valid during t1. If VCC does not become valid, then OFF goes

CC

to the card is shut down.

CC

.

2

.

3

. RSTIN may be set high before t

4

, however the sequencer won’t set

4

t2 = 1.5 µs, I/O goes to reception state t3 = >0.5 µs, CLK starts

Rev. 1.3 9

Figure 3: Activation Sequence – RSTIN low when CMDVCC goes low

73S8024C Data Sheet DS_8024C_023

t4 ≥ 42000 card clock cycles (time for RST to become the copy of RSTIN).

CMDVCC

VCC

IO

CLK

RSTIN

t

1

t

2

t

3

t

4

RST

The following steps and Figure 4 show the activation sequence and the timing of the card cont rol signals
when the system controller pulls CMDVCC low while RSTIN is high:

1. CMDVCC is set low.

2. Next, the internal V
the voltage V

CC

the system controller and the V

3. After the fall of RSTIN at t

4. CLK is applied to the card at the end of t

5. RST is a copy of RSTIN after t

control circuit checks the presence of VCC at the end of t1. In normal operation,

CC

to the card becomes valid during this time. If not, OFF goes low to report a fault to

power to the card is shut down.

CC

, turn I/O (AUX1, AUX2) to reception mode.

2

after I/O is in reception mode.

3

. RSTIN may be set high before t

4

, however the sequencer will not

4

set RST high until 42,000 clock cycles after the st art of CLK.

t1 = 0.510 ms (timing by 1.5MHz internal Oscillator)

= 1.5 µs, I/O goes to reception state t3 ≥ 0.5 µs, CLK active

t

2

Figure 4: Activation Sequence – RSTIN high when CMDVCC goes low

9 Deactivation Sequence

Deactivation is initiated either by the system controller by setting the CMDVCC high, or automatically in
the event of hardware faults. Hardware faults are over-current, overheating, V

fault, V

DD

extraction during the session.
The following steps and

Figure 5 show the deactivation sequence and the timing of the card control signals

when the system controller sets the CMDVCC high or OFF goes low due to a fault or card removal:

1. RST goes low at the end of time t

2. CLK is set low at the end of time t

3. I/O goes low at the end of time t

4. V

is turned off at the end of time t4. After a delay t5 (discharge of the VCC capacitor), V

CC

.

1

.

2

. Out of reception mode.

3

fault, and card

CC

is low.

CC

10 Rev. 1.3

DS_8024C_023 73S8024C Data Sheet

PRES

OFF

CMDVCC

VCC

outside card session within card session

OFF is low by
card extracted

OFF is low by

any fault

within card

session

RST
CLK

I/O

VCC

t

1

t

2

t

3

t

4

t

5

CMDVCC

-- OR --

OFF

t1≥ 0.5 µs, timing by 1.5 MHz internal Oscill ator

≥ 7.5 µs t3 ≥ 0.5 µs t4 ≥ 0.5 µs

t

2

t

= depends on VCC filter capacitor

5

For NDS application, C

= 1 µF making t

F

+ t2 + t3 + t4 + t5 < 100 µs

1

Figure 5: Deactivation Sequence

10 OFF and Fault Detection

There are two cases for which the syste m cont roller can monitor the OFF signal: to query regarding the
card presence outside card sessions, or for fault detection during card sessions.

Monitoring Outside a Card Session
In this condition, CMDVCC is alway s high, OFF is low if the card is not present, and high if t he car d i s

present. Because it is outside a card session, any fault detection will not act upon the OFF signal. No
deactivation is required during this time.

Monitoring During a Card Session
CMDVCC is always low, and OFF falls l ow i f the card is extracted or if any fault is detected. At the same

time that OFF is set low, the sequencer starts the deactivation process.

Figure 6 shows the timing diagram for the CMDVCC, PRES, and OFF signals during a card session and

outside the card session.

Figure 6: Timing Diagram – Management of the Interrupt Line OFF

Rev. 1.3 11

73S8024C Data Sheet DS_8024C_023

Neutral

State

I/OUC

in

I/O

reception

I/OICC

in

No

Yes

No

No

No

Yes

No

Yes

I/O

&

not I/OUC

I/OUC

&

not I/O

I/OUC

I/O

yesyes

Delay from I/O to I/OUC: t

= 100 ns t

= 25 ns

Delay from I/OUC to I/O: t

I/OUC_HL

= 100 ns t

I/OUC_LH

= 25 ns

IO

IOUC

t

IO_HL

t

IO_LH

t

IOUC_HL

t

IOUC_LH

11 I/O Circuitry and Timing

The I/O, AUX1, and AUX2 pins are in the low state after power on reset and they are in the high state
when the activation sequencer turns on the I/O reception state. See Section 8 Activation Sequence for
more details on when the I/O reception is on.

The state of the I/OUC, AUX1UC, and AUX2UC is hi gh after power on reset. Within a card session and
when the I/O reception state is on, the first I/O line on which a falling edge is detected becomes the input
I/O line and the other becomes the output I/O line. When the input I/O line rising edge is detect ed, both
I/O lines return to their neutral state.

Figure 7 shows the state diagram of how the I /O and I/OUC lines are managed to become input or output.

The delay between the I/O signals is shown in Figure 8.

12 Rev. 1.3

Figure 7: I/O and I/OUC State Diagram

IO_HL

IO_LH

Figure 8: I/O – I/OUC Delays: Timing Diagram

DS_8024C_023 73S8024C Data Sheet

C2
22pF

C3

22pF

See NOTE 5

RSTIN_from_uC
CMDVCC_from_uC

C6

100nF

5V/3V_select_from_uC

AUX1UC_to.f rom_uC

AUX2UC_to/f rom_uC

SO28

See NOTE 1

See NOTE 4

CLK trac k should be rou ted
far from RST, I/O, C4 and
C8.

Lo w E SR (< 1 0 0 moh ms) C1
should be placed near the SC
connecter contact

See NOTE 2

Ext ernal_c loc k _f rom uC

See NOTE 3

- OR -

VDD

R2

20K

See NOTE 6

Car d det ection
sw itch is
normally
clos ed.

C1

ND S & I SO7816=1uF, EMV=3.3uF

L1 10uH

R1

Rext1

See
note 7

CLKDIV2_f rom_uC

CLKDIV1_f rom_uC

See note 8

VDD

See
NOTE 1

R3

Rext2

VDD

NOTES:

1) VDD supply must be =2.7V to 3.6V DC.

2) Optional , can be left open

3) Required if external cl ock from uP is used.

4) Required if crystal i s used.
Y1, C2 and C3 must be removed if ext ernal cl ock i s used.

5) Pin can not fl oat. Must be driven or connected to GND
if power down functi on i s not used.

6)Internal pull-up allows it to be left open if unused.

7) Rext 1 and Rext 2 are external resi stors to ground and
Vdd to modify the VDDfault voltage. Can be left open

8) Keep L 1 close to pi n 5

OFF_interrupt_to_uC

VDD

IOUC_to/from_uC

PWRDN_from_uC

Y1

CRYSTAL

Smart C ard C onnec t or

VCC

1

RST

2

CLK

3

C4

4

GND

5

VPP

6

I/O

7

C8

8

SW-19SW-2

10

U5

73S8024C

CLKDIV1

1

CLKDIV2

2

5V3V_

3

GND

4

LIN

5

VDD

6

NC

7

AUX2

12

PWRDN

8

PRESB

9

PRES

10

I/O

11

AUX1

13

GND

14

CLK

15

RST

16

VCC

17

VDD_ADJ

18

CMDVCC_

19

RSTIN

20

VDD

21

GND

22

OFF_

23

AUX2UC

28

AUX1UC

27

XTALOUT

25

XTALIN

24

I/OUC

26

C4

100nF

C5
10uF

12 Typical Application Schematic

Rev. 1.3 13

Figure 9: 73S8024C Typical Application Schematic

73S8024C Data Sheet DS_8024C_023

13 Electrical Specification

13.1 Absolute Maximum Ratings

Operation outside these rating limits may cause permanent damage to the device.

Parameter Rating

Supply Voltage V -0.5 to 4.0 VDC
Input Voltage for Digital Inputs -0.3 to (VDD +0.5) VDC
Storage Temperature -60 °C to 150 °C
Pin Voltage (except LIN and card interface) -0.3 to (VDD +0.5) VDC
Pin Voltage (LIN) -0.3 to 6.0 VDC
Pin Voltage (card interface) -0.3 to (VCC + 0.5) VDC
ESD Tolerance – Card interface pins +/- 6 kV
ESD Tolerance – Other pins +/- 2 kV

ESD testing on Card pins uses the HBM condition, 3 pulses, each polarity referenced to ground.

13.2 Recommended Operating Conditions

DD

Parameter Rating

Supply Voltage V
Ambient Operating Temperature -40 °C to +85 °C
Input Voltage for Digital Inputs 0 V to VDD + 0.3 V

DD

2.7 to 3.6 VDC

14 Rev. 1.3

DS_8024C_023 73S8024C Data Sheet

°

Card supply voltage including

13.3 Card Interface Characteristics

Symbol Parameter Condition Min. Typ. Max. Unit
Card Power Supply (VCC) DC-DC Converter

General conditions, -40

V

CC

I

CCmax

I I

CCF

V

SR

V

SF

C

F

L Inductor (LIN to V
Limax Imax in inductor

η

ripple and noise

Maximum supply current to
the card

CC

V
activate

V
deactivate

External filter capacitor
(V

Efficiency

C < T < 85 °C, 2.7 V < VDD < 3.6 V

slew rate – Rise rate on

CC

slew rate – Fall rate on

CC

to GND)

CC

DD

Inactive mode -0.1 0.1 V
Inactive mode

=1 mA

I

CC

Active mode

< 65 mA; 5 V

I

CC

Active mode

< 65 mA; 3 V

I

CC

-0.1

4.75

2.8

0.4 V

5.25 V

3.2 V

Active mode

single pulse of 100 mA

for 2 µs; 5 V,

4.6 5.25 V

fixed load = 25 mA

Active mode

single pulse of 100 mA

for 2 µs; 3 V,

2.76 3.2 V

fixed load = 25 mA

Active mode

current pulses of 40 nAs

with peak |I

| < 200 mA,

CC

4.6

5.25 V

t < 400 ns; 5 V

Active mode

current pulses of 40 nAs

with peak |I

| < 200 mA,

CC

2.76

3.2 V

t < 400 ns; 3 V

Static load current,

V

> 4.6 or 2.7 volts as

CC

100

mA

selected, L=10 µH

fault current 100 125 180 mA

C

C

on V

F

on V

F

CC

CC

0.05 = 1 µF 0.15 0.25

0.1 = 1 µF 0.3 0.5

0.47 1 3.3

) 10

V

CC

V

CC

= 5 V, I

V

DD

= 5 V, I

V

DD

= 65 mA,

CC

= 2.7 V

= 65 mA,

CC

= 3.3 V

400 mA

80 %

V/µs

V/µs

µF
µH

Rev. 1.3 15

73S8024C Data Sheet DS_8024C_023

1011B01 Converter efficiency (VCC 5V)

50

55

60

65

70

75

80

85

90

95

100

0 20 40 60 80 100

Icc [mA]

Efficiency [%]

2.7V

3.0V

3.3V

3.6V

1011B01 Converter efficiency (VCC 3V)

50

55

60

65

70

75

80

85

90

95

100

0 20 40 60 80 100

Icc [mA]

Efficiency [%]

2.7V

3.0V

3.3V (Linear)

3.6V (Linear)

Converter Efficiency (VCC 5 V)

Converter Efficiency (VCC 3 V)

Figure 10: DC – DC Converter efficiency (V

Output current on V

at 5 V. Input voltage on V

CC

= 5 V)

CC

at 2.7, 3.0, 3.3 and 3.6 volts.

DD

16 Rev. 1.3

Output current on V

Figure 11: DC – DC Converter Efficiency (V

at 3 V. Input voltage on VDD at 2.7, 3.0, 3.3 and 3.6 volts.

CC

= 3 V)

CC

DS_8024C_023 73S8024C Data Sheet

OH

IL

OL

OL

IL

IL

IN

OH

Symbol Parameter Condition Min. Typ. Max. Unit
Interface Requirements – Data Signals: I/O, AUX1, AUX2, and host interfaces: I/OUC, AUX1UC,

AUX2UC. I

requirements only pertain to I//OUC, AUX1U C, and AUX2UC.

I

IL

V

OH

V

OH

V Output level, low

I

OL

V

1.8 V

IH

V

1.8 V

IH

V Input level, low

-0.3 0.8 V

V

INACT

I Input leakage

VIH = V

LEAK

I Input current, low

IL

, I

SHORTL

Output level, high (I/O, AUX1,
AUX2)

Output level, high (I/OUC,
AUX1UC, AUX2UC)

Input level, high (I/O, AUX1,
AUX2)

Input level, high (I/OUC,
AUX1UC, AUX2UC)

Output voltage when outside
of session

SHORTH

, and V

requirements do not pertain to I//OUC, A UX1UC, and AUX2UC.

INACT

I

OH

I

OL

I

V
V

I

OH

= -40 µA

I

OH

= -40 µA

I

CC

10

0.9 V = 0

0.75 V

0.9 V = 0

0.75 V

V

CC

V

CC

V

DD

V

DD

CC
CC
DD
DD

= 1 mA 0.3 V

CC

DD

= 0 0.1 V
= 1 mA 0.3 V

= 0, CS = 1 0.65 mA
= 0, CS = 0 5 μA

V + 0.1
V + 0.1
V + 0.1
V + 0.1

V + 0.30

V + 0.30

µA

For output low,

I Short circuit output current

SHORTL

shorted to V

CC

15 mA

through 33 Ω

For output high,

I Short circuit output current

SHORTH

shorted to ground

15 mA

through 33 Ω

C

= 80 pF, 10% to

L

tR, t Output rise time, fall times

F

90%. For I/OUC,

AUX1UC, AUX2UC,

100 ns

CL = 50 pF

tIR, t Input rise, fall times

IF

R Internal pull-up resistor

PU

FD Maximum data rate

1

MAX

Output stable for

> 200ns

1

8 11 14

µs

kΩ

MHz

Delay, I/O to I/OUC,

T

100 ns

FDIO

I/OUC to I/O
(falling edge to falling edge)

C Input capacitance

10 pF

Reset and Clock for card interface, RST, CLK

V Output level, high

OH

V Output level, low

OL

V

INACT

I Output current limit, RST

RST_LIM

I Output current limit, CLK

CLK_LIM

tR, t Output rise time, fall time

F

δ

Output voltage when outside
of a session

30 mA
70 mA

Duty cycle for CLK, except for f
= f

XTAL

I

= -200 µA

I

= 200 µA

OL

I

OL

I

OL

= 35 pF for CLK,

C

L

10% to 90%

= 200 pF for RST,

C

L

10% to 90%

=35 pF,

C

L

F

≤ 20 MHz

CLK

0.9 V
0

CC

V V

CC

0.3 V
= 0 0.1 V
= 1 mA 0.3 V

45

8 ns

100 ns

55 %

Rev. 1.3 17

73S8024C Data Sheet DS_8024C_023

13.4 Digital Signals

Symbol Parameter Condition Min. Typ. Max. Unit
Digital I/O except for OSC I/O

VIL Input Low Voltage -0.3 0.8 V
VIH Input High Voltage 1.8 VDD + 0.3 V
VOL Output Low Voltage IOL = 2 mA 0.45 V
VOH Output High Voltage IOH = -1 mA VDD - 0.45 V
ROUT Pull-up resistor, OFF 20

kΩ

|IIL1| Input Leakage Current GND < VIN < VDD -5 5 μA

Oscillator (XTALIN) I/O Parameters

V Input Low Voltage - XTALIN

-0.3 0.3 V V

ILXTAL

V Input High Voltage - XTALIN

0.7 V

IHXTAL

I Input Current - XTALIN

GND < VIN < V -30

ILXTAL

f Max freq. Osc or external clock

27 MHz

MAX

t

δin

External input duty cycle limit

R/F < 10% fIN,

45% <

δ

CLK

< 55%

30 μA

DD

V

DD

48

52 %

DD

DD

V + 0.3

13.5 DC Characteristics

Symbol Parameter Condition Min. Typ. Max. Unit

I Supply Current on V

PC

DD

Linear mode, ICC = 0
I/O, AUX1, AUX2 = high

Step up mode, ICC = 0
I/O, AUX1, AUX2 = high

4.9 mA

4.7 mA

PWRDN=1,

I

DD_PD

Supply Current on V
Power Down mode

DD

Start/stop bit = 0

in

All digital inputs driven

0.11 2.5

with a true logical 0 or 1

13.6 Voltage / Temperature Fault Detection Circuits

Symbol Parameter Condition Min. Typ. Max. Unit

V

fault (V

V

DDF

V

CCF

T Die over temperature fault

115 145

F

I Card over current fault

90 150 mA

CCF

DD

supervisor threshold)
V

fault (V

CC

supervisor threshold)

Voltage

DD

Voltage

CC

No external resistor on

VDDF_ADJ

V

CC

V

CC

2.15 2.4 V

4.20 = 5 V 4.6 V

2.5 = 3 V 2.7 V

µA

°C

18 Rev. 1.3

DS_8024C_023 73S8024C Data Sheet

.335 (8.509)
.320 (8.128)

.420 (10.668)

.390 (9.906)

.050 TYP. (1.270)

.305 (7.747)
.285 (7.239)

.715 (18.161)
.695 (17.653)

.0115 (0.29)
.003 (0.076)

.016 nom (0.40)

.110 (2.790)
.092 (2.336)

PIN NO. 1
BEVEL

14 Mechanical Drawings (28-SO)

Figure 12: 28 Lead SO

Rev. 1.3 19

73S8024C Data Sheet DS_8024C_023

73S8024C

1

18

17

16

15

14

13

12

11

10

9

8

7

6

5

4

3

2

19

20

28

27

26

25

24

23

22

21

CLKDIV1
CLKDIV2

5V/#V

GND

VDD

PRES

PRES

I/O
AUX2
AUX1

GND

AUX2UC
AUX1UC
I/OUC

XTALIN

XTALOUT

OFF

VDD
RSTIN

CMDVCC

VCC
RST
CLK

NC

LIN

PWRDN

VDDF_ADJ

GND

15 Package Pin Designation (28-SO)

Use handling procedures necessary for a static sensitive component.

(Top View)

Figure 11: 73S8024C 28-SO Pin Out

20 Rev. 1.3

DS_8024C_023 73S8024C Data Sheet

16 Ordering Information

Part Description Order Number Packaging Mark

73S8024C-SO 28-pin Lead-Free SO 73S8024C-IL/F 73S8024C-IL
73S8024C-SO 28-pin Lead-Free SO Tape / Reel 73S8024C-ILR/F 73S8024C-IL

17 Related Documentation

The following 73S8024C documents are availabl e from Teridian Semiconductor Corporation:

73S8024C Data Sheet (this document)
73S8024C Demo Board User’s Guide

18 Contact Information

For more information about Teridian Semiconductor products or to check the availability of the
73S8024C, contact us at:

6440 Oak Canyon Road
Suite 100
Irvine, CA 92618-5201

Telephone: [phone]
FAX: [phone]
Email: [e-mail]

For a complete list of worldwide sales offices, go to http://www.teridian.com

.

Rev. 1.3 21