TERIDIAN Semiconductor 73S8014R Technical data

73S8014R

Smart Card Interface

Simplifying System Integration™

September 2008

DATA SHEET

DESCRIPTION

The Teridian 73S8014R is a single smart card (ICC) interface
circuit, firmware compatible with 8024-type devices for
configurations where only asynchronous cards must be
supported. It is derived from the 73S8024RN industry­standard electrical interface. The 73S8014R has been
optimized to match most of the typical Set-Top-Box / A/V
Conditional Access applications. Optimization essentially
involved a smaller pin-count, support for single I/O, and
maximum card current of 65mA (ISO-7816 / EMV
compliance).

The 73S8014R interfaces with the host processor through the
same bus (digital I/Os) as the 73S8024RN, which is

compatible with any other 8024-type IC. As a result, the

73S8014R is a very attractive cost-reduction path from
traditional 8024 ICs. The 73S8014R has been designed to

provide full electrical compliance with ISO 7816-3 and EMV

4.0 specifications.

Interfacing with the system controller is done through a
control bus, composed of digital inputs to control the
interface, and one interrupt output to inform the system
controller of the card presence and faults.

The card clock can be generated by an on-chip oscillator
using an external crystal or by connection to an externally
supplied clock signal.

The 73S8014R incorporates an ISO 7816-3
activation/deactivation sequencer that controls the card
signals. Level-shifters drive the card signals with the
selected card voltage (3V or 5V), coming from an internal
Low Drop-Out (LDO) voltage regulator. This LDO regulator is
powered by a dedicated power supply input V
circuitry is powered separately by a digital power supply V
With its embedded LDO regulator, the 73S8024RN is a
cost-effective solution for any application where a 5V
(typically -5% +10%) power supply is available.

Emergency card deactivation is initiated upon card extraction
or upon any fault detected by the protection circuitry. The
fault can be a card over-current, VCC undervoltage or power
supply fault (V

). The card over-current circuitry is a true

DD

current detection function, as opposed to V
detection, as usually implemented in non-Teridian 8024
interface ICs.

The V

voltage fault has a threshold voltage that can be

DD

adjusted with an external resistor network. It allows
automated card deactivation at a customized V
threshold value. It can be used, for instance, to match the
system controller operating voltage range.

. Digital

PC

voltage drop

CC

voltage

DD

DD

.

APPLICATIONS

• Set-Top-Box Conditional Access and Pay-per-View

• General purpose smart card readers

ADVANTAGES

• Same advantages as the Teridian 73S80xxR family:

 VCC card generated by an LDO regulator
 Very low power dissipation (saves up to 1/2W)
 Fewer external components are required

 Better noise performance

• True card over-current detection

• Firmware compatibility with all 8024 ICs

• Small format 20SO package

FEATURES

• Card Interface:

 Complies with ISO 7816-3 and EMV 4.0
 Supports 3V / 5V cards
 ISO 7816-3 Activation / Deactivation sequencer

 Automated deactivation upon hardware fault (i.e. upon

drop on V

 The V

be externally adjusted

 Over-current detection 130mA max
 Card CLK clock frequency up to 20MHz

• System Controller Interface:

 3 Digital inputs control the card activation /

deactivation, card reset and card voltage

 2 Digital inputs control the card clock frequency
 1 Digital output, interrupt to the system controller,

reports to the host the card presence and faults

 Crystal oscillator or host clock, up to 27MHz

• Regulator Power Supply:
 4.75V to 5.5V

• Digital Interfacing: 2.7V to 5.5V

• 6kV ESD protection on the card interface

• Package: SO 20-pin

• RoHS compliant (6/6) lead-free package

power supply or card overcurrent)

DD

voltage supervisor threshold value (fault) can

DD

Rev. 1.0 © 2008 Teridian Semiconductor Corporation 1

73S8014R Data Sheet DS_8014R_012

FUNCTIONAL DIAGRAM

VDD VPC

VDDF_ADJ

CMDVCC

RSTIN

5V/#V

TEST

OFF

CKDIV1
CKDIV2

XTALIN

XTALOUT

IOUC

vdd circui ts

INTERNAL POWER SUPPLY

VOLTAGE REFERENCE

VPD - internal supply

CONTROLLER

REGISTERS

FAULT LOGIC

XTAL

OSC

GENERATION

vdd circuits

VDD FAULT

bias currents

1.5MHz

AND

CLOCK

CLOCK

SMART CARD I/O BUFFER

VCC FAULT

vref

R-C

OSC.

SC

SEQUENCER

LDO

REGULATOR

RESET

BUFFER

CLOCK

BUFFER

GND

VCC

RST

CLK

VDD CKT

PRES

I/O

vcc circuits

GND

Figure 1: 73S8014R Block Diagram

2 Rev. 1.0

DS_8014R_012 73S8014R Data Sheet

Table of Contents

1 Pinout ................................................................................................................................................................ 5

2 Electrical Specifications .................................................................................................................................. 8

2.1 Absolute Maximum Ratings ........................................................................................................................ 8

2.2 Recommended Operating Conditions ......................................................................................................... 8

2.3 Package Thermal Parameters .................................................................................................................... 9

2.4 Smart Card Interface Requirements ........................................................................................................... 9

2.5 Characteristics: Digital Signals.................................................................................................................. 11

2.6 DC Characteristics .................................................................................................................................... 12

2.7 Voltage Fault Detection Circuits ................................................................................................................ 13

3 Applications Information ............................................................................................................................... 14

3.1 Example 73S8014R Schematics .............................................................................................................. 14

3.2 System Controller Interface ....................................................................................................................... 16

3.3 Power Supply and Voltage Supervision .................................................................................................... 16

3.4 Card Power Supply ................................................................................................................................... 17

3.5 On-Chip Oscillator and Card Clock ........................................................................................................... 17

3.6 Activation Sequence ................................................................................................................................. 18

3.7 Deactivation Sequence ............................................................................................................................. 19

3.8 Fault Detection and OFF ........................................................................................................................... 20

3.9 I/O Circuitry and Timing ............................................................................................................................ 20

4 Equivalent Circuits ......................................................................................................................................... 22

5 Mechanical Drawing ....................................................................................................................................... 27

6 Ordering Information ..................................................................................................................................... 28

7 Related Documentation ................................................................................................................................. 28

8 Contact Information ....................................................................................................................................... 28

Rev. 1.0 3

73S8014R Data Sheet DS_8014R_012

Figures

Figure 1: 73S8014R Block Diagram .......................................................................................................................... 2

Figure 2: 73S8014R 20-SOP Pin Out ........................................................................................................................ 5

Figure 3: 73S8014R – Typical Application Schematic ............................................................................................ 15

Figure 4: Activation Sequence – RSTIN Low When CMDVCC Goes Low ............................................................. 18

Figure 5: Activation Sequence – RSTIN High When CMDVCC Goes Low ............................................................. 19

Figure 6: Deactivation Sequence ............................................................................................................................ 19

Figure 7: Timing Diagram – Management of the Interrupt Line OFF ...................................................................... 20

Figure 8: I/O and I/OUC State Diagram................................................................................................................... 21

Figure 9: I/O – I/OUC Delays – Timing Diagram ..................................................................................................... 21

Figure 10: Open Drain type – OFF .......................................................................................................................... 22

Figure 11: Power Input/Output Circuit, VDD, VPC, VCC ........................................................................................ 22

Figure 12: Smart Card CLK Driver Circuit ............................................................................................................... 23

Figure 13: Smart Card RST Driver Circuit ............................................................................................................... 23

Figure 14: Smart Card IO Interface Circuit .............................................................................................................. 24

Figure 15: Smart Card IOUC Interface Circuit ......................................................................................................... 24

Figure 16: General Input Circuit .............................................................................................................................. 25

Figure 17: Oscillator Circuit ..................................................................................................................................... 25

Figure 18: VDDF_ADJ ............................................................................................................................................. 26

Figure 19: Mechanical Drawing 20-Pin SO Package .............................................................................................. 27

Tables

Table 1: 73S8014R 20-Pin SOP Pin Definitions ....................................................................................................... 6

Table 2: Absolute Maximum Device Ratings ............................................................................................................. 8

Table 3: Recommended Operating Conditions ......................................................................................................... 8

Table 4: Package Thermal Parameters ..................................................................................................................... 9

Table 5: DC Smart Card Interface Requirements ..................................................................................................... 9

Table 6: Digital Signals Characteristics ................................................................................................................... 11

Table 7: DC Characteristics ..................................................................................................................................... 12

Table 8: Voltage Fault Detection Circuits ................................................................................................................ 13

Table 9: Order Numbers and Packaging Marks ...................................................................................................... 28

4 Rev. 1.0

DS_8014R_012 73S8014R Data Sheet

1 Pinout

The 73S8014R is supplied as a 20-pin SO package.

OFF

RSTIN

I/OUC

VPC

CLKDIV2

1

2

3

4

5

20

19

18

17

16

CLKDIV1
PRES
VCC

CLK
GND

73S8014R

CMDVCC

5V/#V

GND

XTALIN

XTALOUT

6

7

8

9

10

Figure 2: 73S8014R 20-SOP Pin Out

15

14

13

12

11

RST

I/O

VDD
VDDF_ADJ

GND

Rev. 1.0 5

73S8014R Data Sheet DS_8014R_012

Table 1 provides the 73S8014R pin names, pin numbers, type, equivalent circuits and descriptions.

Table 1: 73S8014R 20-Pin SOP Pin Definitions

Pin Name

Pin
Number

Type

Equivalent

Circuit

Description

Card Interface

I/O 14 IO Figure 14

Card I/O: Data signal to/from card. Includes an 11k pull-up
resistor to V

CC.

RST 15 O Figure 13 Card reset: provides reset (RST) signal to card.

Card clock: provides clock signal (CLK) to card. The rate of this

CLK 17 O Figure 12

clock is determined by the external crystal frequency or frequency
of the external clock signal applied on XTALIN and CLKDIV
selections.

PRES 19 I Figure 16

Card Presence switch: active high indicates card is present.
Includes a high-impedance pull-down current source.

Card power supply – logically controlled by sequencer, output of

VCC 18 PSO Figure 11

LDO regulator. Requires an external filter capacitor to the card
GND.

GND 16 GND – Card ground.

Host Processor Interface

Command VCC (negative assertion): Logic low on this pin causes

CMDVCC

6 I Figure 16

the LDO regulator to ramp the V

supply to the card and initiates

CC

a card activation sequence, if a card is present.

5 volt / 3 volt card selection: Logic one selects 5 volts for VCC and
card interface, logic low selects 3 volt operation. When the part is

5V/#V 7 I Figure 16

to be used with a single card voltage, this pin should be tied to
either GND or V

. However, it includes a high impedance pull-up

DD

resistor to default this pin high (selection of 5V card) when not
connected. This pin shall not be changed when CMDVCC is low.

Sets the divide ratio from the XTAL oscillator (or external clock
input) to the card clock. These pins include a pull-up resistor for
CLKDIV1 and CLKLDIV2 to provide a default rate of divide by
two.

CLKDIV1
CLKDIV2

20

5

I Figure 16

CLKDIV1 CLKDIV2 CLOCK RATE

0 0 XTALIN/8

0 1 XTALIN/4

1 1 XTALIN/2

1 0 XTALIN

Interrupt signal to the processor. Active Low - Multi-function

OFF 1 O Figure 10

indicating fault conditions and card presence. Open drain output
configuration – It includes an internal 20kΩ pull-up to V

DD.

RSTIN 2 I Figure 16 Reset Input: This signal is the reset command to the card.

I/OUC 3 IO Figure 15

System controller data I/O to/from the card. Includes an 11K
pull-up resistor to V

DD.

6 Rev. 1.0

DS_8014R_012 73S8014R Data Sheet

Miscellaneous Inputs and Outputs

Crystal oscillator input: can either be connected to crystal or

XTALIN 9 Figure 17

driven as a source for the card clock. Note: When not using the
crystal, the capacitors must be removed.

Crystal oscillator output: connected to crystal. Left open if

XTALOUT 10 Figure 17

XTALIN is being used as external clock input. Note: When not
using the crystal, the capacitors must be removed.

VDD fault threshold adjustment input: this pin can be used to adjust

VDDF_ADJ 12 Figure 18

the V

value (that controls deactivation of the card). Must be

DDF

left open if unused.

Power Supply and Ground

VDD 13 PSO Figure 11

System interface supply voltage and supply voltage for internal
circuitry.

VPC 4 PSO Figure 11 LDO regulator power supply source.

GND 8, 11 GND – Digital ground.

Rev. 1.0 7

73S8014R Data Sheet DS_8014R_012

2 Electrical Specifications

This section provides the following:

 Absolute maximum ratings
 Recommended operating conditions
 Package thermal parameters
 Smart card interface requirements
 Digital signals characteristics
 DC Characteristics
 Voltage Fault Detection Circuits

2.1 Absolute Maximum Ratings

Table 2 lists the maximum operating conditions for the 73S8014R. Permanent device damage may occur if
absolute maximum ratings are exceeded. Exposure to the extremes of the absolute maximum rating for extended
periods may affect device reliability. The smart card interface pins are protected against short circuits to V
ground, and each other.

2.2 Recommended Operating Conditions

Table 2: Absolute Maximum Device Ratings

Parameter Rating

Supply Voltage VDD -0.5 to 6.0 VDC

Supply Voltage VPC -0.5 to 6.0 VDC

Input Voltage for Digital Inputs -0.3 to (VDD +0.5) VDC

Storage Temperature -60 to 150°C

Pin Voltage (except card interface) -0.3 to (VDD +0.5) VDC

Pin Voltage (card interface) -0.3 to (VCC + 0.5) VDC

ESD Tolerance – Card interface pins +/- 6kV

ESD Tolerance – Other pins +/- 2kV

*Note: ESD testing on smart card pins is HBM condition, 3 pulses, each polarity referenced to ground.

Note: Smart Card pins are protected against shorts between any combinations of Smart Card pins.

CC

,

Function operation should be restricted to the recommended operating conditions specified in Table 3.

Table 3: Recommended Operating Conditions

Parameter Rating

Supply Voltage VDD 2.7 to 5.5 VDC

Supply Voltage VPC 4.75 to 5.5 VDC

Ambient Operating Temperature -40°C to +85°C

Input Voltage for Digital Inputs 0V to VDD + 0.3V

8 Rev. 1.0

DS_8014R_012 73S8014R Data Sheet

2.3 Package Thermal Parameters

Table 4 lists the 73S8014R Smart Card interface requirements.

Table 4: Package Thermal Parameters

Parameter Rating

20 SO

50

°C / W

2.4 Smart Card Interface Requirements

Table 5 lists the 73S8014R Smart Card interface requirements.

Table 5: DC Smart Card Interface Requirements

Symbol Parameter Condition Min Nom Max Unit

Card Power Supply (VCC) Regulator

General conditions, -40°C < T < 85°C, 4.75V < VPC < 5.5V, 2.7V < VDD < 5.5V

Card supply voltage

VCC

V

V

CCrip

I

CCmax

I

I

CCF

including ripple and
noise

Card supply output
current

Ripple f

CC

fault current

CC

Inactive mode

Inactive mode, ICC = 1mA

Active mode; ICC <65mA; 5V

Active mode; ICC <65mA; 3V

Active mode; ICC <40mA; 1.8V

Active mode; single pulse of 100mA for

2μs; 5 volt, fixed load = 25mA

Active mode; single pulse of 100mA for

2μs; 3v, fixed load = 25mA

Active mode; current pulses of 40nAs

with peak |I

t <400ns; 5V

Active mode; current pulses of 40nAs

with peak |I

t <400ns; 3V

= 20K – 200MHz 350 mV

RIPPLE

Static load current, V
as selected

| <200mA,

CC

| <200mA,

CC

>4.6V or 2.7V

CC

-0.1

-0.1

4.65

2.85

1.68

4.6

2.76

4.6

2.7

65 mA

70

0.1 V

0.4 V

5.25 V

3.15 V

1.92 V

5.25 V

3.2 V

5.25 V

3.15 V

130 mA

V

V

SR

VSF V

C

F

Rev. 1.0 9

slew rate, rise

CC

slew rate, fall

CC

External filter cap

to GND)

(V

CC

= 1.0μF on VCC

C

F

= 1.0μF on VCC

C

F

CF should be ceramic with low ESR
(<100mΩ).

0.06 0.150 0.30

0.075 0.150 0.60

0.5 1.0 1.5

V/μs

V/μs

μF