TERIDIAN Semiconductor 73S8010C Technical data
73S8010C
Smart Card Interface
Simplifying System Integration™
DATA SHEET
April 2009
DESCRIPTION
The Teridian 73S8010C is a single smart card
interface IC. It provides full electrical compliance
with ISO-7816-3 and EMV 4.0 specifications.
Interfacing with the host is done through the two-wire
I2C bus. Data exchange with the card is managed
from the system controller using the I/O line (and
eventually the auxiliary I/O lines).
An on-chip oscillator using an external crystal, or
connection to a clock signal coming from the
system controller can generate the card clock
signal.
The 73S8010C IC incorporates an ISO-7816-3
activation/deactivation sequencer that controls the
card signals. Level shifters drive the card signals
with the selected card voltage (3 V or 5 V), coming
from an internal DC-DC converter.
With its high-efficiency DC-DC converter, the
Teridian 73S8010C is a cost-effective solution for
any smart card reader application to be powered
from a single 2.7 V to 3.6 V power supply.
Hardware support for auxiliary I/O lines, C4 / C8
contacts, is provided.
Emergency card deactivation is initiated upon card
extraction or upon any fault generated by the
protection circuitry. The fault can be a VDD (digital
power supply), a VCC (card power supply), a card
over-current, or an over-heating fault.
ADVANTAGES
FEATURES
Card Interface:
Complies with ISO-7816-3 and EMV 4.0
A DC-DC Converter provides 3V / 5V to the
card from an external power supply input
High-efficiency converter: > 80% @ V
V
= 5 V and ICC = 65 mA
CC
= 3.3 V,
DD
Up to 100 mA supplied to the card
ISO-7816-3 Activation / Deactivation sequencer
with emergency automated deactivation on
card removal or fault detected by the protection
circuitry
Protection include 2 voltage supervisors that
detect voltage drops on card V
and VDD
CC
power supplies
The V
voltage supervisor threshold value
DD
can be externally adjusted
True over-current detection (150 mA max.)
1 card detection input
Auxiliary I/O lines, for C4 / C8 contact signals
Host Interface:
Fast mode, 400 kbps I
2
C slave bus
8 possible devices in parallel
One control register and one status register
Interrupt output to the host for fault
detection
Crystal oscillator or host clock, up to 27 MHz
Power Supply:
: 2.7 V to 3.6 V
V
DD
6 kV ESD Protection on the card interface
Package: SO28 or 32QFN
Single smart card interface
The inductor-based DC-DC converter provides
higher current and efficiency than the usual
charge-pump capacitor-based converters
Ideal for battery-powered applications
Suitable for high current cards and
SAMs: (100 mA max)
APPLICATIONS
Set-Top-Boxes, DVD / HDD Recorders:
Conditional Access and Pay-per-View slots
Point of Sales and Transaction Terminals
EMV slots in cell phones and PDAs
Power down mode: 2 A typical
Small Format (5x5mm) 32-QFN package option
Rev. 1.5 © 2009 Teridian Semiconductor Corporation 1
73S8010C Data Sheet DS_8010C_024
FUNCTIONAL DIAGRAM
Figure 1: 73S8010C Block Diagram
Pin number reference to SO28 Package
[Pin number] reference to 32QFN Package
2 Rev. 1.5
DS_8010C_024 73S8010C Data Sheet
Table of Contents
1 Pin Description .................................................................................................................................... 5
1.1 Card Interface ............................................................................................................................... 5
1.2 Miscellaneous Inputs and Outputs ................................................................................................ 5
1.3 Power Supply and Ground ............................................................................................................ 5
1.4 Microcontroller Interface ............................................................................................................... 6
2 Host Interface (I2C Bus) ...................................................................................................................... 7
2.1 Host Interface Control ................................................................................................................... 7
2.2 Host Interface Status .................................................................................................................... 8
2.3 I2C-bus Timing .............................................................................................................................. 9
3 Oscillator ............................................................................................................................................ 10
4 DC-DC Converter – Card Power Supply ......................................................................................... 10
5 Voltage Supervision ......................................................................................................................... 11
6 Power Down ....................................................................................................................................... 11
7 Over-temperature Monitor ................................................................................................................ 12
8 Activation Sequence ......................................................................................................................... 12
9 Deactivation Sequence ..................................................................................................................... 13
10 Interrupt ............................................................................................................................................. 13
11 Warm Reset .................................................................................................................... ................... 14
12 I/O Timing ........................................................................................................................................... 14
13 Typical Application Schematic ........................................................................................................ 15
14 Electrical Specification ..................................................................................................................... 16
14.1Absolute Maximum Ratings ........................................................................................................ 16
14.2Recommended Operating Conditions......................................................................................... 16
14.3DC Characteristics: Card Interface ............................................................................................. 17
14.4DC Characteristics: Digital Signals ............................................................................................. 20
14.5DC Characteristics: Supply ......................................................................................................... 20
14.6DC Characteristics: I2C Interface ................................................................................................ 21
14.7Voltage / Temperature Fault Detection Circuits .......................................................................... 21
15 Mechanical Drawings ....................................................................................................................... 22
15.132-pin QFN ................................................................................................................................. 22
15.228-pin SO .................................................................................................................................... 23
16 Package Pin Designation ................................................................................................................. 24
16.132-pin QFN ................................................................................................................................. 24
16.228-pin SO .................................................................................................................................... 25
17 Ordering Information ........................................................................................................................ 26
18 Related Documentation .................................................................................................................... 26
19 Contact Information .......................................................................................................................... 26
Revision History ........................................................................................................................................ 27
Rev. 1.5 3
73S8010C Data Sheet DS_8010C_024
Figures
Figure 1: 73S8010C Block Diagram ............................................................................................................. 2
Figure 2: I2C Bus Write Protocol ................................................................................................................... 8
Figure 3: I2C Bus Read Protocol ................................................................................................................... 9
Figure 4: I2C Bus Timing Diagram ................................................................................................................ 9
Figure 5: Power Down Mode Operation ...................................................................................................... 12
Figure 6: Activation Sequence .................................................................................................................... 12
Figure 7: Deactivation Sequence ................................................................................................................ 13
Figure 8: FAULT Functions, INT operation ................................................................................................. 13
Figure 9: Warm Reset operation ................................................................................................................. 14
Figure 10: I/O Timing .................................................................................................................................. 14
Figure 11: 73S8010C – Typical Application Schematic .............................................................................. 15
Figure 12: DC – DC Converter Efficiency (VCC = 5 V) ................................................................................ 18
Figure 13: DC – DC Converter Efficiency (VCC = 3 V) ................................................................................ 18
Figure 14: 32-pin QFN Package Drawing ................................................................................................... 22
Figure 15: 28-pin SO Package Drawing ..................................................................................................... 23
Tables
Table 1: Device Address Selections ............................................................................................................. 7
Table 2: Host Control Register ...................................................................................................................... 7
Table 3: Host Status Register ....................................................................................................................... 8
Table 4: Choice of Vcc Capacitor ............................................................................................................... 10
4 Rev. 1.5
DS_8010C_024 73S8010C Data Sheet
1 Pin Description
1.1 Card Interface
Name
Pin
(SO)
I/O 11 9 Card I/O: Data signal to/from card. Includes a pull-up resistor to V
PIN
(QFN)
Description
CC.
AUX1 13 11 AUX1: Auxiliary data signal to/from card. Includes a pull-up resistor to V
AUX2 12 10 AUX2: Auxiliary data signal to/from card. Includes a pull-up resistor to V
RST 16 14 Card reset: provides reset (RST) signal to card.
CLK 15 13
Card clock: provides clock (CLK) signal to card. The rate of this clock is
determined by the crystal oscillator frequency and CLKSEL bits in the
control register.
PRES 10 7
Card Presence switch: active high indicates card is present. Includes a
pull-down resistor.
VCC 17 15
Card power supply: logically controlled by sequencer, output of DC-DC
converter. Requires an external filter capacitor to the card GND.
GND 14 12 Card ground.
1.2 Miscellaneous Inputs and Outputs
Name
PIN
(SO)
XTALIN 24 23
XTALOUT 25 24
VDDF_ADJ 18 17
NC 7, 9
PIN
(QFN)
4, 6, 8,
16, 25,
32
Description
Crystal oscillator input: can either be connected to a crystal or driven
as a source for the card clock.
Crystal oscillator output: connected to crystal. Left open if XTALIN is
being used as an external clock input.
V
threshold adjustment input: this pin can be used to overwrite a
DD
higher V
value (that controls deactivation of the card). Must be
DDF
left open if unused.
Non-connected pin.
1.3 Power Supply and Ground
CC.
CC.
Name
PIN
(SO)
VDD 6, 21 3, 20
Pin
(QFN)
Description
System controller interface supply voltage: supply voltage for internal
circuitry and DC-DC converter power supply source.
GND 4 1 DC-DC converter ground.
GND 14 12 Smart Card I/O ground.
GND 22 21 Digital ground.
LIN 5 2
External inductor: Connect external inductor from pin 5 to V
. Keep the
DD
inductor close to pin 5.
Rev. 1.5 5
73S8010C Data Sheet DS_8010C_024
1.4 Microcontroller Interface
Name
PIN
(SO)
INT 23 22
PWRDN 8 5
PIN
(QFN)
Description
Interrupt output (negative assertion): Interrupt output signal to the
processor. A 20 kΩ pull up to V
DD
Power Down control input: Active High. When Power Down (PD) mode is
activated, all internal analog functions are disabled to place the 73S8010C
in its lowest power consumption mode. Must be tied to ground when the
power down function is not used.
SAD0
SAD1
SAD2
1
2
3
Serial device address bits: Digital inputs for address selection that allow
29
the connection of up to 8 devices in parallel. Address selections as follows:
30
31
SAD2 SAD1 SAD0 I
0 0 0 0x40
0 0 1 0x42
0 1 0 0x44
0 1 1 0x46
1 0 0 0x48
1 0 1 0x4A
1 1 0 0x4C
1 1 1 0x4E
Pins SAD0 and SAD1 are internally pulled-down and SAD2 is
internally pulled-up.
The default address when left unconnected is 48h.
SCL 19 18 I2C clock signal input.
SDA 20 19 I2C bi-directional serial data signal.
I/OUC 26 26
AUX1UC 27 27
AUX2UC 28 28
System controller data I/O to/from the card. Includes internal pull-up
resistor to V
DD.
System controller auxiliary data I/O to/from the card. Includes internal pullup resistor to V
DD.
System controller auxiliary data I/O to/from the card. Includes internal pullup resistor to V
DD.
is provided internally.
2
C Address (7 bits)
6 Rev. 1.5
DS_8010C_024 73S8010C Data Sheet
2 Host Interface (I2C Bus)
A fast-mode 400 kHz I2C bus slave interface is used for controlling the device and reading the status of
the device via the data pin SDA and clock pin SCL. The bus has 3 address select pins, SAD0, SAD1,
and SAD2. This allows up to 8 devices to be connected in parallel.
Table 1: Device Address Selections
SAD2 SAD1 SAD0 I
0 0 0 0x40
0 0 1 0x42
0 1 0 0x44
0 1 1 0x46
1 0 0 0x48
1 0 1 0x4A
1 1 0 0x4C
1 1 1 0x4E
Bit 0 of the I
2
C address is the R/W bit. Refer to Figure 2 and Figure 3 for usage.
2.1 Host Interface Control
2
C Address (7 bits)
Table 2 describes the Host Interface Control Register bits (power-on Reset = 0x00).
Table 2: Host Control Register
Name Bit Description
Start/Stop 0
When set, initiates an activation and a cold reset procedure; when reset, initiates
a deactivation sequence.
Warm reset 1
When set, initiates a warm reset procedure; automatically reset by hardware
when the card starts answering or when the card is declared mute.
5 V and 3 V 2 When set, VCC = 3 V; when reset, VCC = 5 V.
Clock Stop 3 When set, card clock is stopped. Bit 4 determines the card clock stop level.
Clock Stop
4 When set, card clock stops high; when reset card clock stops low.
Level
Clksel1 5
Bits 5 and 6 determine the clock rate to the card according to the following table.
CLKDIV1 CLKDIV2 Clock Rate
Clksel2 6
0 0 XTALIN/8
0 1 XTALIN/4
1 1 XTALIN/2
1 0 XTALIN
I/O enable 7
When set, data is transferred between I/O (AUX1, AUX2) and I/OUC (AUX1UC,
AUX2UC); when reset, I/O (AUX1, AUX2) and I/OUC (AUX1UC, AUX2UC) are
high impedance.
2
C-bus Write to the Control Register
I
2
The I
C-bus Write command to the control register follows the format shown in Figure 2.
After the START condition, the master sends a slave address. This address is seven bits long followed
by an eighth bit, which is an opcode bit (R/W) – a ‘zero’ indicates the master will write data to the control
register. After the R/W bit, the ’zero’ ACK bit is sent to the master by the device. The master now starts
sending the 8 bits of data to the control register during the DATA bits time. After the DATA bits, the ‘zero’
Rev. 1.5 7
73S8010C Data Sheet DS_8010C_024
ACK bit is sent to the master by the device. The master should send the STOP condition after receiving
the ACK bit.
Figure 2: I
2
C Bus Write Protocol
2.2 Host Interface Status
Table 3 describes the Host Interface Status Register bits (power-on Reset = 0x04).
Table 3: Host Status Register
Name Bit Description
PRES 0 Set when the card is present; reset when the card is not present.
PRESL 1
I/O 2 Set when I/O is high; reset when I/O is low.
SUPL 3
PROT 4
MUTE 5
EARLY 6
ACTIVE 7 Set when the card is active (VCC is on); reset when the card is inactive.
2
I
C-bus Read from the Status Register:
2
The I
C-bus Read Command from the Status Register follows the format shown in Figure 3.
After the START condition, the master sends a slave address. This address is seven bits long followed
by an eighth bit, which is the opcode bit (R/W). A ‘one’ indicates the master will read data from the status
register. After the R/W bit, the ’zero’ ACK bit is sent to the master by the device. The device now starts
sending the 8-bit status register data to the control register during the DATA bits time. After the DATA
bits, the ‘one’ ACK bit is sent to the device by the master. The master should send the STOP condition
after receiving the ACK bit.
Set when the PRES pin changes state (rising/falling edge); reset when the status
register is read. Generates an interrupt when set
Set when a voltage fault is detected; reset when the status register is read.
Generates an interrupt when set.
Set when an over-current or over-heating fault has occurred during a card session;
reset when the status register is read. Generates an interrupt when set.
Set during ATR when the card has not answered during the ISO 7816-3 time
window (40000 card clock cycles); reset when the next session begins or this
register is read.
Set during ATR when the card has answered before 400 card clock cycles; reset
when the next session begins or this register is read.
8 Rev. 1.5
DS_8010C_024 73S8010C Data Sheet
Figure 3: I
2
C Bus Read Protocol
2.3 I2C-bus Timing
Symbol Parameter Conditions Min. Typ. Max. UNIT
Fsclk Clock frequency 400 kHz
Tlow Clock low 1.3
Thi Clock high 0.6
Thdsta Hold time START condition 0.6
Tsudat Data set up time 100 ns
Thddat Data hold time 5 900 ns
Tsusto Set up time STOP condition 0.6
Tbuf
Bus free time between a STOP and
1.3
START condition
SDA
Tbuf
s
s
s
s
s
SCL
Tlow
Thi
Thdsta
Tsudat Thddat Tsusto
Figure 4: I
2
C Bus Timing Diagram
Rev. 1.5 9
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