The Teridian 73S8010C is a single smart card
interface IC. It provides full electrical compliance
with ISO-7816-3 and EMV 4.0 specifications.
Interfacing with the host is done through the two-wire
I2C bus. Data exchange with the card is managed
from the system controller using the I/O line (and
eventually the auxiliary I/O lines).
An on-chip oscillator using an external crystal, or
connection to a clock signal coming from the
system controller can generate the card clock
signal.
The 73S8010C IC incorporates an ISO-7816-3
activation/deactivation sequencer that controls the
card signals. Level shifters drive the card signals
with the selected card voltage (3 V or 5 V), coming
from an internal DC-DC converter.
With its high-efficiency DC-DC converter, the
Teridian 73S8010C is a cost-effective solution for
any smart card reader application to be powered
from a single 2.7 V to 3.6 V power supply.
Hardware support for auxiliary I/O lines, C4 / C8
contacts, is provided.
Emergency card deactivation is initiated upon card
extraction or upon any fault generated by the
protection circuitry. The fault can be a VDD (digital
power supply), a VCC (card power supply), a card
over-current, or an over-heating fault.
ADVANTAGES
FEATURES
Card Interface:
Complies with ISO-7816-3 and EMV 4.0
A DC-DC Converter provides 3V / 5V to the
card from an external power supply input
High-efficiency converter: > 80% @ V
V
= 5 V and ICC = 65 mA
CC
= 3.3 V,
DD
Up to 100 mA supplied to the card
ISO-7816-3 Activation / Deactivation sequencer
with emergency automated deactivation on
card removal or fault detected by the protection
circuitry
6Power Down ....................................................................................................................................... 11
15.228-pin SO .................................................................................................................................... 23
16.228-pin SO .................................................................................................................................... 25
17 Ordering Information ........................................................................................................................ 26
18 Related Documentation .................................................................................................................... 26
19 Contact Information .......................................................................................................................... 26
Revision History ........................................................................................................................................ 27
Table 2: Host Control Register ...................................................................................................................... 7
Table 3: Host Status Register ....................................................................................................................... 8
Table 4: Choice of Vcc Capacitor ............................................................................................................... 10
4 Rev. 1.5
DS_8010C_024 73S8010C Data Sheet
1 Pin Description
1.1 Card Interface
Name
Pin
(SO)
I/O 11 9 Card I/O: Data signal to/from card. Includes a pull-up resistor to V
PIN
(QFN)
Description
CC.
AUX1 13 11 AUX1: Auxiliary data signal to/from card. Includes a pull-up resistor to V
AUX2 12 10 AUX2: Auxiliary data signal to/from card. Includes a pull-up resistor to V
RST 16 14 Card reset: provides reset (RST) signal to card.
CLK 15 13
Card clock: provides clock (CLK) signal to card. The rate of this clock is
determined by the crystal oscillator frequency and CLKSEL bits in the
control register.
PRES 10 7
Card Presence switch: active high indicates card is present. Includes a
pull-down resistor.
VCC 17 15
Card power supply: logically controlled by sequencer, output of DC-DC
converter. Requires an external filter capacitor to the card GND.
GND 14 12 Card ground.
1.2 Miscellaneous Inputs and Outputs
Name
PIN
(SO)
XTALIN 24 23
XTALOUT 25 24
VDDF_ADJ 18 17
NC 7, 9
PIN
(QFN)
4, 6, 8,
16, 25,
32
Description
Crystal oscillator input: can either be connected to a crystal or driven
as a source for the card clock.
Crystal oscillator output: connected to crystal. Left open if XTALIN is
being used as an external clock input.
V
threshold adjustment input: this pin can be used to overwrite a
DD
higher V
value (that controls deactivation of the card). Must be
DDF
left open if unused.
Non-connected pin.
1.3 Power Supply and Ground
CC.
CC.
Name
PIN
(SO)
VDD 6, 21 3, 20
Pin
(QFN)
Description
System controller interface supply voltage: supply voltage for internal
circuitry and DC-DC converter power supply source.
GND 4 1 DC-DC converter ground.
GND 14 12 Smart Card I/O ground.
GND 22 21 Digital ground.
LIN 5 2
External inductor: Connect external inductor from pin 5 to V
. Keep the
DD
inductor close to pin 5.
Rev. 1.5 5
73S8010C Data Sheet DS_8010C_024
1.4 Microcontroller Interface
Name
PIN
(SO)
INT 23 22
PWRDN 8 5
PIN
(QFN)
Description
Interrupt output (negative assertion): Interrupt output signal to the
processor. A 20 kΩ pull up to V
DD
Power Down control input: Active High. When Power Down (PD) mode is
activated, all internal analog functions are disabled to place the 73S8010C
in its lowest power consumption mode. Must be tied to ground when the
power down function is not used.
SAD0
SAD1
SAD2
1
2
3
Serial device address bits: Digital inputs for address selection that allow
29
the connection of up to 8 devices in parallel. Address selections as follows:
Pins SAD0 and SAD1 are internally pulled-down and SAD2 is
internally pulled-up.
The default address when left unconnected is 48h.
SCL 19 18 I2C clock signal input.
SDA 20 19 I2C bi-directional serial data signal.
I/OUC 26 26
AUX1UC 27 27
AUX2UC 28 28
System controller data I/O to/from the card. Includes internal pull-up
resistor to V
DD.
System controller auxiliary data I/O to/from the card. Includes internal pullup resistor to V
DD.
System controller auxiliary data I/O to/from the card. Includes internal pullup resistor to V
DD.
is provided internally.
2
C Address (7 bits)
6 Rev. 1.5
DS_8010C_024 73S8010C Data Sheet
2 Host Interface (I2C Bus)
A fast-mode 400 kHz I2C bus slave interface is used for controlling the device and reading the status of
the device via the data pin SDA and clock pin SCL. The bus has 3 address select pins, SAD0, SAD1,
and SAD2. This allows up to 8 devices to be connected in parallel.
C address is the R/W bit. Refer to Figure 2 and Figure 3 for usage.
2.1 Host Interface Control
2
C Address (7 bits)
Table 2 describes the Host Interface Control Register bits (power-on Reset = 0x00).
Table 2: Host Control Register
Name Bit Description
Start/Stop 0
When set, initiates an activation and a cold reset procedure; when reset, initiates
a deactivation sequence.
Warm reset 1
When set, initiates a warm reset procedure; automatically reset by hardware
when the card starts answering or when the card is declared mute.
5 V and 3 V 2 When set, VCC = 3 V; when reset, VCC = 5 V.
Clock Stop 3 When set, card clock is stopped. Bit 4 determines the card clock stop level.
Clock Stop
4 When set, card clock stops high; when reset card clock stops low.
Level
Clksel1 5
Bits 5 and 6 determine the clock rate to the card according to the following table.
CLKDIV1 CLKDIV2 Clock Rate
Clksel2 6
0 0 XTALIN/8
0 1 XTALIN/4
1 1 XTALIN/2
1 0 XTALIN
I/O enable 7
When set, data is transferred between I/O (AUX1, AUX2) and I/OUC (AUX1UC,
AUX2UC); when reset, I/O (AUX1, AUX2) and I/OUC (AUX1UC, AUX2UC) are
high impedance.
2
C-bus Write to the Control Register
I
2
The I
C-bus Write command to the control register follows the format shown in Figure 2.
After the START condition, the master sends a slave address. This address is seven bits long followed
by an eighth bit, which is an opcode bit (R/W) – a ‘zero’ indicates the master will write data to the control
register. After the R/W bit, the ’zero’ ACK bit is sent to the master by the device. The master now starts
sending the 8 bits of data to the control register during the DATA bits time. After the DATA bits, the ‘zero’
Rev. 1.5 7
73S8010C Data Sheet DS_8010C_024
ACK bit is sent to the master by the device. The master should send the STOP condition after receiving
the ACK bit.
Figure 2: I
2
C Bus Write Protocol
2.2 Host Interface Status
Table 3 describes the Host Interface Status Register bits (power-on Reset = 0x04).
Table 3: Host Status Register
Name Bit Description
PRES 0 Set when the card is present; reset when the card is not present.
PRESL 1
I/O 2 Set when I/O is high; reset when I/O is low.
SUPL 3
PROT 4
MUTE 5
EARLY 6
ACTIVE 7 Set when the card is active (VCC is on); reset when the card is inactive.
2
I
C-bus Read from the Status Register:
2
The I
C-bus Read Command from the Status Register follows the format shown in Figure 3.
After the START condition, the master sends a slave address. This address is seven bits long followed
by an eighth bit, which is the opcode bit (R/W). A ‘one’ indicates the master will read data from the status
register. After the R/W bit, the ’zero’ ACK bit is sent to the master by the device. The device now starts
sending the 8-bit status register data to the control register during the DATA bits time. After the DATA
bits, the ‘one’ ACK bit is sent to the device by the master. The master should send the STOP condition
after receiving the ACK bit.
Set when the PRES pin changes state (rising/falling edge); reset when the status
register is read. Generates an interrupt when set
Set when a voltage fault is detected; reset when the status register is read.
Generates an interrupt when set.
Set when an over-current or over-heating fault has occurred during a card session;
reset when the status register is read. Generates an interrupt when set.
Set during ATR when the card has not answered during the ISO 7816-3 time
window (40000 card clock cycles); reset when the next session begins or this
register is read.
Set during ATR when the card has answered before 400 card clock cycles; reset
when the next session begins or this register is read.
8 Rev. 1.5
DS_8010C_024 73S8010C Data Sheet
Figure 3: I
2
C Bus Read Protocol
2.3 I2C-bus Timing
Symbol Parameter Conditions Min. Typ. Max. UNIT
Fsclk Clock frequency 400 kHz
Tlow Clock low 1.3
Thi Clock high 0.6
Thdsta Hold time START condition 0.6
Tsudat Data set up time 100 ns
Thddat Data hold time 5 900 ns
Tsusto Set up time STOP condition 0.6
Tbuf
Bus free time between a STOP and
1.3
START condition
SDA
Tbuf
s
s
s
s
s
SCL
Tlow
Thi
Thdsta
TsudatThddatTsusto
Figure 4: I
2
C Bus Timing Diagram
Rev. 1.5 9
73S8010C Data Sheet DS_8010C_024
3 Oscillator
The Teridian 73S8010C device has an on-chip oscillator that can generate the smart card clock using an
external crystal, connected between the XTALIN and XTALOUT pins, to set the oscillator frequency.
When the card clock signal is available from another source, it can be connected to the pin XTALIN, and
the pin XTALOUT should be left unconnected.
4 DC-DC Converter – Card Power Supply
An internal DC-DC converter provides the card power supply. This converter is able to provide either a
3 V or 5 V card voltage from the power supply applied on the V
controls the converter. Bit 2 of the Control register selects the card voltage.
The circuit is an inductive step-up converter/regulator. The external components required are 2 filter
capacitors on the power-supply input V
filter capacitor on the card power supply V
operation when V
input supply V
3.6 V, V
= 3 V) the circuit operates as a linear regulator. Depending on the inductor values, the voltage
CC
is below a set point of 5.0 or 3.0 volts minus a comparator hysteresis voltage and the
CC
is less than the set point for VCC. When VDD is greater than the set point for VCC (VDD =
DD
converter can provide current on V
(100 nF + 10 F, next to the LIN pin), an inductor, and an output
DD
. The circuit performs regulation by activating the step-up
CC
as high as 100 mA.
CC
The circuit provides over-current protection and limits I
to 150 mA. When an over-current condition is
CC
sensed, the circuit initiates a deactivation sequence from the control logic and reports back to the host
controller a fault on the interrupt output INT.
Choice of the Inductor
The nominal inductor value is 10 H, rated for 400 mA. The inductor is connected between pin LIN (pin 5
in the SO package, pin 2 in the QFN package) and the V
optimized to meet a particular configuration (I
CC_MAX
DD
). The inductor should be located on the PCB as
close as possible to the LIN pin of the IC.
Choice of the V
Capacitor
CC
Depending on the applications, the requirements in terms of both V
currents that the interface must be able to provide to the card vary. Table 4 shows the recommended
capacitors for each V
power supply configuration and applicable specification.
CC
pin. The digital ISO-7816-3 sequencer
DD
voltage. The value of the inductor can be
minimum voltage and transient
CC
Table 4: Choice of Vcc Capacitor
Specification Requirement Application
Min V
Specification
Allowed During
Transient Current
EMV 4.0 4.6V 30nA.s
ISO-7816-3 4.5V 20nA.s
Voltage
CC
Max Transient
Current Charge
Capacitor Type Capacitor Value
X5R/X7R w/
ESR < 100 m
3.3 F
1 F
10 Rev. 1.5
DS_8010C_024 73S8010C Data Sheet
5 Voltage Supervision
Two voltage supervisors constantly check the level of the VDD and V
voltages. A card deactivation
CC
sequence is forced when a fault occurs for any of these voltage supervisors.
The digital circuitry is powered by the power supply applied on the VDD pin. V
range to interface with the system controller. The V
voltage supervisor is also used to initialize the
DD
also defines the voltage
DD
ISO-7816-3 sequencer at power-on, and to deactivate the card at power-off or when a fault occurs. The
voltage threshold of the V
voltage supervisor is internally set by default to 2.3 V nominal. However, it
DD
may be desirable in some applications, to modify this threshold value. The pin VDDF_ADJ (pin 18 in the
SO package, pin 17 in the QFN package) is used to connect an external resistor R
the V
fault voltage to another value, V
DD
R
= 180 kΩ / (V
EXT
- 2.33)
DDF
(refer to Figure 11). The resistor value is defined as follows:
DDF
to ground to raise
EXT1
An alternative (more accurate) method of adjusting the VDD fault voltage is to use a resistive network of
R3 from the pin to supply and R4 from the pin to ground (see Figure 11). In order to set the new
threshold voltage, the equivalent resistance must be determined. This resistance value will be
designated Kx. Kx is defined as R4/(R4+R5). Kx is calculated as:
Kx = (2.649 / VTH) - 0.6042 where VTH is the desired new threshold voltage.
To determine the values of R4 and R5, use the following formulas.
R5 = 72000 / Kx R4 = R5*(Kx / (1 – Kx))
Taking the example above, where a VDD fault threshold voltage of 2.7 V is desired, solving for Kx gives:
Using standard 1% resistor values gives R5 = 191 kand R4 = 115 kThese values give an equivalent
resistance of Kx = 0.376, a 0.3% error.
If the 2.3 V default threshold is used, the VDDF_ADJ pin must be left unconnected.
6 Power Down
A power down function is provided via the PWRDN pin (active high). When activated, the Power Down
(PD) mode disables all the internal analog functions, including the card analog interface, the oscillators
and the DC-DC converter, to put the 73S8010C in its lowest power consumption mode. PD mode is only
allowed in the deactivated condition (out of a card session, when the Start/Stop bit is set to 0 from the I
2
C
host controller).
The host controller invokes the power down state when it is desirable to save power. The signal PRES
remains functional in PD mode such that a card insertion sets INT high. The micro-controller must then
set PWRDN low and wait for the internal stabilization time prior to starting any card session (prior to
setting the Start/Stop bit to 1).
Resumption of the normal mode occurs approximately 10 ms (stabilization of the internal oscillators +
reset of the circuitry) after PWRDN is set low. No card activation should be invoked during this 10 ms
time period. If a card is present, INT can be used as an indication that the circuit has completed its
recovery from power down state. INT will go high at the end of the stabilization period. Should the
Start/Stop be set to 1 during PWRDN = 1, or within the 10 ms internal stabilization / reset time, it will not
be taken into account and the card interface will remain inactive. Since Start/Stop is taken into account
on its edges, it should be toggled low and high again after the 10 ms to activate a card.
Figure 5 illustrates the sequencing of the PD and Normal modes. PWRDN must be connected to GND if
the power down function is not used.
Rev. 1.5 11
73S8010C Data Sheet DS_8010C_024
PRES
INT
PWRDN during a card
PWRDN
OFF follows PRES regardless of PWRDN
session has no effect
PWRDN has effect when
the cardi s deactivated
Internal RC OSC
~10ms
Start/Stop bit
After setting PWRDN = 0,
the controller must wait at
least 10ms before setting
Start/Stop = 1
EMV / ISO deactivation
time ~= 100 uS
Figure 5: Power Down Mode Operation
7 Over-temperature Monitor
A built-in detector monitors die temperature. When an over-temperature condition occurs (most likely
resulting from a heavily loaded card interface, including short circuits), a card deactivation sequence is
initiated, and a fault condition is reported to the system controller (bit 4 of the status register is set and
generates an interrupt).
8 Activation Sequence
After Power on Reset, the INT signal is low until VDD is stable. When VDD has been stable for
approximately 10 ms and the INT signal is high, the system controller may read the status register to see
if the card is present. If all the status bits are satisfactory, the system controller can initiate the activation
sequence by writing a ‘1’ to the Start/Stop bit (bit 0 of the Control register).
The following steps and Figure 6 show the activation sequence and the timing of the card control signals
when the system controller initiates the Start/Stop bit (bit 0) of the control register:
1. Voltage VCC to the card should be valid by the end of t1. If VCC is not valid for any reason, then the
session is aborted.
2. Turn I/O to reception mode at the end of t
3. CLK is applied to the card at the end of t
4. RST (to the card) is set high at the end of t
.
1
.
2
.
3
t1 = 0.510 ms (timing by 1.5 MHz internal Oscillator), I/O in reception mode
≥ 0.5 μs, CLK starts
t
2
t
≥ 42000 card clock cycles, RST set high
3
Figure 6: Activation Sequence
12 Rev. 1.5
DS_8010C_024 73S8010C Data Sheet
9 Deactivation Sequence
Deactivation is initiated either by the system controller resetting the Start/Stop bit, or automatically in the
event of hardware faults. Hardware faults are over-current, over-temperature, V
card extraction during the session.
The following steps and Figure 7 show the deactivation sequence and the timing of the card control
signals when the system controller clears the Start/Stop bit:
1. RST goes low at the end of t
2. CLK goes low at the end of t
3. I/O goes low at the end of t
4. Shut down V
at the end of time t4.
CC
.
1
.
2
. Out of reception mode.
3
fault, VCC fault, and
DD
t1 ≥ 0.5 μs t3 ≥ 0.5 μs
t
≥ 7.5 μs t4 ≥ 0.5 μs
2
Figure 7: Deactivation Sequence
10 Interrupt
The interrupt is an active low interrupt. It is set low if either a VCC fault or a VDD fault is detected. It is also
set low if one of the following status bit conditions is detected:
Early ATR
Mute ATR
Card insert or card extract
Protection status from Over-current or Over-heating
If the interrupt is set low by the detection of these status bits, then the interrupt is set high when these
status bits are read. (READ STATUS DONE)
INT
ANY FAULT
STATUS BITS
READ STATUS DONE
Figure 8: FAULT Functions, INT operation
Rev. 1.5 13
73S8010C Data Sheet DS_8010C_024
A power-on-reset (POR) event will reset all of the control and status registers to their default states. A VDD fault
event does not reset these registers, but it will signal an interrupt condition and by the action of the timer that
creates interval “t
considered valid for V
,” will not clear the interrupt until VDD is valid for at least the t1 time. The VDD fault can be
1
as low as 1.5 to 1.8 volts. At the lower range of the VDD fault, POR will be asserted.
DD
11 Warm Reset
The 73S8010C automatically asserts a warm reset to the card when instructed through bit 1 of the I2C Control
register (Warm Reset bit). The warm reset length is automatically defined as 42,000 card clock cycles. The bit
Warm Reset is automatically reset when the card starts answering or when the card is declared mute.
IO
Warm Reset
(bit 1)
RST
t
1
t
2
t
3
t1> 1.5 µs, Warm Reset Starts
t2= 42000 card clock cycles, End of Warm Reset
t3= Resets Warm Reset bit 1 when detected ATR or Mute
Figure 9: Warm Reset operation
12 I/O Timing
The states of the I/O, AUX1, and AUX2 pins are low after power on reset and they are high when the
activation sequencer turns on the I/O reception state. See Section 8 Activation Sequence for more
details on when the I/O reception is enabled.
The states of I/OUC, AUX1UC, and AUX2UC are high after power on reset. When the control I/O enable
bit (bit 7 of the Control register) is set, the first I/O line on which a falling edge is detected becomes the
input I/O line and the other becomes the output I/O line. When the input I/O line rising edge is detected
then both I/O lines return to their neutral state. The delay between the I/O signals is shown in Figure 10.
Delay from I/O to I/OUC: t
Delay from I/OUC to I/O: t
Teridian Semiconductor Corporation makes no warranty for the use of its products, other than expressly
contained in the Company’s warranty detailed in the Teridian Semiconductor Corporation standard Terms
and Conditions. The company assumes no responsibility for any errors which may appear in this
document, reserves the right to change devices or specifications detailed herein at any time without
notice and does not make any commitment to update the information contained herein. Accordingly, the
reader is cautioned to verify that this document is current by comparing it to the latest version on
http://www.teridian.com or by checking with your sales representative.
Teridian Semiconductor Corp., 6440 Oak Canyon Rd., Suite 100, Irvine, CA 92618
TEL (714) 508-8800, FAX (714) 508-8877, http://www.Teridian.com
Added ISO and ENV logo, remove leaded package options, replace 32QFN punched
with SAWN, update 28SO dimension.
figure.
Rev. 1.5 27
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