TERIDIAN Semiconductor 73M1922 User Guide

Simplifying System IntegrationTM
73M1922
Demo Board User Manual
June 24, 2010
Rev. 5.1
UM_1922_006
73M1922 Demo Board User M anual UM_1922_006
© 2010 Teridian S emic onduct or Corporation. All r ights reserv ed. Terid i an Semic onductor Corporation is a r egistered trademark of Teridian Sem i conductor Corporation. Simplifying System Integration is a trademark of Teridian Semiconductor Corp or ation. MicroDAA is a regi stered trademark of Teridian Semi conductor Corporation. Micros oft is a registered trademark of Microso ft Corp oration. Windows is a registered trademark of Microsoft C or por ation . All other trademarks are the property of their res pect ive own ers.
Terid i an Semic onductor Corporation makes no warranty for the use of it s products, other t han expressl y contained in the Comp any’s warrant y detailed i n the Teridian Semiconduct or Corporation stan dard Terms and C ondit ions. The company assumes no res ponsibility for an y errors which m ay appear in this document, reserves the right to c hange devices or specific ations detailed herein at an y time without notice and does not make any commitment to updat e the i nform ation contained herein . Accord in gly, the reader is cau tioned to verify that this docum ent i s c urren t by comp ar i ng it to the latest vers ion on http://www.teridian.com or by checking with your sal es representat i ve.
Terid i an Semic onductor Corp., 6440 Oak C anyon, Su ite 100 , Irvine, CA 92618
TEL (714) 508-8800, FAX (714) 508-8877, http://www.teridian.com
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UM_1922_006 73M1922 Demo Board User Manual
Table of Contents
1
Introduction ................................................................................................................................... 5
1.1 Pack age Conten ts.................................................................................................................... 6
1.2 Safety and ESD Not es ............................................................................................................. 6
1.3 Demo Board Options................................................................................................................ 6
2 Connectors .................................................................................................................................... 7
3 Demo Board Schematics, PCB Layouts and Bill of Materials ..................................................... 8
3.1 Schematic ................................................................................................................................ 8
3.2 73M1922 20-Pin TSSO P D emo B oar d Layout .......................................................................... 9
3.3 Demo Board Physical Dimens ion s ......................................................................................... 12
3.4 Bill of Materials ...................................................................................................................... 13
3.5 Pin Descriptions ..................................................................................................................... 14
3.5.1 731 922 Mic r oD AA Pinout ............................................................................................ 15
4 Related Documentation ............................................................................................................... 15
5 Contact Information ..................................................................................................................... 15
Rev. 5.1 3
73M1922 Demo Board User M anual UM_1922_006
Figures
Figure 1 : MicroDAA S ystem Block Di agram Figure 2 : 73M1922 Micr oDAA 20-Pin TS SOP Dem o Board Schematic Di agram Figure 3: 73M1922 20-Pin TSSOP Demo Boar d: Top Sign al Layer Figure 4: 73M1922 20-Pin TSSOP Demo Boar d: Laye r 2, Ground Plane Figure 5: 73M1922 20-Pin TSSOP Dem o Board: Layer 3, Supply Plane Figure 6: 73M1922 20-Pin TSSOP Demo Boar d: Bottom Signal Layer Figure 7: 73M1922 20-Pin TSSOP Demo Boar d: Silk Sc r een Top Figure 8: 73M1922 20-Pin TSSOP Demo Board: Silk Screen Bottom Figure 9: 73M1902/73M1912 20-Pin TSS OP Pac kages: Pinout (top view)
Tables
Table 1: 73M1922 Demo Board Connectors Table 2: 73M1922 Demo Board Configuration Settings Table 3: JS 1 Host Interface Con nect or Table 4: 73M1922 20-Pin TSSO P D emo B oar d Bi ll of Materials Table 5: 73M1902 HIC 20-Pin TSSOP Package Pin Definitions Ta bl e 6: 73M1912 LIC 20-Pi n TSSOP Package Pin Definitions
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UM_1922_006 73M1922 Demo Board User Manual
73M
1902
73M
1912
L
I
N
E I
N
T E
R
F A
C
E
H O S T
I N T E R F A C E
73M1922
Host Interface
Chip (Circuitry)
Line Interface
Chip (Circuitry)
GPIO
FS
FSB
SCLK
SDIN
SDOUT
TYPE
M/S
INT/RGDT
OSCIN
OSCOUT
RGP RGN OFH
DCI
DCB DCE TXN RXM RXP
SRE ACS SRB
DCD
PULSE
TRANSFORMER
SCKM
AOUT
Shaded pins and names are optional depending on packages
1 Introduction
The 73M1922 MicroDAA Chipset D em o Board integrates sil icon D ata Access Ar r angem ent (DA A) function along with Analog Fr o nt E nd functio ns chipsets for worldwide c omp lianc e.
The 73M1922 MicroDAA chipset co nsists of a 73M1902 and a 73M1912. The 73M1902 is the Host Interface Chip ( HIC) providi ng a host microprocessor or DS P in terface by a synchronous serial port (Modem Analog Front En d ( M AFE ) ) and the 73M1912 is the Line Interfac e C hip ( LIC) t o connect to a telephone line.
The 73M1922 chipset is packaged in two 20-pin TSSOP or two 32-pin QFN pack ages for a v ery small ph ysical dimension and offers l ow cost global DA A design.
The 73M1922 performs a modem codec funct i on that interfac es a Host/ D SP and the PSTN (Pu blic Switc hed Telephone Network). The codec suppor ts data rat es up t o V.92 with cal l progress signal i ng. In add i tion to the c odec functi o n, t he 73M192 2 Mic r oD AA ch ipset also performs other necessary DAA functions, such as CI D (caller i dentification) , rin g detection, tip/ring polar ity reversal detecti on, on/off hook switch contr ol, p ulse di al ing , regu l ation of loop current (DC-I V), l ine impedance matching, line in use and parall el p ickup det ection.
All data and control inform ation between the LIC and the HIC is transferred across a low cost pulse transformer barrier. Also all clock and synchronization information needed in LIC is embedded in this data and control bit stream acros s the b ar r ier transfor mer rec eived from H IC an d recons tructed within LIC. The LIC interface to tip/ring of the PSTN significantly lowers the number of external components and their cost.
The DAA feature integrated in this chipset offers a configurable US, ETSI ES 203 021-2, or other World Wide DAA capability to t he tel ephone line interface an d an auxiliary DAC with gain con trol for line monitoring during the call pr ogress period.
Rev. 5.1 5
Figure 1: MicroDAA System Block Diagram
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