TERIDIAN Semiconductor 73M1822 User Guide

Simplifying System IntegrationTM

73M1822

Keychain Demo Board Us er Manual

March 9, 2010

Rev. 5.0

UM_1822_007

73 M1 822 Keych ai n Demo Board User M anual UM_1822_007

© 2010 Teridian Semi conductor Corporati on. Al l r ights r eserved.
Terid i an Semiconductor Corporation is a registered trademark of Terid ian Semiconductor Corporation.
Simplifying System Integration is a trademark of Terid i an Semiconductor Corporation.
MicroDAA is a register ed trad emark of Teridian Semiconduct or Corporati on.
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All other trademark s are the propert y of t heir respective owners .

Terid i an Semiconductor Corporation makes no warranty for the use of its products, other t han expressly
contained in the Company’s warranty detailed in the Teridian S emiconductor C or poration stan dard Term s
and C onditions. The company assumes no responsibilit y fo r any errors which may appear in this
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reader is caut i oned to verify that th i s document is cur r ent by comparing it to the l atest versi on on
http://www.teridian.com or by checki ng with you r sales representative.

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TEL [phone], FAX [phone], http://www.teridian.com

2 Rev. 5.0

UM_1822_007 73M1822 Keychain D emo Board User Manual

Table of Contents

1

Introduction ................................................................................................................................... 5

1.1 Pack age Contents.................................................................................................................... 6

1.2 Safety and E SD Notes ............................................................................................................. 6

1.3 Demo Board Options................................................................................................................ 6

2 Connectors .................................................................................................................................... 7

3 Software Description ..................................................................................................................... 8

3.1 System Initialization ................................................................................................................. 8

3.2 73M1822 Sys te m Ini ti aliz a ti o n .................................................................................................. 9

3.3 Off-H ook Procedure ............................................................................................................... 11

3.4 Dialing ................................................................................................................................... 12

3.4.1 DTMF Dialing .............................................................................................................. 12

3.4.2 Pulse Dialing ............................................................................................................... 12

3.4.3 Adapt ive Dialing .......................................................................................................... 14

3.5 LINE Sensing ......................................................................................................................... 15

3.5.1 Line-In-Use (LI U) - Prior to the Modem Goi ng Off-Hook............................................... 16

LIU Check Procedure ............................................................................................................. 17

3.5.2 Parallel Pick Up (PPU) - While the Modem is Off-Hook................................................ 17

3.5.3 PPU Check Pr ocedure ................................................................................................ 18

3.6 Ring Detect ............................................................................................................................ 18

3.6.1 Ring Detection Setup with Hardware Ring Qualifier ..................................................... 19

3.6.2 Ring Detection Using Coarse Ring Output ................................................................... 20

3.7 Line Polarity Reversal Detection............................................................................................. 20

3.8 Line Snoop / Type I Caller ID Detection .................................................................................. 21

4 Demo Board Schematics, PCB Layouts and Bill of Materials ................................................... 24

4.1 Schematic .............................................................................................................................. 24

4.2 73 M1 822 Mic r oDAA Demo Board PCB Layout ....................................................................... 25

4.2.1 73M1822 42-Pin QFN Keychain Demo Board L ayout .................................................. 25

4.2.2 Keych ain Dem o Board Physical Di mensions ............................................................... 27

4.3 Bill of Materials ...................................................................................................................... 28

4.4 Pin Descriptions ..................................................................................................................... 28

4.4.1 731822 Pinout............................................................................................................. 30

5 Related Documentation ............................................................................................................... 31

6 Contact Information ..................................................................................................................... 31

Rev. 5.0 3

73 M1 822 Keych ai n Demo Board User M anual UM_1822_007

Figures

Figure 1: Mic r oDAA System Block Diagr am
Figure 2: 73 M 1822 Register Polling
Figure 3: Off-Hook Procedure
Figure 4: Pulse Dialing Sequence
Figure 5: Dialing
Figure 6: Adapt ive Dialing
Figure 7: Line-In-Use Det ection
Figure 8: On-Hook TIP-RING DC Reading
Figure 9: Par allel Ph one Off-Hook Detection
Figure 10: Ring Qualifier
Figure 11: R ing Detec tor
Figure 12: Line Polarity Reversal Detection
Figure 13: C aller ID Detection Path
Figure 14: 73M1822 K eyc hain Demo Board Schematic
Figure 15: 73M1822 K eyc hain Demo Board : Top Signal Layer and Silk Screen
Figure 16: 73M1822 K eyc hain Demo Board : Layer 2, Ground Plane
Figure 17: 73M1822 Keychain Demo Board: Layer 3, Supply Plane
Figure 18: 73M1822 K eyc hain Demo Board : Bottom Signal Layer and Silk Screen
Figur e 19: 73M1822 QFN 42-Pin Package: Pinout (top view)

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Tables

Table 1: Host Interface JP2 Connector Pinout
Table 2: Lin e Interface JP1Connector Pinout
Table 3: 73M 1822 Keych ai n Demo Board Bi ll of Materia ls
Table 4: 73M1822 42-Pin QFN Package Pin Definitions

.......................................................................................... 7

........................................................................................... 7

..................................................................... 28

......................................................................... 29

4 Rev. 5.0

GPIO

FS

FSD

SCLK

SDIN

SDOUT

M/S

INT/RGDT

OSCIN

OSCOUT

H
O
S
T

I
N
T
E
R
F
A
C
E

L

I
N
E

I
N
T
E
R
F
A
C
E

RGP
RGN
OFH

DCI

DCB
DCE
TXN
RXM
RXP

SRE
ACS
SRB

DCD

73M1822

PULSE

TRANSFORMER

73M1822

Line Interface

Circuitry

Host Interface

Circuitry

AOUT

UM_1822_007 73M1822 Keychain D emo Board User Manual

1 Introduction

The 73M1822 Keychain Demo Board integrates silicon Data
Acc ess Arrangemen t (DAA) fun ction al ong with Analog Front End
functions chipsets for worldwide com pliance.

The 73M1822 MicroDAA is the world’s first single chip silicon DAA
IC t hat perform the ad vanced si licon Data Access Arrangement
(DAA) function along with Analog Front End functions.

The 73M 1822 MicroDAA i s available in a 42 pi n QFN pac kage for a
very small physical dimension and offers low cost global DAA
design.

Figure 1: MicroDAA System Block Diagram

The 73M1822 performs a modem codec function that interfaces a Host/DSP and the PSTN (Publ ic
Switc hed Telephone Network). The codec supports data rates up to V.92 with call progress si gnaling. In
add i tion t o the codec f unc t ion, the 73M1822 MicroDAA also performs other necessary DAA functions,
such as CID (caller identification), r i ng d etection, tip/ring polari ty reversal detection , on/off hook swit ch
control, p ulse dialing, r egulation of loop current ( D C-IV), line impedanc e m atching, line in use and parallel
pickup detection.

All dat a and control information between t he LIC an d the HIC is trans ferr ed across a low cost pulse
tran sformer b ar r ier. Also all cl ock and synchr onizati on information needed in LIC is embedded in this
data and control bit stream across the barrier transfor mer received from HIC and reconstructed within
LIC. The LIC interface to tip/ring of the PSTN significantly lowers the number of external components and
their cost.

The DAA feature integr ated in this device offers a config urable U S, TBR21, or other World Wide DAA
capability t o the telephon e l ine interface and an auxili ary DAC with gain contr ol for lin e monitoring during
the call progress p er i od.

Rev. 5.0 5

73 M1 822 Keych ai n Demo Board User M anual UM_1822_007

1.1 Package Contents

The 73M1822 Keychain Demo Boar d Kit in cludes:

• A 73 M 1822 Keychain Demo Board ( R ev. D1)

• The following documents on CD:

• 73M1822 Keychain Demo Board User Manual (this document)

• 73M1822/73M1922 Data Sheet

• 73M1822/73M1922 Schematic and Layout Guidelines

• 73M 1x2 2 Wor ldwide Design Gui de

1.2 Safety an d ES D Notes

Connecting live voltages to the Demo Board system will result in potentially h azardous voltages on the
boards.

Extreme caution should be taken when handling the Demo Boards after connection to
live voltages!

The Demo Boards are ESD sensitive! ESD precautions should be taken when handling
these boards!

1.3 Demo Board Options

The 73M1822 Keychain Demo Board has 20-pin right angle connect or s to plug on to a target DSP or
CPU system. Each has a 3. 3 V power receptacle for power i ng on -board cir cuits from target system or
external power supply, or power can be supplie d t hr o u gh the 20-pin connector along with the oth er
signals. The 73M1822 Keychain D emo Board allows the evaluat ion of t he 73M1822 device for universal
modem, voice ap plicat i on and i nterface to a general D SP or CPU system use.

6 Rev. 5.0

UM_1822_007 73M1822 Keychain D emo Board User Manual

2 Connectors

Table 1 and Table 2 show all the connectors and jumpers available on 73M1822 Keychain Demo B oar d.
JP2 is the mai n connec tor for int er facing to a host processor or DSP board. JP1 is a connector for ph one
line connec tion. Be aware that there is no high voltage and current protection circuit included in any
Keych ain Dem o Boards. Make sur e these protection circuit components ar e placed i n between t he
telephone li ne and JP1 connector for a practical design. Line monitor/Call pr ogress monit or speaker and
driver circuits are not available on the Keychai n Demo Boards. Refer to the 73M1822 Keychain Demo
Board schematics for t he protection circui t and Call Progress Monit or circui t referen ces.

Table 1: Host Interface JP2 Connector Pinout

PIN Number Name Description

1
2
3
4
5
6
7
8
9

10

FSBD Delayed FS
RINGD Interrupt Output
VCC 3.3V Su ppl y
RESET Reset Input
AOUT Call progress Monitor ou t
GND Power Signal GND
FS Fram e Sync
SCLK S erial Clock
AFEIN Serial Data In
AFEOUT Serial Data Ou t

Table 2: Line Interface JP1Connector Pinout

PIN Number Name Description

1
2

TIP Phone Line Connection
RING Phone Line Connection

Rev. 5.0 7

LIC ADD -> INDX3:0

(Reg19:3-0)

1-> POLL (Reg 19:7)

POLL(Reg19:7)=0?

MATCH(Reg19:6)=1?

Both HIC and LIC registers

specified by the ADD are

synchronized

Read POLLVAL(Register1F)

END

y

y

n

START

The HIC and LIC registers

specified by the ADD are

different

n

Error Handling

73 M1 822 Keych ai n Demo Board User M anual UM_1822_007

3 Software Description

3.1 System Initialization

This s ection describes softwar e that is not provided with the 73M1822 Keychain Demo Board but must be
provid ed by the Host sys tem.

Once the system starts initialization, the system controll er al so needs to initialize the 73M1822 device set
as one of its peripheral. Some register s contain both control and status bits which are read only. When
using READ-MODIFY-W RITE to update an HIC regis ter, care must be taken not to modify the status and
control bits unintentionally.

Upon power on reset, the HIC registers that contains the copy of the LIC reg isters (Register 0x12
to Register 0x1F) will be initialized to the default reset value. When the power of LIC is fed from
the HIC by setting the ENFEF bit (Register 0x0F Bit 7), LIC will be initialized with the default
register value that are identical to the values in register copy in LIC. Form this point, Any host
control to the LIC register bits by wri ting to an HIC register which is copy of the LIC register will
change both HIC and LIC maintaining images of each other unless data errors occur. In this
situation, there is a LIC register polling mechanism to regain this synchronization by host control.
Figure 2 illustrates how to re-synchronize the HIC and LIC registers by polling.

8 Rev. 5.0

Figure 2: 73M1822 Register Polling

UM_1822_007 73M1822 Keychain Demo Board User Manual

3.2 73M1822 System Initialization

The following exampl e shows the sequ ence to bri ng the 73M18 2 2 MicroDAA out of reset and to s tart up
after power up.

NOTE: The 73M1822 MicroDAA does n ot have a power on reset c ircuit. For p r oper operation, a reset
signal shall be asserted from the host by pulling the reset pin of 73M1822 low ap proximately for 100 ns or
longer after the power is stabil i zed. The 73M1822 device will be ready to use within 100 μs after the
remov al of reset pulse from th e r eset pin.

Resetting the 73M1822

The 73M1822 package does not have a dedicated res et pin due to pin restriction. An alternative reset
can be assert ed through the M/S pin (pi n 21 of 73M1 822 42-pin QFN).

Any low-to-high or high-to-low transition at this pin will r esult i n int er nal reset block to initiat e the reset
process. So if the MA FE needs to be in MASTER configuration, the h ost needs to generate an active low
reset signal as a reset si gnal at this pi n. Use act ive high res et signal for SLAVE mode of MAFE
applications.

• Power up the system.

• Wait for 3.3V power to be stable

• Pull M/S pin low for 100 ns then let it go high if the 73M1822 is in Master configuration. (Pull M/S pin

high for 100 ns or longer then l et it go low in case of slave configuration)

• Wait for 100 μs for PLL, OS C to be stabilized

Initializing MicroDAA

A. Frame Synchronization

• RESET HC bit (Register 0x01 bit 0) in a frame sequence.

• RESET HC bit (Register 0x01 bit 0) in next frame sequence.

• Then the HIC is guaranteed t o be i n software controlled con trol frame mod e, now. All the MAFE

serial data sh all be data only unless host req uest by setting bit 0 of data.

B. Control Frame Generation
Software Controlled Control Frame

• MAS K C TL (TXD Bit 0) as 1 to request a subsequ ent cont r ol frame.

• Write or read t he 73M18 22 HIC regi ster using the MAFE control data form at.

• Make sure to MASK CTL (TXD bit 0) as 0 if the control frame is not needed.

Hardware Controlled Control Frame

• MAS K TX D Bit 0 as 1 to request a subsequent c ontrol frame.

• SET HC bit (Register 0x01 bit0) using the MAFE control dat a format in the next frame.

• From now on, there will be data and control frames alternating. Make sure not to miss this sequence.

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73 M1 822 Keych ai n Demo Board User M anual UM_1822_007

C. 73M1822 HIC Initialize

• Disable daisy chain by writin g 00H to HIC Register 0x01.

• Configure eit her Hardware con trol frame or software control frame by sel ecting the HC bit (Register

0x02:0).

• Configure GPIOs by s el ecting GPIO Data (Regis ter 0x03), GPIO Direction (Register 0x04), GPIO
Interrupt Enable (Register 0x05) and Interrupt Polarity (Register 0x06).

• Timing Chain setup ( R egister 0x08 - - Regi ster 0x0 D). Register 0x0D value shall be written the last.
An y ot her writes to Register 0x08 to Regi ster 0x0C are not r eal ly affec ting to the PLL until Register
0x0D is being written . It is also recommended to set CHNG FS (Register 0x0D:3) bit in case further
sample rate c hanges are r equired for such as V.90 appli cations.

• En able Analog Front End blocks by setting ENFEH bit (Register 0x0F:7). And put device active by
clearing SLEEP bit (Register 0x0F:5).

• Select system clock driven from PLL by setting FRCVCO bi t of Register 0x0E bit 7. (The FR C VCO
bit shall be s et at least 2 sample period aft er writi ng t o R egister 0x0D.)

D. LIC Init

73M1822 LIC initialization shall beg in aft er the73M1822 LIC part is fully powered up and initialized. From
the HIC Initialization above, setting ENFE then the FRVCO bits will start powering the 73M1822 LIC.
From this moment, the Host shall wait for 10 0 to 200m s for t he 73 M1 822 LIC t o be ready.

• Enable Front End functional blocks by setting ENFE bit (Register 0x12:2)

• Write 0x01 t o Regist er 0x18.

• Select prop er fi l ter setting per each sample rat e setting FSCTR b its (Register 0x16:3-0)

• Select prop er AC impedance termination by setting AC Z31,0 (Register 0x17: 4, 3)

• Enable receiver path by setti ng RXEN bit ( Regis ter 0x16:6)

Example 1. Using Software Controlled Control Frame:

static const U16 init_afe_config[] = // Must have Data(LSB=1) , Control,

// Data(LSB=1), Control,.. FRAMES
{
REG02|0x00, REG02|0x00, // Forc e to Software controlled c ontrol frame (HC=0)
CTRL_FRAME, REG04|0x00, // GPIO 7,6,5,4 = outputs
CTRL_FRAME, REG03|0x00, // GPIO 7,6,5,4 output data =0000
CTRL_FRAME, REG05|0x00,
CTRL_FRAME, REG06|0x00,
CTRL_FRAME, REG07|0x00,
CTRL_FRAME, REG08|AFE_CTRL08, // Timi ng chain set up (Smaple Rate)
CTRL_FRAME, REG09|AFE_CTRL09,
CTRL_FRAME, REG0A|AFE_CTRL0A,
CTRL_FRAME, REG0B|AFE_CTRL0B,
CTRL_FRAME, REG0C|AFE_CTRL0C,
CTRL_FRAME, REG0D|AFE_CTRL0D,
CTRL_FRAME, RW B|REG03, // Del ay for 2 sample cycl e time t o
CTRL_FRAME, RW B|REG03, / / let PLL settle before Lockdet by dummy read
GPIO
CTRL_FRAME, REG0F|0x8C / / Set ENF E Bit, Reset Sleep Bit
CTRL_FRAME, REG0E|0x80 // Set FrVCO bit

};
note: CTRL_FRAME = 0x0001

10 Rev. 5.0