TERIDIAN Semiconductor 71M6521BE Technical data

71M6521BE

GENERAL DESCRIPTION

The TERIDIAN 71M6521BE is a highly integrated SOC with an MPU core, FLASH and LCD driver. TERIDIAN’s patented Single Converter Technology™ with a 22-bit delta-sigma ADC, four analog inputs, digital temperature compensation, precision voltage reference, battery voltage monitor, and 32bit computation engine (CE) supports a wide range of residential metering applications with very few low-cost external components. A 32kHz crystal time-base for the entire system further reduces system cost. The IC supports 2-wire single-phase residential metering along with tamperdetection mechanisms.

Maximum design flexibility is provided by multiple UARTs, I 14 DIO pins and in-system programmable FLASH memory, which can be updated with data or application code in operation.

A complete array of ICE and development tools, programming libraries and reference designs enable rapid development and certification of AMR and Prepay meters that comply with worldwide electricity metering standards.

32 kHz

CT/SHUNT

AMR

POWER

FAULT

RX/DIO1

TX/DIO2

LOAD

CONVERTER

VOLTAGE REF

VREF

VBIAS

SERIAL PORTS

SENSE

DRIVE/MOD

COM PARATOR

OSC/PLL

XIN

XOUT

POWER SUPPLY

V3.3

V3.3A

SYS

TERIDIAN

71M6521BE

TEMP

SENSOR

RAM

FLASH

COMPUTE

ENGINE

MPU

TIMERS

ICE

GNDA GNDD

PWR MODE

CONTROL

WAKE-UP

REGULATOR

VBAT

V2.5

DIO, PULSE

COM0..3

SEG0..18

SEG 24..31/

DIO 4..11

SEG 34..37/

DIO 14..17

SEG 32,33,

ICE_E GNDD

11/14/2007

NEUT

C, μWire, up to

BATTERY

3.3V LCD

888888.88

I2C or µWire

EEPROM

TEST PULSE

V3P3D

Energy Meter IC

DATA SHEET

JANUARY 2008

FEATURES

• < 0.4% Wh accuracy over 2000:1 current range

and over temperature

• Exceeds IEC62053 / ANSI C12.20 standards

• Voltage reference < 40ppm/°C

• Four sensor inputs—VDD referenced

• Low jitter Wh test output (10kHz maximum)

• Pulse count for Wh pulse output

• Tamper detection: Neutral current with CT or

shunt

• Line frequency count for time keeping

• Digital temperature compensation

• Sag detection for phase A and B

• Independent 32-bit compute engine

• 46-64Hz line frequency range with same

calibration

• Phase compensation (±7°)

• Battery monitor

• Three battery modes w/ wake-up on push-button

or timer:

Brownout mode (48µA) LCD mode (5.7µA) Sleep mode (2.9µA)

• Energy display on main power failure

• Wake-up with push-button

• 22-bit delta-sigma ADC

• 8-bit MPU (80515), 1 clock cycle per instruction

w/ integrated ICE for MPU debug

• Hardware watchdog timer, power fail monitor

• LCD driver (up to 140 pixels)

• Up to 14 general purpose I/O pins

• 32kHz time base

• 8KB FLASH with security

• 2KB MPU XRAM

• Two UARTs for IR and AMR

• Digital I/O pins compatible with 5V inputs

• 64-pin LQFP

• Lead Free package

V1.0

71M6521BE

Energy Meter IC

DATA SHEET

JANUARY 2008

Table of Contents

GENERAL DESCRIPTION ............................................................................................................................................1

FEATURES......................................................................................................................................................1

HARDWARE DESCRIPTION......................................................................................................................................... 9

Hardware Overview..........................................................................................................................................9

Analog Front End (AFE)...................................................................................................................................9

Input Multiplexer ................................................................................................................................9

A/D Converter (ADC).......................................................................................................................10

FIR Filter.......................................................................................................................................... 10

Voltage References ......................................................................................................................... 10

Temperature Sensor........................................................................................................................ 11

Battery Monitor ................................................................................................................................12

Functional Description .....................................................................................................................12

Digital Computation Engine (CE) ...................................................................................................................12

Meter Equations ..............................................................................................................................13

Real-Time Monitor ........................................................................................................................... 13

Pulse Generator ..............................................................................................................................13

CE Functional Overview ..................................................................................................................14

80515 MPU Core ...........................................................................................................................................16

Memory Organization ......................................................................................................................16

Special Function Registers (SFRs).................................................................................................. 18

Special Function Registers (Generic 80515 SFRs) .........................................................................19

Special Function Registers Specific to the 71M6521BE .................................................................. 21

Instruction Set..................................................................................................................................22

UART...............................................................................................................................................22

Timers and Counters ....................................................................................................................... 25

WD Timer (Software Watchdog Timer)............................................................................................ 27

Interrupts .........................................................................................................................................29

On-Chip Resources .......................................................................................................................................37

Oscillator..........................................................................................................................................37

PLL and Internal Clocks...................................................................................................................37

Temperature Sensor........................................................................................................................ 37

Physical Memory ............................................................................................................................. 37

Optical Interface ..............................................................................................................................38

Digital I/O......................................................................................................................................... 39

LCD Drivers .....................................................................................................................................41

Battery Monitor ................................................................................................................................41

EEPROM Interface .......................................................................................................................... 41

Hardware Watchdog Timer..............................................................................................................45

Program Security.............................................................................................................................45

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Energy Meter IC

DATA SHEET

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Test Ports ........................................................................................................................................ 46

FUNCTIONAL DESCRIPTION..................................................................................................................................... 47

Theory of Operation .......................................................................................................................................47

System Timing Summary...............................................................................................................................48

Battery Modes................................................................................................................................................49

BROWNOUT Mode ......................................................................................................................... 50

LCD Mode .......................................................................................................................................51

SLEEP Mode ...................................................................................................................................51

Fault and Reset Behavior ..............................................................................................................................56

Wake Up Behavior .........................................................................................................................................57

Wake on PB.....................................................................................................................................57

Wake on Timer ................................................................................................................................57

Data Flow.......................................................................................................................................................58

CE/MPU Communication ............................................................................................................................... 58

Temperature Measurement ...........................................................................................................................59

Temperature Compensation ..........................................................................................................................59

APPLICATION INFORMATION ...................................................................................................................................60

Connection of Sensors (CT, Resistive Shunt)................................................................................................ 60

Connecting 5V Devices..................................................................................................................................60

Connecting LCDs........................................................................................................................................... 61

Connecting I

Connecting Three-Wire EEPROMs................................................................................................................63

UART0 (TX/RX) .............................................................................................................................................64

Optical Interface.............................................................................................................................................64

Connecting V1 and Reset Pins ......................................................................................................................65

Connecting the Emulator Port Pins ................................................................................................................ 66

Crystal Oscillator............................................................................................................................................ 67

Flash Programming........................................................................................................................................67

MPU Firmware Library ...................................................................................................................................67

Meter Calibration............................................................................................................................................67

FIRMWARE INTERFACE ............................................................................................................................................68

I/O RAM MAP – In Numerical Order ..............................................................................................................68

SFR MAP (SFRs Specific to TERIDIAN 80515) – In Numerical Order ..........................................................69

I/O RAM DESCRIPTION – Alphabetical Order .............................................................................................. 70

CE Interface Description ................................................................................................................................76

C EEPROMs ............................................................................................................................63

CE Program..................................................................................................................................... 76

Formats ...........................................................................................................................................76

Constants ........................................................................................................................................76

Environment ....................................................................................................................................76

CE Calculations ............................................................................................................................... 77

CE STATUS ....................................................................................................................................77

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Energy Meter IC

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CE TRANSFER VARIABLES ..........................................................................................................79

Other CE Parameters ...................................................................................................................... 80

ELECTRICAL SPECIFICATIONS ................................................................................................................................83

ABSOLUTE MAXIMUM RATINGS ................................................................................................................83

RECOMMENDED EXTERNAL COMPONENTS ...........................................................................................84

RECOMMENDED OPERATING CONDITIONS ............................................................................................84

PERFORMANCE SPECIFICATIONS ............................................................................................................85

INPUT LOGIC LEVELS ................................................................................................................... 85

OUTPUT LOGIC LEVELS ............................................................................................................... 85

POWER-FAULT COMPARATOR.................................................................................................... 85

BATTERY MONITOR......................................................................................................................85

SUPPLY CURRENT........................................................................................................................86

V3P3D SWITCH .............................................................................................................................. 86

2.5V VOLTAGE REGULATOR ........................................................................................................ 86

LOW POWER VOLTAGE REGULATOR......................................................................................... 87

CRYSTAL OSCILLATOR ................................................................................................................87

VREF, VBIAS ..................................................................................................................................87

ADC CONVERTER, V3P3A REFERENCED...................................................................................88

OPTICAL INTERFACE....................................................................................................................88

TEMPERATURE SENSOR .............................................................................................................89

LSB values do not include the 9-bit left shift at CE input. ................................................................89

LCD DRIVERS ................................................................................................................................88

TIMING SPECIFICATIONS ...........................................................................................................................90

RAM AND FLASH MEMORY ..........................................................................................................90

FLASH MEMORY TIMING ..............................................................................................................90

EEPROM INTERFACE.................................................................................................................... 90

RESET ............................................................................................................................................90

TYPICAL PERFORMANCE DATA .................................................................................................. 91

PACKAGE OUTLINE (LQFP 64) ...................................................................................................................92

PINOUT (LQFP-64) .......................................................................................................................................93

PIN DESCRIPTIONS .....................................................................................................................................94

Power/Ground Pins:.........................................................................................................................94

Analog Pins: ....................................................................................................................................94

Digital Pins:......................................................................................................................................95

I/O Equivalent Circuits: .................................................................................................................... 96

ORDERING INFORMATION .........................................................................................................................97

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List of Figures

Figure 1: IC Functional Block Diagram........................................................................................................................... 8

Figure 2: General Topology of a Chopped Amplifier ....................................................................................................11

Figure 3: AFE Block Diagram....................................................................................................................................... 12

Figure 4: Samples from Multiplexer Cycle.................................................................................................................... 14

Figure 5: Accumulation Interval....................................................................................................................................15

Figure 6: Interrupt Structure ......................................................................................................................................... 36

Figure 7: Optical Interface............................................................................................................................................39

Figure 8: Connecting an External Load to DIO Pins..................................................................................................... 40

Figure 9: 3-Wire Interface. Write Command, HiZ=0. ....................................................................................................43

Figure 10: 3-Wire Interface. Write Command, HiZ=1 ...................................................................................................43

Figure 11: 3-Wire Interface. Read Command............................................................................................................... 44

Figure 12: 3-Wire Interface. Write Command when CNT=0.........................................................................................44

Figure 13: 3-Wire Interface. Write Command when HiZ=1 and WFR=1....................................................................... 44

Figure 14: Functions defined by V1.............................................................................................................................. 45

Figure 15: Voltage. Current, Momentary and Accumulated Energy .............................................................................47

Figure 16: Timing Relationship between ADC MUX, Compute Engine, and Serial Transfers. .....................................48

Figure 17: RTM Output Format ....................................................................................................................................49

Figure 18: Operation Modes State Diagram.................................................................................................................50

Figure 19: Functional Blocks in BROWNOUT Mode (inactive blocks grayed out)........................................................ 52

Figure 20: Functional Blocks in LCD Mode (inactive blocks grayed out)......................................................................53

Figure 21: Functional Blocks in SLEEP Mode (inactive blocks grayed out) .................................................................54

Figure 22: Transition from BROWNOUT to MISSION Mode when System Power Returns.........................................55

Figure 23: Power-Up Timing with V3P3SYS and VBAT tied together ..........................................................................55

Figure 24: Power-Up Timing with VBAT only ...............................................................................................................56

Figure 25: Wake Up Timing..........................................................................................................................................57

Figure 26: MPU/CE Data Flow .....................................................................................................................................58

Figure 27: MPU/CE Communication ............................................................................................................................58

Figure 28: Resistive Voltage Divider (Left), Current Transformer (Right) ..................................................................... 60

Figure 29: Resistive Shunt ...........................................................................................................................................60

Figure 30: Connecting LCDs ........................................................................................................................................61

Figure 31: I

Figure 32: Three-Wire EEPROM Connection...............................................................................................................63

Figure 33: Connections for the RX Pin.........................................................................................................................64

Figure 34: Connection for Optical Components ...........................................................................................................65

Figure 35: Voltage Divider for V1 .................................................................................................................................65

Figure 36: External Components for the RESET Pin: Push-Button (Left), EMI Circuit (Right) .....................................66

Figure 37: External Components for the Emulator Interface ........................................................................................66

Figure 38: Wh Accuracy, 0.1A to 200A at 240V/50Hz and Room Temperature........................................................... 91

Figure 39: Meter Accuracy over Harmonics at 240V, 30A............................................................................................91

Figure 40: Typical Meter Accuracy over Temperature Relative to 25°C....................................................................... 92

C EEPROM Connection............................................................................................................................63

V1.0

71M6521BE

Energy Meter IC

DATA SHEET

JANUARY 2008

List of Tables

Table 1: Inputs Selected in Regular and Alternate Multiplexer Cycles ...........................................................................9

Table 2: CE DRAM Locations for ADC Results............................................................................................................13

Table 3: Memory Map ..........................................................................................................................................16

Table 4: Stretch Memory Cycle Width..........................................................................................................................17

Table 5: Internal Data Memory Map.............................................................................................................................18

Table 6: Special Function Registers Locations ............................................................................................................18

Table 7: Special Function Registers Reset Values ......................................................................................................19

Table 8: PSW Register Flags .......................................................................................................................................20

Table 9: PSW Bit Functions .........................................................................................................................................20

Table 10: Port Registers ..........................................................................................................................................21

Table 11: Special Function Registers........................................................................................................................... 22

Table 12: Baud Rate Generation..................................................................................................................................23

Table 13: UART Modes ..........................................................................................................................................23

Table 14: The S0CON Register ...................................................................................................................................23

Table 15: The S1CON register.....................................................................................................................................23

Table 16: The S0CON Bit Functions ............................................................................................................................ 24

Table 17: The S1CON Bit Functions ............................................................................................................................ 24

Table 18: The TCON Register......................................................................................................................................25

Table 19: The TCON Register Bit Functions ................................................................................................................ 25

Table 20: The TMOD Register .....................................................................................................................................26

Table 21: TMOD Register Bit Description ....................................................................................................................26

Table 22: Timers/Counters Mode Description .............................................................................................................. 26

Table 23: Timer Modes ..........................................................................................................................................27

Table 24: The PCON Register .....................................................................................................................................27

Table 25: PCON Register Bit Description.....................................................................................................................27

Table 26: The IEN0 Register (see also Table 32) ........................................................................................................28

Table 27: The IEN0 Bit Functions (see also Table 32).................................................................................................28

Table 28: The IEN1 Register (see also Tables 30/31) .................................................................................................28

Table 29: The IEN1 Bit Functions (see also Tables 31/32) ..........................................................................................28

Table 30: The IP0 Register (see also Table 45)...........................................................................................................29

Table 31: The IP0 bit Functions (see also Table 45).................................................................................................... 29

Table 32: The WDTREL Register.................................................................................................................................29

Table 33: The WDTREL Bit Functions .........................................................................................................................29

Table 34: The IEN0 Register........................................................................................................................................ 30

Table 35: The IEN0 Bit Functions ................................................................................................................................30

Table 36: The IEN1 Register........................................................................................................................................ 30

Table 37: The IEN1 Bit Functions ................................................................................................................................31

Table 38: The IEN2 Register........................................................................................................................................ 31

Table 39: The IEN2 Bit Functions ................................................................................................................................31

Table 40: The TCON Register......................................................................................................................................31

Table 41: The TCON Bit Functions .............................................................................................................................. 31

Table 42: The T2CON Bit Functions ............................................................................................................................ 32

Table 43: The IRCON Register ....................................................................................................................................32

Table 44: The IRCON Bit Functions.............................................................................................................................32

Table 45: External MPU Interrupts ............................................................................................................................... 33

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Energy Meter IC

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Table 46: Interrupt Enable and Flag Bits.....................................................................................................................33

Table 47: Priority Level Groups....................................................................................................................................34

Table 48: The IP0 Register 34

Table 49: The IP1 Register: .........................................................................................................................................34

Table 50: Priority Levels ..........................................................................................................................................35

Table 51: Interrupt Polling Sequence ........................................................................................................................... 35

Table 52: Interrupt Vectors .......................................................................................................................................... 35

Table 53: Data/Direction Registers and Internal Resources for DIO Pin Groups .........................................................39

Table 54: DIO_DIR Control Bit .....................................................................................................................................40

Table 55: Selectable Controls using the DIO_DIR Bits ................................................................................................41

Table 56: EECTRL Status Bits.....................................................................................................................................42

Table 57: EECTRL bits for 3-wire interface.................................................................................................................43

Table 58: TMUX[4:0] Selections...................................................................................................................................46

Table 59: Available Circuit Functions (“—“ means “not active)..................................................................................... 51

Table 60: LCD and DIO Pin Assignment by LCD_NUM............................................................................................... 62

V1.0

71M6521BE

X4MHZ

XIN

XOUT

CKTEST/

SEG19

TEST

OPT_RX/

DIO1

OPT_TX/

DIO2/

WPULSE/

VARPULSE

Energy Meter IC

DATA SHEET

JANUARY 2008

VREF

ΔΣ ADC

4.9MHz

SDCK

SDOUT

SDIN

CONVERTER

ADC_E

VREF

DIV

ADC

CKADC

WPULSE

VARPULSE

RTM

DATA 00-7F

PROG

000-1FF

EEPROM

INTERFACE

0000-FFFF

0000-1FFF

E_RXTX/SEG38

E_TCLK/SEG33

E_RST/SEG32

DATA

PROG

CKFIR

4.9MHz

MEMORY

CE_LCTN

EMULATOR

PORT

1000-11FF

2000-20FF

0000-07FF

E_RXTX E_TCLK E_RST (Open Drain)

MUX

VBIAS

VREF

TEMP

CKOUT_E

EQU MUX_ALT CHOP_E MUX_DIV

(32KHz)

CK_GEN

ECK_DIS MPU_DIV

TEST MODE

UART

OPTICAL

OPT_RXDIS OPT_RXINV OPT_TXE OPT_TXINV OPT_TXMOD OPT_FDC

COMP_STAT

MUX

CTRL

OSC

POWER FAULT

VREF_CAL VREF_DIS

CROSS

CK32

32KHz

4.9MHz

CK_2X

MUX_SYNC

CKCE

<4.9MHz

CONTROL

PLS_INV PLS_INTERVAL PLS_MAXWIDTH CE_LCTN EQU PRE_SAMPS SUM_CYCLES

CKMPU

<4.9MHz

VBIAS

WAKE

FAULTZ

STRT

RTM_0..3 RTM_E CE_E

MCK

PLL

CKOUT_E

32 bit Compute

Engine

CE_BUSY

MPU

(80515)

MPU_RSTZ

XFER BUSY

VBIAS

V3P3A

CK32

32KHz

RESET

Figure 1: IC Functional Block Diagram

FIR

FIR_LEN

CE RAM

(0.5KB)

MEMORY SHARE

VARPULSE

00001FFF

MUX

WPULSE

V3P3A

I/O RAM

MPU XRAM

(2KB)

FLASH

8KB

FLSH66ZT

ICE_E

GNDA

V3P3D

LCD_GEN

LCD_MODE LCD_E

LCD DISPLAY

DRIVER

LCD_NUM LCD_MODE LCD_CLK LCD_E LCD_BLKMAP LCD_SEG LCD_Y

DIGITAL I/O

DIO_EEX DIO_PV/PW DIO_DIR DIO_R LCD_NUM DIO

CONFIG

(I/O RAM)

V3P3SYS

VOLT

REG

LCD_ONLY SLEEP

2.5V to logic

VLC2

VLC1

VLC0

CONFIGURATION

PARAMETERS

TMUX[4:0]

February 2, 2007

SEG32,33 SEG19,38

TEST MUX

DIO1,2

V3P3D

VBAT

GNDD

V2P5

COM0..3

SEG0..18

SEG24/DIO4 .. SEG31/DIO11

SEG34/DIO14 .. SEG37/DIO17

TMUXOUT

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71M6521BE

Energy Meter IC

DATA SHEET

JANUARY 2008

HARDWARE DESCRIPTION

Hardware Overview

The TERIDIAN 71M6521BE single-chip energy meter integrates all primary functional blocks required to implement a solidstate electricity meter. Included on chip are an analog front end (AFE), an independent digital computation engine (CE), an 8051-compatible microprocessor (MPU) which executes one instruction per clock cycle (80515), a voltage reference, a temperature sensor, LCD drivers, RAM, Flash memory, and a variety of I/O pins. Various current sensor technologies are supported including Current Transformers (CT) and Resistive Shunts.

In a typical application, the 32-bit compute engine (CE) of the 71M6521BE sequentially processes the samples from the voltage inputs on pins IA, VA, IB, VB accessed by the MPU, processed further and output using the peripheral devices available to the MPU.

Measurements can be displayed on 3.3V LCD commonly used in low temperature environments. Flexible mapping of LCD display segments will facilitate integration of existing custom LCD. Design trade-off between the number of LCD segments vs. DIO pins can be implemented in software to accommodate various requirements.

The on-chip digital temperature compensation mechanism includes a temperature sensor and associated controls for correction of unwanted temperature effects on measurement. Temperature dependent external components such as crystal oscillator, current sensors, and their corresponding signal conditioning circuits can be characterized and their correction factors can be programmed to produce electricity meters with exceptional accuracy over the industrial temperature range.

One of the two internal UARTs is adapted to support an Infrared LED with internal drive and sense configuration, and can also function as a standard UART. The optical output can be modulated at 38kHz. This flexibility makes it possible to implement AMR meters with an IR interface. A block diagram of the IC is shown in Figure 1. A detailed description of various functional blocks follows.

and performs calculations to measure active energy (Wh). This measurement is then

Analog Front End (AFE)

The AFE of the 71M6521BE is comprised of an input multiplexer, a delta-sigma A/D converter and a voltage reference.

Input Multiplexer

The input multiplexer supports up to four input signals that are applied to pins IA, VA, IB and VB1 of the device. Additionally, using the alternate multiplexer selection, it has the ability to select temperature and the battery voltage. The multiplexer can be operated in two modes:

• During a normal multiplexer cycle, the signals from the IA, IB, VA, and VB pins are selected.

• During the alternate (ALT) multiplexer cycle, the temperature signal (TEMP) and the battery monitor are selected,

along with the signal sources shown in Table 1. To prevent unnecessary drainage on the battery, the battery monitor is enabled only with the BME bit (0x2020[6]) in the I/O RAM.

The alternate multiplexer cycles are usually performed infrequently (e. g. every second or so) by the MPU. In order to prevent disruption of the voltage tracking PLL and voltage allpass networks, VA is not replaced in the ALT multiplexer selections. Missing samples due to an ALT multiplexer sequence are filled in by the CE.

EQU

0 IA VA IB VB TEMP VA IB VBAT

Table 1: Inputs Selected in Regular and Alternate Multiplexer Cycles

: VB is available, but not used in typical 1-phase, 2-wire meters

Regular MUX Sequence ALT MUX Sequence

Mux State Mux State

0 1 2 3 0 1 2 3

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71M6521BE

Energy Meter IC

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JANUARY 2008

In a typical application, IA and IB are connected to current transformers that sense the current on each phase of the line voltage. VA is typically connected to a voltage sensor (resistor divider).

The multiplexer control circuit handles the setting of the multiplexer. The function of the multiplexer control circuit is governed by the I/O RAM registers MUX_ALT, MUX_DIV and EQU. MUX_DIV controls the number of samples per cycle. It can request 2, 3, or 4 multiplexer states per cycle. Multiplexer states above 4 are reserved and must not be used. The multiplexer always starts at the beginning of its list and proceeds until MUX_DIV states have been converted.

The MUX_ALT bit requests an alternative multiplexer frame. The bit may be asserted on any MPU cycle and may be subsequently de-asserted on any cycle including the next one. A rising edge on MUX_ALT will cause the multiplexer control circuit to wait until the next multiplexer cycle and implement a single alternate cycle.

The multiplexer control circuit also controls the FIR filter initiation and the chopping of the ADC reference voltage, VREF. The multiplexer control circuits clocked by CK32, the 32768Hz clock from the PLL block, and launches each pass through the CE program.

A/D Converter (ADC)

A single delta-sigma A/D converter digitizes the voltage and current inputs to the 71M6521BE. The resolution of the ADC is programmable using the FIR_LEN register as shown in the I/O RAM section. ADC resolution can be selected to be 21 bits (FIR_LEN=0), or 22 bits (FIR_LEN=1). Conversion time is two cycles of CK32 with FIR_LEN = 0 and three cycles with FIR_LEN = 1.

In order to provide the maximum resolution, the ADC should be operated with FIR_LEN = 1. Accuracy and timing specifications in this data sheet are based on FIR_LEN = 1.

Initiation of each ADC conversion is controlled by the multiplexer control circuit as described previously. At the end of each ADC conversion, the FIR filter output data is stored into the CE DRAM location determined by the multiplexer selection.

FIR Filter

The finite impulse response filter is an integral part of the ADC and it is optimized for use with the multiplexer. The purpose of the FIR filter is to decimate the ADC output to the desired resolution. At the end of each ADC conversion, the output data is stored into the fixed CE DRAM location determined by the multiplexer selection. FIR data is stored LSB justified, but shifted left by nine bits.

Voltage References

The device includes an on-chip precision bandgap voltage reference that incorporates auto-zero techniques. The reference is trimmed to minimize errors caused by component mismatch and drift. The result is a voltage output with a predictable temperature coefficient.

The amplifier within the reference is chopper stabilized, i.e. the polarity can be switched by the MPU using the I/O RAM register CHOP_E (0x2002[5:4]). The two bits in the CHOP_E register enable the MPU to operate the chopper circuit in regular or inverted operation, or in “toggling” mode. When the chopper circuit is toggled in between multiplexer cycles, DC offsets on the measured signals will automatically be averaged out.

The general topology of a chopped amplifier is given in Figure 2.

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Energy Meter IC

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inp

inn

CROSS

Figure 2: General Topology of a Chopped Amplifier

It is assumed that an offset voltage Voff appears at the positive amplifier input. With all switches, as controlled by CROSS in the “A” position, the output voltage is:

Voutp – Voutn = G (Vinp + Voff – Vinn) = G (Vinp – Vinn) + G Voff

With all switches set to the “B” position by applying the inverted CROSS signal, the output voltage is:

Voutn – Voutp = G (Vinn – Vinp + Voff) = G (Vinn – Vinp) + G Voff, or

Voutp – Voutn = G (Vinp – Vinn) - G Voff

Thus, when CROSS is toggled, e.g. after each multiplexer cycle, the offset will alternately appear on the output as positive and negative, which results in the offset effectively being eliminated, regardless of its polarity or magnitude.

When CROSS is high, the hookup of the amplifier input devices is reversed. This preserves the overall polarity of that amplifier gain, it inverts its input offset. By alternately reversing the connection, the amplifier’s offset is averaged to zero. This removes the most significant long-term drift mechanism in the voltage reference. The CHOP_E bits control the behavior of CROSS. The CROSS signal will reverse the amplifier connection in the voltage reference in order to negate the effects of its offset. On the first CK32 rising edge after the last mux state of its sequence, the mux will wait one additional CK32 cycle before beginning a new frame. At the beginning of this cycle, the value of CROSS will be updated according to the CHOP_E bits. The extra CK32 cycle allows time for the chopped VREF to settle. During this cycle, MUXSYNC is held high. The leading edge of muxsync initiates a pass through the CE program sequence. The beginning of the sequence is the serial readout of the 4 RTM words.

CHOP_E has 3 states: positive, reverse, and chop. In the ‘positive’ state, CROSS is held low. In the ‘reverse’ state, CROSS is held high. In the ‘chop’ state, CROSS is toggled near the end of each Mux Frame, as described above. It is desirable that CROSS take on alternate values at the beginning of each Mux cycle. For this reason, if ‘chop’ state is selected, CROSS will not toggle at the end of the last Mux cycle in a SUM cycle.

The internal bias voltage VBIAS (typically 1.6V) is used by the ADC when measuring the temperature and battery monitor signals.

outp

outn

Temperature Sensor

The 71M6521BE includes an on-chip temperature sensor implemented as a bandgap reference. It is used to determine the die temperature The MPU may request an alternate multiplexer cycle containing the temperature sensor output by asserting MUX_ALT.

The primary use of the temperature data is to determine the magnitude of compensation required to offset the thermal drift in the system (see section titled “Temperature Compensation”).

V1.0

71M6521BE

Energy Meter IC

DATA SHEET

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Battery Monitor

The battery voltage is measured by the ADC during alternative multiplexer frames if the BME (Battery Measure Enable) bit in the I/O RAM is set. While BME is set, an on-chip 45kΩ load resistor is applied to the battery, and a scaled fraction of the battery voltage is applied to the ADC input. After each alternative MUX frame, the result of the ADC conversion is available at CE DRAM address 07. BME is ignored and assumed zero when system power is not available (V1 < VBIAS). See the Battery Monitor section of the Electrical Specifications for details regarding the ADC LSB size and the conversion accuracy.

Functional Description

The AFE functions as a data acquisition system, controlled by the MPU. The main signals (IA, VA, IB, VB) are sampled and the ADC counts obtained are stored in CE DRAM where they can be accessed by the CE and, if necessary, by the MPU. Alternate multiplexer cycles are initiated less frequently by the MPU to gather access to the slow temperature and battery signals.

VREF

VBAT

TEMP

MUX

CTRL

EQU MUX_ALT CHOP_E MUX_DIV

CROSS

CK32

VBIAS

VREF

VREF_CAL VREF_DIS

VBIAS

V3P3A

FIR_DONE

FIR_START

ΔΣ ADC

CONVERTER

ADC_E

VREF

FIR

FIR_LEN

4.9MHz

Figure 3: AFE Block Diagram

Digital Computation Engine (CE)

The CE, a dedicated 32-bit signal processor, performs the precision computations necessary to accurately measure energy. The CE calculations and processes include:

• Multiplication of each current sample with its associated voltage sample to obtain the energy per sample (when

multiplied with the constant sample time).

• Frequency-insensitive delay cancellation on all channels (to compensate for the delay between samples caused by

the multiplexing scheme).

• Pulse generation.

• Monitoring of the input signal frequency (for frequency and phase information).

• Monitoring of the input signal amplitude (for sag detection).

• Scaling of the processed samples based on calibration coefficients.

The CE program resides in flash memory. Common access to flash memory by CE and MPU is controlled by a memory share circuit. Each CE instruction word is two bytes long. Allocated flash space for the CE program cannot exceed 1024 words (2KB). The CE program counter begins a pass through the CE code each time multiplexer state 0 begins. The code pass ends when a HALT instruction is executed. For proper operation, the code pass must be completed before the multiplexer cycle ends (see System Timing Summary in the Functional Description Section).

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The CE program must begin on a 1Kbyte boundary of the flash address. The I/O RAM register CE_LCTN[4:0] defines which 1KB boundary contains the CE code. Thus, the first CE instruction is located at 1024*CE_LCTN[4:0].

The CE DRAM can be accessed by the FIR filter block, the RTM circuit, the CE, and the MPU. Assigned time slots are reserved for FIR, RTM, and MPU, respectively, to prevent bus contention for CE DRAM data access. Holding registers are used to convert 8-bit wide MPU data to/from 32-bit wide CE DRAM data, and wait states are inserted as needed, depending on the frequency of CKMPU.

The CE DRAM is 128 32-bit words. The MPU can read and write the CE DRAM as the primary means of data communication between the two processors.

Table 2 shows the CE DRAM addresses allocated to analog inputs from the AFE.

Address (HEX) Name Description

00 IA Phase A current 01 VA Phase A voltage 02 IB Phase B current 03 VB (Phase B voltage – not used) 04 - Not used 05 - Not used 06 TEMP Temperature 07 VBAT Battery Voltage

Table 2: CE DRAM Locations for ADC Results

The CE of the 71M6521BE is aided by support hardware that facilitates implementation of equations, pulse counters, and accumulators. This support hardware is controlled through I/O RAM locations EQU (equation assist), DIO_PV and DIO_PW (pulse count assist), and PRE_SAMPS and SUM_CYCLES (accumulation assist). PRE_SAMPS and SUM_CYCLES support a dual level accumulation scheme where the first accumulator accumulates results from PRE_SAMPS samples and the second accumulator accumulates up to SUM_CYCLES of the first accumulator results. The integration time for each energy output is PRE_SAMPS * SUM_CYCLES/2520.6 (with MUX_DIV = 1). CE hardware issues the XFER_BUSY interrupt when the accumulation is complete.

Meter Equations

Compute Engine (CE) firmware for residential meter configurations implements the calculations for equation 0 for a singleelement, 2-wire, 1-phase meter with neutral current sense and tamper detection. The energy for element 0 is determined by VA*IA, and the energy for element 1 is determined by VA*IB.

Real-Time Monitor

The CE contains a Real-Time Monitor (RTM), which can be programmed through the UART to monitor four selectable CE DRAM locations at full sample rate. The four monitored locations are serially output to the TMUXOUT pin via the digital output multiplexer at the beginning of each CE code pass. The RTM can be enabled and disabled with RTM_EN. The RTM output is clocked by CKTEST. Each RTM word is clocked out in 35 cycles and contains a leading flag bit. See the Functional Description section for the RTM output format. RTM is low when not in use.

Pulse Generator

The chip contains a pulse generator that creates low-jitter Wh pulses at a rate set by the CE. The I/O RAM bit DIO_PW, as described in the Digital I/O section, can be programmed to route WPULSE to the output pin

DIO6. Pulses can also be output on OPT_TX (see OPT_TXE[1:0] for details). The value of PLS_INTERVAL depends on the sample rate (nominal 2520Hz) and the number of times the pulse generator is

executed in the CE code. Changing these values would require redesign of all CE filters and/or modification of the CE pulse generator code. Since these numbers are fixed for the CE code supplied by TERIDIAN, the value of PLS_INTERVAL is also fixed, to a value of 0x81.

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On-chip hardware provides a maximum pulse width feature: PLS_MAXWIDTH[7:0] selects a maximum negative pulse width to be ‘Nmax’ updates according to the formula: Nmax = (2*PLS_MAXWIDTH+1). If PLS_MAXWIDTH = 255, no width checking is performed.

Given that PLS_INTERVAL = 81, the maximum pulse width is determined by:

Maximum Pulse Width = (2 * PLS_MAXWIDTH +1) * 81*4*203ns = 65.8µs + PLS_MAXWIDTH * 131.5µs

The CE pulse output polarity is programmable to be either positive or negative. Pulse polarity may be inverted with PLS_INV. When this bit is set, the pulses are active high, rather than the more usual active low.

CE Functional Overview

The ADC processes one sample per channel per multiplexer cycle. Figure 4 shows the timing of the samples taken during one multiplexer cycle.

The number of samples processed during one accumulation cycle is controlled by the I/O RAM registers PRE_SAMPS (0x2001[7:6]) and SUM_CYCLES (0x2001[5:0]). The integration time for each energy output is

PRE_SAMPS * SUM_CYCLES / 2520.6, where 2520.6 is the sample rate [Hz]

For example, PRE_SAMPS = 42 and SUM_CYCLES = 50 will establish 2100 samples per accumulation cycle. PRE_SAMPS = 100 and SUM_CYCLES = 21 will result in the exact same accumulation cycle of 2100 samples or 833ms. After an accumulation cycle is completed, the XFER_BUSY interrupt signals to the MPU that accumulated data are available.

1/32768Hz =

30.518µs

13/32768Hz = 397µs per mux cycle

Figure 4: Samples from Multiplexer Cycle

The end of each multiplexer cycle is signaled to the MPU by the CE_BUSY interrupt. At the end of each multiplexer cycle, status information, such as sag data and the digitized input signal, is available to the MPU.

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833ms

20ms

XFER_BUSY

Interrupt to MPU

Figure 5: Accumulation Interval

Figure 5 shows the accumulation interval resulting from PRE_SAMPS = 42 and SUM_CYCLES = 50, consisting of 2100 samples of 397µs each, followed by the XFER_BUSY interrupt. The sampling in this example is applied to a 50Hz signal.

There is no correlation between the line signal frequency and the choice of PRE_SAMPS or SUM_CYCLES (even though when SUM_CYCLES = 42 one set of SUM_CYCLES happens to sample a period of 16.6ms). Furthermore, sampling does not have to start when the line voltage crosses the zero line, and the length of the accumulation interval need not be an integer multiple of the signal cycles.

It is important to note that the length of the accumulation interval, as determined by N

PRE_SAMPS, is not an exact multiple of 1000ms. For example, if SUM_CYCLES = 60, and PRE_SAMPS = 00 (42), the

resulting accumulation interval is:

, the product of SUM_CYCLES and

ACC

32768

4260

2520

62.2520

75.999

This means that accurate time measurements should be not be based on the accumulation interval without correction.

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80515 MPU Core

The 71M6521BE includes an 80515 MPU (8-bit, 8051-compatible) that processes most instructions in one clock cycle. Using a 5MHz clock results in a processing throughput of 5 MIPS. The 80515 architecture eliminates redundant bus states and implements parallel execution of fetch and execution phases. Normally a machine cycle is aligned with a memory fetch, therefore, most of the 1-byte instructions are performed in a single cycle. This leads to an 8x performance (in average) improvement

(in terms of MIPS) over the Intel 8051 device running at the same clock frequency.

Actual processor clocking speed can be adjusted to the total processing demand of the application (metering calculations, AMR management, memory management, LCD driver management and I/O management) using the I/O RAM register MPU_DIV[2:0].

Typical measurement and metering functions based on the results provided by the internal 32-bit compute engine (CE) are available for the MPU as part of TERIDIAN’s standard library. A standard ANSI “C” 80515-application programming interface library is available to help reduce design cycle.

Memory Organization

The 80515 MPU core incorporates the Harvard architecture with separate code and data spaces.

Memory organization in the 80515 is similar to that of the industry standard 8051. There are three memory areas: Program memory (Flash), external data memory (XRAM), physically consisting of XRAM, CE DRAM, and I/O RAM, and internal data memory (Internal RAM). Table 3 shows the memory map.

Address

(hex)

0000-1FFF Flash Memory Non-volatile

on 1K

boundary 0000-07FF Static RAM Volatile MPU data XRAM, 0 2K 1000-11FF Static RAM Volatile CE data 6 512

2000-20FF Static RAM Volatile

Internal and External Data Memory: Both internal and external data memory are physically located on the 71M6521BE IC. “External” data memory is only external to the 80515 MPU core.

Program Memory: The 80515 can theoretically address up to 64KB of program memory space from 0x0000 to 0xFFFF. Program memory is read when the MPU fetches instructions or performs a MOVC operation.

After reset, the MPU starts program execution from location 0x0000. The lower part of the program memory includes reset and interrupt vectors. The interrupt vectors are spaced at 8-byte intervals, starting from 0x0003.

External Data Memory: While the 80515 is capable of addressing up to 64KB of external data memory in the space from 0x0000 to 0xFFFF, only the memory ranges shown in Error! Reference source not found. contain physical memory. The 80515 writes into external data memory when the MPU executes a MOVX @Ri,A or MOVX @DPTR,A instruction. The MPU reads external data memory by executing a MOVX A,@Ri or MOVX A,@DPTR instruction (SFR USR2 provides the upper 8 bytes for the MOVX A,@Ri instruction).

Clock Stretching: MOVX instructions can access fast or slow external RAM and external peripherals. The three low order bits of the CKCON register define the stretch memory cycles. Setting all the CKCON stretch bits to one allows access to very slow external RAM or external peripherals.

Memory

Technology

Flash Memory Non-volatile CE program 0 2K

Memory Type Typical Usage

MPU Program and non-

volatile data

Configuration RAM

I/O RAM

Table 3: Memory Map

Wait States

(at 5MHz)

0 8K

0 256

Memory Size

(bytes)

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Table 4 shows how the signals of the External Memory Interface change when stretch values are set from 0 to 7. The widths of the signals are counted in MPU clock cycles. The post-reset state of the CKCON register, which is in bold in the table, performs the MOVX instructions with a stretch value equal to 1.

CKCON register Read signals width Write signal width

CKCON.2 CKCON.1 CKCON.0

0 0 0 0 1 1 2 1

0 0 1 1 2 2 3 1

0 1 0 2 3 3 4 2

0 1 1 3 4 4 5 3

1 0 0 4 5 5 6 4

1 0 1 5 6 6 7 5

1 1 0 6 7 7 8 6

1 1 1 7 8 8 9 7

There are two types of instructions, differing in whether they provide an eight-bit or sixteen-bit indirect address to the external data RAM.

In the first type (MOVX A,@Ri), the contents of R0 or R1, in the current register bank, provide the eight lower-ordered bits of address. The eight high-ordered bits of address are specified with the USR2 SFR. This method allows the user paged access (256 pages of 256 bytes each) to all ranges of the external data RAM. In the second type of MOVX instruction (MOVX A,@DPTR), the data pointer generates a sixteen-bit address. This form is faster and more efficient when accessing very large data arrays (up to 64 Kbytes), since no additional instructions are needed to set up the eight high ordered bits of address.

It is possible to mix the two MOVX types. This provides the user with four separate data pointers, two with direct access and two with paged access to the entire 64KB of external memory range.

Dual Data Pointer: The Dual Data Pointer accelerates the block moves of data. The standard DPTR is a 16-bit register that is used to address external memory or peripherals. In the 80515 core, the standard data pointer is called DPTR, the second data pointer is called DPTR1. The data pointer select bit chooses the active pointer. The data pointer select bit is located at the LSB of the DPS register (DPS.0). DPTR is selected when DPS.0 = 0 and DPTR1 is selected when DPS.0 = 1.

The user switches between pointers by toggling the LSB of the DPS register. All DPTR-related instructions use the currently selected data pointer for any activity.

The second data pointer may not be supported by certain compilers.

Internal Data Memory: The Internal data memory provides 256 bytes (0x00 to 0xFF) of data memory. The internal data

memory address is always one byte wide and can be accessed by either direct or indirect addressing. The Special Function Registers occupy the upper 128 bytes. This SFR area is available only by direct addressing. Indirect addressing

accesses the upper 128 bytes of Internal RAM.

Stretch Value

memaddr memrd memaddr memwr

Table 4: Stretch Memory Cycle Width

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Internal Data Memory: The lower 128 bytes contain working registers and bit-addressable memory. The lower 32 bytes form

four banks of eight registers (R0-R7). Two bits on the program memory status word (PSW) select which bank is in use. The next 16 bytes form a block of bit-addressable memory space at bit addressees 0x00-0x7F. All of the bytes in the lower 128 bytes are accessible through direct or indirect addressing. Table 5 shows the internal data memory map.

Address Direct addressing Indirect addressing

0xFF

0x80

0x7F

0x30

0x2F

0x20

0x1F

0x00

Special Function Registers (SFRs)

A map of the Special Function Registers is shown in Table 6.

Special Function Registers (SFRs)

Byte-addressable area

Bit-addressable area

Table 5: Internal Data Memory Map

RAM

Bit-address-

Hex\Bin

Only a few addresses are occupied, the others are not implemented. SFRs specific to the 6521BE are shown in bold print. Any read access to unimplemented addresses will return undefined data, while any write access will have no effect. The registers at 0x80, 0x88, 0x90, etc., are bit-addressable, all others are byte-addressable.

able

X000 X001 X010 X011 X100 X101 X110 X111

INTBITS

WDI

WDCON

PSW

T2CON IRCON

IEN1

IEN0

P2 DIR2 DIR0

S0CON

P1 DIR1

TCON

IP1

IP0

S0BUF

TMOD

S0RELH S1RELH

FLSHCTL

S0RELL

IEN2 S1CON

DPS TL0 TL1

DPL DPH

Table 6: Special Function Registers Locations

Byte-addressable

S1BUF S1RELL

ERASE

TH0 TH1

DPL1 DPH1

USR2

EEDATA EECTRL

CKCON

WDTREL PCON

PGADR

Bin/Hex

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Special Function Registers (Generic 80515 SFRs)

Table 7 shows the location of the SFRs and the value they assume at reset or power-up.

Name Location Reset Value Description

P0 0x80 0xFF Port 0 SP 0x81 0x07 Stack Pointer DPL 0x82 0x00 Data Pointer Low 0 DPH 0x83 0x00 Data Pointer High 0 DPL1 0x84 0x00 Data Pointer Low 1 DPH1 0x85 0x00 Data Pointer High 1 WDTREL 0x86 0x00 Watchdog Timer Reload register PCON 0x87 0x00 UART Speed Control TCON 0x88 0x00 Timer/Counter Control TMOD 0x89 0x00 Timer Mode Control TL0 0x8A 0x00 Timer 0, low byte TL1 0x8B 0x00 Timer 1, high byte TH0 0x8C 0x00 Timer 0, low byte TH1 0x8D 0x00 Timer 1, high byte CKCON 0x8E 0x01 Clock Control (Stretch=1) P1 0x90 0xFF Port 1 DPS 0x92 0x00 Data Pointer select Register S0CON 0x98 0x00 Serial Port 0, Control Register S0BUF 0x99 0x00 Serial Port 0, Data Buffer IEN2 0x9A 0x00 Interrupt Enable Register 2 S1CON 0x9B 0x00 Serial Port 1, Control Register S1BUF 0x9C 0x00 Serial Port 1, Data Buffer S1RELL 0x9D 0x00 Serial Port 1, Reload Register, low byte P2 0xA0 0x00 Port 2 IEN0 0xA8 0x00 Interrupt Enable Register 0 IP0 0xA9 0x00 Interrupt Priority Register 0 S0RELL 0xAA 0xD9 Serial Port 0, Reload Register, low byte IEN1 0xB8 0x00 Interrupt Enable Register 1 IP1 0xB9 0x00 Interrupt Priority Register 1 S0RELH 0xBA 0x03 Serial Port 0, Reload Register, high byte S1RELH 0xBB 0x03 Serial Port 1, Reload Register, high byte USR2 0xBF 0x00 User 2 Port, high address byte for MOVX@Ri IRCON 0xC0 0x00 Interrupt Request Control Register T2CON 0xC8 0x00 Polarity for INT2 and INT3 PSW 0xD0 0x00 Program Status Word WDCON 0xD8 0x00 Baud Rate Control Register (only WDCON.7 bit used) A 0xE0 0x00 Accumulator B 0xF0 0x00 B Register

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Table 7: Special Function Registers Reset Values

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Accumulator (ACC, A): ACC is the accumulator register. Most instructions use the accumulator to hold the operand. The

mnemonics for accumulator-specific instructions refer to accumulator as “A”, not ACC.

B Register: The B register is used during multiply and divide instructions. It can also be used as a scratch-pad register to hold temporary data.

Program Status Word (PSW):

MSB LSB

CV AC F0 RS1 RS OV - P

Table 8: PSW Register Flags

Bit Symbol Function

PSW.7 CV Carry flag PSW.6 AC Auxiliary Carry flag for BCD operations PSW.5 F0 General purpose Flag 0 available for user.

F0 is not to be confused with the F0 flag in the CE STATUS register.

PSW.4 RS1

PSW.3 RS0

PSW.2 OV Overflow flag PSW.1 - User defined flag PSW.0 P Parity flag, affected by hardware to indicate odd / even number of “one” bits in the

Stack Pointer (SP): The stack pointer is a 1-byte register initialized to 0x07 after reset. This register is incremented before PUSH and CALL instructions, causing the stack to begin at location 0x08.

Data Pointer: The data pointer (DPTR) is 2 bytes wide. The lower part is DPL, and the highest is DPH. It can be loaded as two registers (e.g. MOV DPL,#data8). It is generally used to access external code or data space (e.g. MOVC A,@A+DPTR or MOVX A,@DPTR respectively).

Program Counter: The program counter (PC) is 2 bytes wide initialized to 0x0000 after reset. This register is incremented when fetching operation code or when operating on data from program memory.

RS1/RS0

00 Bank 0 (0x00 – 0x07)

01 Bank 1 (0x08 – 0x0F)

10 Bank 2 (0x10 – 0x17)

Accumulator, i.e. even parity.

11 Bank 3 (0x18 – 0x1F)

Table 9: PSW Bit Functions

Bank selected Location

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Port Registers: The I/O ports are controlled by Special Function Registers P0, P1, and P2. The contents of the SFR can be

observed on corresponding pins on the chip. Writing a ‘1’ to any of the ports (see Table 10) causes the corresponding pin to be at high level (V3P3), and writing a ‘0’ causes the corresponding pin to be held at low level (GND). The data direction registers DIR0, DIR1, and DIR2 define individual pins as input or output pins (see section Digital I/O for details).

P0 0x80 R/W Register for port 0 read and write operations (pins DIO4…DIO7) DIR0 0xA2 R/W Data direction register for port 0. Setting a bit to 1 means that the corresponding pin is

P1 0x90 R/W Register for port 1 read and write operations (pins DIO8…DIO11, DIO14…DIO15) DIR1 0x91 R/W Data direction register for port 1. P2 0xA0 R/W Register for port 2 read and write operations (pins DIO16…DIO17) DIR2 0xA1 R/W Data direction register for port 2.

All DIO ports on the chip are bi-directional. Each of them consists of a Latch (SFR ‘P0’ to ‘P2’), an output driver, and an input buffer, therefore the MPU can output or read data through any of these ports. Even if a DIO pin is configured as an output, the

SFR

Address

state of the pin can still be read by the MPU, for example when counting pulses issued via DIO pins that are under CE control.

The technique of reading the status of or generating interrupts based on DIO pins configured as outputs, can be used to implement pulse counting.

R/W Description

an output.

Table 10: Port Registers

Special Function Registers Specific to the 71M6521BE

Table 11 shows the location and description of the 71M6521BE-specific SFRs.

Name

ERASE FLSH_ERASE 0x94 W

PGADDR FLSH_PGADR 0xB7 R/W

EEDATA 0x9E R/W I EECTRL 0x9F R/W

SFR

Address

R/W Description

This register is used to initiate either the Flash Mass Erase cycle or the Flash Page Erase cycle. Specific patterns are expected for FLSH_ERASE in order to initiate the appropriate Erase cycle (default = 0x00).

0x55 – Initiate Flash Page Erase cycle. Must be preceded by a write

to FLSH_PGADR @ SFR 0xB7.

0xAA – Initiate Flash Mass Erase cycle. Must be preceded by a write

to FLSH_MEEN @ SFR 0xB2 and the debug port must be

enabled.

Any other pattern written to FLSH_ERASE will have no effect.

Flash Page Erase Address register containing the flash memory page address (page 0 thru 127) that will be erased during the Page Erase cycle (default = 0x00).

Must be re-written for each new Page Erase cycle.

C EEPROM interface data register

C EEPROM interface control register. If the MPU wishes to write a

I byte of data to EEPROM, it places the data in EEDATA and then writes the ‘Transmit’ code to EECTRL. The write to EECTRL initiates the transmit sequence. See the EEPROM Interface section for a description of the command and status bits available for EECTRL.

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FLSHCRL 0xB2

WDI 0xE8

INTBITS INT0…INT6 0xF8 R Interrupt inputs. The MPU may read these bits to see the input to

R/W

Bit 0 (FLSH_PWE): Program Write Enable: 0 – MOVX commands refer to XRAM Space, normal operation (default). 1 – MOVX @DPTR,A moves A to Program Space (Flash) @ DPTR. This bit is automatically reset after each byte written to flash. Writes to this bit are inhibited when interrupts are enabled.

Bit 1 (FLSH_MEEN): Mass Erase Enable: 0 – Mass Erase disabled (default). 1 – Mass Erase enabled. Must be re-written for each new Mass Erase cycle.

Bit 6 (SECURE): Enables security provisions that prevent external reading of flash memory and CE program RAM. This bit is reset on chip reset and may only be set. Attempts to write zero are ignored.

Bit 7 (PREBOOT): Indicates that the preboot sequence is active.

The multi-purpose register WDI contains the following bits: Bit 0 (IE_XFER): XFER Interrupt Flag:

This flag monitors the XFER_BUSY interrupt. It is set by hardware and must be cleared by the interrupt handler

Bit 1: Reserved Bit 7 (WD_RST): WD Timer Reset:

Read: Reads the PLL_FALL interrupt flag Write 0: Clears the PLL_FALL interrupt flag Write 1: Resets the watch dog timer

external interrupts INT0, INT1, up to INT6. These bits do not have any memory and are primarily intended for debug use

Only byte operations on the whole WDI register should be used when writing. The byte must have all

bits set except the bits that are to be cleared.

Table 11: Special Function Registers

Instruction Set

All instructions of the generic 8051 microcontroller are supported. A complete list of the instruction set and of the associated op-codes is contained in the 71M6521 Software User’s Guide (SUG).

UART

The 71M6521BE includes a UART (UART0) that can be programmed to communicate with a variety of AMR modules. A second UART (UART1) is connected to the optical port, as described in the optical port description.

The UART is a dedicated 2-wire serial interface, which can communicate with an external host processor at up to 38,400 bits/s ((with MPU clock = 1.2288MHz). The operation of each pin is as follows:

RX: Serial input data are applied at this pin. Conforming to RS-232 standard, the bytes are input LSB first.

TX: This pin is used to output the serial data. The bytes are output LSB first.

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The 71M6521BE has several UART-related registers for the control and buffering of serial data. All UART transfers are programmable for parity enable, parity, 2 stop bits/1 stop bit and XON/XOFF options for variable communication baud rates from 300 to 38400 bps. Table 12 shows how the baud rates are calculated. Table 13 shows the selectable UART operation modes.

SMOD

UART0

UART1

Note: S0REL and S1REL are 10-bit values derived by combining bits from the respective timer reload registers. SMOD is the SMOD bit in the

SFR PCON.

Mode 0

Mode 1

Mode 2

Mode 3

TH1 is the high byte of timer 1.

Start bit, 8 data bits, stop bit, variable baud

rate (internal baud rate generator or timer 1)

Start bit, 8 data bits, parity, stop bit, fixed

Start bit, 8 data bits, parity, stop bit, variable

baud rate (internal baud rate generator or

baud rate 1/32 or 1/64 of f

Using Timer 1 Using Internal Baud Rate Generator

N/A

-S0REL))

-S1REL))

* f

/ (384 * (256-TH1)) 2

CKMPU

N/A

Table 12: Baud Rate Generation

UART 0 UART 1

N/A

timer 1)

CKMPU

Start bit, 8 data bits, parity, stop bit, variable baud

Start bit, 8 data bits, stop bit, variable baud rate

SMOD

* f

CKMPU

rate (internal baud rate generator)

(internal baud rate generator)

CKMPU

/(32 * (2

/(64 * (2

Table 13: UART Modes

Parity of serial data is available through the P flag of the accumulator. Seven-bit serial modes with parity, such as those used by the FLAG protocol, can be simulated by setting and reading bit 7 of 8-bit output data. Seven-bit serial modes without parity can be simulated by setting bit 7 to a constant 1. 8-bit serial modes with parity can be simulated by setting and reading the 9 SFRs for transmit and RB81 (S1CON.2) for receive operations. SM20 (S0CON.5) and SM21 (S1CON.5) can be used as

handshake signals for inter-processor communication in multi-processor systems.

Serial Interface 0 Control Register (S0CON). The function of the UART0 depends on the setting of the Serial Port Control Register S0CON.

MSB LSB

SM0 SM1 SM20 REN0 TB80 RB80 TI0 RI0

Serial Interface 1 Control Register (S1CON). The function of the serial port depends on the setting of the Serial Port Control Register S1CON.

MSB LSB

SM - SM21 REN1 TB81 RB81 TI1 RI1

bit, using the control bits TB80 (S0CON.3) and TB81 (S1CON.3) in the S0CON and S1CON

Table 14: The S0CON Register

Table 15: The S1CON register

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Bit Symbol Function

S0CON.7 SM0

S0CON.6 SM1

S0CON.5 SM20 Enables the inter-processor communication feature. S0CON.4 REN0 If set, enables serial reception. Cleared by software to disable reception. S0CON.3 TB80 The 9

S0CON.2 RB80 In Modes 2 and 3 it is the 9th data bit received. In Mode 1, if SM20 is 0,

S0CON.1 TI0 Transmit interrupt flag, set by hardware after completion of a serial

S0CON.0 RI0 Receive interrupt flag, set by hardware after completion of a serial

These two bits set the UART0 mode:

Mode Description SM0 SM1

0 N/A 0 0

1 8-bit UART 0 1

2 9-bit UART 1 0

3 9-bit UART 1 1

transmitted data bit in Modes 2 and 3. Set or cleared by the MPU, depending on the function it performs (parity check, multiprocessor communication etc.)

RB80 is the stop bit. In Mode 0 this bit is not used. Must be cleared by software

transfer. Must be cleared by software.

reception. Must be cleared by software

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Table 16: The S0CON Bit Functions

Bit Symbol Function

S1CON.7 SM Sets the baud rate for UART1

0 A 9-bit UART variable

1 B 8-bit UART variable

S1CON.5 SM21 Enables the inter-processor communication feature. S1CON.4 REN1 If set, enables serial reception. Cleared by software to disable reception. S1CON.3 TB81 The 9

S1CON.2 RB81 In Modes A and B, it is the 9th data bit received. In Mode B, if SM21 is 0,

S1CON.1 TI1 Transmit interrupt flag, set by hardware after completion of a serial

S1CON.0 RI1 Receive interrupt flag, set by hardware after completion of a serial

depending on the function it performs (parity check, multiprocessor communication etc.)

RB81 is the stop bit. Must be cleared by software

transfer. Must be cleared by software.

reception. Must be cleared by software

Mode Description Baud Rate

transmitted data bit in Mode A. Set or cleared by the MPU,

Table 17: The S1CON Bit Functions

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Timers and Counters

The 80515 has two 16-bit timer/counter registers: Timer 0 and Timer 1. These registers can be configured for counter or timer operations.

In timer mode, the register is incremented every machine cycle meaning that it counts up after every 12 periods of the MPU clock signal.

In counter mode, the register is incremented when the falling edge is observed at the corresponding input signal T0 or T1 (T0 and T1 are the timer gating inputs derived from certain DIO pins, see the DIO Ports chapter). Since it takes two machine cycles to recognize a 1-to-0 event, the maximum input count rate is 1/2 of the oscillator frequency. There are no restrictions on the duty cycle, however to ensure proper recognition of 0 or 1 state, an input should be stable for at least 1 machine cycle.

The timers/counters are controlled by the TCON Register Timer/Counter Control Register (TCON)

MSB LSB

TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0

Table 18: The TCON Register

Bit Symbol Function

The Timer 1 overflow flag is set by hardware when Timer 1 overflows. This flag

TCON.7 TF1

TCON.6 TR1

TCON.5 TF0

TCON.4 TR0

TCON.3 IE1

TCON.2 IT1

TCON.1 IE0

TCON.0 IT0

can be cleared by software and is automatically cleared when an interrupt is processed.

Timer 1 Run control bit. If cleared, Timer 1 stops.

Timer 0 overflow flag set by hardware when Timer 0 overflows. This flag can be cleared by software and is automatically cleared when an interrupt is processed.

Timer 0 Run control bit. If cleared, Timer 0 stops.

Interrupt 1 edge flag is set by hardware when the falling edge on external pin int1 is observed. Cleared when an interrupt is processed.

Interrupt 1 type control bit. Selects either the falling edge or low level on input pin to cause an interrupt.

Interrupt 0 edge flag is set by hardware when the falling edge on external pin int0 is observed. Cleared when an interrupt is processed.

Interrupt 0 type control bit. Selects either the falling edge or low level on input pin to cause interrupt.

Table 19: The TCON Register Bit Functions

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Four operating modes can be selected for Timer 0 and Timer 1. Two Special Function Registers (TMOD and TCON) are used to select the appropriate mode.

Timer/Counter Mode Control register (TMOD):

MSB LSB

GATE C/T M1 M0 GATE C/T M1 M0

Timer 1 Timer 0

Table 20: The TMOD Register

Bits TR1 (TCON.6) and TR0 (TCON.4) in the TCON register (see Table 18 and Table 19) start their associated timers when set.

Bit Symbol Function

TMOD.7 TMOD.3

TMOD.6 TMOD.2

TMOD.5 TMOD.1

TMOD.4 TMOD.0

Gate If set, enables external gate control (pin int0 or int1 for Counter 0 or 1,

respectively). When int0 or int1 is high, and TRX bit is set (see TCON register), a counter is incremented every falling edge on T0 or T1 input pin

C/T Selects Timer or Counter operation. When set to 1, a Counter operation is

performed. When cleared to 0, the corresponding register will function as a Timer.

M1 Selects the mode for Timer/Counter 0 or Timer/Counter 1, as shown in TMOD

description.

M0 Selects the mode for Timer/Counter 0 or Timer/Counter 1, as shown in TMOD

description.

Table 21: TMOD Register Bit Description

M1 M0

0 0 Mode 0 13-bit Counter/Timer with 5 lower bits in the TL0 or TL1 register and the

0 1 Mode 1 16-bit Counter/Timer. 1 0 Mode 2 8-bit auto-reload Counter/Timer. The reload value is kept in TH0 or TH1,

1 1 Mode 3 If Timer 1 M1 and M0 bits are set to '1', Timer 1 stops. If Timer 0 M1 and M0

Note: In Mode 3, TL0 is affected by TR0 and gate control bits, and sets the TF0 flag on overflow, while TH0 is affected by the TR1 bit, and the TF1 flag is set on overflow.

Mode Function

remaining 8 bits in the TH0 or TH1 register (for Timer 0 and Timer 1, respectively). The 3 high order bits of TL0 and TL1 are held at zero.

while TL0 or TL1 is incremented every machine cycle. When TL(x) overflows, a value from TH(x) is copied to TL(x).

bits are set to '1', Timer 0 acts as two independent 8-bit Timer/Counters.

Table 22: Timers/Counters Mode Description

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Table 23 specifies the combinations of operation modes allowed for timer 0 and timer 1:

Mode 0 Mode 1 Mode 2

Timer 0 - mode 0

Timer 0 - mode 1

Timer 0 - mode 2

Timer/Counter Mode Control register (PCON):

MSB LSB

SMOD -- -- -- -- -- -- --

Table 24: The PCON Register

The SMOD bit in the PCON register doubles the baud rate when set.

YES YES YES

Not allowed Not allowed YES

Table 23: Timer Modes

Timer 1

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Bit Symbol Function

PCON.7 SMOD

Table 25: PCON Register Bit Description

WD Timer (Software Watchdog Timer)

The software watchdog timer is a 16-bit counter that is incremented once every 24 or 384 clock cycles. After a reset, the watchdog timer is disabled and all registers are set to zero. The watchdog consists of a 16-bit counter (WDT), a reload register (WDTREL), prescalers (by 2 and by 16), and control logic. Once the watchdog is started, it cannot be stopped unless the internal reset signal becomes active.

Note: It is recommended to use the hardware watchdog timer instead of the software watchdog timer.

WD Timer Start Procedure: The WDT is started by setting the SWDT flag. When the WDT register enters the state 0x7CFF,

an asynchronous WDTS signal will become active. The signal WDTS sets bit 6 in the IP0 register and requests a reset state. WDTS is cleared either by the reset signal or by changing the state of the WDT timer.

Refreshing the WD Timer: The watchdog timer must be refreshed regularly to prevent the reset request signal from becoming active. This requirement imposes an obligation on the programmer to issue two instructions. The first instruction sets WDT and the second instruction sets SWDT. The maximum delay allowed between setting WDT and SWDT is 12 clock cycles. If this period has expired and SWDT has not been set, the WDT is automatically reset, otherwise the watchdog timer is reloaded with the content of the WDTREL register and the WDT is automatically reset. Since the WDT requires exact timing, firmware needs to be designed with special care in order to avoid unwanted WDT resets.

TERIDIAN strongly discourages the use of the software WDT.

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Special Function Registers for the WD Timer

Interrupt Enable 0 Register (IEN0):

MSB LSB

EAL WDT ET2 ES0 ET1 EX1 ET0 EX0

Table 26: The IEN0 Register (see also Table 32)

Bit Symbol Function

IEN0.6 WDT Watchdog timer refresh flag.

Set to initiate a refresh of the watchdog timer. Must be set directly before SWDT is set to prevent an unintentional refresh of the watchdog timer. WDT is reset by hardware 12 clock cycles after it has been set.

Table 27: The IEN0 Bit Functions (see also Table 32)

Note: The remaining bits in the IEN0 register are not used for watchdog control

Interrupt Enable 1 Register (IEN1):

MSB LSB

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EXEN2 SWDT EX6 EX5 EX4 EX3 EX2

Table 28: The IEN1 Register (see also Tables 30/31)

Bit Symbol Function

IEN1.6 SWDT Watchdog timer start/refresh flag.

Set to activate/refresh the watchdog timer. When directly set after setting WDT, a watchdog timer refresh is performed. Bit SWDT is reset by the hardware 12 clock cycles after it has been set.

Table 29: The IEN1 Bit Functions (see also Tables 31/32)

Note: The remaining bits in the IEN1 register are not used for watchdog control

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Interrupt Priority 0 Register (IP0):

MSB LSB

-- WDTS IP0.5 IP0.4 IP0.3 IP0.2 IP0.1 IP0.0

Table 30: The IP0 Register (see also Table 45)

Bit Symbol Function

IP0.6 WDTS Watchdog timer status flag. Set when the watchdog timer was started. Can be

read by software.

Table 31: The IP0 bit Functions (see also Table 45)

Note: The remaining bits in the IP0 register are not used for watchdog control

Watchdog Timer Reload Register (WDTREL):

MSB LSB

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7 6 5 4 3 2 1 0

Table 32: The WDTREL Register

Bit Symbol Function

WDTREL.7

WDTREL.6

WDTREL.0

The WDTREL register can be loaded and read at any time.

6-0

Prescaler select bit. When set, the watchdog is clocked through an additional divide-by-16 prescaler

Seven bit reload value for the high-byte of the watchdog timer. This value is loaded to the WDT when a refresh is triggered by a consecutive setting of bits WDT and SWDT.

Table 33: The WDTREL Bit Functions

Interrupts

The 80515 provides 11 interrupt sources with four priority levels. Each source has its own request flag(s) located in a special function register (TCON, IRCON, and SCON). disabled by the enable bits in SFRs IEN0, IEN1, and IEN2.

External interrupts are the interrupts external to the 80515 core, i.e. signals that originate in other parts of the

71M6521BE, for example the CE, DIO, EEPROM interface.

Interrupt Overview

When an interrupt occurs, the MPU will vector to the predetermined address as shown in Table 52. Once interrupt service has begun, it can be interrupted only by a higher priority interrupt. The interrupt service is terminated by a return from instruction, "RETI". When an RETI is performed, the processor will return to the instruction that would have been next when the interrupt occurred.

Each interrupt requested by the corresponding flag can be individually enabled or

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When an interrupt occurs, the MPU will vector to the predetermined address as shown in Table 52. Once interrupt service has begun, it can be interrupted only by a higher priority interrupt. The interrupt service is terminated by a return from instruction, "RETI". When a RETI instruction is performed, the processor will return to the instruction that would have been next when the interrupt occurred.

When the interrupt condition occurs, the processor will also indicate this by setting a flag bit. This bit is set regardless of whether the interrupt is enabled or disabled. Each interrupt flag is sampled once per machine cycle, then samples are polled by the hardware. If the sample indicates a pending interrupt when the interrupt is enabled, then the interrupt request flag is set. On the next instruction cycle, the interrupt will be acknowledged by hardware forcing an LCALL to the appropriate vector address, if the following conditions are met:

• No interrupt of equal or higher priority is already in progress.

• An instruction is currently being executed and is not completed.

• The instruction in progress is not RETI or any write access to the registers IEN0, IEN1, IEN2, IP0 or IP1.

Special Function Registers for Interrupts: Interrupt Enable 0 register (IE0)

MSB LSB

EAL WDT ES0 ET1 EX1 ET0 EX0

Table 34: The IEN0 Register

Bit Symbol Function

IEN0.7 EAL EAL=0 – disable all interrupts IEN0.6 WDT Not used for interrupt control IEN0.5 - IEN0.4 ES0 ES0=0 – disable serial channel 0 interrupt IEN0.3 ET1 ET1=0 – disable timer 1 overflow interrupt IEN0.2 EX1 EX1=0 – disable external interrupt 1 IEN0.1 ET0 ET0=0 – disable timer 0 overflow interrupt IEN0.0 EX0 EX0=0 – disable external interrupt 0

Table 35: The IEN0 Bit Functions

Interrupt Enable 1 Register (IEN1)

MSB LSB

SWDT EX6 EX5 EX4 EX3 EX2

Table 36: The IEN1 Register

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TERIDIAN Semiconductor 71M6521BE Technical data

Specifications and Main Features

Frequently Asked Questions

User Manual

GENERAL DESCRIPTION

FEATURES

HARDWARE DESCRIPTION

Hardware Overview

Analog Front End (AFE)

Input Multiplexer

A/D Converter (ADC)

FIR Filter

Voltage References

Temperature Sensor

Battery Monitor

Functional Description

Digital Computation Engine (CE)

Meter Equations

Real-Time Monitor

Pulse Generator

CE Functional Overview

80515 MPU Core

Memory Organization

Special Function Registers (SFRs)

Special Function Registers (Generic 80515 SFRs)

Special Function Registers Specific to the 71M6521BE

Instruction Set

UART

Timers and Counters

WD Timer (Software Watchdog Timer)

Interrupts

Interrupt Overview