Telit ML865G1 User Manual

Download

Page 1

Mod. 08

ML865G1

HW User Guide

1VV0301632 Rev. 4 – 2020-09-23

1.2017]

05 2017-01 Rev.6

Page 2

ML865G1 HW Design Guide

SPECIFICATIONS ARE SUBJECT TO CHANGE WITHOUT NOTICE

NOTICE

While reasonable efforts have been made to assure the accuracy of this document, Telit assumes no liability resulting from any inaccuracies or omissions in this document, or from use of the information obtained herein. The information in this document has been carefully checked and is believed to be reliable. However, no responsibility is assumed for inaccuracies or omissions. Telit reserves the right to make changes to any products described herein and reserves the right to revise this document and to make changes from time to time in content hereof with no obligation to notify any person of revisions or changes. Telit does not assume any liability arising out of the application or use of any product, software, or circuit described herein; neither does it convey license under its patent rights or the rights of others.

It is possible that this publication may contain references to, or information about Telit products (machines and programs), programming, or services that are not announced in your country. Such references or information must not be construed to mean that Telit intends to announce such Telit products, programming, or services in your country.

COPYRIGHTS

This instruction manual and the Telit products described in this instruction manual may be, include or describe copyrighted Telit material, such as computer programs stored in semiconductor memories or other media. Laws in the Italy and other countries preserve for Telit and its licensors certain exclusive rights for copyrighted material, including the exclusive right to copy, reproduce in any form, distribute and make derivative works of the copyrighted material. Accordingly, any copyrighted material of Telit and its licensors contained herein or in the Telit products described in this instruction manual may not be copied, reproduced, distributed, merged or modified in any manner without the express written permission of Telit. Furthermore, the purchase of Telit products shall not be deemed to grant either directly or by implication, estoppel, or otherwise, any license under the copyrights, patents or patent applications of Telit, as arises by operation of law in the sale of a product.

COMPUTER SOFTWARE COPYRIGHTS

The Telit and 3rd Party supplied Software (SW) products described in this instruction manual may include copyrighted Telit and other 3rd Party supplied computer programs stored in semiconductor memories or other media. Laws in the Italy and other countries preserve for Telit and other 3rd Party supplied SW certain exclusive rights for copyrighted computer programs, including the exclusive right to copy or reproduce in any form the copyrighted computer program. Accordingly, any copyrighted Telit or other 3rd Party supplied SW computer programs contained in the Telit products described in this instruction manual may not be copied (reverse engineered) or reproduced in any manner without the express written permission of Telit or the 3rd Party SW supplier. Furthermore, the purchase of Telit products shall not be deemed to grant either directly or by implication, estoppel, or otherwise, any license under the copyrights, patents or patent applications of Telit or other 3rd Party supplied SW, except for the normal non-exclusive, royalty free license to use that arises by operation of law in the sale of a product.

1VV0301632 Rev. 4 Page 2 of 86 2020-09-23

Page 3

ML865G1 HW Design Guide

USAGE AND DISCLOSURE RESTRICTIONS

I. License Agreements

The software described in this document is the property of Telit and its licensors. It is furnished by express license agreement only and may be used only in accordance with the terms of such an agreement.

II. Copyrighted Materials

Software and documentation are copyrighted materials. Making unauthorized copies is prohibited by law. No part of the software or documentation may be reproduced, transmitted, transcribed, stored in a retrieval system, or translated into any language or computer language, in any form or by any means, without prior written permission of Telit

III. High Risk Materials

Components, units, or third-party products used in the product described herein are NOT fault-tolerant and are NOT designed, manufactured, or intended for use as on-line control equipment in the following hazardous environments requiring fail-safe controls: the operation of Nuclear Facilities, Aircraft Navigation or Aircraft Communication Systems, Air Traffic Control, Life Support, or Weapons Systems (High Risk Activities"). Telit and its supplier(s) specifically disclaim any expressed or implied warranty of fitness for such High Risk Activities.

IV. Trademarks

TELIT and the Stylized T Logo are registered in Trademark Office. All other product or service names are the property of their respective owners.

V. Third Party Rights

The software may include Third Party Right software. In this case you agree to comply with all terms and conditions imposed on you in respect of such separate software. In addition to Third Party Terms, the disclaimer of warranty and limitation of liability provisions in this License shall apply to the Third Party Right software.

TELIT HEREBY DISCLAIMS ANY AND ALL WARRANTIES EXPRESS OR IMPLIED FROM ANY THIRD PARTIES REGARDING ANY SEPARATE FILES, ANY THIRD PARTY MATERIALS INCLUDED IN THE SOFTWARE, ANY THIRD PARTY MATERIALS FROM WHICH THE SOFTWARE IS DERIVED (COLLECTIVELY “OTHER CODE”), AND THE USE OF ANY OR ALL THE OTHER CODE IN CONNECTION WITH THE SOFTWARE, INCLUDING (WITHOUT LIMITATION) ANY WARRANTIES OF SATISFACTORY QUALITY OR FITNESS FOR A PARTICULAR PURPOSE.

NO THIRD PARTY LICENSORS OF OTHER CODE SHALL HAVE ANY LIABILITY FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING WITHOUT LIMITATION LOST PROFITS), HOWEVER CAUSED AND WHETHER MADE UNDER CONTRACT, TORT OR OTHER LEGAL THEORY, ARISING IN ANY WAY OUT OF THE USE OR DISTRIBUTION OF THE OTHER CODE OR THE EXERCISE OF ANY RIGHTS GRANTED UNDER EITHER OR BOTH THIS LICENSE AND THE LEGAL TERMS APPLICABLE TO ANY SEPARATE FILES, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.

1VV0301632 Rev. 4 Page 3 of 86 2020-09-23

Page 4

ML865G1 HW Design Guide

ML865G1-WW

APPLICABILITY TABLE

PRODUCTS

1VV0301632 Rev. 4 Page 4 of 86 2020-09-23

Page 5

ML865G1 HW Design Guide

NOTICE 2

COPYRIGHTS .................................................................................................. 2

COMPUTER SOFTWARE COPYRIGHTS ....................................................... 2

USAGE AND DISCLOSURE RESTRICTIONS ................................................ 3

I. License Agreements ....................................................................... 3

II. Copyrighted Materials .................................................................... 3

III. High Risk Materials ........................................................................ 3

IV. Trademarks .................................................................................... 3

V. Third Party Rights ........................................................................... 3

APPLICABILITY TABLE .................................................................................. 4

CONTENTS ...................................................................................................... 5

1. INTRODUCTION ............................................................................ 9

Scope ............................................................................................. 9

Audience ........................................................................................ 9

Contact Information, Support ......................................................... 9

Text Conventions ......................................................................... 10

Related Documents ...................................................................... 11

2. GENERAL PRODUCT DESCRIPTION ........................................ 12

Overview ...................................................................................... 12

Product Variants and Frequency Bands ....................................... 12

Target Market ............................................................................... 13

Main features ................................................................................ 13

TX Output Power .......................................................................... 14

RX Sensitivity ............................................................................... 15

2.6.1. ML865G1-WW .............................................................................. 15

Mechanical Specifications ............................................................ 17

2.7.1. Dimensions ................................................................................... 17

2.7.2. Weight .......................................................................................... 17

Temperature Range ..................................................................... 17

3. PINS ALLOCATION .................................................................... 18

Pin-out .......................................................................................... 18

1VV0301632 Rev. 4 Page 5 of 86 2020-09-23

Page 6

ML865G1 HW Design Guide

Pin Layout .................................................................................... 23

4. POWER SUPPLY ........................................................................ 24

Power Supply Requirements ........................................................ 24

Power Consumption ..................................................................... 25

4.2.1. Idle mode ...................................................................................... 25

4.2.2. ML865G1-WW Connected Mode ................................................. 27

General Design Rules .................................................................. 28

4.3.1. Electrical Design Guidelines ......................................................... 28

4.3.1.1. +5V Source Power Supply Design Guidelines ............................. 28

4.3.1.2. +12V Source Power Supply Design Guidelines ........................... 29

4.3.1.3. Battery Source Power Supply Design Guidelines ........................ 29

4.3.2. Thermal Design Guidelines .......................................................... 30

4.3.3. Power Supply PCB layout Guidelines .......................................... 31

RTC supply ................................................................................... 32

VAUX Power Output ..................................................................... 32

5. DIGITAL SECTION ...................................................................... 34

Logic Levels ................................................................................. 34

Power On ..................................................................................... 35

Auto Power On ............................................................................. 38

Power Off ..................................................................................... 38

Unconditional Shutdown ............................................................... 40

Wake from deep sleep mode ....................................................... 43

Fast power down .......................................................................... 43

5.7.1. Fast Shut Down by Hardware....................................................... 44

5.7.2. Fast Shut Down by Software ........................................................ 45

Communication ports ................................................................... 45

5.8.1. USB 2.0 HS .................................................................................. 45

5.8.2. SPI ................................................................................................ 47

5.8.3. SPI Connections ........................................................................... 48

5.8.4. Serial Ports ................................................................................... 48

5.8.4.1. Modem serial port 1 (USIF0) ........................................................ 48

5.8.4.2. Modem serial port 2 (USIF1) ........................................................ 50

5.8.4.3. RS232 level translation ................................................................ 51

General purpose I/O ..................................................................... 52

5.9.1. Using a GPIO as INPUT ............................................................... 53

5.9.2. Using a GPIO as OUTPUT ........................................................... 54

5.9.3. Indication of network service availability....................................... 54

1VV0301632 Rev. 4 Page 6 of 86 2020-09-23

Page 7

ML865G1 HW Design Guide

External SIM Holder ..................................................................... 55

ADC Converter ............................................................................. 55

5.11.1. Using ADC Converter ................................................................... 56

Forced USB boot .......................................................................... 56

6. RF SECTION ................................................................................ 57

Bands Variants ............................................................................. 57

TX Output power .......................................................................... 57

RX Sensitivity ............................................................................... 57

Antenna requirements .................................................................. 57

6.4.1. PCB Design guidelines ................................................................. 58

6.4.2. PCB Guidelines in case of FCC Certification ............................... 60

6.4.2.1. Transmission line design .............................................................. 60

6.4.2.2. Transmission Line Measurements................................................ 62

6.4.2.3. Antenna Installation Guidelines .................................................... 64

7. AUDIO SECTION ......................................................................... 65

Electrical Characteristics .............................................................. 65

Codec examples ........................................................................... 65

8. GNSS SECTION .......................................................................... 66

GNSS Signals Pin-out .................................................................. 66

RF Front End Design .................................................................... 66

8.2.1. Guidelines of PCB line for GNSS Antenna ................................... 66

8.2.2. Hardware-based solution for GNSS and LTE coexistence ........... 67

GNSS Antenna Requirements ..................................................... 67

8.3.1. GNSS Antenna specification ........................................................ 67

8.3.2. GNSS Antenna – Installation Guidelines ...................................... 68

8.3.3. Powering the External LNA (active antenna) ................................ 68

GNSS Characteristics .................................................................. 69

9. MECHANICAL DESIGN............................................................... 70

Drawing ........................................................................................ 70

10. APPLICATION PCB DESIGN ...................................................... 71

General ......................................................................................... 71

Footprint ....................................................................................... 71

PCB pad design ........................................................................... 73

PCB pad dimensions .................................................................... 73

Stencil ........................................................................................... 74

Solder paste ................................................................................. 75

1VV0301632 Rev. 4 Page 7 of 86 2020-09-23

Page 8

ML865G1 HW Design Guide

Solder Reflow ............................................................................... 75

11. PACKAGING ............................................................................... 77

Tray .............................................................................................. 77

Reel .............................................................................................. 79

Moisture sensitivity ....................................................................... 79

12. CONFORMITY ASSESSMENT ISSUES ..................................... 81

ANATEL Regulatory Notices ........................................................ 81

13. SAFETY RECOMMENDATIONS ................................................. 82

READ CAREFULLY ..................................................................... 82

14. ACRONYMS ................................................................................ 83

15. DOCUMENT HISTORY ................................................................ 85

1VV0301632 Rev. 4 Page 8 of 86 2020-09-23

Page 9

ML865G1 HW Design Guide

1. INTRODUCTION

Scope

Scope of this document is is the description of some hardware solutions useful for developing a product with the Telit ML865G1 module.

Audience

This document is intended for Telit customers, who are integrators, about to implement their application using our ML865G1 module.

Contact Information, Support

For general contact, technical support services, technical questions and report documentation errors contact Telit Technical Support at:

• TS-EMEA@telit.com

• TS-AMERICAS@telit.com

• TS-APAC@telit.com

• TS-SRD@telit.com

Alternatively, use:

http://www.telit.com/support

For detailed information about where you can buy the Telit modules or for recommendations on accessories and components visit:

http://www.telit.com

Our aim is to make this guide as helpful as possible. Keep us informed of your comments and suggestions for improvements.

Telit appreciates feedback from the users of our information.

1VV0301632 Rev. 4 Page 9 of 86 2020-09-23

Page 10

ML865G1 HW Design Guide

This information MUST be followed or catastrophic

Alerts the user to important points about

Text Conventions

Danger – equipment failure or bodily injury may occur.

Caution or Warning – integrating the module, if these points are not followed, the module and end user equipment may fail or malfunction.

Tip or Information – Provides advice and suggestions that may be useful when integrating the module.

All dates are in ISO 8601 format, i.e. YYYY-MM-DD.

1VV0301632 Rev. 4 Page 10 of 86 2020-09-23

Page 11

ML865G1 HW Design Guide

2. GENERAL PRODUCT DESCRIPTION

Overview

The ML865G1 module is a CATM / NBIoT / 2G communication product which allows integrators to plan on availability for even the longest lifecycle applications, highly recommended for new designs specified for coverage worldwide.

The ML865G1 operates with 1.8 V GPIOs, minimizing power consumption and making it even more ideally suited for battery powered and wearable device applications.

Product Variants and Frequency Bands

Product 2G Band (MHz) LTE CATM1 NBIoT Region

ML865G1-WW 850, 900, 1800,

1900

Refer to “RF Section” for details information about frequencies.

NOTE:

B1, B2, B3, B4, B5, B8, B12, B13, B18, B19, B20, B25, B26, B27, B28, B66, B85

B1, B2, B3, B4, B5, B8, B12, B13, B18, B19, B20, B25, B26, B28, B66, B71, B85

Cellular technologies and frequency bands that are enabled may vary based on firmware version and firmware configuration used.

Worldwide

1VV0301632 Rev. 4 Page 12 of 86 2020-09-23

Page 13

ML865G1 HW Design Guide

Target Market

ML865G1 can be used for telematics applications where tamper-resistance, confidentiality, integrity, and authenticity of end-user information are required, for example:

• Telematics services

• Road pricing

• Pay-as-you-drive insurance

• Stolen vehicles tracking

• Internet connectivity

Main features

Function Features

Modem

Interfaces

• CATM, NBIoT, 2G technologies

• SMS support (text and PDU)

• Alarm management

• Real Time Clock

• Main UART for AT command access

• AUX UART used for diagnostic monitoring and

debugging

• USB

• SPI

• 8 GPIOs

• Antenna port

1VV0301632 Rev. 4 Page 13 of 86 2020-09-23

Page 14

ML865G1 HW Design Guide

TX Output Power

ML865G1-WW

Band Mode Class

850/900MHz

1800/1900MHz

B1, B2, B3, B4, B5, B8, B12,

B13, B18, B19, B20, B25, B26,

B27, B28, B66, B85

B1, B2, B3, B4, B5, B8, B12,

B13, B18, B19, B20, B25, B26,

B28, B66, B85

B71

RF power (dBm)

GPRS 4 32.5

EGPRS E2 27

GPRS 1 29.5

EGPRS E2 26

(LTE) CAT-

NB2

(LTE) CAT-

NB2

3 23

5 20

1VV0301632 Rev. 4 Page 14 of 86 2020-09-23

Page 15

ML865G1 HW Design Guide

RX Sensitivity

2.6.1. ML865G1-WW

REFsens (dBm)

3GPP REFsens (dBm)*

Band

Typical

CATM1 / Band1 -106.2 -102.7

CAT M1 / Band2 -107.4 -100.3

CAT M1 / Band3 -106.1 -99.3

CAT M1 / Band4 -107.1 -102.3

CAT M1 / Band5 -106.4 -100.8

CAT M1 / Band8 -105.9 -99.8

CAT M1 / Band12 -103.7 -99.3

CAT M1 / Band13 -107.0 -99.3

CAT M1 / Band18 -107.1 -102.3

CAT M1 / Band19 -105.5 -102.3

CAT M1 / Band20 -106.1 -99.8

CAT M1 / Band25 -107.2 -

CAT M1 / Band26 -106.6 -100.3

CAT M1 / Band27 -107.2 -100.8

CAT M1 / Band28 -106.4 -100.8

1VV0301632 Rev. 4 Page 15 of 86 2020-09-23

Page 16

ML865G1 HW Design Guide

CAT M1 / Band66 -106.8 -

CAT M1 / Band85 -102.2 -

CAT NB2 / Band1 -116.2 -108.2

CAT NB2 / Band2 -116.4 -108.2

CAT NB2 / Band3 -116.2 -108.2

CAT NB2 / Band4 -116.0 -

CAT NB2 / Band5 -116.0 -108.2

CAT NB2 / Band8 -110.6 -108.2

CAT NB2 / Band12 -115.5 -108.2

CAT NB2 / Band13 -115.9 -108.2

CAT NB2 / Band18 -116.1 -108.2

CAT NB2 / Band19 -115.7 -108.2

CAT NB2 / Band20 -115.4 -108.2

CAT NB2 / Band25 -116.4 -

CAT NB2 / Band26 -115.9 -108.2

CAT NB2 / Band28 -115.9 -108.2

CAT NB2 / Band66 -116.4 -108.2

CAT NB2 / Band71 -104.7 -

1VV0301632 Rev. 4 Page 16 of 86 2020-09-23

Page 17

ML865G1 HW Design Guide

CAT NB2 / Band85 -115.9 -

* 3GPP TS 36.521-1 Release 15

Mechanical Specifications

2.7.1. Dimensions

The overall dimensions of ML865G1-WW are:

• Length: 24.0 mm

• Width: 24.0 mm

• Thickness: 2.6 mm

2.7.2. Weight

The nominal weight of the ML865G1-WW is 2 grams.

Temperature Range

Operating Temperature

Range

Storage Temperature

Range

(*) Functional: if applicable, the module is able to make and receive voice calls, data calls, send and receive SMS and data traffic.

–40°C to +85°C

–40°C to +105°C

The module is fully functional (*) and

compliant according to regulatory

The module is not powered and not

connected to power supply

Note

standards.

1VV0301632 Rev. 4 Page 17 of 86 2020-09-23

Page 18

ML865G1 HW Design Guide

The numbering of the pins has been changed accordingly and

3. PINS ALLOCATION

Warning: ML865G1 is adopting a modified 56-pin xL865 Form Factor, pin to pin compatible with the previous 48-pin xL865 FF and with 8 additional pads.

attention has to be paid when comparing with previous 48-pin xL865 FF design.

Pin-out

Pin Signal I/

Function Type Comment

USB HS 2.0 COMMUNICATION PORT

20 USB_D+ I/O USB differential Data

(+)

19 USB_D- I/O USB differential Data

(-)

18 VUSB I Power sense for the

internal USB

transceiver.

Asynchronous Serial Port (USIF0) - Prog. / Data + HW Flow Control

1 C109/DCD O Output for Data carrier

detect signal (DCD) to

DTE

3-5V Internal PD

CMOS

1.8V

(100K)

2 C125/RING O Output for Ring

indicator signal (RI) to

DTE

1VV0301632 Rev. 4 Page 18 of 86 2020-09-23

CMOS

1.8V

Page 19

ML865G1 HW Design Guide

3 C107/DSR O

Output for Data set

ready signal (DSR) to

DTE

4 C108/DTR I Input for Data terminal

ready signal (DTR)

from DTE

5 C105/RTS I

Input for Request to

send signal (RTS)

from DTE

6 C106/CTS O Output for Clear to

send signal (CTS) to

DTE

9 C103/TXD I Serial data input

(TXD) from DTE

10 C104/RXD O Serial data output to

DTE

CMOS

1.8V

CMOS

1.8V

CMOS

1.8V

CMOS

1.8V

CMOS

1.8V

CMOS

1.8V

SIM card interface

11 SIMVCC -

External SIM signal –

Power supply for the

SIM

12 SIMRST O External SIM signal –

Reset

13 SIMCLK O

External SIM signal –

Clock

14 SIMIO I/O External SIM signal –

Data I/O

ADC

15 ADC_IN1 I

Analog/Digital

converter input

1.8V

1.8V Internal pull-up 20K

Auxiliary (USIF1)

1VV0301632 Rev. 4 Page 19 of 86 2020-09-23

Page 20

ML865G1 HW Design Guide

52 RXD_AUX /SPI_MISO I/O

Auxiliary UART (RX Data)/SPI_MISO

53 TXD_AUX / SPI_MOSI I/O Auxiliary UART (TX

Data)/SPI_MOSI

CMOS

1.8V

CMOS

1.8V

Miscellaneous

7 ON_OFF/WAKE I Input Command for

1.8V Active Power ON/OFF and to wake from deep sleep mode (PSM)

55 HW_SHUTDOWN* I UNCONDITIONAL

VBATT

SHUTDOWN

51 V_AUX/PWRMON O 1.8V

56 FORCED_USB_BOOT I CMOS

1.8V

High

40 ANTENNA I/O Antenna pad – 50 Ω RF

37 GNSS_ANT I GNSS receiver input -

50 Ω

GPIO

48 GPIO_01 / DVI_WA0 I/O GPIO01 Configurable

GPIO / Digital Audio

CMOS

1.8V

Interface (WA0)

47 GPIO_02 /DVI_RX I/O GPIO02 I/O pin

Digital Audio Interface

CMOS

1.8V

(RX)

46 GPIO_03 / DVI_TX I/O GPIO03 GPIO I/O pin/

Digital Audio Interface

CMOS

1.8V

(TX)

45 GPIO_04 / DVI_CLK I/O

GPIO04 Configurable GPIO/ Digital Audio

CMOS

1.8V

Interface (CLK)

1VV0301632 Rev. 4 Page 20 of 86 2020-09-23

Page 21

ML865G1 HW Design Guide

GPIO_05/ GNSS_LNA_EN

32 GPIO_06 / SPI_CS I/O GPIO06 Configurable

31 GPIO_07 I/O GPIO07 Configurable

30 GPIO_08 I/O

GPIO05 Configurable

I/O

GPIO

GPIO /SPI_CS

GPIO

GPIO08 Configurable GPIO

CMOS

1.8V

CMOS

1.8V

CMOS

1.8V

CMOS

1.8V

29 SPI_CLK I/O SPI_CLK CMOS

1.8V

Power Supply

44 VBATT - Main power supply

Power

(Baseband)

STAT_LED

alternate

function

43 VBATT_PA - Main power supply

Power

(Radio PA)

42 GND - Ground Power

41 GND - Ground Power

39 GND - Ground Power

38 GND - Ground Power

35 GND - Ground Power

27 GND - Ground Power

23 GND - Ground Power

21 GND - Ground Power

54 GND - Ground Power

1VV0301632 Rev. 4 Page 21 of 86 2020-09-23

Page 22

ML865G1 HW Design Guide

Reserved

8 RFU

16 RFU

17 RFU

22 RFU

24 RFU

25 RFU

26 RFU

28 RFU

34 RFU

36 RFU

49 RFU

50 RFU

1VV0301632 Rev. 4 Page 22 of 86 2020-09-23

Page 23

ML865G1 HW Design Guide

Pin Layout

TOP VIEW

The pins defined as NC/RFU shall be considered RESERVED and must not be connected to any pin in the application.

1VV0301632 Rev. 4 Page 23 of 86 2020-09-23

Page 24

ML865G1 HW Design Guide

Value

having an excessive voltage drop. If the voltage drop is

4. POWER SUPPLY

The power supply circuitry and board layout are a very important part in the full product design and they strongly reflect on the product overall performance, hence read the requirements carefully and the guidelines that will follow for a proper design.

Power Supply Requirements

The external power supply must be connected to VBATT & VBATT_PA signals and must fulfill the following requirements:

Power Supply

Nominal Supply Voltage 3.8V

Operating Voltage Range 3.20 V - 4.20 V

Extended Voltange Range 2.60 V - 4.50 V

VBATT

min

CAUTION:

The range 2.60V - 3.20V can be used only if both USB and 2G are disabled.

NOTE:

The Operating Voltage Range MUST never be exceeded; care must be taken when designing the application’s power supply section to avoid exceeding the limits it could cause a Power Off of the module.

2.7V

The voltage must be at least VBATT

to power on the module.

min

Overshoot voltage (regarding MAX Extended Operating Voltage) and drop in voltage (regarding MIN Extended Operating Voltage) MUST never be exceeded.

1VV0301632 Rev. 4 Page 24 of 86 2020-09-23

Page 25

ML865G1 HW Design Guide

Measure (Typical)

Mode

Description

IDLE MODE

CATM

(mA)

NBIoT

(mA)

NOTE:

For PTCRB approval on the final products the power supply is

required to be within the “Normal Operating Voltage Range”.

Power Consumption

4.2.1. Idle mode

Mode

AT+CFUN=1 9.5 9.2 9.0

AT+CFUN=4 7.5

1.20 0.95 -

0.60 0.60 -

0.181 0.181 -

AT+CFUN=5

0.101 0.101 -

Normal mode: full functionality of the module

Disabled TX and RX; module is not registered on the network

Paging cycle #256 frames (2.56s DRx cycle)

81.92s eDRx cycle length (PTW=2.56s, DRX=1.28s)

327.68s eDRx cycle length (PTW=2.56s, DRX=1.28s)

655.36s eDRx cycle length (PTW=2.56s, DRX=1.28s)

0.051 0.051 -

0.031 0.031 -

- - 0.90 Paging Multiframe 9

1VV0301632 Rev. 4 Page 25 of 86 2020-09-23

1310.72s eDRx cycle length (PTW=2.56s, DRX=1.28s)

2621.44s eDRx cycle length (PTW=2.56s, DRX=1.28s)

Page 26

ML865G1 HW Design Guide

PSM MODE

Measure*

(Typical)

GPS (mA)

Typical (mA)

AT+CPS

MS=1

PSM in between eDRX

Mode

Active State

(GNSS ON,

CFUN=4)

3uA

No current source or sink by any connected

Mode Description

Acquisition 69.3 GPS+GLO, DPO off

22 GPS+GLO, DPO on DWELL=280ms

Navigation

55.9 GPS+GLO, DPO off

Acquisition 68.5 GPS+GLO, DPO off

Active State

(GNSS ON,

CFUN=5 eDRX)

Navigation

15.7 GPS+GLO, DPO on DWELL=280ms

54 GPS+GLO, DPO off

*reference signal @-130 dbm with static scenario

NOTE:

The reported LTE CAT M1 and LTE CAT NB1 values are an average

among all the product variants and bands for each network wireless

technology.

The support of specific network wireless technology depends on

product variant configuration.

1VV0301632 Rev. 4 Page 26 of 86 2020-09-23

Page 27

ML865G1 HW Design Guide

Measure (Typical)

Mode

Description

CONNECTED MODE

Average

(mA)

Peak (mA)

4.2.2. ML865G1-WW Connected Mode

CATM

380 1100

320 900

305 800

240 335

600 1000

500 850

430 750

1 RB, RMC, TBS=5, QPSK, 23dBm,

Band 85, 28, 12

1 RB, RMC, TBS=5, QPSK,23dBm,

Band 13, 26, 5, 18, 19, 20, 8

1 RB, RMC, TBS=5, QPSK, 23dBm,

Band 3, 2, 25, 4, 1, 66

3.75KHz, 1 SC, RU 32ms, TBS=0, BPSK, 20dBm, Band 71

3.75KHz, 1 SC, RU 32ms, TBS=0, BPSK, 23dBm, Band 85, 28, 12

3.75KHz, 1 SC, RU 32ms, TBS=0, BPSK, 23dBm, Band 13, 26, 5, 18, 19, 20, 8

3.75KHz, 1 SC, RU 32ms, TBS=0, BPSK, 23dBm, Band 3, 2, 25, 4, 1, 66

NBIoT

68 300

88 950

78 800

77 730

300 2000 1TX + 1RX, CS1, GMSK, Band 850, 900

GPRS

170 1000 1TX + 1RX, CS1, GMSK, Band 1800, 1900

15KHz, 12 SC, RU 1ms, TBS=5, QPSK,

21dBm, Band 71

15KHz, 12 SC, RU 1ms, TBS=5, QPSK,

23dBm, Band 85, 28, 12

15KHz, 12 SC, RU 1ms, TBS=5, QPSK,

23dBm, Band 13, 26, 5, 18, 19, 20, 8

15KHz, 12 SC, RU 1ms, TBS=5, QPSK,

23dBm, Band 3, 2, 25, 4, 1, 66

1VV0301632 Rev. 4 Page 27 of 86 2020-09-23

Page 28

ML865G1 HW Design Guide

General Design Rules

The principal guidelines for the Power Supply Design embrace three different design steps:

• the electrical design

• the thermal design

• the PCB layout

4.3.1. Electrical Design Guidelines

The electrical design of the power supply depends strongly from the power source where this power is drained. We will distinguish them into three categories:

• +5V input (typically PC internal regulator output)

• +12V input (typically automotive)

• Battery

4.3.1.1. +5V Source Power Supply Design Guidelines

• The desired output for the power supply is 3.8V, hence there's not a big difference

between the input source and the desired output and a linear regulator can be used. A switching power supply will not be suited because of the low drop out requirements.

• When using a linear regulator, a proper heat sink shall be provided in order to

dissipate the power generated.

• A Bypass low ESR capacitor of adequate capacity must be provided in order to cut

the current absorption peaks close to the Module, a 100μF capacitor is usually

suited.

• Make sure the low ESR capacitor on the power supply output rated at least 10V.

An example of linear regulator with 5V input is:

delines

1VV0301632 Rev. 4 Page 28 of 86 2020-09-23

Page 29

ML865G1 HW Design Guide

4.3.1.2. +12V Source Power Supply Design Guidelines

• The desired output for the power supply is 3.8V, hence due to the big difference

between the input source and the desired output, a linear regulator is not suited and shall not be used. A switching power supply will be preferable because of its better efficiency.

• When using a switching regulator, a 500kHz or more switching frequency regulator

is preferable because of its smaller inductor size and its faster transient response. This allows the regulator to respond quickly to the current peaks absorption.

• In any case the frequency and Switching design selection is related to the

application to be developed due to the fact the switching frequency could also generate EMC interferences.

• For car PB battery the input voltage can rise up to 15,8V and this should be kept in

mind when choosing components: all components in the power supply must withstand this voltage.

• A Bypass low ESR capacitor of adequate capacity must be provided in order to cut

the current absorption peaks, a 100μF capacitor is usually suited.

• Make sure the low ESR capacitor on the power supply output is rated at least 10V.

• For Car applications a spike protection diode should be inserted close to the power

input, in order to clean the supply from spikes.

An example of switching regulator with 12V input is in the below schematic:

4.3.1.3. Battery Source Power Supply Design Guidelines

The desired nominal output for the power supply is 3.8V and the maximum voltage allowed is 4.2V, hence a single 3.7V Li-Ion cell battery type is suited for supplying the power to the Telit ML865G1 module.

• A Bypass low ESR capacitor of adequate capacity must be provided in order to cut

the current absorption peaks, a 100μF tantalum capacitor is usually suited.

• Make sure the low ESR capacitor (usually a tantalum one) is rated at least 10V.

• A protection diode should be inserted close to the power input, in order to save the

ML865G1 from power polarity inversion. Otherwise the battery connector should be done in a way to avoid polarity inversions when connecting the battery.

• The battery must be rated to supply peaks of current up to 2A.

1VV0301632 Rev. 4 Page 29 of 86 2020-09-23

Page 30

ML865G1 HW Design Guide

MH, and Pb battery types directly

NOTE:

DON'T USE any Ni-Cd, Niconnected with ML865G1. Their use can lead to overvoltage on the ML865G1 and damage it. USE ONLY Li-Ion battery types.

4.3.2. Thermal Design Guidelines

This section will be available in next document revisions.

1VV0301632 Rev. 4 Page 30 of 86 2020-09-23

Page 31

ML865G1 HW Design Guide

4.3.3. Power Supply PCB layout Guidelines

As seen on the electrical design guidelines the power supply shall have a low ESR capacitor on the output to cut the current peaks on the input to protect the supply from spikes The placement of this component is crucial for the correct working of the circuitry. A misplaced component can be useless or can even decrease the power supply performance.

• The Bypass low ESR capacitor must be placed close to the Telit ML865G1 power

input pads or in the case the power supply is a switching type it can be placed close to the inductor to cut the ripple provided the PCB trace from the capacitor to the ML865G1 is wide enough to ensure a dropless connection even during an 2A current peak.

• The protection diode must be placed close to the input connector where the power

source is drained.

• The PCB traces to the ML865G1 and the Bypass capacitor must be wide enough to

ensure no significant voltage drops occur. This is for the same reason as previous point. Try to keep this trace as short as possible.

• To reduce the EMI due to switching, it is important to keep very small the mesh

involved; thus the input capacitor, the output diode (if not embodied in the IC) and the regulator have to form a very small loop.This is done in order to reduce the radiated field (noise) at the switching frequency (100-500 kHz usually).

• A dedicated ground for the Switching regulator separated by the common ground

plane is suggested.

• The placement of the power supply on the board should be done in such a way to

guarantee that the high current return paths in the ground plane are not overlapped to any noise sensitive circuitry as the microphone amplifier/buffer or earphone amplifier.

• The power supply input cables should be kept separate from noise sensitive lines

such as microphone/earphone cables.

• The insertion of EMI filter on VBATT pins is suggested in those designs where

antenna is placed close to battery or supply lines. A ferrite bead like Murata BLM18EG101TN1 or Taiyo Yuden P/N FBMH1608HM101 can be used for this purpose.

The below figure shows the recommended circuit:

1VV0301632 Rev. 4 Page 31 of 86 2020-09-23

Page 32

ML865G1 HW Design Guide

RTC supply

RTC is functional when ML865G1 is in PSM state and VBATT pin is supplied.

RTC settings are erased if VBATT supply is temporary disconnected.

VAUX Power Output

A regulated power supply output is provided on pin 51 in order to supply small devices

from the module, like: level translators, audio codec, sensors, and others.

Pin 51 can be used also as PWRMON (module powered ON indication) function, because

is always active when the module is powered ON and cannot be set to LOW level by any

AT command.

Host can only detect deep sleep mode (PSM) by monitoring of VAUX/PWRMON output pin,

since there is no pin dedicated to PSM status indicator.

The operating range characteristics of the supply are:

Item Min Typical Max

Output voltage 1.78V 1.80V 1.82V

Output current - - 60mA

Output bypass capacitor

(inside the module)

1uF

VAUX during PSM period is OFF ( PSM has to be enabled

previously by AT+CPSMS command)

1VV0301632 Rev. 4 Page 32 of 86 2020-09-23

Page 33

ML865G1 HW Design Guide

NOTE:

The Output Current MUST never be exceeded; care must be taken when designing the application section to avoid having an excessive current consumption.

1VV0301632 Rev. 4 Page 33 of 86 2020-09-23

Page 34

ML865G1 HW Design Guide

ABSOLUTE MAXIMUM RATINGS – NOT FUNCTIONAL

Operating Range - Interface levels (1.8V CMOS)

Parameter

AVG

CURRENT CHARACTERISTICS:

5. DIGITAL SECTION

ML865G1 has four main operation states:

• OFF state: Vbatt is applied and only RTC is running. Baseband is switched OFF and the only change possible is the ON state.

• ON state: baseband is fully switched on and ML865G1 is ready to accept AT commands. ML865G1 can be idle or connected.

• Sleep mode state: main baseband processor is intermittently switched ON and AT commands can be processed with some latency. ML865G1 is idle with low current consumption.

• Deep sleep mode state: PSM defined in 3GPP Release 12. Baseband is switched OFF most of the time.

Logic Levels

Parameter Min Max

Input level on any digital pin (CMOS 1.8) with respect to ground -0.3V 2.1V

Input high level 1.5V 1.9V

Input low level 0V 0.35V

Output high level 1.6V 1.9V

Output low level 0V 0.2V

Output Current 1mA

Input Current 1uA

1VV0301632 Rev. 4 Page 34 of 86 2020-09-23

Page 35

ML865G1 HW Design Guide

WAKE/ON_OFF

Power On

To turn on the ML865G1 the pad ON_OFF/WAKE must be set HIGH level for at 5 seconds

and then released.

ON_OFF/WAKE pad can make also an asynchronous wakeup of the system from the PSM

Mode, before the scheduled event of timer T3412 expired. To make asynchronous exit from

PSM mode ON_OFF/WAKE pin must be set HIGH level for 5 seconds.

The signal ON_OFF/WAKE can be directly connected to any GPIO (1.8V) of Application

Processor with a totem pole output. A level shifter is not required.

GPIO OUTPUT (totem pole)

ML865G1

Application

Processor

The typical current consumption of the input ON_OFF/WAKE pad is 0.25mA@1.8V.

NOTE:

Don't use any pull down resistor on the ON_OFF/WAKE line, it is

internally pulled down.

The VAUX/PWRMON pin can be monitored by application processor

to check if the device is powered ON.

A flow chart showing the proper turn on procedure is displayed below:

1VV0301632 Rev. 4 Page 35 of 86 2020-09-23

Page 36

ML865G1 HW Design Guide

“Modem ON Proc”

START

ON_OFF = HI

Delay = 5 sec

ON_OFF= LOW

Delay = 1 sec

“Modem ON Proc”

END

N N

VBATT>VBATT

min

PWRMON=ON ?

GO TO

“Start AT Commands””

1VV0301632 Rev. 4 Page 36 of 86 2020-09-23

Page 37

ML865G1 HW Design Guide

A flow chart showing the AT commands managing procedure is displayed below:

“Start AT CMD”

START

Delay = 300 msec

Enter AT <CR>

AT answer in

1 sec ?

GO TO

“HW Shutdown

Unconditional”

“Start AT CMD”

END

GO TO

“Modem ON Proc.”

NOTE:

In order to avoid a back powering effect it is recommended to avoid

having any HIGH logic level signal applied to the digital pins of the

ML865G1 when the module is powered off or during an ON-OFF

transition.

1VV0301632 Rev. 4 Page 37 of 86 2020-09-23

Page 38

ML865G1 HW Design Guide

WARNING

It is recommended to set the ON_OFF/WAKE line HIGH to power on

the module only after VBATT is higher than 3.20V.

In case this condition it is not satisfied you could use the

HW_SHUTDOWN* line to recover it and then restart the power on

activity using the ON_OFF/WAKE line.

After HW_SHUTDOWN* is released you could again use the ON_OFF/WAKE line to

power on the module.

Auto Power On

ML865G1 module can be switched on with ON_OFF/WAKE pin 7 permanently fixed to HI

level (1.8V).

In the configuration there are two limitations:

• the asynchronous PSM wake-up cannot be implemented.

• Power Off can be only implemented via AT command (see ML865G1 Software User

Guide, AT#SHDN)

Power Off

Turning off of the device can be done in two ways:

• via AT command (see ML865G1 Software User Guide, AT#SHDN)

• pin ON_OFF/WAKE asserted (HIGH) for at least 3 seconds

Either ways, the device issues a detach request to network informing that the device will

not be reachable any more.

1VV0301632 Rev. 4 Page 38 of 86 2020-09-23

Page 39

ML865G1 HW Design Guide

“Modem OFF Proc.”

ON OFF/WAKE = HI

PWRMON=ON

Delay >= 3 sec

ON OFF/WAKE = LOW

“Modem OFF Proc.”

NOTE:

To check if the device has been powered off or in PSM mode, the

hardware line PWRMON must be monitored. The device is powered

off when PWRMON goes low.

VBATT can be removed when PWRMON is in LOW state.

In order to avoid a back powering effect it is recommended to avoid

having any HIGH logic level signal applied to the digital pins of the

ML865G1 when the module is powered off or during an ON-OFF

transition.

WARNING:

Not following the recommended shut-down procedures might

damage the device and consequently void the warranty.

The following flow chart shows the proper turn off procedure:

1VV0301632 Rev. 4 Page 39 of 86 2020-09-23

Page 40

ML865G1 HW Design Guide

Unconditional Shutdown

HW_SHUTDOWN* is used to unconditionally shutdown the ML865G1. Whenever this

signal is pulled low, the ML865G1 is reset. When the device is reset it stops any

operation. After the release of the line, the ML865G1 is unconditionally shut down, without

doing any detach operation from the network where it is registered. This behaviour is not a

proper shut down because any cellular device is requested to issue a detach request on

turn off. The HW_SHUTDOWN* is internally controlled on start-up to achieve always a

proper power-on reset sequence, so there's no need to control this pin on start-up.

To unconditionally shutdown the ML865G1, the pad HW_SHUTDOWN* must be tied low

for at least 200 milliseconds and then released.

The signal is internally pulled up so the pin can be left floating if not used.

If used, then it must always be connected with an open collector transistor, to permit

to the internal circuitry the power on reset and under voltage lockout functions.

During PSM mode, HW_SHUTDOWN toggle has no effect. The use of HW_SHUTDOWN*

pin is valid only when ML865G1 has VAUX/PWRMON output HI.

PIN DESCRIPTION

Signal Function I/O Pin

HW_SHUTDOWN*

Unconditional Shutdown of the Module

I 55

WARNING:

The hardware unconditional Shutdown must not be used during

normal operation of the device since it does not detach the device

from the network. It shall be kept as an emergency exit procedure.

A typical circuit is the following:

1VV0301632 Rev. 4 Page 40 of 86 2020-09-23

Page 41

ML865G1 HW Design Guide

For example: Let us assume you need to drive the HW_SHUTDOWN* pad with a totem

pole output of a +3/5 V microcontroller:

1VV0301632 Rev. 4 Page 41 of 86 2020-09-23

Page 42

ML865G1 HW Design Guide

“HW SHUTDOWN

START

HW_SHUTDOWN* = LOW

Delay = 200ms

“HW SHUTDOWN

END

HW_SHUTDOWN* = HIGH

Delay = 1s

In the following flow chart is detailed the proper Unconditional Shutdown procedure:

Unconditional”

Disconnect

VBATT

PWRMON = ON

Unconditional”

NOTE:

In order to avoid a back powering effect it is recommended to avoid

having any HIGH logic level signal applied to the digital pins of the

ML865G1 when the module is powered off or during an ON-OFF

transition.

1VV0301632 Rev. 4 Page 42 of 86 2020-09-23

Page 43

ML865G1 HW Design Guide

Wake from deep sleep mode

ML865G1 supports Power Saving Mode (PSM) functionality defined in 3GPP Release 12.

When Periodic Update Timer expires, ML865G1 power off until the next scheduled wake-

up time.

Asynchronous event controlled by host can wake up from deep sleep mode by asserting

ON_OFF/WAKE pin HIGH level for at least 5 seconds.

Host can detect deep sleep mode by polling VAUX/PWRMON pin if previously configured

in the user schematic for this purpose.

NOTE:

Do not use any pull up resistor on the HW_SHUTDOWN* line nor any

totem pole digital output. Using pull up resistor may bring to latch up

problems on the ML865G1 power regulator and improper functioning

of the module.

To proper power on again the module please refer to the related

paragraph (“Power ON”)

The unconditional hardware shutdown must always be implemented

on the boards and should be used only as an emergency exit

procedure.

Fast power down

The procedure to power off ML865G1 described in Chapter 5.4 normally takes more than

1 second to detach from network and make ML865G1internal filesystem properly closed.

In case of unwanted supply voltage loss the system can be switched off without any risk of

filesystem data corruption by implementing Fast Shut Down feature.

Fast Shut Down feature permits to reduce the current consumption and the time-to-

poweroff to minimum values.

1VV0301632 Rev. 4 Page 43 of 86 2020-09-23

Page 44

ML865G1 HW Design Guide

NOTE:

Refer to ML865G1 series AT command reference guide (Fast power

down - #FASTSHDN) in order to set up detailed AT command.

5.7.1. Fast Shut Down by Hardware

The Fast Power Down can be triggered by configuration of any GPIO. HI level to LOW

level transition of GPIO commands fast power down.

Example circuit:

NOTE:

Consider voltage drop under max current conditions when defining

the voltage detector thereshold in order to avoid unwanted shutdown.

The capacitor is rated with the following formula:

1VV0301632 Rev. 4 Page 44 of 86 2020-09-23

Page 45

ML865G1 HW Design Guide

TIP:

Make check of timings and voltage discharge during system

verification.

5.7.2. Fast Shut Down by Software

The Fast Power Down can be triggered by AT command.

Communication ports

5.8.1. USB 2.0 HS

The ML865G1 includes one integrated universal serial bus (USB 2.0 HS) transceiver.

The following table is listing the available signals:

PAD Signal I/O Function NOTE

20 USB_D+ I/O USB differential Data (+)

19 USB_D- I/O USB differential Data (-)

18 VUSB AI

Power sense for the internal USB transceiver.

The USB_DPLUS and USB_DMINUS signals have a clock rate of 480 MHz, therefore

signal traces should be routed carefully. Trace lengths, number of vias and capacitive

loading should be minimized. The characteristic impedance value should be as close as

possible to 90 Ohms differential.

ESD protection can be added to USB D+/D- lines in case of external connector for cable

Accepted range:

3.0V to 5.5V 100K pull down

connection.

Proper components for USB 2.0 must be used.

1VV0301632 Rev. 4 Page 45 of 86 2020-09-23

Page 46

ML865G1 HW Design Guide

NOTE:

Disconnect or assert to GND the VUSB pin before activating the

Power Saving Mode.

1VV0301632 Rev. 4 Page 46 of 86 2020-09-23

Page 47

ML865G1 HW Design Guide

5.8.2. SPI

The ML865G1 Module is provided by a standard 3-wire master or slave SPI interface with

chip select control.

The following table is listing the available signals:

PAD Signal I/O Function Type NOTE

29 SPI_CLK I/O SPI Clock

52 SPI_MISO I/O SPI MISO

53 SPI_MOSI I/O SPI MOSI

32 SPI_CS I/O SPI Chip Select

NOTE:

Due to the shared functions, SPI port and TX_AUX/RX_AUX port

CMOS

1.8V

CMOS

1.8V

CMOS

1.8V

CMOS

1.8V

Shared

with

RX_AUX

Shared

with

TX_AUX

cannot be used simultanously.

1VV0301632 Rev. 4 Page 47 of 86 2020-09-23

Page 48

ML865G1 HW Design Guide

SPI_MISO

5.8.3. SPI Connections

SPI_MOSI

Application

ML865G1

SPI_CLK

Processor

SPI_CS

5.8.4. Serial Ports

The ML865G1 module is provided with by 2 Asynchronous serial ports:

• MODEM SERIAL PORT 1 (Main)

• MODEM SERIAL PORT 2 (Auxiliary)

Several configurations can be designed for the serial port on the OEM hardware, but the

most common are:

• RS232 PC com port

• microcontroller UART @ 1.8V (Universal Asynchronous Receive Transmit)

• microcontroller UART @ 5V or other voltages different from 1.8V

Depending from the type of serial port on the OEM hardware a level translator circuit may

be needed to make the system work. On the ML865G1 the ports are CMOS 1.8.

5.8.4.1. Modem serial port 1 (USIF0)

The serial port 1 on the ML865G1 is a +1.8V UART with all the 7 RS232 signals. It differs

from the PC-RS232 in the signal polarity (RS232 is reversed) and levels.

The following table is listing the available signals:

1VV0301632 Rev. 4 Page 48 of 86 2020-09-23

Page 49

ML865G1 HW Design Guide

RS232

Signal

1 C109/DCD 1

2 C104/RXD 10

3 C103/TXD 9

4 C108/DTR 4

ML865G1

PAD

Name Usage

Data Carrier Detect

Transmit line *see Note

Receive line *see Note

Data Terminal Ready

6 C107/DSR 3 Data Set Ready

Output from the ML865G1 that indicates the carrier presence

Output transmit line of ML865G1 UART

Input receive of the ML865G1 UART

Input to the ML865G1 that controls the DTE READY condition

Output from the ML865G1 that indicates the module is ready

7 C105/RTS 5

Request to Send

8 C106/CTS 6 Clear to Send

9 C125/RING 2 Ring Indicator

Input to the ML865G1 that controls the Hardware flow control

Output from the ML865G1 that controls the Hardware flow control

Output from the ML865G1 that indicates the incoming call condition

1VV0301632 Rev. 4 Page 49 of 86 2020-09-23

Page 50

ML865G1 HW Design Guide

NOTE:

According to V.24, some signal names are referred to the application

side, therefore on the ML865G1 side these signal are on the opposite

direction:

TXD on the application side will be connected to the receive line

(here named C103/TXD)

RXD on the application side will be connected to the transmit line

(here named C104/RXD)

For a minimum implementation, only the TXD, RXD lines can be

connected, the other lines can be left open provided a software flow

control is implemented.

In order to avoid a back powering effect it is recommended to avoid

having any HIGH logic level signal applied to the digital pins of the

ML865G1 when the module is powered off or during an ON/OFF

transition.

5.8.4.2. Modem serial port 2 (USIF1)

The secondary serial port on the ML865G1 is a CMOS1.8V with only the RX and TX

signals.

The signals of the ML865G1 serial port are:

PAD Signal I/O Function Type NOTE

Shared with SPI_MOSI

Shared with SPI_MISO

53 TX_AUX O

52 RX_AUX I

Auxiliary UART (TX Data to DTE)

Auxiliary UART (RX Data from DTE)

CMOS

1.8V

CMOS

1.8V

1VV0301632 Rev. 4 Page 50 of 86 2020-09-23

Page 51

ML865G1 HW Design Guide

NOTE:

Due to the shared functions, TX_AUX/RX_AUX port and SPI port

cannot be used simultanously.

In order to avoid a back powering effect it is recommended to avoid

having any HIGH logic level signal applied to the digital pins of the

ML865G1 when the module is powered off or during an ON/OFF

transition.

Refer to ML865G1 series AT command reference guide for port

configuration.

5.8.4.3. RS232 level translation

In order to interface the ML865G1 with a PC com port or a RS232 (EIA/TIA-232)

application a level translator is required. This level translator must:

• invert the electrical signal in both directions;

• Change the level from 0/1.8V to +15/-15V.

Actually, the RS232 UART 16450, 16550, 16650 & 16750 chipsets accept signals with

lower levels on the RS232 side (EIA/TIA-562), allowing a lower voltage-multiplying ratio

on the level translator. Note that the negative signal voltage must be less than 0V and

hence some sort of level translation is always required.

The simplest way to translate the levels and invert the signal is by using a single chip level

translator. There are a multitude of them, differing in the number of drivers and receivers

and in the levels (be sure to get a true RS232 level translator not a RS485 or other

standards).

By convention the driver is the level translator from the 0-1.8V UART to the RS232 level.

The receiver is the translator from the RS232 level to 0-1.8V UART.

In order to translate the whole set of control lines of the UART you will need:

• 5 drivers

1VV0301632 Rev. 4 Page 51 of 86 2020-09-23

Page 52

ML865G1 HW Design Guide

• 3 receivers

An example of RS232 level

adaptation circuitry could be done

using a MAXIM transceiver

(MAX218)

In this case the chipset is capable

to translate directly from 1.8V to

the RS232 levels (Example done

on 4 signals only).

The RS232 serial port lines are usually connected to a DB9 connector with the following

layout:

General purpose I/O

The ML865G1 module is provided by a set of Configurable Digital Input / Output pins

(CMOS 1.8V). Input pads can only be read; they report the digital value (high or low)

present on the pad at the read time. Output pads can only be written or queried and set

the value of the pad output.

An alternate function pad is internally controlled by the ML865G1 firmware and acts

depending on the function implemented.

The following table shows the available GPIO on the ML865G1:

1VV0301632 Rev. 4 Page 52 of 86 2020-09-23

Page 53

ML865G1 HW Design Guide

PAD Signal I/O Output

Drive

Strength

48 GPIO_01 I/O 1mA

47 GPIO_02 I/O 1mA

46 GPIO_03 I/O 1mA

45 GPIO_04 I/O 1mA

33 GPIO_05 I/O 1mA

32 GPIO_06 I/O 1mA

31 GPIO_07 I/O 1mA

Default State NOTE

INPUT – PD (100K)

30 GPIO_08 I/O 1mA

INPUT – PD (100K)

5.9.1. Using a GPIO as INPUT

The GPIO pads, when used as inputs, can be connected to a digital output of another

device and report its status, provided this device has interface levels compatible with the

1.8V CMOS levels of the GPIO.

Input current (@1.8V) is about 18uA (corrisponding to 100K pulldown value) in all GPIO

pin. This value is present since ML865 poweron.

If the digital output of the device to be connected with the GPIO input pad has interface

levels different from the 1.8V CMOS, then it can be buffered with an open collector

transistor with a 47K pull up to 1.8V supplied by VAUX/POWERMON (pin 51).

1VV0301632 Rev. 4 Page 53 of 86 2020-09-23

Page 54

ML865G1 HW Design Guide

Device Status

Led Status

NOTE:

In order to avoid a back powering effect it is recommended to avoid

having any HIGH logic level signal applied to the digital pins of the

ML865G1 when the module is powered off or during an ON/OFF

transition.

Refer to ML865G1 series AT command reference guide for GPIO

pins configuration.

5.9.2. Using a GPIO as OUTPUT

The GPIO pads, when used as outputs, can drive 1.8V CMOS digital devices or

compatible hardware. When set as outputs, the pads have a push-pull output and

therefore the pull-up resistor may be omitted.

5.9.3. Indication of network service availability

The STAT_LED pin status shows information on the network service availability and Call

status.

The function is available as alternate function of GPIO_08 (to be enabled using the

AT#GPIO=1,0,2 command).

In the ML865G1 modules, the STAT_LED needs an external transistor to drive an external

LED and its voltage level is defined accordingly to the table below:.

Device off Permanently off

Not Registered Permanently on

Registered in idle Blinking 1sec on + 2 sec off

1VV0301632 Rev. 4 Page 54 of 86 2020-09-23

Page 55

ML865G1 HW Design Guide

Registered in idle + power saving

It depends on the event that triggers the wakeup (In sync with network paging)

Connecting Blinking 1 sec on + 2 sec off

The reference schematic for LED indicator,

R3 must be calculated taking in account VBATT value and LED type. :

External SIM Holder

Please refer to the related User Guide (SIM Holder Design Guides, 80000NT10001a).

ADC Converter

The ML865G1 is provided by one AD converters. It is able to read a voltage level in the

range of 0÷1.8 volts applied on the ADC pin input, store and convert it into 10 bit word.

The input lines are named as ADC_IN1 and they are available on Pin 15.

The following table is showing the ADC characteristics:

1VV0301632 Rev. 4 Page 55 of 86 2020-09-23

Page 56

ML865G1 HW Design Guide

Item Min Typical Max Unit

Input Voltage range 0 - 1.8 Volt

AD conversion - - 10 bits

Input Resistance 1 - - Mohm

Input Capacitance - 1 - pF

5.11.1. Using ADC Converter

Available in a next document revision.

Forced USB boot

In some case of firmware upgrade FORCED_USB_BOOT pin must be set to 1.8V during poweron of ML865G1.

The input current is very low so 10K resistor to 1.8V supply can be used to keep this pin in HI state.

FORCED_USB_BOOT pin must be connected only during firmware upgrade operation and

normally it has to be left open.

FORCED_USB_BOOT pin must be available in the user application circuit throught test

points for easy connection of 10K resistor and 1.8V supply.

1VV0301632 Rev. 4 Page 56 of 86 2020-09-23

Page 57

ML865G1 HW Design Guide

Depending by frequency band(s) provided by the network

6. RF SECTION

Bands Variants

See section 2.2.

TX Output power

See section 2.5.

RX Sensitivity

This information will be available in a next document revision.

Antenna requirements

The antenna connection and board layout design are the most important aspect in the full product design as they strongly affect the product overall performances, hence read carefully and follow the requirements and the guidelines for a proper design.

The antenna and antenna transmission line on PCB for a Telit ML865G1-WW device shall fulfil the following requirements:

Item Value

Frequency range

operator, the customer shall use the most suitable antenna for that/those band(s)

250 MHz in LTE Band 1

140 MHz in LTE Band 2, PCS1900

170 MHz in LTE Band 3, DCS1800

445 MHz in LTE Band 4

70 MHz in LTE Band 5, GSM850

80 MHz in LTE Band 8, GSM900

Bandwidth

1VV0301632 Rev. 4 Page 57 of 86 2020-09-23

47 MHz in LTE Band 12

41 MHz in LTE Band 13

60 MHz in LTE Band 18

60 MHz in LTE Band 19

71 MHz in LTE Band 20

145 MHz in LTE Band 25

80 MHz in LTE Band 26

Page 58

ML865G1 HW Design Guide

62 MHz in LTE Band 27

100 MHz in LTE Band 28

490 MHz in LTE Band 66

81 MHz in LTE Band 71

48 MHz in LTE Band 85

Impedance 50 ohm

Input power ML865G1-WW: > 33dBm Average power

VSWR absolute max ≤ 10:1 (limit to avoid permanent damage)

VSWR recommended ≤ 2:1 (limit to fulfill all regulatory requirements)

6.4.1. PCB Design guidelines

When using the ML865G1, since there's no antenna connector on the module, the

antenna must be connected to the ML865G1 antenna pad (K1) by means of a

transmission line implemented on the PCB.

This transmission line shall fulfil the following requirements:

Item Value

Characteristic

Impedance

Max Attenuation 0,3 dB

Coupling Coupling with other signals shall be avoided

50 ohm (+-10%)

Ground Plane

The transmission line should be designed according to the following guidelines:

• Make sure that the transmission line’s characteristic impedance is 50ohm ;

1VV0301632 Rev. 4 Page 58 of 86 2020-09-23

Cold End (Ground Plane) of antenna shall be equipotential to the ML865G1 ground pins

Page 59

ML865G1 HW Design Guide

• Keep line on the PCB as short as possible, since the antenna line loss shall be less

than about 0,3 dB;

• Line geometry should have uniform characteristics, constant cross section, avoid

meanders and abrupt curves;

• Any kind of suitable geometry / structure (Microstrip, Stripline, Coplanar, Grounded

Coplanar Waveguide...) can be used for implementing the printed transmission line

afferent the antenna;

• If a Ground plane is required in line geometry, that plane has to be continuous and

sufficiently extended, so the geometry can be as similar as possible to the related

canonical model;

• Keep, if possible, at least one layer of the PCB used only for the Ground plane; If

possible, use this layer as reference Ground plane for the transmission line;

• It is wise to surround (on both sides) the PCB transmission line with Ground, avoid

having other signal tracks facing directly the antenna line track.

• Avoid crossing any un-shielded transmission line footprint with other signal tracks

on different layers;

• The ground surrounding the antenna line on PCB has to be strictly connected to the

main Ground Plane by means of via holes (once per 2mm at least), placed close to

the ground edges facing line track;

• Place EM noisy devices as far as possible from ML865G1 antenna line;

• Keep the antenna line far away from the ML865G1 power supply lines;

• If EM noisy devices (such as fast switching ICs, LCD and so on) are present on the

PCB hosting the ML865, take care of the shielding of the antenna line by burying it

in an inner layer of PCB and surround it with Ground planes, or shield it with a metal

frame cover.

• If EM noisy devices are not present around the line, the use of geometries like

Microstrip or Grounded Coplanar Waveguide has to be preferred, since they

typically ensure less attenuation if compared to a Stripline having same length;

The following image is showing the suggested layout for the Antenna pad

connection:

1VV0301632 Rev. 4 Page 59 of 86 2020-09-23

Page 60

ML865G1 HW Design Guide

6.4.2. PCB Guidelines in case of FCC Certification

In the case FCC certification is required for an application using ML865G1, according to

FCC KDB 996369 for modular approval requirements, the transmission line has to be

similar to that implemented on ML865G1 interface board and described in the following

chapter.

6.4.2.1. Transmission line design

During the design of the ML865G1 interface board, the placement of components has

been chosen properly, in order to keep the line length as short as possible, thus leading to

lowest power losses possible. A Grounded Coplanar Waveguide (G-CPW) line has been

chosen, since this kind of transmission line ensures good impedance control and can be

implemented in an outer PCB layer as needed in this case. A SMA female connector has

been used to feed the line.

The interface board is realized on a FR4, 4-layers PCB. Substrate material is

characterized by relative permittivity εr = 4.6 ± 0.4 @ 1 GHz, TanD= 0.019 ÷ 0.026 @ 1

GHz.

1VV0301632 Rev. 4 Page 60 of 86 2020-09-23

Page 61

ML865G1 HW Design Guide

A characteristic impedance of nearly 50 Ω is achieved using trace width = 1.1 mm,

clearance from coplanar ground plane = 0.3 mm each side. The line uses reference

ground plane on layer 3, while copper is removed from layer 2 underneath the line. Height

of trace above ground plane is 1.335 mm. Calculated characteristic impedance is 51.6 Ω,

estimated line loss is less than 0.1 dB. The line geometry is shown below:

1VV0301632 Rev. 4 Page 61 of 86 2020-09-23

Page 62

ML865G1 HW Design Guide

6.4.2.2. Transmission Line Measurements

An HP8753E VNA (Full-2-port calibration) has been used in this measurement session.

A calibrated coaxial cable has been soldered at the pad corresponding to RF output; a

SMA connector has been soldered to the board in order to characterize the losses of the

transmission line including the connector itself. During Return Loss / impedance

measurements, the transmission line has been terminated to 50 Ω load.

Return Loss plot of line under test is shown below:

1VV0301632 Rev. 4 Page 62 of 86 2020-09-23

Page 63

ML865G1 HW Design Guide

Line input impedance (in Smith Chart format, once the line has been terminated to 50 Ω

load) is shown in the following figure:

Insertion Loss of G-CPW line plus SMA connector is shown below:

1VV0301632 Rev. 4 Page 63 of 86 2020-09-23

Page 64

ML865G1 HW Design Guide

6.4.2.3. Antenna Installation Guidelines

• Install the antenna in a place covered by the LTE signal with CAT-M1 support.

• Antenna must not be installed inside metal cases

• Antenna must not be installed according Antenna manufacturer instructions

• Antenna integration should optimize the Radiation Efficiency. Efficiency values >

50% are recommended on all frequency bands

• Antenna integration should not perturb the radiation pattern described in Antenna

manufacturer documentation.

• It is preferable to get an omnidirectional radiation pattern to

• Antenna Gain must not exceed values indicated in regulatory requirements, where

applicable, in order to meet related EIRP limitations. Typical antenna Gain in most

M2M applications does not exceed 2dBi

• If the device antenna is located farther than 20cm from the human body and there

are no co-located transmitter then the Telit FCC/IC approvals can be re-used by the

end product

• If the device antenna is located closer than 20cm from the human body or there are

co-located transmitter then the additional FCC/IC testing may be required for the

end product (Telit FCC/IC approvals cannot be reused)

1VV0301632 Rev. 4 Page 64 of 86 2020-09-23

Page 65

ML865G1 HW Design Guide

7. AUDIO SECTION

The Telit digital audio interface (DVI) of the ML865G1 Module is based on the I2S serial

bus interface standard. The audio port can be connected to end device using digital

interface, or via one of the several compliant codecs (in case an analog audio is needed).

Electrical Characteristics

The product is providing the DVI on the following pins:

Pin Signal I/O Function Type

48 DVI_WA0 O Digital Audio Interface (Word

Alignment / LRCLK)

47 DVI_RX I Digital Audio Interface (RX) CMOS 1.8V

46 DVI_TX O Digital Audio Interface (TX) CMOS 1.8V

45 DVI_CLK O Digital Audio Interface (BCLK) CMOS 1.8V

CMOS 1.8V

Codec examples

Please refer to the Digital Audio Application note.

1VV0301632 Rev. 4 Page 65 of 86 2020-09-23

Page 66

ML865G1 HW Design Guide

8. GNSS SECTION

ML865G1 module includes a state-of-art receiver that can simultaneously search and track satellite signals from multiple satellite constellations. This multi-GNSS receiver uses the entire spectrum of GNSS systems available: GPS, GLONASS, BeiDou, Galileo, and QZSS.

GNSS Signals Pin-out

Pin Signal I/O Function Type

37 ANT_GNSS I GNSS Antenna (50

ohm)

33 GNSS_LNA_EN O

GNSS External LNA

Enable

CMOS

1.8V

RF Front End Design

The ML865G1 Module doesn’t contain the LNA needed to reach the maximum sensitivity. Active antenna (antenna with a built-in low noise amplifier) must be used and must be supplied with proper bias-tee circuit.

8.2.1. Guidelines of PCB line for GNSS Antenna

• Ensure that the antenna line impedance is 50ohm.

• Keep the antenna line on the PCB as short as possible to reduce the loss.

• Antenna line must have uniform characteristics, constant cross section, avoid

meanders and abrupt curves.

• Keep one layer of the PCB used only for the Ground plane, if possible.

• Surround (on both the sides, over and under) the antenna line on PCB with Ground,

avoid having other signal tracks facing directly the antenna line of track.

• The ground around the antenna line on PCB has to be strictly connected to the Ground Plane by placing vias once per 2mm at least.

• Place EM noisy devices as far as possible from antenna line.

• Keep the antenna line far away from power supply lines.

• Keep the antenna line far away from GSM RF lines.

• If you have EM noisy devices around the PCB hosting the module, such as fast

switching ICs, take care of the shielding of the antenna line by burying it inside the layers of PCB and surround it with Ground planes, or shield it with a metal frame cover.

• If you do not have EM noisy devices around the PCB hosting the module, use a strip-line on the superficial copper layer for the antenna line. The line attenuation will be lower than a buried one.

1VV0301632 Rev. 4 Page 66 of 86 2020-09-23

Page 67

ML865G1 HW Design Guide

8.2.2. Hardware-based solution for GNSS and LTE coexistence

When in the user application a stand-alone GNSS receiver is present, the LTE transmission may desensitize the GNSS receiver in particular if the decoupling between LTE and GNSS antennas is low. A SAW filter can be added on LTE side, to protect GNSS receiver from LTE out-of-band emissions, as described in the schematic below.

When the GNSS receiver embedded in the ML865G1 module is used, there is no condition for degradation, because LTE part and GNSS part are never active simultaneously, therefore the filtering on the LTE side is not needed.

GNSS Antenna Requirements

GNSS active antenna must be used or integrated in the application.

8.3.1. GNSS Antenna specification

Item Value

Frequency range 1559.0 ~ 1610.0 MHz

Gain 20 ~ 30dB

Impedance 50 ohm

Noise Figure of LNA < 1.5 (recommended)

DC supply voltage DC 1.8 ~ 3.3V

VSWR ≤ 3:1 (recommended)

1VV0301632 Rev. 4 Page 67 of 86 2020-09-23

Page 68

ML865G1 HW Design Guide

8.3.2. GNSS Antenna – Installation Guidelines

• The antenna must be installed according to the antenna manufacturer’s instructions to obtain the maximum performance of GNSS receiver.

• The antenna location must be evaluated carefully if operating in conjunction with any other antenna or transmitter.

• The antenna must not be installed inside metal cases or near any obstacle that may degrade features like antenna lobes and gain.

8.3.3. Powering the External LNA (active antenna)

The LNA of active antenna needs a source of power because 1.8V or 3V DC voltage needed by active antenna is not supplied by the ML865G1 module, but can be easily included by the host design.

The electrical characteristics of the GPS_LNA_EN signal are:

Level Min Max

Output High Level 1.6V 1.9V

Output Low Level 0V 0.3V

Example of external antenna bias circuitry:

Be aware of max bias current in case of unwanted short on antenna cable, decoupling inductor may be damaged.

In case of LNA with 1.8V supply, VAUX/POWERMON pin can be used to supply active GNSS antenna

1VV0301632 Rev. 4 Page 68 of 86 2020-09-23

Page 69

ML865G1 HW Design Guide

GNSS Characteristics

The table below specifies the GNSS characteristics and expected performance:

Parameters Typical

Measurement

Tracking Sensitivity

Sensitivity

Min Navigation update rate 1Hz

Navigation

Cold Start -144 dBm

-159 dBm

-155 dBm

1VV0301632 Rev. 4 Page 69 of 86 2020-09-23

Page 70

ML865G1 HW Design Guide

9. MECHANICAL DESIGN

Drawing

NOTE:

Dimensions in mm.

General Tolerance ±0.1, Angular Tolerance ±1°, The tolerance is not

cumulative.

1VV0301632 Rev. 4 Page 70 of 86 2020-09-23

Page 71

ML865G1 HW Design Guide

10. APPLICATION PCB DESIGN

General

The ML865G1 modules have been designed to be compliant with a standard lead-free SMT process.

Footprint

1VV0301632 Rev. 4 Page 71 of 86 2020-09-23

Page 72

ML865G1 HW Design Guide

In order to easily rework the ML865G1 is suggested to consider on the application a 1.5 mm placement inhibit area around the module.

It is also suggested, as common rule for an SMT component, to avoid having a mechanical part of the application in direct contact with the module.

NOTE:

In the customer application, the region under WIRING INHIBIT (see figure above) must be clear from signal or ground paths.

1VV0301632 Rev. 4 Page 72 of 86 2020-09-23

Page 73

ML865G1 HW Design Guide

PCB

Copper Pad

Solder Mask

PCB pad design

Non solder mask defined (NSMD) type is recommended for the solder pads on the PCB.

SMD

NSMD

(Solder Mask Defined)

(Non Solder Mask Defined)

PCB pad dimensions

1VV0301632 Rev. 4 Page 73 of 86 2020-09-23

It is not recommended to place via or micro-via not covered by solder resist in an area of 0.3 mm around the pads unless it carries the same signal of the pad itself (see following figure).

Page 74

ML865G1 HW Design Guide

Holes in pad are allowed only for blind holes and not for through holes. Recommendations for PCB pad surfaces:

Finish Layer thickness

Properties

[µm]

good solder ability

Electro-less Ni / Immersion Au

3 –7 / 0.03 – 0.15

protection,

high shear force values

The PCB must be able to resist the higher temperatures which are occurring at the lead-free process. This issue should be discussed with the PCB-supplier. Generally, the wettability of tin-lead solder paste on the described surface plating is better compared to lead-free solder paste. It is not necessary to panel the application PCB, however in that case it is suggested to use milled contours and predrilled board breakouts; scoring or v-cut solutions are not recommended.

Stencil

Stencil’s apertures layout can be the same of the recommended footprint (1:1), we

suggest a thickness of stencil foil ≥ 120 µm.

1VV0301632 Rev. 4 Page 74 of 86 2020-09-23

Page 75

ML865G1 HW Design Guide

Solder paste

Item Lead Free

Solder Paste Sn/Ag/Cu

We recommend using only “no clean” solder paste in order to avoid the cleaning of the modules after assembly

Solder Reflow

Recommended solder reflow profile:

WARNING:

The above solder reflow profile represents the typical SAC reflow

limits and does not guarantee adequate adherence of the module to

the customer application throughout the temperature range.

Customer must optimize the reflow profile depending on the overall

system taking into account such factors as thermal mass and

warpage..

1VV0301632 Rev. 4 Page 75 of 86 2020-09-23

Page 76

ML865G1 HW Design Guide

Profile Feature Pb-Free Assembly Free

Average ramp-up rate (TL to TP) 3°C/second max

Preheat

– Temperature Min (Tsmin)

– Temperature Max (Tsmax)

– Time (min to max) (ts)

Tsmax to TL

– Ramp-up Rate

Time maintained above:

– Temperature (TL)

– Time (tL)

Peak Temperature (Tp) 245 +0/-5°C

Time within 5°C of actual Peak

Temperature (tp)

Ramp-down Rate 6°C/second max.

150°C

200°C

217°C

10-30 seconds

60-180 seconds

3°C/second max

60-150 seconds

Time 25°C to Peak Temperature 8 minutes max.

NOTE:

All temperatures refer to topside of the package, measured

on the package body surface

WARNING:

THE ML865G1 MODULE WITHSTANDS ONE REFLOW

PROCESS ONLY.

1VV0301632 Rev. 4 Page 76 of 86 2020-09-23

Page 77

ML865G1 HW Design Guide

11. PACKAGING

Is possible to order in two packaging system:

• Package on tray

• Package on reel

Tray

The ML865G1 modules are packaged on trays of 40 pieces each. These trays can be used in SMT processes for pick & place handling.

1VV0301632 Rev. 4 Page 77 of 86 2020-09-23

Page 78

ML865G1 HW Design Guide

1VV0301632 Rev. 4 Page 78 of 86 2020-09-23

Page 79

ML865G1 HW Design Guide

Reel

The ML865G1 can be packaged on reels of 200 pieces each.

See figure for module positioning into the carrier.

Moisture sensitivity

The moisture sensitivity level of the Product is “3” according with standard IPC/JEDEC J-STD-020, take care of all the relative requirements for using this kind of components.

Moreover, the customer has to take care of the following conditions:

1VV0301632 Rev. 4 Page 79 of 86 2020-09-23

Page 80

ML865G1 HW Design Guide

a) The shelf life of the Product inside of the dry bag is 12 months from the

bag seal date, when stored in a non-condensing atmospheric environment of < 40°C and < 90% RH.

b) Environmental condition during the production: <= 30°C / 60% RH

according to IPC/JEDEC J-STD-033B.

c) The maximum time between the opening of the sealed bag and the

reflow process must be 168 hours if condition b) “IPC/JEDEC J-STD-033B paragraph 5.2” is

respected. d) Baking is required if conditions b) or c) are not respected e) Baking is required if the humidity indicator inside the bag indicates 10%

RH or more.

1VV0301632 Rev. 4 Page 80 of 86 2020-09-23

Page 81

ML865G1 HW Design Guide

12. CONFORMITY ASSESSMENT ISSUES

ANATEL Regulatory Notices

"Este equipamento não tem direito à proteção contra interferência prejudicial e não pode causar interferência em sistemas devidamente autorizados"

"This equipment is not entitled to protection against harmful interference and must not cause interference in duly authorized systems"

ME910G1-WW, ME310G1-WW, ML865G1-WW Homologation #: 08566-20-02618

1VV0301632 Rev. 4 Page 81 of 86 2020-09-23

Page 82

ML865G1 HW Design Guide

13. SAFETY RECOMMENDATIONS

READ CAREFULLY

Be sure the use of this product is allowed in the country and in the environment required. The use of this product may be dangerous and has to be avoided in the following areas:

• Where it can interfere with other electronic devices in environments such as

hospitals, airports, aircrafts, etc.

• Where there is risk of explosion such as gasoline stations, oil refineries, etc. It is the

responsibility of the user to enforce the country regulation and the specific environment regulation.

Do not disassemble the product; any mark of tampering will compromise the warranty validity. We recommend following the instructions of the hardware user guides for correct wiring of the product. The product has to be supplied with a stabilized voltage source and the wiring has to be conformed to the security and fire prevention regulations. The product has to be handled with care, avoiding any contact with the pins because electrostatic discharges may damage the product itself. Same cautions have to be taken for the SIM, checking carefully the instruction for its use. Do not insert or remove the SIM when the product is in power saving mode.

The system integrator is responsible for the functioning of the final product; therefore, care has to be taken to the external components of the module, as well as any project or installation issue, because the risk of disturbing the GSM network or external devices or having impact on the security. Should there be any doubt, please refer to the technical documentation and the regulations in force. Every module has to be equipped with a proper antenna with specific characteristics. The antenna has to be installed with care in order to avoid any interference with other electronic devices and has to guarantee a minimum distance from the body (20 cm). In case this requirement cannot be satisfied, the system integrator has to assess the final product against the SAR regulation.

The European Community provides some Directives for the electronic equipment introduced on the market. All of the relevant information is available on the European Community website:

http://ec.europa.eu/enterprise/sectors/rtte/documents/

The text of the Directive 99/05 regarding telecommunication equipment is available,

while the applicable Directives (Low Voltage and EMC) are available at:

http://ec.europa.eu/enterprise/sectors/electrical/

1VV0301632 Rev. 4 Page 82 of 86 2020-09-23

Page 83

ML865G1 HW Design Guide

TTSC

Telit Technical Support Centre USB

Universal Serial Bus HS

High Speed DTE

Data Terminal Equipment UMTS

Universal Mobile Telecommunication System WCDMA

Wideband Code Division Multiple Access HSDPA

High Speed Downlink Packet Access HSUPA

High Speed Uplink Packet Access UART

Universal Asynchronous Receiver Transmitter HSIC

High Speed Inter Chip SIM

Subscriber Identification Module SPI

Serial Peripheral Interface ADC

Analog – Digital Converter DAC

Digital – Analog Converter I/O

Input Output GPIO

General Purpose Input Output CMOS

Complementary Metal – Oxide Semiconductor MOSI

Master Output – Slave Input MISO

Master Input – Slave Output CLK

Clock MRDY

Master Ready

14. ACRONYMS

1VV0301632 Rev. 4 Page 83 of 86 2020-09-23

Page 84

ML865G1 HW Design Guide

SRDY

Slave Ready CS

Chip Select RTC

Real Time Clock PCB

Printed Circuit Board ESR

Equivalent Series Resistance VSWR

Voltage Standing Wave Radio VNA

Vector Network Analyzer

1VV0301632 Rev. 4 Page 84 of 86 2020-09-23

Page 85

ML865G1 HW Design Guide

1 (USIF0)".

• RX sensitivity table update, section 2.6

• Section 2.8, Temperature ranges update

15. DOCUMENT HISTORY

Revision Date Changes

0 2019-12-06 First issue

1 2020-06-16

In the table of chapter 3.1 the "Auxiliary" section title has been changed in Auxiliary (USIF1).

The title of chapter 5.8.4.2 has been changed from "Modem serial port 2" in "Modem serial port 2 (USIF1)".

The title of chapter 5.8.4.1 has been changed from "Modem serial port 1" in "Modem serial port

2 2020-07-01 • Power consumption section 4.2 update

• ON/OFF/WAKE pin update, section 5

• GNSS section 8 update

3 2020-07-22 • Conformity assessment update with ANATEL

4 2020-09-23 • Section 2.5, TX Power update

1VV0301632 Rev. 4 Page 85 of 86 2020-09-23

Page 86

Mod. 08

1.2017]

05 2017-01 Rev.6

Telit ML865G1 User Manual

NOTICE

COPYRIGHTS

COMPUTER SOFTWARE COPYRIGHTS

USAGE AND DISCLOSURE RESTRICTIONS

APPLICABILITY TABLE

Contents

1. INTRODUCTION

Scope

Audience

Contact Information, Support

Text Conventions

Related Documents

2. GENERAL PRODUCT DESCRIPTION

Overview

Product Variants and Frequency Bands

Target Market

Main features

TX Output Power

RX Sensitivity

2.6.1. ML865G1-WW

Mechanical Specifications

2.7.1. Dimensions

2.7.2. Weight

Temperature Range

3. PINS ALLOCATION

Pin-out

Pin Layout

4. POWER SUPPLY

Power Supply Requirements

Power Consumption

4.2.1. Idle mode

4.2.2. ML865G1-WW Connected Mode

General Design Rules

4.3.1. Electrical Design Guidelines

4.3.1.1. +5V Source Power Supply Design Guidelines

4.3.1.2. +12V Source Power Supply Design Guidelines

4.3.1.3. Battery Source Power Supply Design Guidelines

4.3.2. Thermal Design Guidelines

4.3.3. Power Supply PCB layout Guidelines

RTC supply

VAUX Power Output

5. DIGITAL SECTION

Logic Levels

Power On

Auto Power On

Power Off

Unconditional Shutdown

Wake from deep sleep mode

Fast power down

5.7.1. Fast Shut Down by Hardware

5.7.2. Fast Shut Down by Software

Communication ports

5.8.1. USB 2.0 HS

5.8.2. SPI

5.8.3. SPI Connections

5.8.4. Serial Ports

5.8.4.1. Modem serial port 1 (USIF0)

5.8.4.2. Modem serial port 2 (USIF1)

5.8.4.3. RS232 level translation

General purpose I/O

5.9.1. Using a GPIO as INPUT

5.9.2. Using a GPIO as OUTPUT

5.9.3. Indication of network service availability

External SIM Holder

ADC Converter

5.11.1. Using ADC Converter

Forced USB boot

6. RF SECTION

Bands Variants

TX Output power

RX Sensitivity

Antenna requirements

6.4.1. PCB Design guidelines

6.4.2. PCB Guidelines in case of FCC Certification

6.4.2.1. Transmission line design

6.4.2.2. Transmission Line Measurements

6.4.2.3. Antenna Installation Guidelines

7. AUDIO SECTION

Electrical Characteristics