Teledyne PCI Express User Manual

Protocol Solutions Group 3385 Scott Blvd. Santa Clara, CA 95054 Tel: +1/408.727.6600 Fax: +1/408.727.6622

PCI Express® 3.0 Mid-Bus Probe

Installation and Usage Manual

For use with

Summit™ T3-16 and Summit T3-8 Systems

September 2013 (V1.3)

Teledyne LeCroy PCIe 3.0 Mid-Bus Probe Installation Guide Version 1.2

Document Disclaim er

The information contained in this document has been carefully checked and is believed to be reliable. However, no responsibility can be assumed for inaccuracies that may not have been detected.

Teledyne LeCroy reserves the right to revise the information presented in this do cum ent withou t notice or penalty.

Trademarks and Servicemarks

Teledyne LeCroy, Summit, Summit T3-8 and Summit T3-16 are trademarks of Teledyne LeCroy Corporation.

Microsoft and Windows are registered trademarks of Microsoft Inc. PCI Express and PCIe are registered trademarks of the PCI-SIG.

All other trademarks are property of their respective companies.

should contain this copyright notice.

Part Number: 919595-00

Teledyne LeCroy PCIe 3.0 Mid-Bus Probe Installation Guide Version 1.2

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Table of Contents

1 INTRODUCTION ...................................................................................................................................... 4

2 PROBE COMPONENTS ............................................................................................................................ 6

3 MECHANICAL DESIGN ............................................................................................................................ 7

3.1 Probe Footprints ............................................................................................................. 7

3.2 Mid-bus Probe Retention ................................................................................................ 9

3.3 Probe Connection to Analyzer ........................................................................................ 9

3.4 Probe Keepout Volume ................................................................................................. 10

3.5 Reference Clock Probe Attachment .............................................................................. 10

3.6 Daisy Chain Cable (for x16 applications) .................................................................... 10

4 ELECTRICAL DESIGN ........................................................................................................................... 12

4.1 Probe Loading Effect .................................................................................................... 12

4.2 Overview of Probe - Pin Assignments .......................................................................... 12

4.3 Pin Assignments for Full-size Probe Connectors ......................................................... 13

4.4 Pin Assignments for Half-size Probe Connectors ......................................................... 24

5 INSTALLATION ..................................................................................................................................... 28

5.1 Reference Clock Cable .................................................................................................. 31

5.2 Daisy Chain Cable ........................................................................................................ 31

6 DUAL PROBE POD SETUP USING EXTERNAL CLOCKING ........................................................................ 32

7 RECORDING TRAFFIC ........................................................................................................................... 33

8 ORDERING INFORMATION ..................................................................................................................... 34

Teledyne LeCroy PCIe 3.0 Mid-Bus Probe Installation Guide Version 1.2

1 Introduction

Teledyne LeCroy offers a wide variety of ways to connect PCI Express protocol analyzers to products under test. There are four common methods: Interposers, Specialty Probes, Mid-Bus Probes and Multilead Probes.

If the product uses a standard PCI Express card connector, an interposer is used which is inserted between the PCIe Card and the card slot. The interposer taps off the data traffic to allow the analyzer to monitor and record traffic with minimal perturbation of the electrical interface.

Specialty probes are used with specific card configurations, and are used in the same manner as an interposer card (in fact a specialty probe is an interposer card designed for a specific interface). Teledyne LeCroy supports a range of specialty probes including ExpressCard, AMC, XMC, Mini Card, External Cable, ExpressModule, and HP Blade Server interfaces.

If the product has an embedded PCI Express bus (e.g., a bus which runs between chips on the same circuit board), then either a mid-bus probe or a multi-lead probe can be used. The mid-bus probe requires a connection footprint (see below) to be designed into the board. The multi-lead probe allows individual connections to each bus trace on the board.

The Teledyne LeCroy mid-bus probes are 16-channel differential signal probes that meet the demand for high-density signal access, accuracy and repeatability while providing connector-less attachment to the device under test. They are based upon the configuration that was initially recommended in the Intel PCI Express Mid-Bus Probing Footprint and Pinout Revision 1.0 document dated 8/05/03 and the subsequent revisions.

A mid-bus probe is one of the tools that can greatly help engineers debugging PCI Express buses. A PCI Express mid-bus probing solution provides direct probing capability of a PCI Express bus at a width of up to 16 lanes. To accommodate a mid-bus probe, a special pad layout is required to expose the PCI Express differential pairs on the surface of the target board.

Although not part of the PCI Express specifications, the industry has developed common mid-bus probe footprints for PCIe 1.0a, PCIe

2.0 and PCIe 3.0 applications (the “full-size” PCIe 3.0 footprint is shown on the right). These footprints are designed into the PCB. For PCIe 3.0 applications, the probe cable attachment uses a probe connector which is mounted the PCB as shown in the lower image on the right.

The appropriate footprint is recommended for use with all types of test equipment including protocol analyzers, logic analyzers and oscilloscopes. The required pad layout can be in x4 (half-size), x8 (full-size) or x16 (dual full-size) configurations depending on the maximum number of lanes that need to be probed. Al l f ootprint si zes su pport pr ob ing at reduc ed la ne widths (e.g., x1) and at lane widths up to the maximum footprint size. The illustration on page 3 shows the completed assembly for probing up to x8 configurations (for x16 configurations, a second Y-cable, probe pod, header cable assembly and probe connector are used, but connection is made to the same Summit T3-16 analyzer). As noted, a single full-size probe connector supports up to x8 lane widths bidirectional, but can also be configured to support x16 unidirectional (as can a half-size probe connector support x8 unidirectional).

Note that this manual documents the mid-bus footprint used for PCIe 3.0 applications; the probe footprints for PCIe 1.0a and PCIe 2.0 are covered in the Gen2 Mid-Bus Probe User Manual.

Teledyne LeCroy makes three versions of mid-bus probes, one for PCIe 1.0a (2.5 GT/s data rates, also referred to as “Gen1”) , one f or PCIe 2.0 (2.5 and 5 GT/s data rates, also referred to as “Gen2”) and one

Teledyne LeCroy PCIe 3.0 Mid-Bus Probe Installation Guide Version 1.2

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for PCIe 3.0 (2.5, 5 and 8 GT/s data rates, also referred to as “Gen3”). The PCIe 3.0 mid-bus probe is for use with the Summit T3-16 and Summit T3-8 analyzers, and is documented in this manual.

The PCIe 3.0 mid-bus probe, in a similar fashion to the PCIe 1.0a and PCIe 2.0 implementations that preceded it, is available in two versions: a full-size probe and a half-size probe. The full-size probe for is shown on page 6. It has a four-strand ribbon cable and a x16 connection header. A half-size probe has a two strand ribbon cable and a x8 connection header.

The part numbers and components of the T el edyne LeCroy PCIe 3.0 mid-bus probe are as follows: (1) PE058ACA-X PCIe 3.0 Mid-Bus Probe Kit, x8 Lane Width, Full-size Connector, which includes

• PE010UCA-X iPass Y-Cable

• PE055ACA-X PCIe 3.0 Mid-Bus Probe Pod

• PE057ACA-X PCIe 3.0 x8 Mid-bus Probe Cable

• PE009UCA-X Daisy Chain Clock Cable

• PE014UCA-X Reference Clock Cable

• PE047UIA-X Gen3 Mid-bus Probe Connector Full-size

(2) PE050ACA-X PCIe 3.0 Mid-Bus Probe Kit, x4 Lane Width, Half-size Modu le, w hich inc ludes :

• PE010UCA-X iPass Y-Cable

• PE055ACA-X PCIe 3.0 x8 Mid-Bus Pod

• PE056ACA-X Mid-bus Probe Cable (x4)

• PE009UCA-X Daisy Chain Clock Cable

• PE014UCA-X Reference Clock Cable

• PE054UIA-X PCIe 3.0 Mid-bus Probe Connector Half-Size

PE058ACA-X PCIe 3.0 x8 Full-Size Probe Kit

x1 x2 x4 x8 x16

Uni Bidir Uni Bidir Uni Bidir Uni Bidir Uni Bidir

*For bidirectional x16, two PE050ACA-X kits are required.

PE059ACA-X PCIe 3.0 x4 Half-Size Probe Kit

x1 x2 x4 x8 x16

Uni Bidir Uni Bidir Uni Bidir Uni Bidir Uni Bidir

Teledyne LeCroy PCIe 3.0 Mid-Bus Probe Installation Guide Version 1.2

2 Probe Components

• Y-Cable to Analyzer

• Gen3 Mid-Bus Probe Pod

• Probe Header Cable Assembly

• Probe Connector (mounted to board)

• Clocking Cable Cable* (not shown)

* The Intel-based mid-bus footprint specification only supplies differential lane signaling and ground reference. Should a reference clock (RefClk) be required a separate connection must be made. Teledyne LeCroy PCI Express protocol analyzers can use a reference clock probe in conjunction with the mid-bus analysis. Each mid-bus probe is equipped with one clock probe. The mid-bus reference clock probe is designed to facilitate capturing clock signals from the system board in the two configurations recommended by the Intel guideline, i.e., a tap off of an existing clock or a dedicated clock.

Teledyne LeCroy PCIe 3.0 Mid-Bus Probe Installation Guide Version 1.2

3 Mechanical Design

This section describes footprint dimensions, keepout volumes, and probe pin assignments.

3.1 Probe Footprints

The Mid-bus Probe is fully compatible with the standardized mid-bus footprint recommended by the Intel guideline, as shown in the following figures.

Full-Size Probe Footprint

Teledyne LeCroy PCIe 3.0 Mid-Bus Probe Installation Guide Version 1.2

Half-Size Probe Footprint

Teledyne LeCroy PCIe 3.0 Mid-Bus Probe Installation Guide Version 1.2

The PCB layout of a PCIe 3.0 mid-bus footprint would look as follows:

Full-Size PCIe 3.0 Probe Footprint Half-Size PCIe 3.0 Probe Footprint

3.2 Mid-bus Probe Retention

To prepare a circuit board for PCI Express mid-bus probing, the midbus footprint has to be laid out onto the target system board and a probe connector has to be attached to the board. Attachment of the probe connector is simple and quick. There are two through-hole screws and one protrusion key underneath the probe connector. Align the key of the probe connector with the keying/alignment hole in the mid-bus footprint on the target system board, and connect the small screws (supplied) through the PCB and into the threaded holes on the underside of the Mid-bus connector module, and tighten the screws to ensure good contact between the contacts of the connector and the pads on the PCB. The mid-bus probe can then be attached to the target system board through the probe connector to provide mechanical support for pin-to-pin alignment. The mid-bus cable has 2 retention screws that connect to the probe connector to hold the probe in place.

NOTE: The attachment screws supplied will provide secure attachment for most PCB designs. If the PCB is very thick, the screws may not be long enough to pass through the PCB and securely attach the Mid-bus connector module, in which cases longer screws will be needed. The screws supplied are 5mm long (McMaster-Carr P/N 91292A005), and longer lengths can be obtained directly from McMaster-Carr in 6mm (91292A006), 8mm (91292A008), or longer lengths as needed.

The probe connector should not be confused with a PCB connector because it is not part of the electrical circuits of either the target system or the probe.

PCIe 3.0 probe connectors can be purchased through Teledyne LeCroy:

• Full-size: P/N PE047UIA-X

• Half-size: P/N PE054UIA-X

3.3 Probe Connection to Anal yz er

The bus signals captured by the mid-bus probe are connected to a mid-bus probe pod for amplification. This reduces the load imposed by the mid-bus probe on the target system, while allowing a longer cable to attach to the Teledyne LeCroy PCI Express protocol analyzer. The Teledyne LeCroy PCI Express protocol analyzer can then interpret these signals for full decoding and protocol analysis.

Teledyne LeCroy PCIe 3.0 Mid-Bus Probe Installation Guide Version 1.2

Signal

Pin Number

REFCLKp

1 (or 3)

Unused

REFCLKn

3 (or 1)

3.4 Probe Keepout Volume

As with any connection to a PCB, sufficient clearance must be allowed around the point where the probe will connect. This is defined as the keep-out volume, which must be kept clear of other components mounted on the PCB.

The probe keepout volumes are shown in the diagrams in Section 3.1

3.5 Reference Clock Probe Attachment

Should SSC clocking be used in the system under test or if the link varies the bit rate by more than 100 MHz ± 300ppm (see Section 4.3.7 of Base Spec 3.0), a reference clock tap may be required. The connection from the reference clock to the analyzer is a 3-pin header (1 by 3, 0.050” center spacing) which is placed on the clock signal transmission line of the DUT. The PE014UCA-X Reference Clock Cable provides a three-pin micro socket that connects from this header to the CLK IN port on the Mid-Bus Pod.

If the reference clock is sampled by tapping off an existing clock, the header shall be located on the existing clock transmission line, where a high impedance clock probe from the mid-bus probe is connected with no significant loading effects. In the case of a dedicated clock, the header shall be located at the end of a dedicated clock transmission line without termination, where a 50-Ohm cable is connected and the termination for the clock signal is provided on the mid-bus probe board.

The connectivity of the clock header pins follows the following table:

Note that the analyzer is not sensitive to the polarity of the reference clock. Therefore, the probe can be plugged onto the pin header in either orientation.

The following 3-pin header can be used for the reference clock:

Samtec Part No: TMS-103 (Vertical Orientation)

The reference clock is captured separately with a dedicated probe cable. Considering the possibility that one clock may be shared between two physically separated mid-bus probes, each mid-bus probe pod is equipped with a reference clock output port. The reference clock probe can capture signals from the target system or receive a duplicated reference clock from another mid-bus probe board.

3.6 Daisy Chain Cable (for x16 appl ic a t ions)

A single mid-bus probe pod can capture traffic on bus widths up to x8. If x16 lane widths are required (e.g., when using a Summit T3-16 Analyzer with a x16 device), two Mid-Bus Probe Pods are required.

In this configuration, one of the pods is connected to the DUT to tap the Reference Clock signal, and the second pod is “daisy-chained” to the first pod using the PE009UCA-X Daisy Chain Cable. Connect the Ref Clock cable to the CLK IN port of the first pod, and connect the Daisy Chain Cable between the CLK OUT port of the first pod and the CLK IN port of the second pod.

Teledyne LeCroy PCIe 3.0 Mid-Bus Probe Installation Guide Version 1.2

Mid-bus Probe Setup for x16 lane widths (using Summit T3-16 Analyzer, Clocking Cable not shown)

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