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TLA5200 Series Logic Analyzer

ZZZ

Product Speciﬁcations & Performance Veriﬁcation

Technical Reference

*P077250201*

077-2502-01

TLA5200 Series Logic Analyzer

ZZZ

Product Speciﬁcations & Performance Veriﬁcation

Technical Reference

This document applies to TLA System Software Version

5.1SP1 and above

Warning

These servicing instructions are for use by qualiﬁed personnel only. To avoid personal injury, do not perform any servicing unless you are qualiﬁed to do so. Refer to all safety summaries prior to performing service.

www.tektronix.com

077-2502-01

Copyright © Tektronix. All rights reserved. Licensed software products are owned by Tektronix or its subsidiaries or suppliers, and are protected by national copyright laws and international treaty provisions.

Tektronix products are covered by U.S. and foreign patents, issued and pending. Information in this publication supersedes that in all previously published material. Speciﬁcations and price change privileges reserved.

TEKTRONIX and TEK are registered trademarks of Tektronix, Inc.

MagniVu and iView are registered trademarks of Tektronix, Inc.

Contacting Tektronix

Tektronix, Inc. 14200 SW Karl Braun Drive P.O . Bo x 50 0 Beaverton, OR 97077 USA

For product information, sales, service, and technical support:

In North America, call 1-800-833-9200. World wi de, v i sit www.tektronix.com to ﬁnd contacts in your area.

Table of Contents

General Safety Summary ......................................................................................... iv

Service Safety Summary.......................................... ................................ ................ vi

Preface ............................................................................................................. vii

Related Doc

Speciﬁcations .................. .................................. ................................ ................... 1

External Oscilloscope (iView) Characteristics ..................... ................................ ............ 15

Performance Veriﬁcation Procedures............................................................................ 17

Summary Veriﬁcation ........................................................................................ 17

Certiﬁcation . ................................ ................................ .................................. 17

Test Equ

Functional Veriﬁcation ....... ................................ .................................. .............. 19

Performance Veriﬁcation........................... ................................ .......................... 21

Checking the 10 MHz System Clock (CLK10) . ................................ .......................... 22

Threshold Accuracy .......................................................................................... 23

Setup and Hold.................................... .................................. .......................... 26

Fixtures.................. .................................. ................................ .................... 30

Test

Threshold Accuracy Test Fixture ........................................................................... 30

Setup and Hold Test Fixture ............................... ................................ .................. 31

Calibration Data Report........................................... ................................ ................ 33

TLA5200 Series............................................................................................... 33

Test Data....................................................................................................... 33

umentation ..................................................................................... vii

ipment................................ .................................. .............................. 18

TLA5200 Series Product Speciﬁcations & Performance Veriﬁcation i

Table of Contents

List of Figure

Figure 1: Dimensions of the TLA5200 series logic analyzer................. ................................ 14

Figure 2: De

Figure 3: Setting trigger parameters . ... ... . ... ... . ... ... . ... ... . .. . ... ... . ... ... . ... ... . ... ... . ... ... . .. . ... .... 24

Figure 4: Set the trigger states ............................. .................................. .................... 28

Figure 5: Threshold Accuracy test ﬁxture ...................................................................... 30

Figure 6: Solder square pins to the SMA connector......... ................................ .................. 31

Figure 7: Solder the SMA connectors together ........................ ................................ ........ 32

Figure 8:

ﬁning group parameters............................................................................ 23

Completed ﬁxture with termination and coupler ..... .................................. ............ 32

ii TLA5200 Series Product Speciﬁcations & Performance Veriﬁcation

List of Tables

Table i: Related Documentation ............. ................................ ................................ ... vii

Table 1: Atm

Table 2: TLA5200 input parameters with probes ...................... ................................ ......... 2

Table 3: TLA5200 timing latencies .............................................................................. 2

Table 4: TLA5200 external signal interface........................ ................................ ............. 3

Table 5: TLA5200 channel width and depth .................................................................... 5

Table 6: Reference clock (CLK10) ........................ ................................ ....................... 5

Table 7: T

Table 8: TLA5200 trigger system ................................................................................ 8

Table 9: TLA5200 MagniVu feature ............................................................................ 10

Table 10: TLA5200 Data Placement ............................................................................ 10

Table 11: TLA5200 Data handling .............................................................................. 11

Table 12: TLA5200B internal controller........................................................................ 11

13: TLA5200 internal controller.......................................................................... 11

Table

Table 14: TLA5200 display system ....... ................................ ................................ ...... 12

Table 15: TLA5200 front-panel interface....................................................................... 13

Table 16: TLA5200 rear-panel interface...................................... .................................. 13

Table 17: TLA5200 AC power source ...... .................................. ................................ .. 13

Table 18: TLA5200 cooling...................................................................................... 13

ble 19: TLA5200 mechanical characteristics................................................................ 14

Table 20: External oscilloscope (Integrated View or iView) characteristics. . ... ... . ... ... . ... ... . ... ... . .. 15

Table 21: TDS1000, TDS1000B, TDS2000, and TDS2000B Series oscilloscope waveform edge

alignment ...................................................................................................... 16

Table 22: Test equipment ....................... ................................ ................................ .. 18

Table 23: Functional veriﬁcation procedures....................... .................................. .......... 19

Table 24: Parameters checked by veriﬁcation procedures .................................................... 21

ospheric characteristics............................................................................. 1

LA5200 clocking ....................................................................................... 6

Table of Contents

TLA5200 Series Product Speciﬁcations & Performance Veriﬁcation iii

General Safety Summary

General Safet

To Avoid Fire or Person al

Injury

ySummary

Review the fo this product or any products connected to it.

To avoid potential hazards, use this product only as speciﬁed.

Only qualiﬁed personnel should perform service procedures.

While using this product, you may need to access other parts of a larger system. Read the safety sections of the other component manuals for warnings and cautions related to operating the system.

Use Proper Power Cord. Use only the power cord speciﬁed for this product and certiﬁed for the country of use.

Connect and Disconnect Properly. Do not connect or disconnect probes or test leads while they are connected to a voltage source.

Ground the Product. This product is grounded through the grounding conductor of the power cord. To avoid electric shock, the grounding conductor must be connected to eart terminals of the product, ensure that the product is properly grounded.

llowing safety precautions to avoid injury and prevent damage to

h ground. Before making connections to the input or output

Observe All Terminal Ratings. To avoid ﬁre or shock hazard, observe all ratings and markings on the product. Consult the product manual for further ratings information before making connections to the product.

The inputs are not rated for connection to mains or Category II, III, or IV circuits.

Power Disconnect. The power cord disconnects the product from the power source. Donotblockthepowercord;itmustremain accessible to the user at all times.

Do Not Operate Without Covers. Do not operate this product with covers or panels removed.

Do Not Operate With Suspected Failures. If you suspect that there is damage to this product, have it inspected by qualiﬁed service personnel.

Avoid Exposed Circuitry. Do not touch exposed connections and components when power is present.

Use Proper Fuse. Useonlythefusetypeandratingspeciﬁed for this product.

Do Not Operate in Wet/Damp Conditions.

Do Not Operate in an Explosive Atmosphere.

Keep Product Surfaces Clean and Dry.

Provide Proper Ventilation. Refer to the manual’s installation instructions for

details on installing the product so it has proper ventilation.

iv TLA5200 Series Product Speciﬁcations & Performance Veriﬁcation

General Safety Summary

Terms in this Manual

Symbols and Terms on the

Product

These terms may

WAR N ING. Warning statements identify conditions or practices that could result

in injury or loss of life.

CAUTION. Caution statements identify conditions or practices that could result in

damage to this product or other property.

These terms may appear on the product:

DANGER in the marking.

WAR NI NG read the marking.

CAUTIO

The following symbol(s) may appear on the product:

appear in this manual:

dicates an injury hazard immediately accessible as you read

indicates an injury hazard not immediately accessible as you

N indicates a hazard to property including the product.

TLA5200 Series Product Speciﬁcations & Performance Veriﬁcation v

Service Safety Summary

Service Safet

y Summary

Only qualiﬁe Safety Summary and the General Safety Summary before performing any service procedures.

Do Not Service Alone. Do not perform internal service or adjustments of this product unless another person capable of rendering ﬁrst aid and resuscitation is present.

Disconnect Power. To avoid electric shock, switch off the instrument power, then disconnect the power cord from the mains power.

Use Care When Servicing With Power On. Dangerous voltages or currents may exist in disconnect test leads before removing protective panels, soldering, or replacing components.

To avoid electric shock, do not touch exposed connections.

d personnel should perform service procedures. Read this Service

this product. Disconnect power, remove battery (if applicable), and

vi TLA5200 Series Product Speciﬁcations & Performance Veriﬁcation

Preface

Related Documentation

This document lists the characteristics and speciﬁcations of the TLA5200 and TLA5200B series logic analyzers. It also includes the performance veriﬁcation procedures. otherwise noted. Microprocessor-related products and individual logic analyzer probes have their own documentation for characteristics and speciﬁcations.

To prevent personal injury or damage consider the following requirements before attempting service:

The procedures in this manual should be performed only by qualiﬁed service personnel.

Read the General Safety Summary and Service Safety Summary found at the beginning of this manual.

Be sure to follow all warnings, cautions, and notes in this manual.

The following table lists related documentation available for your logic analyzer. The documentation is available on the TLA Documentation CD included with your logic analyzer, and on the Tektronix Web site (www.Tektronix.com).

All references to TLA5200 also apply to TLA5200B, unless

To obtain documentation not speciﬁed in the table, contact your local Tektronix representative.

Table i: Related Documentation

Item Purpose Location

TLA Quick Start User Manual

Online Help

Installation Quick Reference Cards Basic installation information

Installation Manuals

YZs of Logic A nalyzers

TLA Product Speci ﬁcations Speciﬁcations for other TLA products

Basic operational overview

In depth operation and UI help

Detailed ﬁrst-time installation information

Introduction to logic analyzer basics

TLA5200 Series Product Speciﬁcations & Performance Veriﬁcation vii

Preface

Table i: Related Documentation (cont.)

Item Purpose Location

TPI.NET Documentation

Detailed information for controlling the logic analyzer u sing .NET

Field upgrade kits

Optional Service Manuals Self-service documentation for modules

TLA Application Software Release N otes Software description, compatibility,

Upgrade information for your logic analyzer p

and mainframes

impact of installation, upgrade, and operational notes, and known issues.

roduct

changes, contact information,

Go to Start→All Programs→Tektronix logic Analyzer→TLA Release Notes

viii TLA5200 Series Product Speciﬁcations & Performance Veriﬁcation

Speciﬁcations

The following tables list the speciﬁcations for the TLA5200B and TLA5200 series logic analyzers. All references to TLA5200 also apply to TLA5200B, unless otherwise no

ted. All speciﬁcations are guaranteed unless noted Typ i ca l . Typical characteristics describe typical or average performance and provide useful reference information.

Speciﬁcations that are marked with the indirectly) in the Performance Veriﬁcation chapter of this document.

The performance limits in this speciﬁcation are valid with these conditions:

For op documentation for any external oscilloscopes used with your Tektronix logic analyzer to determine the warm-up period and signal-path compensation requirements.

Table 1: Atmospheric characteristics

racteristic

Cha

Temperature

Relative humidity

Altitude

cription

Des

rating (no media in CD or DVD drive)

Ope

°C to +50 °C, 15 °C/hr m aximum gradient, noncondensing (derated 1 °C per 305 m (1000 ft)

+5 above 1524 m (5000 ft) altitude)

Nonoperating (no media in drive)

-20 °C to +60 °C, 15 °C/hr maximum gradient, noncondensing

Operating (no media in drive)

20% to 80% relative humidity, noncondensing. Maximum wet bulb temperature: +29 °C (derates relative humidity to approximately 22% at +50 °C).

Nonoperating (no media in drive)

8% to 80% relative humidity, noncondensing. Maximum wet bulb temperature: +29 °C (derates relative humidity to approximately 22% at +50 °C).

Operating

To 3000 m (9843 ft), (derated 1 °C per 305 m (1000 ft) above 1524 m (5000 ft) altitude.

Nonoperating

12,190 m (40,000 ft )

symbol are checked directly (or

The instr

ument must be in an environment with temperature, altitude, humidity, and vibration within the operating limits described in these speciﬁcations.

The instrument must have had a warm-up period of at least 30 minutes.

The ins

trument must have been calibrated/adjusted at an ambient temperature

between +20 °C and +30 °C.

timum performance using an external oscilloscope, please consult the

TLA5200 Series Product Speciﬁcations & Performance Veriﬁcation 1

Speciﬁcations

Table 2: TLA520

0 input parameters with probes

Characteristic Description

Threshold Accuracy

Threshold range and step size

±100 mV

Settable from +4.5 V to -2 V in 5 mV steps

Threshold channel selection 16 threshold groups assigned to channels. P6410, P6417, P6418, and

P6419 probes have two threshold settings, one for the clock/qualiﬁer channel and one for the data channels. P6434 probes have four threshold settings, one for each of the clock/qualiﬁer channels and two for the data channels (one per 16 data channels).

Channel-to-channel skew

Channel-to-channel skew (Typical)

Sample uncertainty

≤ ±150 ps maximum

≤ ±75 ps

Asynchronous

Sample period

Synchronous

125 ps

Input voltage range –2.5 to +5 V

Probe input resistance (Typical) 20 kΩ

Probe in

(Typical)

put capacitance

P6410, P

P6418 1.4 pF data channels

6417, P6434

2pF

2pFCLK

/Qual channels

P6419 < 0.7 pF

Minimum slew rate (Typical) 0.2 V/ns

Maximum operating signal 6.0 V

Probe

overdrive

, P6417, P6418,

P6410 P6419

P6434

p-p

±250 mV or ±25% of signal swing minimum required beyond threshold, whichever is greater

±300 mV or ±25% of signal swing minimum required beyond threshold,

chever is greater

whi

±4 V maximum beyond threshold

imum nondestructive input signal to probe

Max

nimum input pulse width signal (single channel)

(Typical)

Delay time from probe tip to module input probe

±15

5 ns (P6434)

1.25 ns (P6410, P6417, P6418, P6419)

33 ns ±100ps

connector (Typical)

Table 3: TLA5200 timing latencies

Characteristic Description

System Trigger and External Signal Input Latencies

(Typical)

External System Trigger Input to LA Probe Tip

External Signal Input to LA Probe Tip via Signal 3, 4 –656 ns + Clk

External Signal Input to LA Probe Tip via Signal 1, 2

–656 ns

–656 ns + Clk

2 TLA5200 Series Product Speciﬁcations & Performance Veriﬁcation

Speciﬁcations

Table 3: TLA5200 timing latencies (cont.)

Characteristic Description

System Trigger and External Signal Output Latencies (Typical)

All system trigger and external signal input latencies are measured from a falling-ed ge transition (active true low) with signals measured in the wired-OR conﬁguration.

In the Waveform window, triggers are always marked immediately except when delayed to the ﬁrst sample. In the Listing window, triggers are always marked on the next sample period following their occurrence.

CLK represents the time to the next master clock at the destination. In Normal clocking, this represents the delta time to the next sample clock. In External clocking, this represents the time to the next master clock generated by the setup of the clocking state machine and the supplied SUT clocks and qualiﬁcation date.

Signals 1 and 2 (ECLTRG 0, 1) are limited to a "broadcast" mode of operation, where only one source is allowed to drive the signal node at any one time. That single source can be used to drive any combination of destinations.

SMPL represents the time from the event to the next valid data sample at the probe tip input. In the Normal Internal clock mode, this represents the delta time to the next sample c lock. In the MagniVu Internal clock mode, this represents 125 ps. In the External clock mode, this represents the time to the next masterclock generated by the setup of the clocking state machine, the SUT-supplied clocks, and the qualiﬁcation data.

All signal output latencies are validated to the rising edge of an active (true) high output.

LA Probe Tip to External S ystem Trigger Out

LA Probe Tip to External Signal Out via Signal 3,

LA Probe Tip to External Signal Out via Signal 1, 2

456

OR function 772 ns + SMPL

AND function 772 ns + SMPL

normal function 772 ns + SMPL

inverted logic on backplane

778 ns + SMPL

774 ns + SMPL

Table 4: TLA5200 external signal interface

Characteristic Description

System trigger input

External signal input

Input destination

Input levels

Input mode

Minimum pulse width 12 ns

Active period Accepts system triggers during valid acquisition periods via real-time

Maximum input voltage 0 to +5 V peak

Input destination

Input levels

Input mode

Input bandwidth

Active period Accepts signals during valid acquisition periods via real-time gating.

Maximum input voltage 0 to +5 V peak

TTL compatible input via rear panel mounted BNC connectors

System trigger

TTL compatible input

≥ 2.0 V

≤ 0.8 V

Falling edge sensitive, latched (active low)

gating, resets system trigger input latch between valid acquisition periods.

TTL compatible input via rear panel mounted BNC connectors

Signal 1, 2, 3, 4

TTL compatible input

≥ 2.0 V

≤ 0.8 V

Active (true) low, level sensitive

Signal 1, 2 Signal 3, 4

50 MHz square wave minimum 10 MHz square wave minimum

TLA5200 Series Product Speciﬁcations & Performance Veriﬁcation 3

Speciﬁcations

Table 4: TLA5200 external signal interface (cont.)

Characteristic Description

System trigger output

Source selection System trigger

Source mode Active (true) low, falling edge latched

Active period

Output levels

Output protection Short-circuit protected (to ground)

External signal output

Source selection Signal 1, 2, 3, 4, or 10 MHz clock

Output modes level sensitive

Output levels

Active period

Output protection Short-circuit protected (to ground)

The input bandwidth speciﬁcation only applies to signals to the External Signal input; it does not apply to signals applied to the External Signal input and sent back to the External Signal output.

The output bandwidth speciﬁcation only applies to signals to the External Signal output; it does not apply to signals applied to the External Signal output and sent back to the External Signal input.

TTL compatible output via rear panel mounted BNC connectors

Outputs system trigger state during valid acquisition period, resets system

trigger output to false state between valid acquisitions

50 Ω back terminated TTL-compatible output

≥4 V into open circuit

≥ 2Vinto50Ω to ground

≤ 0.7 V sinking 10 mA

TTL compatible outputs via rear panel mounted BNC connectors

User deﬁnable active (true) low or active (true) high

50 Ω back terminated TTL output

≥4 V into open circuit

≥2Vinto50Ω to ground

≤ 0.7 V sinking 10 mA

Signal 1, 2 Signal 3, 4Output bandwidth

50 MHz square wave minimum 10 MHz square wave minimum

Outputs signals during valid acquisition periods, resets signals to false

state between valid acquisitions

Outputs 10 MHz clock continuously

4 TLA5200 Series Product Speciﬁcations & Performance Veriﬁcation

Speciﬁcations

Table 5: TLA520

0 channel width and depth

Characteristic Description

Product

TLA5201

TLA5202

TLA5203

TLA5204

Acquisition memory depth

Product Memory depth

TLA520XB 2 M or optionally 8 M or 32 M

TLA520X 512 K or optionally 2 or 8 M

PowerFlex options

Table 6: Reference clock (CLK10)

Characteristic Description

Clock accuracy

10 MHz ±100 ppm

ChannelsNumber of channels

32 data and 2 c

lock

64 data and 4 clock

96 data, 4 clock, and 2 qualiﬁer

128 data, 4 c

samples

lock, and 4 qualiﬁer

TLA5200 Series Product Speciﬁcations & Performance Veriﬁcation 5

Speciﬁcations

Table 7: TLA520

0 clocking

Characteristic Description

Asynchronous

Internal sampling period

clocking

500 ps to 50 ms store data when it has changed (transitional storage)

2 ns minimum for all channels

1nsminimum

0.5 ns minimum for quarter c hannels (using 4:1 demultiplex mode)

Minimum recognizable word2(across all channels)

Channel-to-channel skew + sample uncertainty

Example: for a 2 ns sample period and a P6419, or P6434 Probe = 400 ps +2ns=2.4n

Synchron

Number of

ous clocking

master clock channels

Product

TLA5201

TLA5202

TLA5203

TLA5204

Number of qualiﬁer channels

Product

TLA5201

TLA5202

TLA52

TLA5204

Setup and hold window size

Setup and hold window size (Typical)

1 ns maximum, any clock to any single data or qualiﬁer channel

1.5 ns, all channels

in a 1-2-5 sequence. Storage control can be used to only

for half channels (using 2:1 demultiplex mode)

Clock Cha

nnels

Qualiﬁer Channels

6 TLA5200 Series Product Speciﬁcations & Performance Veriﬁcation

Speciﬁcations

Table 7: TLA5200 clocking (cont.)

Characteristic Description

Setup and hold w indow range For each channel, the setup and hold window can be moved from +8.0 ns

(Ts) to -8.0 ns (Ts) in 0.125 ns steps. T he hold time follows the setup time by the setup and hold window size.

Maximum synchronous clock rate

2X Demux clocking

TLA5203, TLA5204

TLA5201, TLA5202

Time between Demultiplex clock edges (Typical) Same limitations as normal synchronous acquisition

4X Demux clocking

TLA5203, TLA5204

235 MHz in full speed mode (4.25 ns minimum between active clock edges)

Any individual channel may be demultiplexed with its partner channel. Channels demultiplex as follows:

A3(7:0) to/from

A2(7:0) to/from

A1(7:0) to/from

A0(7:0) to/from

C3(7:0) to/from

C2(7:0) to/from

E3(7:0) to/from

E2(7:0) to/from

CK3 to/from

CK2 to/from

CK1 to/from

CK0 to/from

Any individual channel may be demultiplexed with its partner channel. Channels demultiplex as follows:

A3(7:0) to/from

A2(7:0) to/from

A1(7:0) to/from

A0(7:0) to/from

Unlike 2X demultiplexing, the channels within a group of four cannot arbitrarily drive the others.

E3(7:0) to

A3(7:0) to

A1(7:0) to

C3(7:0) to

CK3 to

CK1 to

D3(7:0)

D2(7:0)

D1(7:0)

D0(7:0)

C1(7:0)

C0(7:0)

E1(7:0) (TLA5204 only)

E0(7:0) (TLA5204 only)

Q2 (TLA5204 only)

Q3 (TLA5204 only)

C3(7:0)

C2(7:0)

D1(7:0) (TLA5202 only)

D0(7:0)( TLA5202 only)

E2(7:0), E1(7:0), E0(7:0) (TLA5204 only)

A2(7:0), D3(7:0), D2(7:0)

A0(7:0), D1(7:0), D0(7:0)

C2(7:0), C1(7:0), C0(7:0)

CK2, Q3, Q2 (TLA5204 only)

CK0, Q1, Q0

TLA5200 Series Product Speciﬁcations & Performance Veriﬁcation 7

Speciﬁcations

Table 7: TLA5200 clocking (cont.)

2X Demux clocking

TLA5201, TLA5202

Unlike 2X demultiplexing, the channels within a group of four cannot

arbitrarily drive the others.

A1(7:0) to

C3(7:0) to

A0(7:0), D1(7:0), D0(7:0) TL:A5202 only

C2(7:0), A3(7:0), A2(7:0)

Time between Demultiplex clock edges (Typical) Same limitations as normal synchronous acquisition

Clocking state machine

Pipeline delays

Each channel can be programmed with a pipeline delay of 0 through 7

active clock edges.

sible to use storage control and only store data when it has changed (transitional storage).

It is pos Applies to asynchronous clocking only. Setup and hold window speciﬁcation applies to synchronous clocking only.

Any or all of the clock channels may be enabled. For an enabled clock channel, either the rising, falling, or both edges can be selected as the active clock edges. The clock channels are stored.

All qualiﬁer channels are stored. For custom clocking there are an additional 4 qualiﬁer channels on C2 3:0 regardless of channel width.

Table 8: TLA5200 trigger system

Characteristic Description

Triggering Resources

Word/Range recognizers

16 word recognizers. The word recognizers can be combined to form full width, double bounded, range recognizers. The following selections are available:

16 word recognizers

13 word recognizers

10 word recognizers

7 word recognizers

4 word recognizers

Range recognizer channel order

From most-signiﬁcant probe group to least-signiﬁcant probe group: C3 C2 C1 C0 E3 E2 E1 E0 A3 A2 D3 D2 A1 A0 D1 D0 Q3 Q2 Q1 Q0 CK3 CK2 CK1 CK0

Missing channels for instruments with fewer than 136 channels are omitted.

Glitch detector

Channel groups can be enabled to detect glitches.

Glitches are s ubject to pulse width variations of up to ±125 ps

Minimum detectable glitch pulse width (Typical)

Setup and hold v iolation detector

1.25 ns (single channel with P6434 probe)

1.0 ns (P6410, P6417, P6418, P6419 probe)

Any channel can be enabled to detect a setup or hold violation. The range is from 8.0 ns before the clock edge to 8.0 ns after the clock edge in 0.125 ns steps. The channel setup and hold violation size can be i ndividually programmed.

The range can be shifted towards the positive region by 0 ns, 4 ns, or 8 ns. With a 0 ns shift, the range is +8 ns to -8 ns; with a 4 ns shift, the range is +12 ns to -4 ns; with an 8 ns shift, the range is +16 ns to 0 ns. The sample point selection region is the same as the setup and hold window.

Any setup value is subject to variation of up to the channel skew speciﬁcation. Any hold value is subject to variation of up to the channel skew speciﬁcation.

0 range recognizers

1 range recognizer

2 range recognizers

3 range recognizers

4 range recognizers

8 TLA5200 Series Product Speciﬁcations & Performance Veriﬁcation

Speciﬁcations

Table 8: TLA5200 trigger system (cont.)

Characteristic Description

Transition detector

Counter/Timers 2 counter/timers, 51 bits wide, can be clocked up to 500 MHz.

External Signal In

External Trigger In A backplane input signal that causes both the main acquisition and the MagniVu acquisition

Active trigger resources

Trigger States

Trigger State sequence rate

er Machine Actions

Trigg

Main acquisition trigger Triggers the main acquisition memory.

Main trigger position

MagniVu™ acquisition trigger

MagniVu™ trigger position

crement & decrement counter

Reloadable word recognizer

Reloadable word recognizer latency

Start/Stop timer Either of the two counter/timers used as timers can be started or stopped.

Reset counter/timer Either of the two counter/timers can be reset.

Signal out

Trigger out A trigger out signal sent to the backplane to trigger other instruments.

Storage Control

Global storage Storage is allowed only when a speciﬁc condition is met. This condition can use any of the

16 transition detectors.

Any channel group can be enabled or disabled to detect a rising transition, a falling transition, or both rising and falling transitions between the current valid data sample and the previous valid data sample.

Maximum count is 2

Maximum time is 4.5 X 10

-1.

seconds or 52 days.

Counters and timers can be set, reset, or tested and have zero reset latency.

A backplane input signal.

to trigger if they are not already triggered.

16 maximum (excluding counter/timers)

Word recognizers are traded off one-by-one as External Signal In, glitch detection, setup and hold detection, or transition detection resources are added.

Same rate as valid data samples received, 500 MHz maximum.

Trigger position is programmable to any data sample (2 ns boundaries).

Triggering of MagniV memory is controlled by the main acquisition trigger machine.

The MagniV trigger position is programmable within 2 ns boundaries and separate from the

n acquisition memory trigger position.

mai

ther of the two counter/timers used as counters can be increased or decreased.

ads the current acquired data sample into the reference value of the word recognizer via

Lo a trigger machine action. All data channels are loaded into their respective word recognizer reference register on a one-to-one manner.

378 ns

When a counter/timer is used as a timer and is reset, the timer continues from the started or stopped state that it was in prior to the reset.

A signal sent to the backplane to be used by other instruments.

trigger machine resources except for the counter/timers. Storage commands deﬁned in the current trigger state will override the global storage control.

Global storage can be used to start the acquisition with storage initially turned on (default) or turned off.

TLA5200 Series Product Speciﬁcations & Performance Veriﬁcation 9

Speciﬁcations

Table 8: TLA5200 trigger system (cont.)

Characteristic Description

By event

Block storage

Glitch violation storage The acquisition memory can be enabled to store glitch violation information with each data

Setup and hold violation storage The acquisition memory can be enabled to store setup and hold violation information with each

e of External Signal In, glitch detector, setup and hold violation detector, or transition detector requires a trade-off of one word recognizer resource.

Each us Any glitch is subject to pulse width variation of up to the channel-to-channel skew speciﬁcation + 0.25 n s.

Any setup value is subject to variation of up to the channel skew speciﬁcation. Any hold value is subject to variation of the channel skew speciﬁcations.

Storage can be turned on or off; only the current sample can be stored. The event storage control overrides any global storage commands.

When enabled, 31 samples are stored before and after the valid sample.

Not allowed when glitch storage or setup and hold violation is enabled.

sample when asynchronous clocking is used. The probe data storage size is reduced by one half (the other half holds the violation information). The fastest asynchronous clocking rate is reduced to 4 ns.

data sample when synchronous clocking is used. The probe data storage size is reduced by one half (the o ther half holds the violation information). T he maximum clock rate in this mode is 235 MHz.

Table 9: TLA5200 MagniVu feature

Characteristic Description

MagniVu memory depth 16,000 samples per channel

MagniVu sampling period Data is asynchronously sampled and stored every 125 ps in a separate

high resolution memory. The storage speed may be changed (by software)

to 250 ps, 500 ps, or 1000 ps so that MagniVu memory covers more time

at a lower resolution.

Table 10: TLA5200 Data Placement

racteristic

Cha

stem time zero placement error (Typical)

ta correlation error (Typical)

elative timestamp accuracy (Typical)

Timestamp counter and resolution 125 ps resolution

cription

Des

±4 ns + backplane 10 MHz skew

l stored data is referenced to this point.

±200 ps + system time zero placement error

±100 ps + sample uncertainty + backplane 10 MHz clock jitter and

olerance

This speciﬁcationcanbeusedtoindicatetheaccuracyofatime

measurement between samples. When measuring between samples,

nly the time difference between samples should be used to i ndicate

accuracy. For example, if one sample has a timestamp of one hour and

another sample has a timestamp of one hour and 10 ms, the 10 ms is

the period of time used to determine the amount of error caused by the

10 MHz clock tolerance.

3.25 days duration

10 TLA5200 Series Product Speciﬁcations & Performance Veriﬁcation

Speciﬁcations

Table 11: TLA52

Characteristic Description

Nonvolatile memory retention time (Typical) Battery is integral to the NVRAM. Battery life is > 10 years.

00 Data handling

Table 12: TLA5200B internal controller

Characteristic Description

Operating system Microsoft Windows

Microprocessor

Main memory

Cache memory

Real-time clock and CMOS setups NVRAM

Hard disk drive

CD-DVD drive Standard PC compatible IDE (Integrated Device Electronics)

Floppy disk drive

Style 184 pin DDR2 SDRAM DIMM gold-plated

Speed 266 MHz DDR2 PC2100

Installed c onﬁguration

Maximum conﬁguration 4 GB (four 1 GB DIMMs)

Capacity

Style

Intel Celeron, 2.93 GHz

512 MB

Level 2 (L2) Write-back cache

256 KB

Integrated

Real-time clock/calendar. Standard and advanced PC CMOS setups. Battery life is typically > 3 years when the logic analyzer is not connected to line voltage. When connected to line voltage the life of the battery is extended. Lithium battery, CR2032

80 GB standard PC compatible IDE (Integrated Device Electronics) hard disk drive residing on a serial ATA interface.

Continually subject to change due to the fast-moving PC component environment. Storage capacities valid at product introduction.

CD-RW/DVD-R drive residing on an EIDE interface.

Continually subject to change due to the fast-moving PC component environment.

Standard 3.5 inch 1.44 MB PC compatible high-density, double-sided ﬂoppy disk drive on the USB bus

Table 13: TLA5200 internal controller

Characteristic Description

Operating system Microsoft Windows

Microprocessor

Main memory

Style 184 pin DIMM, 2 Sockets

Speed

Installed c onﬁguration

Intel Celeron, 2 GHz

PC2100 DDR SDRAM

100 MHz

512 MB loaded in one socket

TLA5200 Series Product Speciﬁcations & Performance Veriﬁcation 11

Speciﬁcations

Table 13: TLA5200 internal controller (cont.)

Characteristic Description

Real-time clock and CMOS setups, plug & play NVRAM retention time

Hard disk drive

CD-RW drive Standard PC compatible IDE (Integrated Device Electronics) CD-RW drive

Floppy disk drive

Battery life is typically > 3 years when the logic analyzer is not connected

to line voltage. When connected to line voltage the life of the battery is

extended. Lithium battery, CR2032

80 GB standard PC compatible IDE (Integrated Device Electronics) hard

disk drive residing on an EIDE interface.

Continually subject to change due to the fast-moving PC component

environment. Storage capacities valid at product introduction.

residing on an EIDE interface.

Continually subject to change due to the fast-moving PC component

environment.

Standard 3.5 inch 1.44 MB PC compatible high-density, double-sided

ﬂoppy disk drive.

Table 14: TLA5200 display system

Characteristic Description

Display memory

Display selection

play modes

Dis

ternal display

Ex drive

Primary display size (RAGE M1

hip)

Secondary display size (845GV chip)

8 MB SDRAM-onboard the ATI Mobility I video controller

Hardware sense of external SVGA monitor connected to the external primary display

ector prior to the BIOS boot sequence enables the operation of that display output.

conn The internal LCD display is enabled at all times. The internal LCD and the primary external displays operate at the same resolution (limited to 1024 X 768 on current TFT

) and display rates. Dynamic Display Conﬁguration 1 (DDC1) support for the

LCD external SVGA monitor is provided.

Three displays can be driven independently, the LCD display and two external displays. The LCD display and one of the external displays are driven from the ATI RAGE Mobility

chip and are the primary displays; the two displays are independent. A third display

M1 is the second external display port driven from the motherboard (secondary display).

TwoVGa, SVGA, or XGA-compatible analog output ports.

Display size selected via Windows

Resolution (pixels) Colors Refresh rates

1024 x 768, 1280 x 1024, or 1600 x 1200

Resolution (pixels) Colors Refresh rates

640 x 480

800 x 600

1024 x 768

1280 x 1024

1600 x 1200

1920 x 1440

256, 64 K , 16.8 M 60, 75, 85, 100

256, 64 K , 16.8 M

256, 64K

60, 75, 85

60, 75

12 TLA5200 Series Product Speciﬁcations & Performance Veriﬁcation

Speciﬁcations

Table 14: TLA5200 display system (cont.)

Characteristic Description

Internal D isplay

Classiﬁcation Thin Film Transistor (TFT) 10.4 inch active-matrix color LCD display; CCFL backlight;

intensity controllable via software.

Resolution 1024 x 768 pixels

Color Scale

Refresh rate

256K

Table 15: TLA5200 fr ont-panel interface

Characteristic Description

QWERTY ASCII to support naming of ﬁles, traces, and keyboard equivalents of

ng device inputs for menus.

pointi

l Function Knobs

Specia

Variou

s functions

Table 16: TLA5200 rear-panel interface

Characteristic Description

Parallel Interface Port (LPT) 25-pin sub-D Parallel Port Connector, Extended Parallel Port (EPP), or

Enhanced Capabilities Port (ECP)

Serial Interface Port (COM 1) 9-pin male sub-D connector to support RS-232 serial port

Two USB Ports Two USB 2.0 (Universal Serial Bus) compliant ports

SVGA Output Ports (SVGA OUT) 15-pin sub-D SVGA connectors (two each, one Primary, one Secondary)

Mouse Port

Keyboard Port

PS/2 compatible mouse port utilizing a m ini DIN connector

PS/2 compatible keyboard port utilizing a mini DIN connector

Table 17: TLA5200 AC power source

Characteristic Description

Source Voltage and Frequency 100 V

Maximum Power Consumption

Steady-State Input Current

Inrush Surge Current

Power Factor Correction

240 Watts line power maximum

65 A maximum

Yes

RMS

maximum

RMS

to 240 V

±10%,47Hzto63Hz

RMS

On/Standby Switch and Indicator Front Panel On/Standby switch, w ith indicator.

The power cord provides main power disconnect.

Table 18: TLA5200 cooling

Characteristic D escription

Cooling System Forced air circulation (negative pressurization) utilizing two fans operating

in parallel

Cooling Clearance 51 mm (2 in), sides and rear; unit should be operated on a ﬂat,

unobstructed surface

TLA5200 Series Product Speciﬁcations & Performance Veriﬁcation 13

Speciﬁcations

Table 19: TLA52

Characteristic Description

Overall Dimensions (See Figure 1.)

Weight

00 mechanical characteristics

Includes empty accessory pouch and front cover

TLA5201

TLA5202

TLA5203

TLA5204

11.8Kg(25lb15oz)

11.85Kg(26lb2oz)

11. 9 Kg (26 l

12 Kg (26 lb 7 oz)

b4oz)

Figure 1: Dimensions of the TLA5200 series logic analyzer

14 TLA5200 Series Product Speciﬁcations & Performance Veriﬁcation

External Oscilloscope (iView) Characteristics

External Osci

lloscope (iView) Characteristics

The followin

g table lists the characteristics for iView (Integrated View) and for

the Tektronix logic analyzer when connected to an external oscilloscope. For detailed information on the individual speciﬁcations of the external oscilloscope, refer to the documentation that accompanies the oscilloscope.

Table 20: External oscilloscope (Integrated View or iView) characteristics

Character

Supporte

TLA appli

Minimum recommended TLA controller RAM

Supported external oscilloscopes as of January, 2008

(For th visit our Web site at www.tektronix.com.)

External oscilloscope software or ﬁrmware version number

aximum number of external oscilloscopes

iView cable length

istic

d Tektronix logic analyzer instruments

cation software version

e latest list of supported external oscilloscopes,

Descripti

TLA5200 and TLA5200B series

TLA7012,

V5.1SP1 o

256 MB

TDS1000, TDS200023, TDS1000B and TDS2000B Series

TDS300 module required)

DPO4000 and MSO4000 Series

TDS500

TDS6000, TDS6000B, and TDS6000C Series

DPO7000 and DPO7000B Series

DPO70

TDS7000 and TDS7000B Series

CSA7000 and CSA7000B Series

TDS6

TDS754C, T DS784C, TDS724D, TDS754D, TDS784D, TDS794D

Prod

TDS

TDS3000 series

DPO4000 series

TDS

TDS6000 series

DPO7000 series

.56 ft (2 m)

TLA7016

r greater

0 and TDS3000B Series (TDS3GM GPIB/RS-232 communication

0 and TDS5000B Series

000 and DSA70000 series

54C, TDS684C, TDS694C

uct

684C, TDS694C

5000 series

S7000, CSA7000 series

ne per Tektronix logic analyzer mainframe

ion

Vers

Any version

version

Any

Any version

version

Any

Version 1.2 or greater

TLA5200 Series Product Speciﬁcations & Performance Veriﬁcation 15

External Oscilloscope (iView) Characteristics

Table 20: External oscilloscope (Integrated View or iView) characteristics (cont.)

Characteristic Description

Time correlation uncertainty6(Typical at system trigger)

If RAM is less than 256 MB, the record length of the external oscilloscope may be limited to 1 M.

An GPIB extender is needed to connect the iView cable to the oscilloscope. One end of a standard GPIB cable can be used.

If you encounter possible alignment problems with the logic analyzer and oscilloscope waveform edges, refer to Aligning Logic Analyzer and Oscillos cope Waveform Edges. (See page 16, Aligning Logic Analyzer and Oscilloscope Waveform Edges.)

AGPIBtoU

When used with a TLA7016 mainframe and an external PC (such as TLA7PC1), the instruments must be physically located close together so that the iView cable can span both instruments. Removing the sleeving from the iView cable assembly increases the spacing distance available between the external PC and the TLA7016 mainframe.

Includes sampling uncertainty, typical jitter, slot-to-slot skew, and probe-to-probe variations to provide a typical number for the measurement.

SB adapter (TEK-USB-488) is required to connect the iView cable to the oscilloscope.

3 ns Logic analyzer triggers external

oscilloscope

(2 ns + logic analyzer sample period + external oscilloscope sample period)

5ns

External oscilloscope triggers logic analyzer

(4 ns + logic analyzer sample period + external oscilloscope sample period)

Aligning Logic Analyzer

and Oscilloscope

Waveform Edges

The ﬁrst time that you take an acquisition after changing the horizontal scale setting on TDS1000, TDS1000B, TDS2000, or TDS2000B series oscilloscopes, the logic analyzer and oscilloscope w av eform edges may not be aligned within the listed speciﬁcation. You can realign the waveform positions in the waveform

w that contains the oscilloscope data (Menu bar > Data > Time Alignment).

windo Make sure that the external oscilloscope is the data source and then adjust the time offset to align the waveforms. Use the following approximate offsets for various horizontal scale settings. (See Table 21.)

Table 21: TDS1000, TDS1000B, TDS2000, and TDS2000B Series oscilloscope waveform edge alignment

Horizontal scale Time offset

100 ns

250 ns –11 ns

500 ns –18 ns

1 μs –12 ns

2.5 μs –50 ns

5 μs

10 μs –250 ns

25 μs –650 ns

–5 ns

–120 ns

16 TLA5200 Series Product Speciﬁcations & Performance Veriﬁcation

Performance Veriﬁcation Procedures

This chapter contains procedures for functional veriﬁcation, certiﬁcation, and performance veriﬁcation procedures for the TLA5200 and TLA5200B series logic

nframes. Generally, you should perform these procedures once per

Summary Veriﬁcation

analyzer mai year or following repairs that affect certiﬁcation.

Functional veriﬁcation procedures verify the basic functionality of the instrument inputs, outputs, and basic instrument actions. These procedures include power-on diagnostics, extended diagnostics, and manual check procedures. These procedures can be used for incoming inspection purposes.

Performance veriﬁcation procedures conﬁrm that a product meets or exceeds the performance requirements for the published speciﬁcations documented in the Speciﬁcations chapter of this manual. The performance veriﬁcation procedures

y the accuracy of an instrument and provide a traceability path to national

certif standards.

tiﬁcation

Cer

As you calibration data report to keep on ﬁle with your instrument. A blank copy of the calibration data report is provided with this manual. The calibration data report is intended to be copied and used to record the results of the calibration/certiﬁcation procedures.

The system clock of the controller is checked for accuracy, and the input probe channels are checked for threshold accuracy and setup and hold accuracy. The in performance veriﬁcation procedures and record the certiﬁable parameters in a copy of the Calibration Data Report at the end of this chapter.

complete the performance veriﬁcation procedures, you can ﬁll out a

strument is certiﬁable if these parameters meet speciﬁcations. Complete the

TLA5200 Series Product Speciﬁcations & Performance Veriﬁcation 17

Performance Veriﬁcation Procedures

Test Equipment

These procedures use external, traceable signal sources to directly test characteristics that are designated as checked this manual. Always warm up the equipment for 30 minutes before beginning the procedures.

in the Speciﬁcations chapter of

Table 22: Te

Item number description Minimum requirements Example

1. Logic anal

2. Logic analyzer probes

3. Frequency counter

4. Digital

generator

5. DC voltage source (see fo

6. Digital multimeter with probe

7. Cabl 50 Ω coaxial

8. Setup and Hold test ﬁxture

9. Threshold Accuracy test ﬁxture

Some timing generators (for example, the Tektronix DTG5274) include an internal DC voltage source that can be used instead of a separate power source.

Only needed to verify the output of the voltage source if the source does not meet speciﬁcation. In this case, the DMM becomes the traceable instrument.

st equipment

and

yzer

timing

otnote)

e, precision

TLA5200 or

General purpose Tektronix logic analyzer probes; one probe required

Frequen 100 MHz

>235 MHz, ± 0.1% accuracy

DC output: 0–5 V, ± 0.1% accuracy

0–5 V, ± 0.1% accuracy Tektronix PS281

6.5 digit display, 35 ppm, 1 year accuracy, 1000 readings per minut

50 Ω,

User-built (See page 30, Te st F i xt u r e s.)

TLA5200B series logic analyzer

for every 17 channels.

cy accuracy: <0.0025% Frequency range: 1 kHz to

36 in, m ale-to-male BNC connectors

TLA5201, T TLA5202B, TLA5203, TLA5203B, TLA5204, TLA5204B

P6410, P6417, or P6418

Agilent 33131A

Tektronix DTG5274

Fluke

Tektronix part number 012-0482-XX

LA501B, TLA5202,

8845A/8846A

18 TLA5200 Series Product Speciﬁcations & Performance Veriﬁcation

Performance Veriﬁcation Procedures

Functional Ve

Power-o

n and Fan

riﬁcation

Operation

The following table lists functional veriﬁcation procedures for the benchtop and portable mainframes. If necessary, refer to the TLA5200B Series Logic Analyzer

Installatio

Table 23: Functional veriﬁcation procedures

Instrument Procedure

TLA5200 Series logic analyzers

Complete the following steps to check the power-on and fan operation of the logic analyzer:

1. Power on the instrument and observe that the On/Standby switch illuminates.

2. Check that the fans spin without undue noise.

3. If there are no failures indicated, the power-on diagnostics pass when you

n Manual for installation instructions.

Power-on and fan operation

Power-up diagnostics

Extended diagnostics

CheckIt Utilities diagnostics

power on the mainframe(s).

TLA5200 Series Product Speciﬁcations & Performance Veriﬁcation 19

Performance Veriﬁcation Procedures

Extended Diagnostics

Do the followin

NOTE. Running the extended diagnostics will invalidate any acquired data. If

you want to save any of the acquired data, do so before running the extended diagnostics.

Prerequisites Warm-up time: 30 minutes

Perform the

1. If you have not already done so, power on the instrument and start the logic analyzer a

2. Go to the System menu and select Calibration and Diagnostics.

3. Verify that all power-on diagnostics pass.

4. Click the Extended Diagnostics tab.

5. Select All Modules, All Tests, and then clicktheRunbuttonontheproperty

sheet.

All tests that displayed an "Unknown" status will change to a Pass or Fail status depending on the outcome of the tests.

g steps to run the extended diagnostics:

following tests to complete the functional veriﬁcation procedure:

pplication if it did not start by itself.

CheckIt Utilities

6. Scroll through the tests and verify that all tests pass.

kIt Utilities is a comprehensive software application used to check and verify

Chec the operation of the hardware in the instrument. To run the software, you must have either a keyboard, mouse, or other pointing device.

NOTE. To check the DVD/CD drive, you must hav e a test disc installed before

starting the CheckIt CD-ROM test. The disc needs to contain a ﬁle with a size between 5 MB and 15 MB.

To run CheckIt Utilities, follow these instructions:

uit the logic analyzer application.

1.Q

2. Click the Windows Start button.

3. Select All Programs → CheckIt Utilities.

4. Run the tests. If necessary, refer to the CheckIt Utilities online help for

information on running the software and the individual tests.

20 TLA5200 Series Product Speciﬁcations & Performance Veriﬁcation

Performance Veriﬁcation Procedures

Performance V

Tests Performed

eriﬁcation

This section contains procedures to verify that the instrument performs as warranted. Verify instrument performance whenever the accuracy or function of your instrum

Do the following tests to verify the performance of the TLA5200 Series logic analyzers. (See Table 24.) You will need test equipment to complete the performan equipment, always choose instruments that meet or exceed the minimum requirements speciﬁed.

Also note that setup procedures for your equipment m ay differ from those described in the procedures, due to changes in the equipment or ﬁrmware. For example, output connectors might be BNC or SMA, and setup menus c an differ between models.

Table 24: Parameters checked by veriﬁcation procedures

Parameter Veriﬁcation method

System clock (CLK10) accuracy

Threshold accuracy

Setup and hold window size (data and qualiﬁers)

Channel-to-channel skew Veriﬁed indirectly by the setup and hold

Internal sampling period

Minimum recognizable word (across all channels)

Maximum synchronous clock rate

Counters and timers Veriﬁed by diagnostics

Trigger state sequence rate

ent is in question.

ce veriﬁcation procedures. (See Table 22 on page 18.) If you substitute

Certiﬁable parameter

Veriﬁed by the 10 MHz system clock test

Veriﬁed by the threshold accuracy test. Certiﬁed by running the certiﬁcation procedure.

Veriﬁed directly by setup and hold procedure.

procedure

Veriﬁed indirectly by the 10 MHz system clock test

Veriﬁed indirectly by the setup and hold procedure and by the Internal Sampling Period

Diagnostics verify the clock detection/sampling circuitry. Bandwidth is veriﬁed indirectly by the at-speed diagnostics, the setup and hold test, and the clock test.

Veriﬁed indirectly by at-speed diagnostics

Prerequisites

Thelogicanalyzer,testﬁxture, and other related test equipment must be installed, connected, and operating for at least 30 minutes at an ambient temperature between +20 C and +30 C.

TLA5200 Series Product Speciﬁcations & Performance Veriﬁcation 21

Performance Veriﬁcation Procedures

Checking the 1

0 MHz System Clock (CLK10)

The following procedure checks the accuracy of the 10 MHz system clock:

Equipment re

Prerequisi

1. Verify that all of the prerequisites above are met for the procedure.

2. Connect th

on the instrument.

3. Select Sy

4. In the System Conﬁguration dialog box, select 10 MHz Clock from the list of

routabl

5. Verify that the output frequency at the External Signal Out connector is 10 MHz ± report and disconnect the frequency counter.

6. In the S to None.

quired

tes

e frequency counter to the External Signal Out BNC connector

stem Conﬁguration from the System menu.

e signals in the External Signal Out selection box and click OK.

1 kHz. Record the measurement on a copy of the calibration data

ystem Conﬁguration dialog box, reset the External Signal Out signal

Frequency co

Precision BNC cable

Warm-up tim

unter

e: 30 minutes

22 TLA5200 Series Product Speciﬁcations & Performance Veriﬁcation

Threshold Accuracy

Performance Veriﬁcation Procedures

This procedure veriﬁes the threshold voltage accuracy of the logic analyzer.

Test Equipment Setup

TLA5200 Setup

Equipment required

Prerequisites Warm-up time: 30 minutes

Precision vo generator and precision digital voltmeter

Threshold Accuracy test ﬁxture

Logic analy

ltage reference or a DC signal

zer probe

Connect a P6410, P6417, or P6418 probe from the logic analyzer to the voltage source, using the Threshold Accuracy test ﬁxture. If the voltage source does not have the r

equired output accuracy, use a multimeter with the required accuracy to

verify the voltage output levels speciﬁed in the procedure.

To set up the logic analyzer for this test, you must deﬁne the characteristics of the channel

that you are testing, and then set the trigger parameters:

1. Open the Setup window, and in the Probe Channel table, delete all the groups. You w il

ldeﬁne new groups in the following steps.

2. In the Group column, enter a name for the probe group that you are testing

t” in the example).

(“Tes

a. Deﬁne the probe channels for the group that you are testing.

Figure 2: Deﬁning group parameters

b. Set the clocking to Internal, 2 ns.

c. Set Acquire to Normal.

d. Set the Memory Depth to 128 K or less.

TLA5200 Series Product Speciﬁcations & Performance Veriﬁcation 23

Performance Veriﬁcation Procedures

4. Go to the Trigge program that triggers the logic analyzer when it doesn’t see all highs or all lows:

a. Click the If Then button.

b. Set the chan

r window and select the Power Trigger tab. Create a trigger

nel deﬁnition to match the ﬁgure below.

Figure 3: Setting trigger parameters

c. Click OK.

24 TLA5200 Series Product Speciﬁcations & Performance Veriﬁcation

Performance Veriﬁcation Procedures

Veriﬁcation Procedure

Complete the fo the copy of the Calibration Data Sheet.

1. Go to the Setup voltages to 4 V.

2. Set the volt

3. Start the logic analyzer and verify that it does not trigger.

4. Increase the voltage in 10 mV steps, waiting at least 3 seconds between steps

to make sure that the logic analyzer continues to run without triggering. Continue u

5. Set the voltage source to 4.12 V.

6. Start the logic analyzer and verify that it does not trigger.

7. Decrease the voltage in 10 mV steps, waiting at least 3 seconds between

steps to make sure that the logic analyzer continues to run without triggering. Continue until the logic analyzer triggers and then record the voltage.

8. Add the two voltage values and divide by two. Verify that the result is

4.00 V ±100 m V. Record the voltage on the Calibration D ata Sheet.

9. Go to the Setup window and set the logic analyzer threshold voltages to –2.0 V.

llowing steps to complete this procedure. Record the results on

window of the logic analyzer and set the probe threshold

agesourceto3.88V.

ntil the logic analyzer triggers and then record the voltage.

10. Repeat steps 3 through 8 for –2.12 V and –1.88 V.

11. Repeat the procedure for each probe channel group that you want to verify.

TLA5200 Series Product Speciﬁcations & Performance Veriﬁcation 25

Performance Veriﬁcation Procedures

Setup and Hold

This procedure veriﬁes the setup and hold speciﬁcations of the logic analyzer.

Digital Timing Generator

Setup

Equipment re

Prerequisites Warm-up time: 30 minutes

quired

Digital timi

Precision BNC cable

Setup and Hold test ﬁxture

ng generator

1. Verify that the digital timing generator (DTG) has been calibrated so that the channel-to-channel skew is minimized.

2. Set up the DTG so that a channel (CH1 for example), is set to be a clock pattern of alternating 1 and 0 (101010… binary) starting with 1 (rising edge).

3. Set the output frequency to 235MHz. (This may require you to set the DTG base clo

ck to 470 MHz for this pattern to represent 235 MHz at the channel

output.)

4. Set ano

ther channel of the DTG (CH2 for example) to a data pattern representing half the period of CH1 (for example 001100110011...binary, starting with 00).

5. Connect the setup and hold test ﬁxtures to the DTG channels that you have set up. Connect 50 Ω SMA terminations to the test ﬁxtures.

6. Connect the DTG channel that you set up as a clock to the appropriate TLA CK[x] input.

7. Connect the other DTG channel to two of the TLA data channels that you want to test.

If you want to test other TLA data channels simultaneously and your DTG has additional outputs available, set up those DTG channels like the ﬁrst data channel, and connect them to the other logic analyzer channels that you want to test. (You will need another test ﬁxture for each additional channel pair.) Otherwise, repeat the procedure for each new pair of logic analyzer channels.

8. SettheterminationtoopenoneachDTGchannel.

9. Set the DTG output voltage levels to 2.50V High and 0.0V Low, with no

offset.

26 TLA5200 Series Product Speciﬁcations & Performance Veriﬁcation

Performance Veriﬁcation Procedures

TLA5200 Setup

1. Start the TLA Ap

2. Click the DM button to default the module.

3. Set the following parameters:

a. Clocking: External

b. Acquire: No

c. Acquisition Length: 1K or greater

d. Click More… Select the positive edge of the clock line that you will be

using to clock the data (CK[x] in the example).

4. Close the External Clocking dialog box.

5. While still in the Setup window, open the Probes dialog box and select the

Thresholds tab.

6. Enter .62 and click Set All.

With the 50 Ω external termination attached at the SMA ﬁxture end, this sets the logic analyzer threshold voltage levels to one-half the resulting termination voltage, which should be about 620 mV (not 1.25 V).

7. Create a new group: right click in the Group Name column.

plication and open the Setup Window.

rmal

8. Select Add Group from the pop-up window. Rename the new group Test.

9. In the Probe Channels column, enter the names of the two adjacent data

channels that will be used to connect to CH2 of the DTG.

Trigger Logic. To complete the setup, you must conﬁgure a trigger to occur whenever the two data lines are neither 00 nor 11 (binary). This will capture

e condition when the two data signals are 01 or 10, as they transition to their

th common values. To set this up, do the following:

pen the LA Trigger window and select the Power Trigger tab. Set up three

10.O

states as shown. (See Figure 4 on page 28.)

TLA5200 Series Product Speciﬁcations & Performance Veriﬁcation 27

Performance Veriﬁcation Procedures

Figure 4: Set the trigger states

28 TLA5200 Series Product Speciﬁcations & Performance Veriﬁcation

Performance Veriﬁcation Procedures

Veriﬁcation Procedure

Complete the fo on the Calibration Data Sheet.

1. Press the RUN b

2. Increase the delay of the DTG clock channel (starting from 0.000 ns), until

triggering

Note that the logic analyzer might trigger because of a glitch when you make a delay chan transitioning at the same time and at the correct frequency), then ignore this "false trigger" and start the logic analyzer again.

As an alternative, you may want to run the logic analyzer in continuous loop mode if the DTG causes a false trigger on the logic analyzer each time you change the delay. Then observe if the data is correct in the waveform window and ignore any false triggers. Continue increasing the clock delay until the waveform window displays data that was not acquired correctly. Record this delay.

3. Add1.00nstothedelayvaluethatyourecordedinstep2andincreasethe DTG cl measured 0.85 ns, increase the delay to 1.85 ns.)

4. Press that the setup and hold window is 1.00 ns or less, which is the guaranteed speciﬁcation for a single channel. If you are testing more than one channel, you may need to add 1.50 ns to the value that you recorded in step 2 (1.5 ns is the typical speciﬁcation for multiple channels).

llowing steps to complete this procedure. Record the results

utton and wait a few seconds to verify that it doesn’t trigger.

begins to occur. Record this delay amount.

ge. If the data in the waveform window is correct (all data

ock delay to match this cumulative value. (For example, if you

Run and wait a few seconds to verify that it doesn’t trigger. This veriﬁes

If you want to measure the actual setup and hold window size for your application, slowly decrease the clock delay in steps (waiting a few seconds between steps to verify that it doesn’t trigger), until the logic analyzer triggers.

ecord this second value. The difference between this second value and the

R value that you measured in step 2 is the measured setup and hold window size.

TLA5200 Series Product Speciﬁcations & Performance Veriﬁcation 29

Test Fixtures

This section includes information and procedures for building the test ﬁxtures used in the performance veriﬁcation tests.

Threshold Accuracy Test Fixture

Use this ﬁxture to gain access to the logic analyzer probe pins. The ﬁxture connects all ground pins together, and all signal pins together.

Equipment Required

Build Procedure

You will need the following items to build the test ﬁxture:

Item Description Example part number

Square-pin strip

Wire 20 gauge

Soldering iron and solder

Use the following procedure to build the test ﬁxture.

1. Set the square-pin strip down and lay a wire across o ne row of pins on one side of the insulator as shown. Leave some extra wire at one end for connecting to a test lead. (See Figure 5.)

2. Solder the wire to each pin in the row.

3. Repeat for the other row of pins.

0.100 x 0.100, 2 x 8 contacts (or two 1 x 8 contacts )

50 W

SAMTEC part number TSW-102-06-G-S

Figure 5: Threshold Accuracy test ﬁxture

30 TLA5200 Series Product Speciﬁcations & Performance Veriﬁcation

Test F i x t u re s

Setup and Hold

Equipment Required

Build Procedure

Test Fixture

This ﬁxture provides square-pin test points for logic analyzer probes when they are used to probe in-line SMA connections. Note that you need a minimum of two test ﬁxtures

You will need the following items to build the test ﬁxture:

Item Descriptio

SMA connec required for each ﬁxture)

Square-pin strip

SMA termination 50 Ω, ≥2 GHz bandwidth

SMA adapter

Soldering iron and solder

Use the

to complete the procedure.

tor (two

Female, PC

0.100 x 0. (or two 1 x 2 contacts )

Male-to-male Johnson part number

50 W

B mount

100, 2 x 2 contacts

following procedure to build the test ﬁxture.

Example par

SV Microwa 2985-6035, -6036, or -6037

SAMTEC part number TSW-102-06-G-S

Johnson part number 142-0801-866

142-0901-811

t number

ve part number

1. Arrange one SMA connector as shown. (See Figure 6.)

2. Align the square pins at a right angle to the connector.

Figure 6: Solder square pins to the SMA connector

3. Solder one set of square pins to the SMA ground conductor.

4. Solder the other set of square pins to the SMA center conductor.

TLA5200 Series Product Speciﬁcations & Performance Veriﬁcation 31

Test Fixtures

5. Align the secon conductors of the connectors together. (See Figure 7.)

Figure 7: Solder the SMA connectors together

7. Solder the ground conductors of the SMA connectors together.

8. Attach the termination and coupler to the ﬁxture.

d SMA connector to the ﬁrst as shown and solder the center

Figure 8: Completed ﬁxture with termination and coupler

32 TLA5200 Series Product Speciﬁcations & Performance Veriﬁcation

Calibration Data Report

Calibration D

ata Report

Photocopy th instrument.

is table and use it to record the performance test results for your

TLA5200 Series

Instrument model number:

Serial number:

Certiﬁcate number:

Veriﬁcation performed by:

Veriﬁcation date:

Test Dat

Characteristic Speciﬁcation Tolerance Incoming data Outgoing data

Clock frequency

Threshold accuracy

Setup and hold window:

single channel

multiple channels

10 MHz ±1 kHz

(9.9990 MHz-10.0010 MHz)

+4 V ±100 mV

(3.900 V to 4.100 V)

-2 V ±100 mV (–1.900 V to –2.100 V)

≤1.00 ns ≤1.50 ns

none

TLA5200 Series Product Speciﬁcations & Performance Veriﬁcation 33

Tektronix TLA5201, TLA5202, TLA5203, TLA5204, TLA5201B Performance Verification

Specifications and Main Features

Frequently Asked Questions

User Manual