MHL data eye diagram test - mask movement...........................................................................319
Map the My TekExpress folder..................................................................................................322
viii MHL Printable Online Help
Welcome
MHL application
Engineers designing and validating the Mobile High-definition Link (MHL)
Interface of their devices face constant pressure to improve efficiency. Engineers
need to perform a wide range of compliance tests quickly and reliably right on
their bench.
The MHL 1.X, 2.0, 1.3/2.1, 3.2 specification enables mobile devices to transmit
uncompressed audio/video to an HDTV or receiver with HD capability. Option
MHD advanced analysis and compliance test software meets the MHL 1.X,
2.0 and 1.3/2.1 CTS specification and option MHD3 advanced analysis and
compliance test software meets the MHL 3.0 early CTS, 3.2 CTS and 3.3 CTS
specification . MHD3 automates a comprehensive range of tests, enabling
unprecedented efficiency with reliable results.
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CTS 3.3
MHL Printable Online Help ix
Welcome
■
CTS 1.X, 2.0, 1.3 / 2.1
x MHL Printable Online Help
Getting help and support
Technical support
Tektronix values your feedback on our products. To help us serve you better,
please send us your suggestions, ideas, or comments on your application or
oscilloscope. Contact Tektronix through mail, telephone, or the Web site,
www.tektronix.com.
When you contact Tektronix Technical Support, please include the following
information (be as specific as possible):
■
General Information
All instrument model numbers
■
Hardware options, if any
■
Probes used
■
Your name, company, mailing address, phone number, FAX number
■
Please indicate if you would like to be contacted by Tektronix about your
suggestion or comments.
Application Specific
Information
■
Software version number
■
Description of the problem such that technical support can duplicate the
problem
■
If possible, save the setup files for all the instruments used and the
application.
■
If possible, save the TekExpress setup files, log.xml, *.TekX (session files
and folders), and status messages text file.
■
If possible, save the waveform on which you are performing the
measurement as a .wfm file.
MHL Printable Online Help 1
Getting help and support
2 MHL Printable Online Help
Overview and key specifications
Overview and key specifications
The TekExpress MHL Advanced Analysis and Compliance Solution gives you
the tools to easily run Mobile High-definition Link (MHL) tests under the MHL
compliance test specifications 1.X, 2.0, 1.3 / 2.1 and 3.2. It provides a complete
and reliable solution for quick testing.
The application functionality is generally divided into six parts:
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MHL 3.0 Transmitter test (CTS 3.3)
■
MHL 3.0 Receiver test (CTS 3.3)
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MHL Transmitter test (CTS 1.X, 2.0, 1.3 / 2.1)
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MHL Receiver test (CTS 1.X, 2.0, 1.3 / 2.1)
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MHL Cable test (CTS 1.3 / 2.1)
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MHL Receiver Protocol test (CTS 1.X, 2.0, 1.3 / 2.1)
Select the suite and version of the CTS by clicking on the Setup panel and
clicking the DUT tab. See Application basics for more information.
Supported Tests:
TekExpress MHL 3.0 Transmitter supports these automated Data, Clock and
eCBUS tests.
TekExpress MHL 3.0 Receiver supports these automated Sink and Dongle tests.
TekExpress MHL Transmitter supports these automated Clock and Data tests.
TekExpress MHL Receiver supports these automated Sink and Dongle tests.
TekExpress MHL Cables supports these automated Clock and Data tests.
Additional tests may be performed manually by loading the test patterns on the
Tektronix Arbitrary Waveform Generator (AWG).
MHL Cable Assembly Electrical Tests
NOTE. Contact your local Tektronix representative for the MOI of cable tests.
■
Impedance
■
Intra-Pair Skew
■
Delay
■
Insertion Loss
■
Differential and Common Mode Conversion
MHL Printable Online Help 3
Overview and key specifications
Supported Resolutions:
See also:
MHL Transmitter supports these resolutions.
MHL Receiver supports these resolutions.
MHL Cables supports these resolutions.
Application basics
Equipment connection setup MHL 3.0 Transmitter
Equipment connection setup MHL 3.0 Receiver
Equipment connection setup MHL Transmitter
Equipment connection setup MHL Receiver
Equipment connection setup MHL Cables
Install the software
Application directories and usage
File name extensions
Supported tests: MHL 3.0 Transmitter
TekExpress MHL 3.0 Transmitter supports the following automated Data, Clock
and eCBUS tests:
These tests are supported for CTS Version 3.3:
MHL 3.0 Transmitter output tests
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TMDS Data
■
3.7.2.1: Single-ended high level output voltage of differential TMDS data
+/-: V
SE_HIGH_DF_TMDS_DATA
This test confirms that the single-ended high level voltage of the
differential TMDS data output is within the specified limits.
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3.7.2.2: Single-ended low level output voltage of differential TMDS data
+/-: V
SE_LOW_DF_TMDS_DATA
This test confirms that the single-ended low level voltage of the
differential TMDS data is within the specified limits.
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3.7.2.5: Differential output swing voltage of differential TMDS data:
V
DF_SWING_DF_TMDS_DATA
This test confirms that the differential swing voltage of the differential
TMDS data is within the specified limits.
■
3.7.2.13: Rise time of differential TMDS data: T
R_DF_TMDS_DATA
This test confirms that the rise time of differential TMDS data is within
the specified limits.
4 MHL Printable Online Help
Overview and key specifications
■
3.7.2.14: Fall time of differential TMDS data: T
F_DF_TMDS_DATA
This test confirms that the fall time of differential TMDS data is within
the specified limits.
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3.7.2.17: Peak-to-peak amplitude of differential TMDS data:
T
PP_TP1_DF_TMDS_DATA
This test confirms that the peak-to-peak amplitude of differential TMDS
data is within the specified limits.
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3.7.2.27: Differential TMDS data eye diagram at TP2
This test confirms that the differential TMDS data eye diagram is within
the specified limits.
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MHL Clock
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3.7.2.7: Single-ended high level output voltage of single-ended MHL
clock data: V
SE_HIGH_SE_MHL_CLK
This test confirms that the single-ended high level voltages of the singleended MHL clock are within the specified limits. This test is applied only
to the DUT with eCBUS-S.
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3.7.2.8: Single-ended low level output voltage of single-ended MHL
clock data: V
SE_LOW_SE_MHL_CLK
This test confirms that the single-ended low level voltages of the singleended MHL clock are within the specified limits. This test is applied only
to the DUT with eCBUS-S.
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3.7.2.9: Single-ended output swing voltage of single-ended MHL clock
data: V
SE_SWING_SE_MHL_CLK
This test confirms that the single-ended output swing voltages of the
Single-Ended MHL clock are within the specified limits. This test is
applied only to the DUT with eCBUS-S.
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3.7.2.20: Single-ended MHL clock frequency: F
SE_MHL_CLK
This test confirms that the single-ended MHL clock frequency is within
the specified limits. This test is applied only to the DUT with eCBUS-S.
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3.7.2.21: Single-ended MHL clock front porch: T
CFP_SE_MHL_CLK
This test confirms that the single-ended MHL clock front porch time is
within the specified limits. This test is applied only to the DUT with
eCBUS-S.
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3.7.2.22: Single-ended MHL clock back porth: T
CBP_SE_MHL_CLK
This test confirms that the single-ended MHL clock back porch time is
within the specified limits. This test is applied only to the DUT with
eCBUS-S.
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3.7.2.23: Rise time of single-ended MHL clock: T
TR_SE_MHL_CLK
MHL Printable Online Help 5
Overview and key specifications
This test confirms that the rise time of single-ended MHL clock is within
the specified limits. This test is applied only to the DUT with eCBUS-S.
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3.7.2.26: Single-ended MHL clock jitter at TP2:
T
CLOCK_JITTER_TP2_SE_MHL_CLK
This test confirms that single-ended MHL clock jitter at TP2 is within the
specified limits. This test is applied only to the DUT with eCBUS-S.
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MHL eCBUS
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3.7.2.7: Single-ended high level output voltage of single-ended eCBUS-S
forward data: V
SE_HIHG_SE_eCBUS_FWD
This test confirms that the single-ended high level voltages of the singleended eCBUS-S forward data are within the specified limits. This test is
applied only to the DUT with eCBUS-S.
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3.7.2.8: Single-ended low level output voltage of single-ended eCBUS-S
forward data: V
SE_LOW_SE_eCBUS_FWD
This test confirms that the single-ended low level voltages of the singleended eCBUS-S forward data are within the specified limits. This test is
applied only to the DUT with eCBUS-S.
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3.7.2.9: Single-ended output swing voltage of single-ended eCBUS-S
forward data: V
SE_SWING_SE_eCBUS_FWD
This test confirms that the single-ended output swing voltages of the
single-ended eCBUS-S forward data are within the specified limits. This
test is applied only to the DUT with eCBUS-S.
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3.7.2.24: Fall time of single-ended MHL clock, eCBUS-S forward data:
T
F_SE_eCBUS_CLK
, T
F_SE_eCBUS_FWD
This test confirms that the fall times of single-ended MHL clock and
eCBUS-S forward data are within the specified limits. This test is applied
only to the DUT with eCBUS-S.
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3.7.2.25: Peak--to-peak amplitude of eCBUS-S forward data:
V
PP_TP1_SE_eCBUS_FWD
This test confirms that the peak-to-peak amplitude of eCBUS-S forward
data is within the specified limits. This test is applied only to the DUT
with eCBUS-S.
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3.7.2.29: eCBUS-S forward data eye diagram at TP2
This test confirms that the clock jitter of the TMDS differential clock
complies with the limits mentioned in specification.
6 MHL Printable Online Help
Overview and key specifications
MHL 3.0 Transmitter input tests
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MHL eCBUS tests
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3.7.2.32: Input DC voltage Tolerance of eCBUS-S backward data:
V
IDC_SE_eCBUS_BWD
This test confirms that the source DUT tolerates the input DC voltage
levels of eCBUS-S backward data specified in the specification.
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3.7.2.36: Jitter tolerance of eCBUS-S backward data
This test confirms that the source DUT tolerates the maximum jitter of
input eCBUS-S backward data specified in the specification.
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3.7.2.40 Duty Cycle Tolerance of Single-Ended MHLClock - Source
This test confirms that the Source DUT tolerates duty cycle variation of
the input Single-Ended MHL Clock during the eCBUS-S Start-Up
sequence specified in the specification
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Auto Calibration (for 3.7.2.36 Jitter Tolerance of eCBUS-S BWD Data)
This test confirms that the Nominal Jitter & Error patterns used for
"3.7.2.36 - Jitter tolerance of eCBUS-S backward data" test meets the
required specification.
NOTE.
For Eye diagram test, TekExpress MHL solution uses the Auto mask feature to
automatically place the mask to achieve zero or minimal hits. In case of Mask hit,
Manual mode options permit user to manually place the mask. Refer to the Mask
movement procedure.
TekExpress MHL solution supports only Horizontal movement of mask.
MHL Printable Online Help 7
Overview and key specifications
Supported tests: MHL 3.0 Receiver
TekExpress MHL 3.0 Receiver supports the following automated Sink and
Dongle tests.
These tests are supported for CTS Version 3.3:
MHL 3.0 Receiver output tests
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MHL Sink
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4.7.2.14: Single-ended high level output voltage of eCBUS-S backward
data: V
This test confirms that the single-ended high level voltage of eCBUS-S
backward data output is within the specified limits.. This test is applied
only to the DUT with eCBUS-S.
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4.7.2.15: Single-ended low level output voltage of eCBUS-S forward
data: V
This test confirms that the single-ended low level voltage of eCBUS-S
backward data output is within the specified limts. This test is applied
only to the DUT with eCBUS-S.
SE_HIGH_SE_eCBUS_BWD
SE_LOW_SE_eCBUS_BWD
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4.7.2.16: Single-ended output swing voltage of eCBUS-S backward data:
V
SE_SWING_SE_eCBUS_BWD
This test confirms that the single-ended output swing voltage of eCBUSS backward data output is within the specified limits. This test is applied
only to the DUT with eCBUS-S.
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4.7.2.20: Rise time of eCBUS-S backward data: T
R_SE_eCBUS_BWD
This test confirms that the rise time of eCBUS-S backward data output is
within the specified limits. This test is applied only to the DUT with
eCBUS-S.
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4.7.2.21: Fall time of eCBUS-S backward data: T
F_SE_eCBUS_BWD
This test confirms that the fall time of eCBUS-S BWD data output is
within the specified limits. This test is applied only to the DUT with
eCBUS-S.
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4.7.2.22: Peak-to-peak amplitude of eCBUS-S backward data:
V
PP_TP2_SE_eCBUS_BWD
This test confirms that the peak-to-peak amplitude of eCBUS-S
backward data output is within the specified limits.. This test is applied
only to the DUT with eCBUS-S.
■
4.7.2.24: eCBUS-S backward data eye diagram at TP1
8 MHL Printable Online Help
Overview and key specifications
This test confirms that the eCBUS-S backward data eye diagram at TP1
is within the specified limits. This test is applied only to the DUT with
eCBUS-S.
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MHL Dongle
■
5.7.2.16: Output DC voltage of eCBUS-S backward data:
V
ODC_SE_eCBUS_BWD
This test confirms that the DC voltage level of eCBUS-S backward data
output signal is within the specified limits. This test is applied only to the
DUT with eCBUS-D.
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5.7.2.17: Single-ended output swing voltage of eCBUS-S backward data:
V
SE_SWING_SE_eCBUS_BWD
This test confirms that the single-ended output swing voltage of eCBUSS backward data output is within the specified limits. This test is applied
only to the DUT with eCBUS-S.
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5.7.2.19: eCBUS-S backward data eye diagram at TP3
This test confirms that the eCBUS-S backward data eye diagram at TP3
is within the specified limits. This test is applied only to the DUT with
eCBUS-S.
MHL 3.0 Receiver input tests
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MHL Sink
■
4.7.2.1: Input DC voltage tolerance of differential TMDS data:
V
IDC_DF_TMDS_DATA
This test confirms that the Sink device supports the DC voltage level of
the differential TMDS data input signal allowed by the specification.
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4.7.2.3: Differential input swing voltage tolerance of differential TMDS
data: V
IDF_SWING_DF_TMDS_DATA
This test confirms that the Sink device supports the differential swing
voltage of the differential TMDS data input signal allowed by the
specification.
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4.7.2.5: Input DC voltage tolerance of single-ended MHL clock and
eCBUS-S forward data: V
This test confirms that the single-ended MHL clock and eCBUS-S
forward data input signals allowed by the specification. This test is
applied only to the DUT with eCBUS-S.
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4.7.2.7: Differential intra-pair skew tolerance of differential TMDS data:
T
SKEW_TP2_DF_TMDS_DATA
IDC_SELMHL_CLK
, V
IDC_SE_eCBUS_FWD
This test confirms that the Sink device tolerates the differential intra-pair
skew of the differential TMDS data input signal allowed by the
specification.
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4.7.2.10: Jitter tolerance of single-ended MHL clock:
T
CLOCK_JITTER_TP2_SE_MHL_CLK
MHL Printable Online Help 9
Overview and key specifications
This test confirms that the Sink device tolerates the single-ended MHL
clock jitter. This test is applied only to the DUT with eCBUS-S.
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4.7.2.28 Duty Cycle Tolerance of Single-Ended MHLClock - Sink
This test confirms that the Sink DUT tolerates duty cycle variation of the
input Single-Ended MHL Clock during the eCBUS-S Start-Up sequence
specified in the specification.
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MHL Dongle
■
5.7.2.1: Single-ended high level input voltage tolerance of differential
TMDS data: V
SE_HIGH_DF_TMDS_DATA
This test confirms that the Dongle device supports the single-ended high
level voltage of the differential TMDS data input signal allowed by the
specification.
■
5.7.2.2: Single-ended low level input voltage tolerance of differential
TMDS data: V
SE_LOW_DF_TMDS_DATA
This test confirms that the Dongle device supports the single-ended low
level voltage of the differential TMDS data input signal allowed by the
specification.
■
5.7.2.5: Differential input swing voltage tolerance of differential TMDS
data: V
IDF_SWING_DF_TMDS_DATA
This test confirms that the Dongle device supports the differential swing
voltage of the differential TMDS data input signal allowed by the
specification.
■
5.7.2.7: Single-ended high level input voltage tolerance of single-ended
MHL clock and eCBUS-S forward data: V
V
SE_HIGH_SE_eCBUS_FWD
SE_HIGH_SE_MHL_CLK
This test confirms that the Dongle device supports the single-ended high
level voltage of the single-ended MHL clock and eCBUS-S forward data
input signals allowed by the specification. This test is applied only to the
DUT with eCBUS-S.
■
5.7.2.8: Single-ended low level input voltage tolerance of single-ended
MHL clock and eCBUS-S forward data: V
V
SE_LOW_SE_eCBUS_FWD
SE_LOW_SE_MHL_CLK
This test confirms that the Dongle device supports the single-ended low
level voltage of the single-ended MHL clock and eCBUS-S forward data
input signals allowed by the specification. This test is applied only to the
DUT with eCBUS-S.
■
5.7.2.10: Differential intra-pair skew tolerance of differential TMDS
data: T
SKEW_TP3_DF_TMDS_DATA
,
,
This test confirms that the Donge device tolerates the differential intrapair skew of the differential TMDS data input signal allowed by the
specification.
■
5.7.2.13: Jitter tolerance of single-ended MHL clock
10 MHL Printable Online Help
Overview and key specifications
This test confirms that the Dongle device tolerates the single-ended MHL
clock jitter and eCBUS-S forward data eye diagram impairments and
differential TMDS data eye diagram impairments allowed by the
specification. This test is applied only to the DUT with eCBUS-S.
■
5.7.2.23 Duty Cycle Tolerance of Single-Ended MHLClock - Dongle
This test confirms that the Dongle device tolerates duty cycle variation of
the input Single-Ended MHL Clock during the eCBUS-S Start-Up
sequence specified in the specification.
Supported tests: MHL Transmitter
TekExpress MHL Transmitter supports the following automated Clock and Data
tests:
These tests are supported for CTS Version 1.0:
Clock tests
■
3.1.1.1: Standby (Off) Output Voltage Test - V
OFF
This test measures that the MHL source output voltage is within the specified
level limits when the source device is in Standby State or power off mode as
specified in the CDF.
■
3.1.1.5: Common-mode Output Swing Voltage Test - V
CMSWING
This test confirms that common-mode output voltage swing amplitude is
within the specified limits when the DUT operates in normal mode.
■
3.1.1.7: Common-mode Rise and Fall Times Test - T
R_CM
, T
F_CM
This test confirms that the rise time and fall time of the common-mode output
signal are within the specified limits.
■
3.1.1.10: MHL Clock Duty Cycle Test - 24 Bit or Packed Pixel Mode
This test confirms that the MHL clock duty cycle in 24-bit or packed pixel
mode does not exceed the limits allowed by the specification.
■
3.1.1.11: MHL Clock Jitter Test
This test confirms that the MHL Clock output does not contain excessive
jitter larger than the limit allowed by the specification.
Data tests
■
3.1.1.2: Single-ended High Level Voltage Test - V
SE_HIGH
This test confirms that the single-ended high output voltage level is within
the specified limits when the DUT is in normal mode.
■
3.1.1.3: Single-ended Low Level Voltage Test - V
SE_LOW
This test confirms that the single-ended low output voltage level is within the
specified limits when the DUT is in normal mode.
■
3.1.1.4: Differential Output Swing Voltage Test - V
DF_SWING
MHL Printable Online Help 11
Overview and key specifications
This test confirms that the differential output voltage swing amplitude is
within the specified limits when the DUT is in normal mode.
■
3.1.1.6: Differential Rise and Fall Times Test - T
R_DF
, T
F_DF
This test confirms that the rise and fall times of the differential output signal
are equal to or larger than the minimum limit.
■
3.1.1.8: Differential Intra-Pair Skew Test - T
SKEW_DF
This test confirms that the timing skew in the differential signal pair is below
the specified limits.
■
3.1.1.12: MHL Data Eye Diagram Test
This test confirms that the MHL Data output has signal quality that meets the
eye opening required by the specification.
NOTE.
For Eye diagram test, TekExpress MHL solution uses the Auto mask feature to
automatically place the mask to achieve zero or minimal hits. In case of Mask hit,
Manual mode options permit user to manually place the mask. Refer to the Mask
movement procedure.
TekExpress MHL solution supports only Horizontal movement of mask.
These tests are supported for CTS Version 2.0:
Clock tests
■
3.1.1.1: Standby (Off) Output Voltage Test - V
OFF
This test measures that the MHL source output voltage is within the specified
level limits when the source device is in Standby State or power off mode as
specified in the CDF.
■
3.1.1.5: Common-mode Output Swing Voltage Test - V
CMSWING
This test confirms that common-mode output voltage swing amplitude is
within the specified limits when the DUT operates in normal mode.
■
3.1.1.7: Common-mode Rise and Fall Times Test - T
R_CM
, T
F_CM
This test confirms that the rise time and fall time of the common-mode output
signal are within the specified limits.
■
3.1.1.10: MHL Clock Duty Cycle Test - Normal Mode
This test confirms that the MHL clock duty cycle does not exceed the limits
allowed by the specification in Normal Mode.
■
3.1.1.11: MHL Clock Jitter Test - Normal Mode
This test confirms that the MHL Clock output does not contain excessive
jitter greater than the limit allowed by the specification in Normal Mode.
■
3.1.1.14: MHL Clock Duty Cycle Test - Packed Pixel Mode
12 MHL Printable Online Help
Overview and key specifications
This test confirms that the MHL clock duty cycle in packed pixel mode does
not exceed the limits allowed by the specification.
■
3.1.1.15: MHL Clock Jitter Test - Packed Pixel Mode
This test confirms that the MHL Clock output does not contain excessive
jitter larger than the limit allowed by the specification in Packed Pixel Mode.
Data tests
■
3.1.1.2: Single-ended High Level Voltage Test - V
SE_HIGH
This test confirms that the single-ended high output voltage level is within
the specified limits when the DUT is in normal mode.
■
3.1.1.3: Single-ended Low Level Voltage Test - V
SE_LOW
This test confirms that the single-ended low output voltage level is within the
specified limits when the DUT is in normal mode.
■
3.1.1.4: Differential Output Swing Voltage Test - V
DF_SWING
This test confirms that the differential output voltage swing amplitude is
within the specified limits when the DUT is in normal mode.
■
3.1.1.6: Differential Rise and Fall Times Test - T
R_DF
, T
F_DF
This test confirms that the rise and fall times of the differential output signal
are equal to or larger than the minimum limit.
■
3.1.1.8: Differential Intra-Pair Skew Test - T
SKEW_DF
This test confirms that the timing skew in the differential signal pair is below
the specified limits.
■
3.1.1.12: MHL Data Eye Diagram Test - Normal Mode
This test confirms that the MHL Data output has signal quality that meets the
eye opening required by the specification in Normal Mode.
■
3.1.1.16: MHL Data Eye Diagram Test - Packed Pixel Mode
This test confirms that the MHL Data output has signal quality that meets the
eye opening required by the specification in Packed Pixel Mode.
NOTE.
For Eye diagram test, TekExpress MHL solution uses the Auto mask feature to
automatically place the mask to achieve zero or minimal hits. In case of Mask hit,
Manual mode options permit user to manually place the mask. Refer to the Mask
movement procedure.
TekExpress MHL solution supports only Horizontal movement of mask.
These tests are supported for CTS Version 1.3/2.1:Clock Tests
■
3.1.1.1: Standby (Off) Output Voltage Test - V
OFF
MHL Printable Online Help 13
Overview and key specifications
This test measures that the MHL source output voltage is within the specified
level limits when the source device is in Standby State or power off mode as
specified in the CDF.
■
3.1.1.5: Common-mode Output Swing Voltage Test - V
CMSWING
This test confirms that common-mode output voltage swing amplitude is
within the specified limits when the DUT operates in normal mode.
■
3.1.1.7: Common-mode Rise and Fall Times Test - T
R_CM
, T
F_CM
This test confirms that the rise time and fall time of the common-mode output
signal are within the specified limits.
■
3.1.1.10: MHL Clock Duty Cycle Test - Normal Mode
This test confirms that the MHL clock duty cycle does not exceed the limits
allowed by the specification in Normal Mode.
■
3.1.1.14: MHL Clock Duty Cycle Test - Packed Pixel Mode
This test confirms that the MHL clock duty cycle in packed pixel mode does
not exceed the limits allowed by the specification.
■
3.1.1.17: TP2 Clock Jitter Test - Normal Mode
This test confirms that the TP2 Clock output does not contain excessive jitter
larger than the limit allowed by the specification in Normal Mode.
■
3.1.1.19: TP2 Clock Jitter Test - Packed Pixel Mode
This test confirms that the TP2 Clock output does not contain excessive jitter
larger than the limit allowed by the specification in Packed Pixel Mode.
Data tests
■
3.1.1.2: Single-ended High Level Voltage Test - V
SE_HIGH
This test confirms that the single-ended high output voltage level is within
the specified limits when the DUT is in normal mode.
■
3.1.1.3: Single-ended Low Level Voltage Test - V
SE_LOW
This test confirms that the single-ended low output voltage level is within the
specified limits when the DUT is in normal mode.
■
3.1.1.4: Differential Output Swing Voltage Test - V
DF_SWING
This test confirms that the differential output voltage swing amplitude is
within the specified limits when the DUT is in normal mode.
■
3.1.1.6: Differential Rise and Fall Times Test - T
R_DF
, T
F_DF
This test confirms that the rise and fall times of the differential output signal
are equal to or larger than the minimum limit.
■
3.1.1.18: TP2 Data Eye Diagram Test - Normal Mode
This test confirms that the TP2 Data output has signal quality that meets the
eye opening required by the specification in Normal Mode.
■
3.1.1.20: TP2 Data Eye Diagram Test - Packed Pixel Mode
14 MHL Printable Online Help
Overview and key specifications
This test confirms that the TP2 Data output has signal quality that meets the
eye opening required by the specification in Packed Pixel Mode.
NOTE.
For Eye diagram test, TekExpress MHL solution uses the Auto mask feature to
automatically place the mask to achieve zero or minimal hits. In case of Mask hit,
Manual mode options permit user to manually place the mask. Refer to the Mask
movement procedure.
TekExpress MHL solution supports only Horizontal movement of mask.
Supported tests: MHL Receiver
TekExpress MHL Receiver supports the following automated Sink and Dongle
tests.
These tests are supported for CTS version 1.0:
MHL Sink tests
■
4.1.1.1: Input Signal DC Voltage Level Tolerance Test
This test confirms that the Sink device supports input signal DC voltage level
allowed by the specification.
■
4.1.1.2: Input Signal Minimum and Maximum Swing Voltages Tolerance
Test
This test confirms that the Sink device supports input signal DC voltage level
and swing voltage allowed by the specification.
■
4.1.1.3: Intra Pair Skew Tolerance Test
This test confirms that the Sink device can tolerate the maximum intra-pair
skew allowed by the specification.
■
4.1.1.4: Jitter Tolerance Test
This test confirms that the Sink device can tolerate the maximum clock and
data jitter amounts allowed by the specification.
MHL Dongle tests
■
5.1.1.1: Input Signal Single-Ended Voltage Level Tolerance Test
This test confirms that the Dongle device supports input signal single-ended
voltage level allowed by the specification.
■
5.1.1.2: Input Signal Minimum and Maximum Swing Voltages Tolerance
Test
This test confirms that the Dongle device supports input signal minimum and
maximum swing voltages allowed by the specification.
■
5.1.1.3: Intra-Pair Skew Tolerance Test
MHL Printable Online Help 15
Overview and key specifications
This test confirms that the Dongle device can tolerate the maximum intra-pair
skew allowed by the specification.
■
5.1.1.4: Jitter Tolerance Test
This test confirms that the Dongle device can tolerate the maximum clock
and data jitter amounts allowed by the specification.
These tests are supported for CTS version 2.0 and version 1.3/2.1:
MHL Sink tests
■
4.1.1.1: Input Signal DC Voltage Level Tolerance Test
This test confirms that the Sink device supports input signal DC voltage level
allowed by the specification.
■
4.1.1.2: Input Signal Minimum and Maximum Swing Voltages Tolerance
Test
This test confirms that the Sink device supports input signal DC voltage level
and swing voltage allowed by the specification.
■
4.1.1.3: Intra Pair Skew Tolerance Test
This test confirms that the Sink device can tolerate the maximum intra-pair
skew allowed by the specification.
■
4.1.1.4: Jitter Tolerance Test in Normal Mode
This test confirms that the Sink device can tolerate the maximum clock and
data jitter amounts allowed by the specification in Normal Mode with cable
emulator.
■
4.1.1.8: Jitter Tolerance Test – Packed Pixel Mode
This test confirms that the Sink device can tolerate the maximum clock and
data jitter amounts allowed by the specification in Packed Pixel Mode.
MHL Dongle tests
■
5.1.1.1: Input Signal Single-Ended Voltage Level Tolerance Test
This test confirms that the Dongle device supports input signal single-ended
voltage level allowed by the specification.
■
5.1.1.2: Input Signal Minimum and Maximum Swing Voltages Tolerance
Test
This test confirms that the Dongle device supports input signal minimum and
maximum swing voltages allowed by the specification.
■
5.1.1.3: Intra-Pair Skew Tolerance Test
This test confirms that the Dongle device can tolerate the maximum intra-pair
skew allowed by the specification.
■
5.1.1.4: Jitter Tolerance Test – Normal Mode
16 MHL Printable Online Help
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