Tektronix DPO70404, DPO70604, DPO70804 User manual

Technical Reference

RT-Eye® PCI Express® Compliance Module Methods of Implementation (MOI)

071-2041-01

www.tektronix.com

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Methods of Implementation

Table of Contents

1 Introduction to the RT-Eye PCI Express Compliance Module.............1

2 PCI Express Compliance Specifications..................................................2

2.1 Differential Transmitter (TX) Output Specifications.............................3

2.2 Differential Transmitter (TX) Compliance Eye Diagrams....................4

2.3 Differential Receiver (RX) Input Specifications.....................................5

2.4 Differential Receiver (RX) Compliance Eye Diagrams..........................5

2.5 Add-In Card Transmitter Path Compliance Specifications..................6

2.6 Add-In Card Compliance Eye Diagrams ................................................7

2.7 System Board Transmitter Path Compliance Eye Diagrams................8

2.8 System Board Compliance Eye Diagrams...............................................8

2.9 PCI ExpressModule™ Compliance Specifications.................................9

2.9.1 ExpressModule Add-In Card Transmitter Path

Specifications....................................................................................9

2.9.2 ExpressModule System Board Transmitter Path Compliance

Eye Diagrams................................................................................10

2.9.3 Express Module System Board Compliance Eye Diagrams......10

2.10 PCI Express External Cabling Specifications.......................................11

2.10.1 External Cabling Transmitter Path Specifications....................11

2.10.2 Cable (Transmitter Side) Eye Diagrams.....................................11

2.10.3 External Cabling Receiver Path Specifications..........................12

2.10.4 Cable (Receive Side) Eye Diagrams.............................................12

2.11 PCMCIA ExpressCard

2.11.1 ExpressCard - Module Transmitter Path Specifications...........13

2.11.2 ExpressCard Transmitter Path Eye Diagrams ..........................13

2.11.3 ExpressCard - Host System Transmitter Path Specifications...14

2.11.4 ExpressCard – Host System Eye Diagrams................................14

2.12 Reference Clock Compliance Specifications.........................................15

Specifications...............................................13

3 Preparing to Take Measurements..........................................................16

3.1 Required Equipment...............................................................................16

3.2 Probing Options for Transmitter Testing .............................................16

3.2.1 SMA Input Connection.................................................................17

3.2.2 ECB Pad Connection ....................................................................18

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3.3 Initial Oscilloscope Setup........................................................................19

3.4 Running the RT-Eye Software ...............................................................19

3.5 Configuring the Software to take measurements..................................20

3.5.1 Select Standard..............................................................................20

3.5.2 Select Test Point ............................................................................20

3.5.3 Select Probe Type..........................................................................21

3.5.4 Select Measurements.....................................................................21

3.5.5 Configure Source of Waveforms..................................................24

3.5.6 Configure Clock Recovery ...........................................................25

3.5.7 Configure Plots..............................................................................27

4 PCI Express Transmitter Compliance Testing.....................................28

4.1 Probing the link for TX compliance.......................................................28

4.2 TX Compliance Test Load......................................................................28

4.3 Running a Transmitter (TX) Compliance Test.....................................29

4.3.1 TX Unit Interval Measurement MOI..........................................30

4.3.2 TX Differential Pk-Pk Output Voltage MOI..............................31

4.3.3 TX De-Emphasized Differential Output Voltage (Ratio)

MOI................................................................................................33

4.3.4 Minimum TX Eye Width MOI ....................................................34

4.3.5 TX Median-to-Max Jitter MOI....................................................35

4.3.6 TX Output Rise/Fall Time MOI ..................................................36

4.3.7 TX AC Common Mode Output Voltage MOI............................38

4.3.8 TX Delta DC Common Mode Voltage MOI ...............................39

4.3.9 TX Total Jitter@BER MOI .........................................................40

4.3.10 Spectrum Analysis Based Rj/Dj Separation on Repeating

Pattern...........................................................................................40

4.3.11 Arbitrary Pattern Analysis Based Rj/Dj Separation .................42

4.3.12 TX Deterministic MOI (Using Dual-Dirac Model) ....................43

4.3.13 Rj/Dj Separation Based on Dual-Dirac Model...........................43

4.3.14 TX Waveform Eye Diagram Mask Test MOI............................44

5 PCI Express Receiver (RX) Compliance Testing..................................44

5.1 Probing the Link for RX Compliance....................................................44

5.2 Running a Complete RX Compliance Test ...........................................44

5.2.1 RX Unit Interval Measurement MOI..........................................45

5.2.2 RX Differential Pk-Pk Input Voltage MOI.................................46

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5.2.3 Minimum RX Eye Width MOI....................................................46

5.2.4 RX Median-to-Max Jitter MOI ...................................................47

5.2.5 RX Total Jitter@BER MOI.........................................................48

5.2.6 RX Deterministic Jitter@BER using Dual-Dirac model...........48

5.2.7 RX Waveform Eye Diagram Mask Test MOI............................49

6 PCI Express Interconnect Test Point Testing.......................................50

6.1 Unit Interval Measurement MOI...........................................................51

6.2 Transition and Non-Transition Bit Eye Height Measurement MOI ..51

6.3 Eye Width Measurement MOI...............................................................53

6.4 Interconnect Median-to-Max Jitter and Total Jitter@BER MOI......54

7 PCI Express Reference Clock Compliance Measurements.................55

7.1 Probing the Link for Reference Clock Compliance .............................55

7.2 Running a Complete Reference Clock Compliance Test.....................55

7.2.1 Reference Clock Frequency Measurement Test MOI ...............56

7.2.2 Reference Clock Differential Voltage Hi and Lo Test MOI......57

7.2.3 Reference Clock Differential rise and fall edge rates test

MOI................................................................................................57

7.2.4 Reference clock Duty cycle Test MOI.........................................58

7.2.5 Reference Clock Jitter Test MOI.................................................59

8 Using SigTest............................................................................................60

9 Using Dynamic Test Points.....................................................................63

9.1 Test Point File Syntax..............................................................................64

9.2 Creating the New Test Point...................................................................66

9.3 Running a test with the new DTP...........................................................67

10 Giving a Device an ID..............................................................................68

11 Creating a Compliance Report...............................................................68

12 Further Analysis Techniques..................................................................68

13 Ensuring Compliance over specified population..................................69

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iv RT-Eye PCI Express Compliance Module

Methods of Implementation

1 Introduction to the RT-Eye PCI Express Compliance

Module

This document provides the procedures for making PCI Express compliance measurements with the

Tektronix TDS6000 Series and TDS7704B, real time oscilloscopes (6 GHz models and above), the

DPO/DSA70000 series and probing solutions.

The PCI Express (PCI-E) Compliance Module Version 2.0 (Opt. PCE) is an optional software plug-in to the RT-Eye Serial Data Compliance and Analysis software (Opt. RTE). The PCI Express Compliance module provides transmitter path measurements (amplitude, timing, and jitter), waveform mask testing, and Reference Clock (RefClk) compliance measurements described in multiple variants of the PCI Express specifications. Specifications covered in this document and the PCE module includes a total of eighteen data and reference clock test points defined in the following specifications.

Additional test points can also be added by the user, or provided by Tektronix representatives, using

Dynamic Test Point (DTP) definition, described in detail in Section 9. Refer to the release notes (readme.txt)

for information on the additional test point files that may have been added after this release.

Table 1 – Supported Specifications

Test Methods Spec

Revision

Rev1.0a

Rev1.0a Base Specification Transmitter and Receiver

PCI Express Specification Title Test Points Defined

(Section 4.3) Rev 1.0 Mobile Graphics Lower Power Addendum Transmitter (Section 2.2) Rev1.0a CEM (Card Electro-Mechanical) Specification System and Add-In Card

(Section 4.7) Rev 1.0a PCMCIA Express Card Standard Host System Transmitter

Express Card Transmitter

(Section 4.2.1.2)

Rev1.1

Disclaimer: The tests provided in the PCI Express compliance module (which are described in this document) do not guarantee PCI Express

compliance. The test results should be considered “Pre-Compliance”. Official PCI Express compliance and PCI-SIG Integrator List qualification is governed by the PCI-SIG (Special Interest Group) and can be achieved only through official PCI-SIG sanctioned testing.

Rev1.1 Base Specification Transmitter & Receiver

(Section 4.3) Rev1.1 CEM Specification System and Add-In Card

(Section 4.7)

Reference Clock (Section 2.1) Rev1.0 Express Module Specification Transmitter Path and System

Board (Section 5.4) Rev0.4C External Cabling Specification Transmitter and Receiver Path

(Section 3.3)

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Test Methods Spec

Revision

TBD Future 2.5 Gb/s Variants Dynamic Test Points as

Rev2.0

Rev2.0 Base Specification Transmitter & Receiver

Rev2.0 CEM Specification System and Add-In Card

TBD Future 5 Gb/s Variants Dynamic Test Points as

PCI Express Specification Title Test Points Defined

specifications are defined

(Section 4.4)

Mobile Low Power Transmitter

(Section 4.4)

(Section 4.7)

specifications are defined

Refer to http://www.pcisig.com/specifications/pciexpress/ for the latest specifications.

The PCE module can also be used to automate setup procedures for SigTest by using its SigTest Import

feature (Refer to Section 8).

In this document, for all references to the PCI Express Base Specification and Card Electrical Mechanical (CEM) specification, refer to all versions of the Spec. (Rev 1.0a, 1.1, and 2.0). Differences between the

specifications are specifically called out when appropriate.

In the subsequent sections, step-by-step procedures are described to help you perform PCI Express measurements. Each measurement is described as a Method of Implementation (MOI). For further reference, consult the Compliance checklists offered to PCI-SIG members at

www.pcisig.com.

2 PCI Express Compliance Specifications

As shown in Table 1, Electrical Specifications for PCI Express are provided in multiple documents. This section provides a summary of the measurement parameters measured in the RT-Eye PCE module and how they are related to the symbol and test limits in the specification.

2 RT-Eye PCI Express Compliance Module

Methods of Implementation

2.1 Differential Transmitter (TX) Output Specifications

The following table shows the available measurements in the PCE Module and their test limits defined in each of the Base specifications.

Table 2- Supported base specification transmitter measurements

Parameter Symbol(s)

2.5 GT/s 2.5 GT/s 5.0 GT/s Rev1.0a Rev1.1 Rev2.0

Unit interval 400 ps 400 ps 200 ps UI

+/- 300 ppm +/- 300 ppm +/- 300 ppm

Specification

Differential p-p TX voltage swing

Low power differential p-p TX voltage swing

De-emphasized output voltage ratio

TX-SWING

TX-SWING-LOW

pDIFFpTX

−−

Not Specified Not Specified

RATIODETXV−−

0.8 V (min) 0.8 V (min) 0.8 V (min)

1.2 V (max) 1.2 V (max) 1.2 V (max)

0.4 V (min)

0.7 V (max)

-3.0 dB (min) -3.0 dB (min) -5.5 dB (min)

-4.0 dB (max) -4.0 dB (max) -6.5 dB (max) or

-3.0 dB (min)

-4.0 dB (max)

Instantaneous lane pulse

width Transmitter eye including all

jitter sources

Maximum time between the jitter median and maximum deviation from the median

Deterministic jitter D+/D- TX output rise/fall

Time

MIN-PULSE

EYETXT−

TX-EYE_TJ

TX-EYEMEDIAN-to-MAXJITTER

TX-DJ-DD

RISETXT−

FALLTXT−

Not Specified Not Specified 0.9 UI (min) T

0.70 UI (min) 0.75 UI (min) 0.75 UI (min)

0.125 UI (max) .125 UI (max) Not Specified

0.15 UI (max)

0.125 UI (min) 0.125 UI (min)

0.15 UI (min)

AC RMS common mode output voltage

Absolute delta of DC common mode voltage between D+ and D-

ACpCMTXV−−

DELTALINEDCCMTX

−−−−

20 mV (max) Not Specified Not Specified

0 V (min) 0 V (min) 0 V (min)

25 mV (max) 25 mV (max) 25 mV (max)

Instantaneous lane pulse width defined in the Gen2 specification is not supported in the RT-Eye PCI Express Compliance

module. It is recommended that TDSJIT3 Advanced Jitter Analysis Data Period (Min) be used for this measurement.

Rise/Fall time measurements in RT-Eye PCI Express Module are compliant to the Rev1.0a and Rev1.1 specification. For Gen2,

rise and fall time is limited to TF2 and TR2 as defined in section 4.3.3.8 of the Base Specification

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2.2 Differential Transmitter (TX) Compliance Eye Diagrams

Figure 1a shows the eye mask definitions for the Rev1.1 Base specification. It provides an example of a transmitter mask for a signal with de-emphasis. Transition and non-transition bits must be separated to perform the mask testing. The amplitude and jitter mask geometries are derived from the amplitude and jitter specifications. Low power transmitter variants in both Gen1 and Gen2 do not use de-emphasis (This is shown in Figure 1b).

Figure 1a: Transmitter eye masks for transition and non-transition bits

Figure 1b: Transmitter eye mask for low power variant where de-emphasis is not used

4 RT-Eye PCI Express Compliance Module

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2.3 Differential Receiver (RX) Input Specifications

The following table shows the available measurements in the PCE Module and their test limits defined in each of the Base specifications.

Table 3 – Supported base specification receiver measurements

Parameter Symbol 2.5 GT/s 2.5 GT/s 5.0 GT/s

Rev1.0a

Unit interval 400 ps 400 ps 200 ps UI

+/- 300 ppm +/- 300 ppm +/- 300 ppm

Minimum receiver eye height

RX_EYE

0.175 V (min) 0.175 V (min) 0.120 V (min)

1.2 V (max) 1.2 V (max) 1.2 V (max)

Minimum receiver eye width Receiver deterministic jitter –Dj

Maximum time between the jitter median and maximum

EYERXT−

RX_DJ_DD

TX-EYEMEDIAN-to-

MAXJITTER

0.40 UI (min) 0.40 UI (min) 0.40 UI (min)

Not Specified Not Specified 0.44 UI (max)

0.30 UI (max) 0.30 UI (max)

deviation from the median.

Rev1.1 Rev2.0

Not

Specified

2.4 Differential Receiver (RX) Compliance Eye Diagrams

Figure 2 shows the receiver eye mask definitions for the Rev1.1 Base specification. The amplitude and jitter mask geometries are derived from the amplitude and jitter specifications.

Figure 2: Receiver input eye mask

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2.5 Add-In Card Transmitter Path Compliance Specifications

Table 4 is derived from the Electrical Mechanical Specifications (CEM). See the CEM Specification for additional notes and test definitions.

Table 4 – Supported CEM add-in card measurements

Parameter Symbol 2.5 GT/s 2.5 GT/s 5.0 GT/s 5.0 GT/s

Rev1.0a Rev1.1 Rev2.0 Rev2.0

DeEmphasis Setting 3.5 dB 3.5 dB 3.5 dB 6.0 dB Unit interval 400 ps 400 ps 200 ps 200 ps UI

+/- 300 ppm +/- 300 ppm +/- 300 ppm +/- 300 ppm

TXA

TXA_d

0.514 V (min) 0.514 V (min) 0.380 V (min) 0.306 V (min)

1.2 V (max) 1.2 V (max) 1.2 V (max) 1.2 V (max)

0.360 V (min) 0.360 V (min) 0.380 V (min) 0.260 V (min)

Eye height of transition bits

Eye height of nontransition bits

Eye width across any 250 UIs

Eye width with sample

size of 10

Jitter eye opening at

-12

BER 10 Total Jitter at BER 10

Deterministic Jitter at

-12

BER 10 Maximum median-max

TXA

In Rev1.0a T

TXA

In Rev1.1 T

TXA

In Rev2.0

-12

Not Specified Not Specified 77 ps (max) 77 ps (max) Tj at BER 10

TXA-MEDIAN-to-MAX-JITTER

237 ps (min) Not Specified Not Specified Not Specified

Not Specified 287 ps (min) Not Specified Not Specified

Not Specified 274 ps (min) 123 ps (min) 123 ps (min)

with Crosstalk with Crosstalk

-12

Not Specified Not Specified 57 ps (max) 57 ps (max) Max Dj

Not Specified 56.5 ps (max) Not Specified Not Specified

jitter outlier with sample

size of 10

Maximum median-max jitter outlier with sample

size of 10

Not Specified 63 ps (max) Not Specified Not Specified

6 RT-Eye PCI Express Compliance Module

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2.6 Add-In Card Compliance Eye Diagrams

The amplitude and jitter masks are derived from the amplitude and jitter specifications in Table 4.

Figure 3: Add-in card compliance eye masks

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2.7 System Board Transmitter Path Compliance Eye Diagrams

Table 5 is derived from the Electrical Mechanical Specifications (CEM). See the CEM Specification for additional notes and test definitions.

Table 5 – Supported CEM System Board Measurements

Parameter Symbol 2.5 GT/s 2.5 GT/s 5.0 GT/s

Rev1.0a Rev1.1

Rev2.0

Unit interval 400 ps 400 ps 200 ps UI

+/- 300 ppm +/- 300 ppm +/- 300 ppm

Eye height of transition bits

TXS

0.274 V (min) 0.274 V (min) 0.300 V (min)

1.2 V (max) 1.2 V (max) 1.2 V (max)

V T

TXS

TXS_d

0.253 V (min) 0.253 V (min) 0.300 V (min) 183 ps (min) Not Specified Not Specified

Eye height of non-transition bits Eye width across any 250 UIs

In Rev1.0a

Eye width with sample size of 106 UI Not Specified 246 ps (min) Not Specified T

TXS

In Rev1.1

Jitter eye opening at BER 10

Maximum median-max jitter outlier with

sample size of 10

Maximum median-max jitter outlier with

sample size of 10

-12

Not Specified 233 ps (min) 95 ps (min) T

TXS

In Rev2.0 J

TXA-MEDIAN-

to-MAX-JITTER

with Crosstalk

Not Specified 77 ps (max) Not Specified

Not Specified 83.5 ps (max) TBD

2.8 System Board Compliance Eye Diagrams

The amplitude and jitter masks are derived from the amplitude and jitter specifications in Table 5.

Figure 4: System Board Compliance Eye Masks

At 5GT/s, the PCI Express 2.0 CEM specification requires dual port measurement. The dual port measurement requires differential Clock and Data capture and analysis, which is not supported in the RT-Eye. The test point offered in the RT-Eye software recovers the clock from the data signal. For dual port measurements, PCI-SIG SigTest version 3.0 and above is recommended.

8 RT-Eye PCI Express Compliance Module

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2.9 PCI ExpressModule™ Compliance Specifications

The specifications in this section are taken from the PCI Express ExpressModule™ specification, which is

a companion specification to the PCI Express Base specification. Its primary focus is the implementation

of a modular I/O form factor that is focused on the needs of workstations and servers. Measurements in the PCE module support add-in card and system transmitter path measurements at the PCI Express connector.

2.9.1 ExpressModule Add-In Card Transmitter Path Specifications

Table 6 is derived from Section 5.4.1 of the ExpressModule Electro-Mechanical Specifications Rev1.0.

Table 6 – Supported ExpressModule Add-In Card Measurements

Parameter Symbol Rev1.0

Unit interval 400 ps UI

+/- 300 ppm

Eye height of transition Bits

Eye height of non-transition Bits Eye width with sample size of 106 UI 287 ps (min) T

Jitter eye opening at BER 10

-12

274 ps (min)

Maximum median-max jitter outlier

with sample size of 10

Maximum median-max jitter outlier

with sample size of 10

TXA

TXA_d

TXA

In Rev1.1

TXA-MEDIAN-to-

MAX-JITTER

0.514 V (min)

1.2 V (max)

0.360 V (min)

56.5 ps (max)

63 ps (max)

Figure 5: ExpressModule add-in card compliance eye masks

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2.9.2 ExpressModule System Board Transmitter Path Compliance Eye Diagrams

Table 7 is derived from Section 5.4.3 of the ExpressModule Electro-Mechanical Specifications Rev1.0.

Table 7 – Supported ExpressModule system board measurements

Parameter Symbol Gen1

Rev1.0

Unit interval 400 ps UI

+/- 300 ppm

Eye height of transition bits

Eye height of non-transition bits Eye width with sample size of 106 UI 246 ps (min) T Jitter eye opening at BER 10

-12

233 ps (min)

Maximum median-max jitter outlier

with sample size of 10

Maximum median-max jitter outlier

with sample size of 10

TXS

TXS_d

TXS

TXAMEDIAN-toMAX-JITTER

0.274 V (min)

1.2 V (max)

0.253 V (min)

77 ps (max)

83.5 ps (max)

2.9.3 Express Module System Board Compliance Eye Diagrams

The amplitude and jitter masks are derived from the amplitude and jitter specifications in Table 7.

Figure 6: ExpressModule system board compliance eye masks

10 RT-Eye PCI Express Compliance Module

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2.10 PCI Express External Cabling Specifications

The specifications in this section are taken from the PCI Express External Cabling Specification. Its primary focus is the implementation of a cabled interconnect. Measurements in the PCE module support transmitter path and receiver path measurements. These measurements represent the test points at the transmitter end of the cable and the receiver end of the cable respectively.

2.10.1 External Cabling Transmitter Path Specifications

Table 8 is derived from Section 3.3.1 of the External Cabling Specification Rev. 0.4C.

Table 8 – Supported external cabling transmitter path measurements

Parameter Symbol Rev0.4C

Unit interval 400 ps UI

+/- 300 ppm

V T

TXA

TXA_d

TXA

0.659 V (min)

1.2 V (max)

0.456 V (min) 309 ps (min)

Eye height of transition bits

Eye height of non-transition bits Eye width with sample size of

10 Jitter eye opening at BER 10

-12

296 ps (min)

2.10.2 Cable (Transmitter Side) Eye Diagrams

The amplitude and jitter masks are derived from the amplitude and jitter specifications in Table 8.

Figure 7: Cable (transmitter side) compliance eye masks

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2.10.3 External Cabling Receiver Path Specifications

Table 9 is derived from Section 3.3.2 of the External Cabling Specification Rev. 0.4C.

Table 9 – Supported CEM system board measurements

Parameter Symbol Gen1

Rev1.0

Unit interval 400 ps UI

+/- 300 ppm

RXA

RXA_d

RXA

0.219 V (min)

1.2 V (max)

0.200 V (min) 247 ps (min) T

Eye height of transition bits

Eye height of non-transition bits Eye width with sample size of 106

UI Jitter eye opening at BER 10

-12

234 ps (min)

2.10.4 Cable (Receive Side) Eye Diagrams

The amplitude and jitter masks are derived from the amplitude and jitter specifications in Table 9.

Figure 8: Cable (receiver side) compliance eye masks

12 RT-Eye PCI Express Compliance Module

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2.11 PCMCIA ExpressCard

Specifications

The specifications in this section are taken from the PCMCIA ExpressCard Standard (Release 1.0). Its primary focus is a small modular add-in card technology based on PCI Express and USB interfaces. Measurements in the PCE module support host system and ExpressCard transmitter path measurements.

2.11.1 ExpressCard - Module Transmitter Path Specifications

Table 10 is derived from Section 4.2.1.3.2 of the ExpressCard Specification Release 1.0.

Table 10 – Supported ExpressCard transmitter path measurements

Parameter Symbol Release 1.0

Unit interval 400 ps UI

+/- 300 ppm

TXA

TXA_d

TXA

538 V (min)

1.2 V (max)

0.368 V (min)

Eye height of transition bits

Eye height of non-transition bits Eye width across any 250 UIs 237 ps (min) T

2.11.2 ExpressCard Transmitter Path Eye Diagrams

The amplitude and jitter masks are derived from the amplitude and jitter specifications in Table 10.

Figure 9: ExpressCard Module Transmitter compliance eye masks

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2.11.3 ExpressCard - Host System Transmitter Path Specifications

Table 11 from Section 4.2.1.3.2 of the ExpressCard Specification Release 1.0.

Table 11 – Supported ExpressCard Host System Transmitter Path Measurements

Parameter Symbol Release 1.0

Unit interval 400 ps UI

+/- 300 ppm

txS

txS_d

TxS

0.262 V (min)

1.2 V (max)

0.247 V (min)

Eye height of transition bits

Eye height of non-transition bits Eye width across any 250 UIs 183 ps (min) T

2.11.4 ExpressCard – Host System Eye Diagrams

The amplitude and jitter masks are derived from the amplitude and jitter specifications in Table 11.

Figure 10: ExpressCard Host System compliance eye masks

14 RT-Eye PCI Express Compliance Module

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2.12 Reference Clock Compliance Specifications

Table 12 is derived from Section 2.1 of the Gen1 Rev1.1 Electrical Mechanical Specifications (CEM). Reference Clock measurements for Rev2.0 are not currently supported in RT-Eye.

Table 12 – Supported reference clock measurements

Parameter Symbol Gen1 5.0 GT/s

Rev1.1 Rev2.0

Rise edge rate

Rise Edge Rate

0.6 V/ns (min)

4.0 V/ns (max)

Fall edge rate

Fall Edge Rate 0.6 V/ns (min)

4.0 V/ns (max)

Differential input high voltage

VIH

150 mV (max)

Differential input low voltage VIL -150 mV (min) Absolute period (including jitter

and spread spectrum)

PERIOD_ABS

9.847 ns (min)

10.203 ns (max)

Duty cycle 40% (min) Duty Cycle

60% (max)

Maximum peak-peak filtered

-12

BER

108 ps (max) Jitter @ 10

phase jitter

In RT-Eye software.

For Rev2.0 RefClk

Compliance tools,

Not supported

refer to the tools

library at

www.pcisig.com

Maximum peak-peak filtered phase jitter

RMS jitter T

CLK_RJ

86 ps (max) Jitter @ 10-6 BER

RT-Eye PCI Express Compliance Module 15

Methods of Implementation

3 Preparing to Take Measurements

3.1 Required Equipment

The following equipment is required to take the measurements:

• Oscilloscope Selection:

ο Gen1 (2.5 Gb/s) – The PCI-SIG recommends a minimum of 6 GHz system BW for Gen1

Measurements. Tektronix models that meet this recommendation include: All the TDS6000B/C series instruments, TDS7704B, and the DPO/DSA70000 series.

ο Gen2 (5 Gb/s) – It is recommended that >12 GHz system BW is used for Gen2. This ensures that

• RT-Eye software (Opt. RTE) and PCI Express Compliance Module (PCE) installed.

• Probes – Probing configuration is MOI specific. Refer to each MOI for proper probe configuration.

• Test fixture breakout from transmitter to differential SMA connectors. The Compliance Base Board

(CBB) used for add-in card compliance tests and a Compliance Load Board (CLB) used for system compliance tests are available through the PCI-SIG at the following URL:

http://www.pcisig.com/specifications/ordering_information/ordering_information

• Test fixtures for ExpressCard testing are available from the following URL:

http://www.expresscard.org/web/site/testtools.jsp

the 5

harmonic is represented in the measurements. Tektronix models that meet this

recommendation are TDS6000C models.

3.2 Probing Options for Transmitter Testing

The first step is to probe the link. Use one of the following four methods to connect probes to the link.

Table 13 – Example Probing configurations for a PCI express link

16 RT-Eye PCI Express Compliance Module

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3.2.1 SMA Input Connection

1. Two TCA-SMA inputs using SMA cables (Ch1) and (Ch3)

The differential signal is created by the RT-Eye software from the math waveform Ch1-Ch3. The Common mode AC measurement is also available in this configuration from the common mode waveform (Ch1+Ch3)/2. This probing technique requires breaking the link and terminating into a 50 Ω/side termination of the oscilloscope. While in this mode, the PCI Express SerDes will transmit the compliance test pattern. Ch-Ch de-skew is required using this technique because two channels are used. This

Probe Configuration A

SMA Psuedo-differential

configuration does not compensate for cable loss in the SMA cables. The measurement reference plane is at the input of the TCA-SMA connectors on the oscilloscope. Any cable loss should be measured and entered into the vertical attenuation menu for accurate measurements at the SMA cable attachment point.

2. One P7300SMA series differential active probe (Ch1)

The differential signal is measured across the termination resistors inside the P7300SMA series probe. This probing technique requires breaking the link. While in this mode, the PCI Express SerDes will transmit the compliance test pattern. Matched cables are provided with the probe to avoid introducing de-skew into the system. Only one channel of the oscilloscope is used. The P7300SMA provides a calibrated system at the Test Fixture attachment point, eliminating the need to compensate for cable loss associated with the

Probe Configuration B

SMA Input Differential Probe

probe configuration A.

RT-Eye PCI Express Compliance Module 17

+ 52 hidden pages

Tektronix DPO70404, DPO70604, DPO70804 User manual

Specifications and Main Features

Frequently Asked Questions

User Manual

2 PCI Express Compliance Specifications

2.1 Differential Transmitter (TX) Output Specifications

2.2 Differential Transmitter (TX) Compliance Eye Diagrams

2.3 Differential Receiver (RX) Input Specifications

2.4 Differential Receiver (RX) Compliance Eye Diagrams

2.5 Add-In Card Transmitter Path Compliance Specifications

2.6 Add-In Card Compliance Eye Diagrams

2.7 System Board Transmitter Path Compliance Eye Diagrams

2.8 System Board Compliance Eye Diagrams

2.9 PCI ExpressModule™ Compliance Specifications

2.9.1 ExpressModule Add-In Card Transmitter Path Specifications

2.9.2 ExpressModule System Board Transmitter Path Compliance Eye Diagrams

2.9.3 Express Module System Board Compliance Eye Diagrams

2.10 PCI Express External Cabling Specifications

2.10.1 External Cabling Transmitter Path Specifications

2.10.2 Cable (Transmitter Side) Eye Diagrams

2.10.3 External Cabling Receiver Path Specifications

2.10.4 Cable (Receive Side) Eye Diagrams

2.11.1 ExpressCard - Module Transmitter Path Specifications

2.11.2 ExpressCard Transmitter Path Eye Diagrams

2.11.3 ExpressCard - Host System Transmitter Path Specifications

2.11.4 ExpressCard – Host System Eye Diagrams

2.12 Reference Clock Compliance Specifications

3 Preparing to Take Measurements

3.1 Required Equipment

3.2 Probing Options for Transmitter Testing

3.2.1 SMA Input Connection