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related to operating the instrument.
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details on installing the product so it has proper ventilation.
TLA 7QS Training Manual
ix
General Safety Summary
Symbols and Terms
T erms in this Manual. These terms may appear in this manual:
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in injury or loss of life.
CAUTION. Caution statements identify conditions or practices that could result in
damage to this product or other property.
T erms on the Product. These terms may appear on the product:
DANGER indicates an injury hazard immediately accessible as you read the
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WARNING indicates an injury hazard not immediately accessible as you read the
marking.
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High Voltage
Protective Ground
(Earth) T erminal
CAUTION
Refer to Manual
Double
Insulated
x
TLA 7QS Training Manual
Preface
The TLA 7QS QuickStart Training Manual is part of the TLA 7QS QuickStart
package. It is intended to be used with the Tektronix Logic Analyzer Family as a
training tool to learn some of the specific features of the logic analyzer.
You can use the training manual together with the online help to learn a basic
overview of the Tektronix Logic Analyzer Family.
How to Use This Document
Use this training manual with the TLA 7QS QuickStart board to work through a
series of exercises showing the features and benefits of the Tektronix Logic
Analyzer Family. The exercises are intended to simulate typical problems that
you may encounter and require a logic analysis system to remedy the problems.
The training manual is made up of the following sections:
HThe Getting Started chapter provides information on prerequisites, product
accessories, product installation, and basic product care and maintenance.
HThe General Purpose Exercises provide examples to demonstrate the timing
analysis features of the logic analyzers.
HThe Microprocessor Support Exercises provide examples to demonstrate the
microprocessor features of the logic analyzers.
HThe Embedded Software Debug Exercises provide examples to demonstrate
the software debugging features of the logic analyzers.
HThe Pattern Generator Exercises provide examples to demonstrate the
pattern generation features of the logic analyzers.
HAppendix A: How to Create Setups Used in this Book shows how to use the
menus of the logic analyzer to create the setups for the first general purpose
exercise. It provides a means to become familiar with the menus in creating a
logic analyzer setup.
HAppendix B: Training Board Connections shows the hardware connections
on the training board.
TLA 7QS Training Manual
xi
Preface
Contacting Tektronix
Phone1-800-833-9200*
AddressTektronix, Inc.
Department or name (if known)
14200 SW Karl Braun Drive
P.O. Box 500
Beaverton, OR 97077
USA
Web sitewww.tektronix.com
Sales support1-800-833-9200, select option 1*
Service support1-800-833-9200, select option 2*
Technical supportEmail: support@tektronix.com
1-800-833-9200, select option 3*
1-503-627-2400
6:00 a.m. – 5:00 p.m. Pacific time
*This phone number is toll free in North America. After office hours, please leave a
voice mail message.
Outside North America, contact a Tektronix sales office or distributor; see the
Tektronix web site for a list of offices.
xii
TLA 7QS Training Manual
Getting Started
Getting Started
Prerequisites
This chapter provides basic information that you need to be aware of before
attempting any of the product exercises. It includes the following information:
HPrerequisites. This section contains a list of requirements that you need to be
aware of before using this product.
HAccessories. This section provides a brief overview of standard product
accessories.
HConfiguration. This section provides information on the allowable logic
analyzer configurations for the exercises in this manual and software
installation information.
HCare and Maintenance. This section provides basic cleaning information,
static precautions, and information on obtaining replacement parts.
The exercises and examples in this training manual are based on the following
prerequisites and assumptions:
HTo use this product, it is assumed that you are familiar with Microsoft
Windows. The Tektronix Logic Analyzers operate on a Microsoft Windows
platform. This training manual is not intended to teach you how to use
Windows. You may want to refer to the Windows online help for information
on using a Windows based product.
HIt is assumed that you are familiar with the basics of logic analysis. This
training manual is not intended to teach you logic analysis and basic digital
circuit theory.
HIt is assumed that you have some familiarity with the Tektronix Logic
Analyzer Family application. Refer to the online help or to the printed
documentation for details on using the Tektronix Logic Analyzer Family
application.
HIt is assumed that the Tektronix Logic Analyzer and any accessories are
properly set up. For example, it is assumed that any oscilloscope probes that
you intend to use with the DSO module are properly calibrated.
TLA 7QS Training Manual
1–1
Getting Started
Accessories
Configuration
The TLA 7QS QuickStart package comes with the following standard accessories:
HThis training manual and the CD containing software setups for the exercises
in training manual
HThe TLA 7QS QuickStart training board with appropriate power adapter
The following paragraphs list the configuration requirements for the Tektronix
Logic Analyzer and for the training board.
Logic Analyzer
To complete all the exercises in this training manual you will need a Tektronix
Logic Analyzer with a logic analyzer module (with probes), an oscilloscope
(DSO) module (with probes), and a pattern generator module (with probes).
To complete the general purpose exercises, you can use any version of the logic
analyzer module or any version of the TLA 600 logic analyzer. To complete the
microprocessor exercises and the embedded software debug exercises, you will
need a logic analyzer with 102 data acquisition channels or higher (for example,
a TLA 7x3, TLA 7x4 module, TLA 6x3, or TLA 6x4).
You will need to install the TLA 7QS Exercise software on the logic analyzer.
The exercise software consists of instrument setups and associated software for
the individual exercises.
Complete the following steps to install the TLA 7QS Exercise software.
NOTE. This version of QuickStart software is compatible with Tektronix Logic
Analyzer software version 3.2 and above.
Before continuing, remove any previous versions of QuickStart software by
opening the Windows Explorer and deleting the Quick Start folder under
C:\Program Files\TLA 700.
1–2
1. Insert the CD labeled TLA 7QS QuickStart Software in the CD ROM drive.
2. Click on the Windows Start button and select Run.
3. Enter the program name D:\QStart.exe in the dialog and click OK. (If the CD
ROM drive has a different designation enter that letter instead of D).
The logic analyzer will install the exercise software and place it in the
following location on the hard disk: C:\Program Files\TLA 700\Quick Start.
TLA 7QS Training Manual
Getting Started
4. Click the Unzip button in the dialog that appears.
5. Click OK when the dialog appears indicating that all files were installed
successfully.
6. Click the Close button.
7. Click on the Windows Start button and select Run.
8. Enter the program name D:\Support\Setup.exe in the dialog and click OK.
The logic analyzer will install the support software and place it in the
following location on the hard disk: C:\Program Files\TLA 700\Supports\.
9. Click OK when the dialog appears indicating that all files were installed
successfully.
10. Click OK and then remove the CD.
Training Board
Care and Maintenance
Cleaning
Preventing Electrostatic
Discharge
The TLA 7QS QuickStart Training Board requires no special configuration
procedures. Connect the probes to the training board as described in each
chapter. Then connect the power adapter and apply power to the training board.
The training board will execute the power-on diagnostics. When the power-on
diagnostics are complete, select the program as defined in the individual
exercises.
The TLA 7QS QuickStart Training Board does not require scheduled or periodic
maintenance. However to keep good electrical contact and efficient heat
dissipation, keep the training board free of dirt, dust, and contaminants. When
not in use, store the training board in the protective box.
Clean dirt and dust with a soft bristle brush. For more extensive cleaning, use
only a damp cloth moistened with deionized water; do not use any other
chemical cleaning agents.
When handling the training board adhere to the following precautions to avoid
damaging electronic components.
TLA 7QS Training Manual
CAUTION. Static discharge can damage semiconductor components on the
training board.
1–3
Getting Started
Obtaining Parts
1. Minimize handling of the training board.
2. Transport and store the training board in the static protected container.
3. Discharge the static voltage from your body by wearing a grounded antistatic
wrist strap while handling the training board.
4. Nothing capable of generating or holding a static charge should be allowed
on the work station surface.
5. Handle the training board by the edges when possible.
6. Do not slide the training board over any surface.
7. Avoid handling the training board in areas that have a floor or work-surface
covering capable of generating a static charge.
Electrical and mechanical replacement parts are described in the TLA 7QSTechnical Reference Manual. Refer to that manual for replacing and ordering
parts and for any other service information.
1–4
TLA 7QS Training Manual
General Purpose Exercises
General Purpose Exercises Setups
The following series of exercises use the Signal Sources section of the training
board to demonstrate the timing analysis features of the Tektronix Logic
Analyzer. You should read through this section before attempting any exercises
in this training manual. The exercises rely on a single setup of the training board.
Hardware Setups
Connect the P6418 or P6417 probe to the C2/C3 connector on the logic analyzer
module. You will use the same probe connections through the remainder of this
chapter. If you have an oscilloscope module (DSO), connect an oscilloscope
probe to Channel 1 of the DSO module.
Set up the P6417 Probes
Depending on the number of your logic analyzer probes, you may need to
reconfigure your probes. The following sections provide basic probe setup
information.
Removing Podlets
To complete the exercises in this section, you must remove and separate the
P6417 probe podlets from the podlet holder. Refer to Figure 2–1 and open the
podlet holder as shown and remove the podlets one at a time.
Remove
podlet cables
Pull open the podlet holder
Figure 2–1: Removing probe podlets
TLA 7QS Training Manual
2–1
General Purpose Exercises Setups
Reinstalling Podlets
Connect the Probes
When reinstalling the podlets, make sure all the ground sides of the podlets line
up with the ground side of the podlet connector. Arrange the podlets by their
color-coded rings; use the key on the reverse side of the podlet holder to place
the podlets in the correct channel order.
Complete the following steps to connect the logic analyzer probes to the training
board. If you are using the P6418 probes, use the flying lead sets and refer to
Figure 2–2 while connecting the probes; if you are using the P6417 probes, refer
to Figure 2–3 while connecting the probes to the training board. Make sure that
you connect the signal side of the probes to signal side of the square pins
(ground signals are toward the rear of the training board as you face the LCD
display).
1. Connect the clock channel (CK3) of the C2-C3 probe to J760 (CNTR CLK)
on the training board.
2. Connect the C2:0, C2:1, C2:2 probe podlets of the C2-C3 probe to J860 on
the training board.
3. Connect the Channel 1 oscilloscope probe to the unused J860 signal square
pin labeled FF-Q.
2–2
C2:CLK3 CNTR
CLK (J7600)
C2:0 FF–D
(J860)
C2:1 FF–Q
(J860)
DSO CH1
FF–Q (J860)
Figure 2–2: P6418 probe connections for the timing exercises
TLA 7QS Training Manual
Ground
C2:2 Burst
(J860)
General Purpose Exercises Setups
C2:CLK3 CNTR
CLK (J7600)
C2:0 FF–D
(J860)
C2:1 FF–Q
(J860)
DSO CH1
FF–Q (J860)
C2:2 Burst
(J860)
Figure 2–3: P6417 probe connections for the timing exercises
Start the Tektronix Logic Analyzer Family application and continue with the
following steps. You will use the same hardware setups through the remainder of
this chapter.
TLA 7QS Training Manual
2–3
General Purpose Exercises Setups
Load the Setups
Perform the following steps to load the timing exercises. All timing exercises are
contained in the same folder (C:\Program Files\TLA 700\Quick Start\Hardware
Analysis).
NOTE. Each exercise contains two saved setup files. One file contains only setup
information and requires you to capture live acquisition data to complete the
exercises. The other file contains setup information and saved data. Use the
saved data files to complete nearly every exercise without the need for acquiring
live data.
You can also use TLAVu to complete the exercises off-line without needing any
acquisition hardware.
1. Select Load System from the File menu.
2. Open the Workbook folder and select the file as defined in the individual
exercises (for example, load the 1-Capture and Trigger on a Glitch.tla file for
Exercise 1).
The logic analyzer display should look similar to Figure 2–4.
Figure 2–4: Load System dialog box
2–4
TLA 7QS Training Manual
General Purpose Exercises Setups
3. When prompted to load without saving the current system, click on Yes.
4. If you get a message telling you that the configuration in the file does not
match your current hardware, click on OK. A new dialog box appears.
a. Drag the “My Analyzer” icon (and the “My DSO” icon, if needed) from
the top of the window to the shaded LA1 icon in the Current System
window.
b. Click on OK to continue with the exercise.
NOTE. If the Load System Options dialog box appears and you want to view
saved data, you may need to complete steps 5 through 8 to load a data window
with saved acquisition data.
To determine if you need to perform the following steps, click on one of the data
window icons. If data appears in the data window, you can continue with the
exercise. If no data appears, complete the following steps after you complete
step 4 above.
5. Select Load Data Window from the Window menu; the Load Data Window
dialog box displays.
6. Click the Browse button, navigate to the Hardware Analysis setup folder,
and then double-click the setup for the current exercise.
7. Select the data window from the list in the Load Data Window dialog and
then click OK; the Name Data Window dialog box displays.
8. Change the name of the data window (it is recommended that you only
change one or two characters so the name is similar to the original data
window).
Now you have a data window that displays saved acquisition data for the current
exercise. If you want to continue with the exercise and capture live data, refer
back to the original data window that was loaded with the setup.
TLA 7QS Training Manual
2–5
General Purpose Exercises Setups
Exercise Overview
These exercises focus on a metastable problem caused by driving the clock input
of a flip-flop with a 50 MHz clock and the D input (FF-D) with an asynchronous
10 MHz data stream. Under these conditions the setup and hold times of the
flip-flop are often violated. When the violation occurs, the output of the flip-flop
goes into a potentially metastable state.
When the flip-flop is in a metastable state, the outputs are unpredictable. This
can result in the flip-flop producing a glitch (the output pulse is shorter than
normal), the outputs could briefly oscillate, or the outputs may not change at all.
These type of failures are usually intermittent and can be difficult to find.
The key to isolating these kinds of timing faults is to trigger the logic analyzer
when the Q output (FF-Q) of a flip-flop has a shorter pulse width than the period
of the driving clock signal (FF-CLK). When an edge-triggered flip-flop works
properly, the minimum time between changes on the Q output must be equal to
or greater than the driving clock period.
The device used in these exercises is a 74F174 flip-flop with the specifications in
Table 2–1. The training board provides connections to the flip-flop (see
Figure 2–2 on page 2–2 or Figure on 2–3 page 2–3).
T able 2–1: 74F174 electrical characteristics
74F174
1
FF-Q
ParameterLimits
Setup time (ts)3.0 ns
Hold time (th)1.0 ns
Propagation Delay (t
1
Some of the specifications, such as the propagation
delay , may vary because of circuit design and load
conditions.
FF-D
FF-CLK
)4.0 ns (min.) to 8.0 ns (max.)
PHL
Flip-Flop
2–6
TLA 7QS Training Manual
Triggering on a Glitch (Exercise 1)
In system design, glitches are annoying pulses that can be very difficult to detect
and capture. The glitches can be caused by any number of conditions such as
cross talk, race conditions, or timing violations.
Glitches can be extremely intermittent and hard to find. They are usually narrow
pulses and require high-speed timing to see. Their effects on a system-under-test
are often unpredictable.
This exercise shows how you can set up the Tektronix Logic Analyzer to capture
a glitch on a specific channel or waveform. You will use a glitch detector as an
event in the trigger machine. You can then use the MagniVu feature with the 2
GHz resolution to determine the cause of the glitch.
In this exercise, you will monitor the Q output of the flip-flop described in the
previous section.
TLA 7QS Training Manual
2–7
Triggering on a Glitch (Exercise 1)
Load the Setup
1. Select Load System from the File menu.
2. Open the Hardware Analysis folder and load the system setup 1-Capture and
Trigger on a Glitch.tla.
The restored setup should look similar to Figure 2–5. You will not have a
DSO icon if your logic analyzer does not contain a DSO module.
2–8
Figure 2–5: Restored system for Exercise 1
3. Click on the Run button to begin acquiring data.
The logic analyzer will acquire and capture glitch data.
TLA 7QS Training Manual
View the Resultant Data
Triggering on a Glitch (Exercise 1)
1. Open the waveform data window labeled FF Analysis.
2. Note the glitches, displayed in red on the FF Q-OUT(0) waveform (see
Figure 2–6).
3. Click on the Run button a few times to see if the glitch data changes.
Figure 2–6: Glitch data for Exercise 1
Notice the red area to the left of the trigger indicator. These markings indicate
the presence of a glitch on those signals. But what actually caused the glitches?
Was it a single pulse or several pulses? To find out, you can use the MagniVu
feature of the Tektronix Logic Analyzer to look at the data more closely.
4. Minimize the current data window and then open the waveform data window
labeled MAG FF-Anlys.
Notice the greater resolution available with the 2 GHz sampling. The MagniVu
feature provides you with the ability to make measurements with 500 ps
resolution. The glitch data in Figure 2–6 now appears as a single narrow pulse
(see Figure 2–7). The pulse only became visible using the MagniVu feature with
2 GHz sampling.
Look at the relationship of other channels using the MagniVu feature to
determine the events that caused the glitch. The glitch is a pulse that appeared
between clock edges (these pulses are often missed by basic logic analyzers).
TLA 7QS Training Manual
2–9
Triggering on a Glitch (Exercise 1)
Figure 2–7: Waveform display with the MagniV u feature
The next few steps will show you how to measure the pulse width using the
cursors in the waveform window:
5. Click on the Zoom In button (the right-most active button on the tool bar) or
use the front panel horizontal SCALE or POSITION controls of the portable
logic analyzer to zoom in on the pulse.
a. Move the mouse pointer to the leading (rising) edge of the pulse (on the
FF-Q channel) to the left of the trigger mark. Right-click the mouse and
select Move Cursor 1 Here. Cursor 1 will be placed at the position of the
pointer.
b. Move the mouse pointer to the trailing (falling) edge of the pulse to the
left of the trigger mark. Right-click the mouse and select Move Cursor 2
Here.
c. Determine the actual pulse width by the readouts at the top of the
display.
NOTE. Use the procedure in the above steps to move the cursors from anywhere
outside the displayed information in the window to the mouse position. This
saves time by not having to scroll through the data to find the cursors.
2–10
The pulse in Figure 2–7 appears to be 500 ps wide (the pulse width on your logic
analyzer may be different). Most logic analyzers do not have the resolution to
measure such a narrow pulse. Using the MagniVu feature of the Tektronix Logic
Analyzer, you can capture and identify very narrow pulses.
TLA 7QS Training Manual
View the Trigger Setup
Triggering on a Glitch (Exercise 1)
1. Minimize the data window and click on the Trig button on the logic analyzer
icon to open the Trigger window. The Trigger window should be similar to
Figure 2–8.
The Trigger window shows the conditions that the logic analyzer uses to
detect and capture the data of interest. The Trigger window is made up of
trigger states with a series of action and event clauses.
NOTE. For a detailed explanation of how to define the trigger setups and how
the trigger setups work in this exercise, refer to Define the Trigger Window on
page A–3.
TLA 7QS Training Manual
Figure 2–8: Trigger window for Exercise 1
2. Click on the If-Then button to view the clause definition for the trigger state.
3. Click on the Define Glitches button in the upper right corner of the dialog
box.
The Glitch Detection dialog box defines which channels will acquire the
glitches. In this exercise you are only interested in the Q output of the flip-flop.
The dialog box should be similar to Figure 2–9.
2–11
Triggering on a Glitch (Exercise 1)
Figure 2–9: Glitch Detection dialog box for Exercise 1
The Tektronix Logic Analyzer uses high-speed glitch detectors to watch for
glitches, store glitches, and trigger on glitches. These high-speed glitch detectors
are available on all channels of the logic analyzer.
2–12
TLA 7QS Training Manual
View the Channel Setups
1. Open the Setup window to see how the probe channels are defined and
Triggering on a Glitch (Exercise 1)
labeled for this exercise. Figure 2–10 shows an example of the Setup
window; similar setups will be used for the logic analyzer module for all of
the general purpose exercises.
Figure 2–10: Channel setups for Exercise 1
After viewing the setups, minimize any open windows (except the System
window), and continue with the next exercise.
TLA 7QS Training Manual
2–13
Triggering on a Glitch (Exercise 1)
2–14
TLA 7QS Training Manual
Capture a Pulse Width Violation (Exercise 2)
The output of a flip-flop should never be less than the period of the driving
clock. If the output of the flip-flop is stable for less than the period of the driving
clock, a timing violation occurs. You can use the logic analyzer to monitor a
single data channel and measure the actual pulse width of the flip-flop output. In
the following exercise you will set up the logic analyzer to trigger if the Q-output
pulse of a flip-flop is less than or equal to 16 ns.
Load the Setup
1. Select Load System from the File menu.
2. Load the following saved system:
C:\Program Files\TLA 700\Quick Start\Hardware Analysis\
2-Capture a Pulse Width Violation.tla.
The restored system should look similar to Figure 2–11. You may have a DSO
icon if your logic analyzer contains a DSO module.
TLA 7QS Training Manual
Figure 2–11: Restored system for Exercise 2
3. Click on the Run button to begin acquiring data.
2–15
Capture a Pulse Width Violation (Exercise 2)
View the Acquired Data
1. Open the view labeled FF-Analysis.
The logic analyzer monitored the Q-output signal. As long as the pulse width
was greater than 16 ns, the logic analyzer did not trigger. However, when the
pulse width was less than 16 ns, the logic analyzer triggered. Your waveform
display should look similar to Figure 2–12.
Figure 2–12: Timing waveform display for Exercise 2
2. Use the cursors to measure the pulse width:
a. Move the mouse pointer to the leading (rising) edge of the pulse (on the
FF-Q channel) to the left of the trigger mark.
b. Right-click the mouse and select Move Cursor 1 Here. Cursor 1 will be
placed at the position of the pointer.
c. Move the mouse pointer to the trailing (falling) edge of the same pulse.
d. Right-click the mouse and select Move Cursor 2 Here.
NOTE. Use the procedure in step 2 to move the cursors from areas outside the
window to the mouse position. This saves time by not having to scroll through
the data to find the cursors.
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Capture a Pulse Width Violation (Exercise 2)
3. Determine the actual pulse width by the Delta Time readout at the top of the
display.
The sample rate of the conventional acquisition system is 250 MHz (4 ns) and
the pulse can only be resolved in 4 ns increments. Therefore, a captured pulse is
always represented in 4 ns increments (4 ns, 8 ns, 12 ns ...). The sample rate of
the MagniVu feature is 2 GHz, providing 500 ps resolution for your measurements.
4. Minimize the current Waveform window and then open the Waveform
window labeled MAG_FF-anlys (see Figure 2–13). Notice the greater
resolution available with the 2 GHz sampling rate. Using 2 GHz sampling
(MagniVu acquisition), you can take measurements with 500 ps resolution.
5. Repeat the measurement performed in step 2.
The pulse in Figure 2–12 appears to be approximately 4 ns wide because of the
250 MHz resolution. However, by using the higher resolution available with the
MagniVu feature, the actual pulse width is closer to 1.5 ns (±500 ps) as shown in
Figure 2–13. No pulse can appear to be shorter than the clock period in a logic
analyzer.
TLA 7QS Training Manual
Figure 2–13: Timing waveform using MagniVu acquisition
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Capture a Pulse Width Violation (Exercise 2)
View the Trigger Program
1. To understand how the logic analyzer triggered on the signal, view the
Trigger window. Your trigger should be similar to the setup shown in
Figure 2–14. (You will need to scroll or resize the Trigger window).
2. To see the details of the trigger setup, click on the If-Then button to display
the details of the Clause Definition dialog box. You may want to examine
other areas within the Clause Definition dialog box for specific information
on the channel definitions.
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Figure 2–14: LA Trigger window for Exercise 2
The logic analyzer ignored all the pulses on Channel FF-Q that were greater than
or equal to the value in the Time field (16 ns). The logic analyzer triggered only
when the conditions in the Trigger window were met.
NOTE. For a detailed explanation of how to define the trigger and how the
trigger works in this exercise, refer to Define the Trigger Window on page A–3.
TLA 7QS Training Manual
View the Channel Setups
1. Open the Setup window to see how the probe channels are defined and
Capture a Pulse Width Violation (Exercise 2)
labeled for this exercise. Figure 2–15 shows an example of the Setup
window.
Figure 2–15: Channel setups for Exercise 2
2. After viewing the setup, proceed with the next exercise.
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Capture a Pulse Width Violation (Exercise 2)
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TLA 7QS Training Manual
Capture a Setup and Hold Violation (Exercise 3)
Setup and hold violations can be difficult to detect and capture even with a
high-speed timing analyzer. It may even be impossible to detect the violations
with a high-channel count, general purpose logic analyzer. However, with the
special setup and hold triggering of the Tektronix Logic Analyzer, capturing
setup and hold violations becomes an easy task.
Load the Setup
1. Select Load System from the File menu.
2. Load the saved system 3-Capture a Setup or Hold Violation.tla.
3. Click on the Run button to begin acquiring data.
View the Resultant Data
1. Open the waveform data window labeled MAG_FF-Anlys.
2. Measure the setup and hold times nearest the trigger mark (measure from the
rising edge of the clock to the data transition of the FF-D channel).
Notice the excellent resolution available with the MagniVu feature using the
2 GHz sampling. The waveform display should look similar to Figure 2–16.
TLA 7QS Training Manual
Figure 2–16: Timing waveform display for Exercise 3
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Capture a Setup and Hold Violation (Exercise 3)
3. Click on the Run button several times to see how the timing violation varies
with each data acquisition.
The logic analyzer actually evaluates every clock for a setup and hold
violation. While the logic analyzer monitors millions of events, it captures
only those that fail the setup and hold requirements.
4. Using the data just acquired, select an adjacent clock edge and use the
cursors to measure the propagation delay of the flip-flop (measure from the
rising edge of the FF-CLK channel to the FF-Q channel transition). If
necessary, use the Zoom Out button on the Tool bar to display a wider range
of samples to take the measurement.
Does the delay exceed the specifications of the flip-flop? (See Table 2–1 on
page 2–6.)
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View the Trigger Setup
Capture a Setup and Hold Violation (Exercise 3)
To understand how the logic analyzer captured the setup and hold violation, view
the setups in the Trigger window.
1. Minimize the Waveform window and open the Trigger window.
2. Click on the If-Then button to view the clause definition.
Note the Define Violation button in the upper right corner of the clause
definition.
3. Click on the Define Violation button to open the dialog box.
The dialog box lets you define the setup and hold parameters for the
channels. The dialog box should be similar to Figure 2–17.
TLA 7QS Training Manual
Figure 2–17: Define Violation dialog box for Exercise 3
4. Close the Trigger window and click on the Setup button in the Logic
Analyzer icon.
Note that the clocking is set up to use CLK3 as the external clock source. To
trigger on a setup and hold violation, you must use either External Clocking
or Custom Clocking (used with microprocessor support).
5. After viewing the setups, minimize any open windows (except the System
window), and continue with the next exercise.
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Capture a Setup and Hold Violation (Exercise 3)
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TLA 7QS Training Manual
Counting Setup and Hold Violations (Exercise 4)
In addition to detecting setup and hold violations, you may want to count how
many violations occur over a period of time. This can help you decide if your
electronic circuit needs to be redesigned depending on the actual number of
violations. The frequency of some violations may not cause any noticeable
problems. However, some violations may have a noticeable effect on your
circuitry and the problems must be eliminated.
In this example, you will use a counter in the logic analyzer to track the actual
number of setup and hold violations. You will also use a timer to let you know
the number of violations occurring over a period of time. When a specific
number of violations occur (100 million), you can trigger the logic analyzer.
Load the Setup
1. Select Load System from the File menu.
2. Load the system setup 4-Counting Setup and Hold Violations.tla.
3. Click on the Status button to the left of the Run button in the System
window to open the Status Monitor.
You can use the Status Monitor to view the status of the logic analyzer while
it is waiting for the trigger conditions to be met. The Status Monitor shows
the status of any counters, timers, or other flags set up in the Trigger
window.
4. Click on the Run button to begin acquiring data (if necessary, move the
Status Monitor dialog box to access the Run button).
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Counting Setup and Hold Violations (Exercise 4)
View the Status Monitor
Watch the count in the Status Monitor as it increases to the terminal count of 100
million. The Tektronix Logic Analyzer has a zero (0 ns) latency that allows it to
count every failure without missing a single one. In some situations a failure
could happen once a minute, once an hour, and even less than once a day. A
critical application in a real time system with one failure a week could be
disastrous. The Tektronix Logic Analyzer can help find these types of failures.
The Status Monitor should look similar to Figure 2–18.
Figure 2–18: Status Monitor for Exercise 4
NOTE. If you do not want to wait for the logic analyzer to reach the terminal
count, you can click on the Stop button at any time.
Note the use of timers in Figure 2–18. You can use a timer to keep track of how
many violations occurred over a period of time. In Figure 2–18, you can see that
the logic analyzer detected and counted over 100,000,000 violations in just under
34 seconds. By using a timer on intermittent violations, you can see how many
violations actually occurred over certain number of hours or days.
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TLA 7QS Training Manual
View the Setups
Counting Setup and Hold Violations (Exercise 4)
Close the Status Monitor and open the Trigger window. Your trigger setups
should be similar to Figure 2–19.
Figure 2–19: LA Trigger window for Exercise 4
The Trigger window is set up to detect setup and hold violations. When the logic
analyzer detects the first violation, it starts a counter and a timer. The counter
counts the number of violations while the timer keeps track of the time since the
first violation.
The logic analyzer continues to count the violation until it reaches a terminal
count. When the terminal count is achieved, the logic analyzer stops the timer
and triggers all modules. The final counter and timer values are displayed in the
Status Monitor.
After viewing the setups, minimize any open windows (except the System
Window), and continue with the next exercise.
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Counting Setup and Hold Violations (Exercise 4)
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TLA 7QS Training Manual
Capturing Data Bursts Using Transitional Storage
(Exercise 5)
Often times you need to capture a series of events that are separated by wide
time intervals. Using conventional storage, your logic analyzer quickly fills with
redundant data thereby limiting your overall time window. What is needed is a
method where your logic analyzer stores data only when there is a transition
thereby avoiding redundant data storage. A logic analyzer with transitional
storage effectively extends your acquisition memory by lengthening the overall
time window covered by the acquisition. Using the Tektronix Logic Analyzer’s
transitional storage, you can sample at up to 4 ns on all channels so that events
that are seconds, minutes, hours, or even up to 6.5 days apart are still captured
with 4 ns timing resolution. You can then use the MagniVu 500 ps timing
resolution for a closer look at the data.
In the following exercise, you will set up the logic analyzer to capture a
repetitive signal consisting of four groups of eight 20 ns (50 MHz) pulses
separated by 1.3 ms of inactivity using both conventional and transitional storage
techniques. You will then contrast the difference in an effective overall time
window.
NOTE. Make sure that the C2:2 channel of the acquisition probe is connected to
the Burst signal on J860 on the training board. If necessary, refer to Connect the
Probes on page 2–2 for probe connection information.
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Capturing Data Bursts Using Transitional Storage (Exercise 5)
Load the Setup
1. Select Load System from the File menu.
2. Load the system setup:
5a-Capture Data Bursts Using Conventional Storage.tla.
The restored system should look similar to Figure 2–20.
Figure 2–20: Restored system for Exercise 5
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TLA 7QS Training Manual
View the Channel Setups
1. Open the Setup window; it should look similar to Figure 2–21. The sampling
Capturing Data Bursts Using Transitional Storage (Exercise 5)
is set to 4 ns and the memory depth is set to 1 K for the Burst signal.
Figure 2–21: Setup window for Exercise 5
2. Minimize the Setup window.
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Capturing Data Bursts Using Transitional Storage (Exercise 5)
View the Trigger Program Using Conventional Storage
1. Open the Trigger window; your trigger setups should look similar to
Figure 2–22.
The logic analyzer is set to trigger on the first data burst of the Burst signal using
conventional storage (transitional storage is disabled).
Figure 2–22: Trigger window using conventional storage for Exercise 5
2. Minimize the Trigger window.
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Capturing Data Bursts Using Transitional Storage (Exercise 5)
View the Acquired Data Using Conventional Storage
1. Open the waveform window labeled Burst and ensure that it is maximized.
2. Click the Run button to begin acquiring data. The acquired data should look
similar to Figure 2–23.
Figure 2–23: Timing waveform using conventional storage for Exercise 5
There will be four groups of eight 20 ns (50 MHz) pulses following the trigger.
The next four data bursts appear approximately 1.31 ms later with no signal
activity in between. However, since you have selected 1 K memory depth, you
can only see the first burst of four groups of eight pulses. You don’t have the
depth to see the next burst which is approximately 1.31 ms away.
3. Right-click the mouse in the waveform window and Select Zoom > All (it
may take a few seconds for the right-click menu to appear).
Notice that the overall time window is only approximately 4.1 ms.
Observe that there is a tremendous amount of redundant data being stored (all
zeros). What if you only stored when the data transitioned thereby widening the
time window to see the next data burst and yet maintain the 4 ns timing
resolution?
4. Minimize the waveform window.
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Capturing Data Bursts Using Transitional Storage (Exercise 5)
View the Trigger Program Using Transitional Storage
1. Select Load System from the File menu.
2. Load the system setup:
5b-Capture Data Bursts Using Transitional Storage.tla.
3. Go to the Trigger window. It should look similar to Figure 2–24.
The logic analyzer is set to trigger on the first data burst of the Burst signal with
transitional storage enabled. Note that the Storage drop-down menu has
Transitional selected. Also note that the Change Detect clause under Storage is
open and shows that the Burst group is selected.
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Figure 2–24: Trigger window using transitional storage for Exercise 5
4. Minimize the Trigger window.
TLA 7QS Training Manual
Capturing Data Bursts Using Transitional Storage (Exercise 5)
View the Acquired Data Using Transitional Storage
1. Open the waveform window labeled Burst and ensure that it is maximized.
2. Click the Run button to begin acquiring data.
3. Right-click the mouse in the waveform window and Select Zoom All (it may
take a few seconds for the right-click menu to appear).
4. The waveform window should look similar to Figure 2–25.
TLA 7QS Training Manual
Figure 2–25: Timing waveform using transitional storage for Exercise 5
Notice that instead of one burst of four groups of eight pulses, the memory is
filled with 16 bursts of the four groups of eight pulses and that the time window
changed from approximately 4.1 ms to 19.7 ms.
For the Burst signal, this represents an overall time window that is almost 4800
times greater using transitional storage compared to conventional storage!
5. Change the Time/Div to 100 ns.
6. Right-click the mouse, and select Go To, followed by Go To to display the
Go To dialog box.
7. Double-click System Trigger in the Go To dialog box.
8. Center the four groups of eight pulses so that the waveform window appears
similar to Figure 2–26 (use the horizontal scroll bars in the waveform
window or use the front-panel Horizontal Position control on the TLA600 or
on the portable mainframe).
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Capturing Data Bursts Using Transitional Storage (Exercise 5)
Figure 2–26: Waveform data at 100 ns Time/Div
9. Move Cursor 1 to the leading edge of the first pulse in the burst.
10. Move Cursor 2 to the leading edge of the second pulse in the burst.
Note that the periods is 20 ns (50 MHz) and the the data was acquired with
4 ns resolution.
11. To obtain 500 ps timing resolution, add the MagniVu version of the Burst
signal by doing the following steps:
a. Click the Add Waveform button (the left-most button) on the Waveform
window tool bar to display the Add Waveform dialog box.
b. Select LA 1 - MagniVu from the Data Source list at the top of the dialog
box.
c. Select Sample and then click the Add button on the top right side of the
dialog box.
d. Click on the plus sign to the left of Mag_Burst, select Mag_Burst(0),
and then click on the Add button again.
e. Click the Close button.
12. Select the Mag_Burst(0) waveform and change the vertical size using the
Vertical Size knob until the waveform window appears similar to Figure 2–27. (You can also select the waveform, right-click the mouse and then
select Properties. Adjust the Height selection in the dialog box.)
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Capturing Data Bursts Using Transitional Storage (Exercise 5)
Figure 2–27: Timing waveform using transitional storage with
MagniVu for Exercise 5
Optional
You can now view the Burst signal with eight times better resolution (500 ps
timing resolution).
Transitional storage also works with synchronous or external clocking; that is
why transitional storage is a trigger storage function. Also note that the
maximum time window with transitional storage enabled is highly dependent on
the data rate.
Set the memory depth of the logic analyzer to the maximum depth. Use the
cursors to observe the maximum time window difference between conventional
and transitional storage techniques. For example, Table 2–2 shows the number of
data bursts and overall time windows at the specified memory depths.
T able 2–2: Relationship between the number of data bursts and overall time
windows
Memory
depth using
transitional
storage
256 KB1.2 GB5.4 seconds44, 886
Memory
depth using
conventional
storage
Overall time window
Number of data
bursts captured
TLA 7QS Training Manual
4 MB19.2 GB1 minute, 26 seconds715, 684
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Capturing Data Bursts Using Transitional Storage (Exercise 5)
You can find the overall time window in the upper, right corner of the waveform
window on the Sample group. You should perform a Zoom-All operation so that
the entire acquisition memory is displayed. You can also monitor the progress of
the amount of acquisition memory by opening the Status Monitor dialog box
(click the Status button to the left of the Run button in the System window).
Conclusion
With transitional storage, you can quickly capture intermittent events which
dramatically extends the time window covered by the logic analyzer. You can
then use the 500 ps MagniVu timing resolution to obtain greater timing detail.
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TLA 7QS Training Manual
Using the DSO to Trigger the Logic Analyzer on a Runt
Pulse (Exercise 6)
NOTE. This exercise can only be completed with a Tektronix Logic Analyzer with
a digitizing oscilloscope module (DSO).
Runt pulses can be the result of the same conditions that cause a glitch (described in the first exercise). However, runt pulses can also be due to other
system problems such as power supply dropouts, bus contention, or high
resistance connections. Runt pulses are serious problems in the design of digital
systems. The digitizing oscilloscope (DSO) adds the flexibility to your Tektronix
Logic Analyzer to detect events of more analog characteristics than using a logic
analyzer alone.
A runt pulse is defined as a pulse with the amplitude greater than the lower
threshold voltage, but less than the higher threshold voltage. A runt pulse can
also be defined in terms of pulse width (that is, any pulse width equal to or
greater than a specified pulse width). The logic analyzer may not be able to
detect the runt pulse by itself. However you can set up the DSO to look for a runt
pulse and then trigger the logic analyzer.
Load the Setup
1. Select Load System from the File menu.
2. Open the Hardware Analysis folder and load the saved system 5-DSO
Captures a Runt and Triggers LA.tla.
Make sure that you restore both the My DSO and My Analyzer setups.
3. Click the On button in the MY DSO icon.
You can enable or disable a module from a setup by clicking the On or Off
button in the module icon. The DSO module had been disabled in the
previous exercises; to enable it, you must click the On button.
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Using the DSO to Trigger the Logic Analyzer on a Runt Pulse (Exercise 6)
View the Resultant Data
1. Open the waveform data window labeled FF-Analysis.
2. Note the Repetitive Run button to the right of the Run button.
The button should have a loop as shown in the illustration below. The
Repetitive Run button lets you acquire data continuously until you click on
the Stop button or until you click on the Repetitive Run button to change it
to the Single Acquisition mode (default setting).
3. Click on the Run button to begin acquiring data.
The logic analyzer will acquire data continuously.
4. Notice how the data appears with each acquisition.
The data is different at various acquisitions because of when the logic
analyzer sampled the data. You can use the Repetitive Run mode to see how
often the data changes and to help you decide when you have a good data
sample to continue your measurements.
5. Click on the Stop button.
6. If the waveform data window doesn’t show the data that you want to
measure, acquire another sample and then click on the Stop button again.
The waveform data window should look similar to Figure 2–28.
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Using the DSO to Trigger the Logic Analyzer on a Runt Pulse (Exercise 6)
Figure 2–28: Timing waveform display for Exercise 6
7. Use the cursors to measure width and voltage magnitude of the runt pulse.
To measure the voltage levels, move cursor 1 over the peak of the runt pulse,
then click on the My DSO:FF_Q-OUT waveform label. The voltage level for
the captured runt pulse will appear on the measurement bar, next to C1.
8. Refer to the logic analyzer data and view the pulse.
Depending on the amplitude of the runt pulse, the logic analyzer may not
have captured the runt pulse (see Figure 2–28).
You can use the high resolution mode to see the runt pulse more often. Add a
new waveform using the MagniVu feature by completing the following steps:
9. Position the mouse cursor over the waveform My DSO:FF_Q-OUT and
right-click on the mouse.
10. Select Add Waveform from the popup menu.
11. In the Data Source field, select My Analyzer-MagniVu.
12. Click on By Group and then click on the plus sign next to the Mag_FF
Q-OUT waveform.
13. Select the line containing the signal name Mag_FF-Q.
TLA 7QS Training Manual
14. Click on Add and then Close.
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Using the DSO to Trigger the Logic Analyzer on a Runt Pulse (Exercise 6)
15. Click on Run and notice the difference in the waveforms when the logic
analyzer captures the runt pulse. Also notice how the logic analyzer data
correlates with the DSO data.
NOTE. Because of minor differences in the training boards, you may have
perform several acquisitions to see the runt pulse captured by the logic analyzer.
View the Trigger Setups
1. Close the waveform data window and click on Setup in the DSO icon.
The DSO Setup window shows the setups for each vertical input channel,
horizontal channel information, and trigger information. Your DSO setups
for Channel 1 should be similar to Figure 2–29.
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Figure 2–29: DSO channel 1 setups for Exercise 6
2. Click on the DSO Trigger tab. The DSO Trigger window should be similar
to Figure 2–30.
The DSO Trigger shows the trigger setups for the DSO. For this exercise, the
DSO is looking for a runt pulse within the specified parameters. When the
DSO detects a runt pulse, it triggers the logic analyzer module.
TLA 7QS Training Manual
Using the DSO to Trigger the Logic Analyzer on a Runt Pulse (Exercise 6)
Figure 2–30: DSO trigger setups for Exercise 6
3. Now look at the logic analyzer setups.
Note that in this exercise the logic analyzer did not specify a trigger
condition. In other words, you used the DSO to look for a trigger event and
then display the DSO data and logic analyzer data without specifying any
special logic analyzer trigger details.
4. After viewing the setups, minimize any open windows (except the System
Window), and continue with the next exercise.
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Using the DSO to Trigger the Logic Analyzer on a Runt Pulse (Exercise 6)
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TLA 7QS Training Manual
Using the Logic Analyzer to Trigger the DSO (Exercise 7)
NOTE. This exercise can only be completed with a Tektronix Logic Analyzer with
a digitizing oscilloscope module (DSO).
With the high speeds of digital circuitry, design engineers are no longer able to
rely on circuits working perfectly because they are logically or functionally
correct. Analog characteristics of digital signals can become critical. Phenomenons such as reflections caused by unterminated signals or stubs can cause
serious design problems.
Today’s high-speed digital designer needs the ability to closely examine analog
characteristics to determine the actual cause of failures. The ability to use a logic
analyzer to trigger on a failure and then to analyze the analog characteristics of
the signals involved in causing such failures can be critical in providing a correct
solution for the problem.
This exercise uses setups similar to Exercise 1. The logic analyzer is set up to
look for a glitch using the MagniVu feature.
Load the Setup
1. Select Load System from the File menu.
2. Load the system setup 6-LA Triggers DSO.tla.
3. Click on the Run button to begin acquiring data.
The logic analyzer will acquire and capture glitch data.
TLA 7QS Training Manual
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Using the Logic Analyzer to Trigger the DSO (Exercise 7)
View the Resultant Data
1. Open the waveform data window labeled FF Analysis. The window should
look similar to Figure 2–31.
Figure 2–31: Waveform display for Exercise 7
The logic analyzer captured a glitch, but you really want to know more about the
glitch. You want to know what caused the glitch and what was the actual signal
amplitude. To do this you want to look at the signal with an oscilloscope.
You can easily add an oscilloscope waveform to the current waveform display
and correlate the data.
2. Move the mouse cursor over the FF–Q waveform and right-click the mouse.
3. Select Add Waveform from the popup menu.
4. In the Data Source field, select DSO 1.
5. Select Channel 1.
6. Click on Add and then Close.
The DSO waveform is added to the view.
7. Click on the Run button to acquire the data.
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Using the Logic Analyzer to Trigger the DSO (Exercise 7)
Figure 2–32 shows the resultant data (your data may be different). Notice
how the glitch correlates to the signal acquired by the DSO. By using a logic
analyzer side-by-side with a DSO, you have a powerful troubleshooting and
design tool.
Figure 2–32: Resultant waveform data for Exercise 7
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Using the Logic Analyzer to Trigger the DSO (Exercise 7)
View the Setups
The logic analyzer Trigger window was set up to detect a glitch and then to
trigger all modules. The DSO trigger was set up to wait for the system trigger
from the logic analyzer module (see Figure 2–33). When the DSO received the
system trigger, it acquired the data on the channel 1 probe.
Figure 2–33: DSO channel trigger setups for Exercise 7
This completes the general purpose hardware exercises. The exercises in the next
chapter show how to use a logic analyzer and an oscilloscope to identify and
isolate problems in microprocessor-based systems.
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Microprocessor Support
Debug Exercises
Microprocessor Exercises Setup
The following exercises use the Microprocessor section of the training board to
demonstrate the microprocessor hardware and software analysis features of the
Tektronix Logic Analyzers.
Hardware Setups
To complete the exercises in this chapter, you will need a logic analyzer with 102
or more data channels (TLA 7N3, TLA 7N4, TLA 7P4 logic analyzer modules,
or TLA 6x3 or TLA 6x4) with six P6418 or P6417 Probes or three P6434
Probes. A DSO module is optional, but not required for any of the exercises in
this chapter.
Connect the probes to the appropriate A, D, and C connectors on the logic
analyzer module. You will use the same probe connections through the remainder
of this chapter.
Set Up the P6418 or P6417 Probes
You will need all P6418 or P6417 Probe podlets properly installed in the podlet
holders. If you need to reinstall the probe podlets, refer to Reinstalling Podlets
on page 2–2, and reinstall the podlets in the podlet holders before continuing
with the exercises in this chapter.
NOTE. If you decide to connect the P6418 or P6417 Probe podlets individually,
make sure that you connect each podlet in the correct order.
TLA 7QS Training Manual
3–1
Microprocessor Exercises Setup
Connect the Probes
Refer to Figure 3–1 through Figure 3–3 and connect the probes to the Microprocessor section of the TLA 7QS QuickStart training board as shown. Choose the
figure according to the type of probe that you have.
If you have P6417 probes, connect the probes to the training board as shown in
Figure 3–1. Connect the address, data, and control groups to the appropriate
connectors on the training board. Connect the clock/qualifier leads to appropriate
pins on the training board. Make sure that you connect the signal side of the
probes to signal side of the square pins (ground connections are toward the rear
of the training board as you face the LCD display; refer to the markings on the
training board, if necessary).
If you have P6418 probes, connect the probes to the training board as shown in
Figure 3–2. Connect the address, data, and control groups to the appropriate
connectors on the training board. Connect the clock/qualifier leads to appropriate
pins on the training board. Make sure that you connect the signal side of the
probes to signal side of the square pins (ground connections are toward the rear
of the training board as you face the LCD display; refer to the markings on the
training board, if necessary).
Start the Tektronix Logic Analyzer Family application and continue with the
following steps. You will use the same hardware setup through the remainder of
this chapter.
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Load the Setups
Microprocessor Exercises Setup
Perform the following steps to load the microprocessor exercises. All microprocessor exercises are contained in the same folder (C:\Program Files\TLA 700\
Quick Start\Microprocessor Analysis).
NOTE. Each exercise contains two saved setup files. One file contains only setup
information and requires you to capture live acquisition data to complete the
exercises. The other file contains setup information and saved data. Use the
saved data files to complete nearly every exercise without the need for acquiring
live data.
You can also use TLAVu to complete the exercises off-line without needing any
acquisition hardware.
1. Select Load System from the File menu.
2. Open the Microprocessor Analysis folder and select the file as defined in the
individual exercises (for example, load the 1-Capture Power Up Code.tla file
for Exercise 1).
The logic analyzer display should look similar to Figure 3–4.
Figure 3–4: Load System dialog box
3. When prompted to load without saving the current system, click on Yes.
TLA 7QS Training Manual
4. If you get a message telling you that the configuration in the file does not
match your current hardware, click on OK.
3–5
Microprocessor Exercises Setup
5. A Load System Options dialog box appears, similar to Figure 3–5.
3–6
Figure 3–5: Load System Options dialog box
6. Drag the QSTART icon (and the My DSO icon, if needed) from the top of
the dialog box to the shaded LA1 icon in the Current System area of the
dialog box.
7. Click on OK to continue with the exercise.
TLA 7QS Training Manual
Microprocessor Exercises Setup
NOTE. If the Load System Options dialog box appears and you want to view
saved data, you may need to complete steps 8 through 11 to load a data window
with saved acquisition data.
To determine if you need to perform the following steps, click on one of the data
window icons. If data appears in the data window, you can continue with the
exercise. If no data appears, complete the following steps.
8. Select Load Data Window from the Window menu; the Load Data Window
dialog box displays.
9. Click the Browse button, navigate to the Microprocessor Analysis setup
folder, and then double-click the setup for the current exercise.
10. Select the data window from the list in the Load Data Window dialog and
then click OK; the Name Data Window dialog box displays.
11. Change the name of the data window (it is recommended that you only
change one or two characters so the name is similar to the original data
window).
Now you have a data window that displays saved acquisition data for the current
exercise. If you want to continue with the exercise and capture live data, refer
back to the original data window that was loaded with the setup.
TLA 7QS Training Manual
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Microprocessor Exercises Setup
3–8
TLA 7QS Training Manual
Trigger on a Power-on Reset and Capture the Controller
Startup Code (Exercise 1)
Verifying the startup code of a microprocessor-based system can be easy using a
logic analyzer. If you know the reset vectors, you can set up the logic analyzer to
look for the reset address and then display the disassembled data in a Listing
window.
In this exercise you will capture the startup code of the training board.
Load the Setup
1. Power off the training board.
2. Load the 1-Capture Power Up Code.tla system setup from the C:\Program
3. Click on the Run button to begin acquiring data.
4. When the Run button changes to Stop, the logic analyzer status changes to
Running, and the animated TEK icon in the upper right hand corner is
moving, power on the training board.
The logic analyzer should trigger and capture the startup code of the training
board.
TLA 7QS Training Manual
3–9
Trigger on a Power-on Reset and Capture the Controller Startup Code (Exercise 1)
View the Resultant Data
1. Open the Listing window labeled RESET Code. The window should contain
the disassembled startup code and should look similar to Figure 3–6.
Figure 3–6: Listing window for Exercise 1
2. Notice how the RESET sequence and all software instructions are high-
lighted.
3. Examine the code to see how the microprocessor reads the stack pointer
followed by the startup address.
4. Scroll through the data until you find a flush in the mnemonics column.
The flush should be approximately 70 samples after RESET. A flush
indicates that an instruction was fetched into the prefetch queue, but was
then flushed from the queue because a branch was taken before the instruction was executed.
5. Right-click once on any column label to open a menu.
6. Select Properties from the menu; then select the Disassembly tab in the
Properties dialog box.
7. Change the Highlight and Show fields in the Properties dialog box.
8. Apply the changes and see how they affect the display.
Notice how you can focus on hardware, software, control flow, or subroutines.
3–10
TLA 7QS Training Manual
Trigger on a Power-on Reset and Capture the Controller Startup Code (Exercise 1)
9. Right-click on any column label to open a menu.
10. Select Properties from the menu; then select the Column tab.
11. Change the color of the selected column.
12. Apply the changes and see how you can use color to emphasize one or more
columns in the display.
13. Minimize the RESET Code Listing window.
14. Open the RST Bus Cycl Waveform window to view the detailed timing of a
bus cycle. Notice the high resolution provided by the MagniVu feature with
2 GHz sampling.
The RST Bus Cycl view should look similar to Figure 3–7.
TLA 7QS Training Manual
Figure 3–7: Timing waveform display for Exercise 1
3–11
Trigger on a Power-on Reset and Capture the Controller Startup Code (Exercise 1)
View the Trigger and Channel Setups
1. Minimize the Waveform window and click on the Trig button in the logic
analyzer icon.
2. The Trigger window should be similar to Figure 3–8.
3. Click on the If-Then button to open the Clause Definition dialog box.
Notice that the Trigger setups use symbol files rather than hexadecimal or
binary code. Symbol files make it easier to define and display the setups.
Figure 3–8: Trigger window for Exercise 1
4. Close the Trigger window and click on the Setup button in the logic analyzer
icon.
The channel setups are dependent on the microprocessor support package.
Note the use of Custom clocking and the individual channel assignments.
5. When you are done looking at the setups, minimize any open windows
(except the System window), and continue with the next exercise.
3–12
TLA 7QS Training Manual
Use Trigger Timers to Measure Interrupt Latency
(Exercise 2)
The training board is a microprocessor-based system controlled by buttons. The
buttons send interrupts to the microprocessor. The microprocessor interprets the
interrupt and determines the proper action to respond to the interrupt.
This exercise focuses on using multiple trigger states and timers to measure
interrupt latency. To do this, the logic analyzer starts a timer on the assertion of
an interrupt (when a button is pushed) and then triggers when the interrupt
service routine ends.
Load the Setup
1. Select Load System from the File menu.
2. Load the system setup 2-Measuring Interrupt Latency.tla.
3. Click on the Run button to begin acquiring data.
TLA 7QS Training Manual
3–13
Use Trigger Timers to Measure Interrupt Latency (Exercise 2)
Measure Timers
1. Click on the Status button to the left of the Run button in the System
window to open the Status Monitor.
2. When the Run button changes to Stop, push the F1 button on the training
board.
3. Note the timer values after the logic analyzer triggers.
NOTE. You may not have a DSO section in the Status Monitior.
3–14
Figure 3–9: Status Monitor
Timer 1 measured the time from the assertion of the interrupt (when you pushed
the F1 button) to the time that the microprocessor read the resultant interrupt
vectors. Timer 2 measured the time to finish the interrupt service routine.
TLA 7QS Training Manual
View the Resultant Data
Use Trigger Timers to Measure Interrupt Latency (Exercise 2)
1. Close the Status Monitor and open the Int Svc Code Listing window.
2. Notice the highlighted instructions in the window.
Highlighting helps you identify the Int Ack Cycle, interrupt auto vectors, the
start of the interrupt service routine, and the RTE instruction that ends the
interrupt service routine (you may need to scroll the display to view all of
the instructions).
The Int Svc Code Listing window should look similar to Figure 3–10.
TLA 7QS Training Manual
Figure 3–10: Listing window for Exercise 2
3–15
Use Trigger Timers to Measure Interrupt Latency (Exercise 2)
View the Setups
1. To understand how the logic analyzer uses timers to measure interrupt
latency, view the setups in the Trigger window (see Figure 3–11).
3–16
Figure 3–11: Trigger window for Exercise 2
2. State 1 clears the transition recognizer to a known state before looking for a
transition on channel IRQ~3 in State 2. You must never use a transition
recognizer in State 1.
3. Notice the multiple trigger states that start a timer on the insertion of an
interrupt and then trigger the logic analyzer when the Interrupt Service
Routine ends.
4. After studying the trigger setups, minimize any open windows (except the
System window), and continue with the next exercise.
TLA 7QS Training Manual
Trigger on Faulty Data Written to the LED Display
(Exercise 3)
The remaining exercises in this chapter focus on using a logic analyzer to
troubleshoot the system so that you can detect software or hardware problems.
The exercises use one of the programs on the training board, the AUTO DELAY
program. The program simulates a hardware problem in the form of a data
readback error that causes an improper LED display on the training board.
A data read error causes the microprocessor to write the wrong data value to the
LEDs. The LED register must contain a logic low to light the LED. For example,
if the value AAAA is written to the LED port on the QuickStart training board,
the LEDs display 5555.
The following exercises are set up to simulate a typical troubleshooting
sequence. In exercise 3, you will use disassembly to determine where the data is
being written. In Exercise 4, you will verify that the written data is actually
wrong and use the high resolution MagniVu feature to determine from where the
microprocessor gets the incorrect data. Exercise 5 shows how to use setup and
hold triggering to verify that a timing error is the cause of the problem.
The microprocessor executes code in the following sequence:
1. The CPU reads data from address 0054 0000.
2. The CPU complements the data.
3. The CPU then writes data to address 0044 0000 (the LED port).
TLA 7QS Training Manual
3–17
Trigger on Faulty Data Written to the LED Display (Exercise 3)
Load the Setup
1. Select Load System from the File menu.
2. Load the system setup 3-Capture Error on LEDs.tla.
3. Click on the Run button to begin acquiring data.
4. Find the AUTO DELAY program on the training board by using the UP and
DN buttons to scroll through the program list.
5. Press the RUN button on the training board to start the AUTO DELAY
program.
The LEDs should display the data as directed by the program. At one point
the LEDs will display incorrect data that will trigger the logic analyzer.
View the Resultant Data
1. After the logic analyzer triggers and captures the data, open the LED Error
Listing window. This window contains the disassembled data and should
look similar to Figure 3–12.
3–18
Figure 3–12: Listing window for Exercise 3
2. Locate the trigger mark in the LED Error Listing window and find the data
value that caused the logic analyzer to trigger.
The data written by the microprocessor to address 0044 0000 was not AAAA
as expected.
TLA 7QS Training Manual
View the Setups
Trigger on Faulty Data Written to the LED Display (Exercise 3)
1. To understand how the logic analyzer triggered on the faulty data, view the
setups in the Trigger window (see Figure 3–13).
2. Notice that the word recognizer is set up to trigger when the microprocessor
writes data other than AAAA to the LED.
Figure 3–13: Trigger window for Exercise 3
3. Click on the If/Then button to see other trigger definitions and windows that
are used in this exercise.
4. Before proceeding to the next exercise, press the STOP button on the
training board, and minimize all open windows (except the System window).
TLA 7QS Training Manual
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Trigger on Faulty Data Written to the LED Display (Exercise 3)
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TLA 7QS Training Manual
Trigger on Faulty Data Read by the CPU (Exercise 4)
In the previous exercise, you used the logic analyzer to verify that the data
written to the LEDs was incorrect. You already know that you do not have an
LED hardware problem because the LEDs occasionally display the correct data.
The next step in isolating the problem is to determine if the microprocessor reads
the correct data.
In this exercise you will use the logic analyzer to trigger on faulty data being
read by the microprocessor to capture a register read error. You will use the high
resolution timing MagniVu feature to check the circuit timing.
NOTE. Make sure that the AUTO DELAY program is not running on the training
board before you start this exercise.
Load the Setup
1. Select Load System from the File menu.
2. Load the saved system 4-Capture a Faulty Data Read by the CPU.tla.
3. Click on the Run button to begin acquiring data.
4. Press the RUN button on the training board to start the AUTO DELAY
program.
TLA 7QS Training Manual
3–21
Trigger on Faulty Data Read by the CPU (Exercise 4)
View the Resultant Data
1. Open the Read Error Listing window after the logic analyzer triggers.
2. Locate the trigger mark and see what data value the microprocessor read.
The Read Error Listing window contains the disassembled data and should
look similar to Figure 3–14. The data read from address 0054 0000 was not
5555 as expected. This explains why the data written to the LEDs is
incorrect. The next step is to find out why the data is incorrect.
3–22
Figure 3–14: Listing window for Exercise 4
3. Open the Mag Read Err Waveform window and check the circuit timing.
The window uses the MagniVu feature of the logic analyzer to help you
analyze the timing of the failing bus cycle. According to the microprocessor
specifications, the data must be stable for 5 ns before the falling edge of the
clock before the data strobe (DS) signal goes high. The Mag Read Err
Waveform window should look similar to Figure 3–15.
Notice that the data was not stable 5 ns before the falling edge of the clock.
TLA 7QS Training Manual
Trigger on Faulty Data Read by the CPU (Exercise 4)
Figure 3–15: Waveform window for Exercise 4
4. Zoom in on the faulty data, and you can see the actual data read by the logic
analyzer in the Listing window (Figure 3–14).
5. To zoom in on the data, move the mouse pointer to just before the data
changes on the Mag_Data bus. Press and hold the left mouse button and drag
the mouse to create a dashed box. Your display should look like Figure 3–16.
Right-click the mouse and select Zoom from the menu.
TLA 7QS Training Manual
Figure 3–16: Waveform window with dashed zoom box
3–23
Trigger on Faulty Data Read by the CPU (Exercise 4)
6. To alternately zoom on the data, click on the Zoom In button on the top right
of the display. If you have a portable mainframe, you can use the front panel
Horizontal SCALE and POSITION controls to zoom in on the data.
View the Setups
1. To understand how the logic analyzer triggered on the faulty data, view the
setup in the Trigger window (see Figure 3–17).
Notice that the word recognizer is set up to trigger when the CPU reads data
other than 5555.
3–24
Figure 3–17: Trigger window for Exercise 4
2. Press the STOP button on the training board.
3. Before proceeding to the next exercise, minimize all open windows (except
the System window).
TLA 7QS Training Manual
Trigger on a Setup Violation of the CPU Read Cycle
(Exercise 5)
In the previous two exercises, you discovered that a timing problem is causing
the LEDs to display the wrong data. In this exercise, you will use the logic
analyzer to trigger on a setup violation on the data signals to verify the problem.
NOTE. Make sure that the AUTO DELAY program is not running on the training
board before you start this exercise.
Load the Setup
1. Select Load System from the File menu.
2. Load the saved system 5-Capture a CPU Read Setup Violation.tla.
3. Click on the Run button to begin acquiring data.
View the Resultant Data
4. Press the RUN key on the training board to start the AUTO DELAY
program.
1. Open the Mag Read Err waveform data window after the logic analyzer
triggers. The view should look similar to Figure 3–18.
2. Notice how the logic analyzer displays the data and address lines in
busforms rather than displaying each address or data line individually.
The busforms help you focus on the area of interest. In this case you are
interested at the point where the data transition takes place. Using the
MagniVu timing mode to analyze the timing of the failed bus cycle, you can
see that the data was not stable at the time the microprocessor executed the
read cycle. The microprocessor specifications require that the data must be
stable for 5 ns before the falling edge of the clock before the data strobe (DS)
signal goes high.
TLA 7QS Training Manual
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Trigger on a Setup Violation of the CPU Read Cycle (Exercise 5)
Figure 3–18: Waveform data window for Exercise 5
3. To see which data channel caused the setup failure, you can expand the data
bus. Right-click on the Mag_Data signal label on the left side of the
waveform window. Then select Expand Channels. Notice that the 16 data
channels now show in the waveform window.
4. Scroll up until you see Mag_Data_13. The waveform data should look
similar to Figure 3–19. This data channel is transitioning too late and causes
the setup violation.
3–26
Figure 3–19: Expanded data channels showing a setup violation for Exercise 5
TLA 7QS Training Manual
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