There are no current European directives that
apply to this product. This product provides cable
and test lead connections to a test object of
electronic measuring and test equipment.
This document supports firmware version 1.00
and above.
Warning
The servicing instructions are for use by qualified
personnel only. To avoid personal injury, do not
perform any servicing unless you are qualified to
do so. Refer to all safety summaries prior to
performing service.
Copyright T ektronix, Inc. All rights reserved. Licensed software products are owned by Tektronix or its suppliers and
are protected by United States copyright laws and international treaty provisions.
Use, duplication, or disclosure by the Government is subject to restrictions as set forth in subparagraph (c)(1)(ii) of the
Rights in T echnical Data and Computer Software clause at DFARS 252.227-7013, or subparagraphs (c)(1) and (2) of the
Commercial Computer Software – Restricted Rights clause at F AR 52.227-19, as applicable.
T ektronix products are covered by U.S. and foreign patents, issued and pending. Information in this publication supercedes
that in all previously published material. Specifications and price change privileges reserved.
Printed in the U.S.A.
T ektronix, Inc., P.O. Box 1000, Wilsonville, OR 97070–1000
TEKTRONIX and TEK are registered trademarks of T ektronix, Inc.
MagniVu is a registered trademark of T ektronix, Inc.
Review the following safety precautions to avoid injury and prevent damage to
this product or any products connected to it. To avoid potential hazards, use this
product only as specified.
Only qualified personnel should perform service procedures.
While using this product, you may need to access other parts of the system. Read
the General Safety Summary in other system manuals for warnings and cautions
related to operating the system.
To Avoid Fire or
Personal Injury
Connect and Disconnect Properly . Do not connect or disconnect probes or test
leads while they are connected to a voltage source.
Observe All Terminal Ratings. To avoid fire or shock hazard, observe all ratings
and marking on the product. Consult the product manual for further ratings
information before making connections to the product.
Do not apply a potential to any terminal, including the common terminal, that
exceeds the maximum rating of that terminal.
Use Proper AC Adapter. Use only the AC adapter specified for this product.
Do Not Operate Without Covers. Do not operate this product with covers or panels
removed.
Use Proper Fuse. Use only the fuse type and rating specified for this product.
Avoid Exposed Circuitry. Do not touch exposed connections and components
when power is present.
Do Not Operate With Suspected Failures. If you suspect there is damage to this
product, have it inspected by qualified service personnel.
Do Not Operate in Wet/Damp Conditions.
Do Not Operate in an Explosive Atmosphere.
Keep Product Surfaces Clean and Dry .
Provide Proper Ventilation. Refer to the manual’s installation instructions for
details on installing the product so it has proper ventilation.
TLA QuickStart Technical Reference Manual
vii
General Safety Summary
Symbols and Terms
T erms in this Manual. These terms may appear in this manual:
WARNING. Warning statements identify conditions or practices that could result
in injury or loss of life.
CAUTION. Caution statements identify conditions or practices that could result in
damage to this product or other property.
T erms on the Product. These terms may appear on the product:
DANGER indicates an injury hazard immediately accessible as you read the
marking.
WARNING indicates an injury hazard not immediately accessible as you read the
marking.
CAUTION indicates a hazard to property including the product.
Symbols on the Product. The following symbols may appear on the product:
WARNING
High Voltage
Protective Ground
(Earth) T erminal
CAUTION
Refer to Manual
Double
Insulated
viii
TLA QuickStart Technical Reference Manual
Service Safety Summary
Only qualified personnel should perform service procedures. Read this Service
Safety Summary and the General Safety Summary before performing any service
procedures.
Do Not Service Alone. Do not perform internal service or adjustments of this
product unless another person capable of rendering first aid and resuscitation is
present.
Disconnect Power. To avoid electric shock, disconnect the main power by means
of the power cord or, if provided, the power switch.
Use Care When Servicing With Power On. Dangerous voltages or currents may
exist in this product. Disconnect power, remove battery (if applicable), and
disconnect test leads before removing protective panels, soldering, or replacing
components.
To avoid electric shock, do not touch exposed connections.
TLA QuickStart Technical Reference Manual
ix
Preface
The TLA 7QS Technical Reference Manual is an optional accessory to the TLA
7QS package. It is intended to provide technical and service information for the
TLA 7QS training board.
How to Use This Document
The manual is made up of the following sections:
The Getting Started chapter provides a brief overview of the product.
The Reference chapter consists of basic reference information on the training
The Specifications chapter lists specifications and various characteristics of
The Theory of Operation chapter describes the basic operation of the
board. It consists of subsections describing the hardware features, software
features, memory maps, and programming information for using the training
board.
the training board.
electronic circuitry on the training board. This chapter can be used in
conjunction with the schematics to provide an overall understanding of the
operation and capabilities of the training board.
The Functional Verification Procedures chapter provides information for
verifying functional operation beyond the power-on diagnostics.
The Maintenance chapter provides information on the basic service strategy,
static handling procedures, inspection and cleaning procedures, simple
troubleshooting procedures, and repackaging instructions.
The Replaceable Electrical Parts chapter lists the electronic components on
the training board.
The Schematics chapter provides individual schematics for the circuitry on
the training board.
The Replaceable Mechanical Parts chapter lists the mechanical replaceable
parts and accessories for the training board.
Appendix A: Source Code provides information on the program code used
with the training board software. It also provides examples of code that can
be used to create programs and to download them to the training board.
TLA QuickStart Technical Reference Manual
xi
Preface
Related Documentation
Manual Conventions
Several other pieces of documentation are available to use with the TLA 700
Series Logic Analyzers. The information consists of both online documentation
and paper copies.
The TLA 700 Series Logic Analyzer User Manual provides basic user
information for the TLA 700 Series Logic Analyzers.
Use the online help in the TLA 700 Series logic analyzer to obtain operating
information and for specific information on windows, menus, and fields
within the application.
The TLA 7QS QuickStart Training Manual provides examples of exercises to
demonstrate the capabilities of the TLA 700 Series logic analyzers.
The following manual conventions are found in this document:
Contacting Tektronix
Active low signals are identified by an asterisk (*) after the signal name.
The term training board represents the TLA 7QS QuickStart training board.
Product
Support
Service
Support
For other
information
To write usTektronix, Inc.
For application-oriented questions about a Tektronix measurement product, call toll free in North America:
1-800-TEK-WIDE (1-800-835-9433 ext. 2400)
6:00 a.m. – 5:00 p.m. Pacific time
Or contact us by e-mail:
tm_app_supp@tek.com
For product support outside of North America, contact your
local Tektronix distributor or sales office.
Contact your local Tektronix distributor or sales office. Or visit
our web site for a listing of worldwide service locations.
http://www.tek.com
In North America:
1-800-TEK-WIDE (1-800-835-9433)
An operator will direct your call.
P.O. Box 1000
Wilsonville, OR 97070-1000
xii
TLA QuickStart Technical Reference Manual
Getting Started
Product Description
This document provides technical reference information for the TLA 7QS
training board. The manual provides information for running the embedded
programs, downloading user-defined programs from a host, specifications,
schematics, parts lists, and miscellaneous service information.
The TLA 7QS training board is used to demonstrate the Tektronix logic analyzer
products. It consists of an electronic circuit board with rubber feet standoff and a
digital display. The circuit board has a built-in M68340 microcontroller with
supporting electronic circuitry, and several connectors.
The training board has several embedded programs accessible by the user
interface or by a remote host connection. The embedded programs are designed
to send digital and analog signals to the various connectors on the training board.
These signals can be used to demonstrate the capabilities of the TLA 700 Series
Logic Analyzers.
The training board is used with the TLA 7QS Training Manual. The training
manual provides examples of using the training board to demonstrate the
capabilities of the TLA 700 Series Logic Analyzers.
Accessories
The training board is available with the following standard accessories:
TLA 7QS Training Manual
TLA 7QS Software
Wall mount power adapter (power dependent on country)
The TLA 7QS Technical Reference Manual is available as an optional accessory
and comes with the TLA 7QS. development software.
Configuration
The default training board has no configurations. The training board can be set
up, however, to download user specific programs. The programs reside in the
flash memory.
TLA QuickStart Technical Reference Manual
1–1
Getting Started
Functional Check
The basic operation of the TLA 7QS training board is verified by the power-up
diagnostics. The power-up diagnostics run at power-on or when the RESET
signal is asserted by pressing the RESET button.
To perform a more detailed functional verification of the training board, refer to
the Functional Verification Procedures beginning on page 5–1.
1–2
TLA QuickStart Technical Reference Manual
Hardware Features
This section describes the hardware features of the TLA 7QS training board. It
provides information on using the hardware to demonstrate features of logic
analyzers and oscilloscopes. Detailed information on individual circuits is
provided in the Theory of Operation beginning on page 4–1.
Circuit Board Modules
The training board can be divided into the following circuit board modules:
The microprocessor module consists of a Motorola M68340 microcontroller in a
TQFP package and the associated static RAM and flash memory. The flash
memory is divided into a user flash and system flash. The user flash area is
intended for use with additional applications; it can be modified with the proper
software development tools. The system Flash is initially programmed at the
factory and can be updated by field service upgrade kits (when they become
necessary).
Microprocessor Chip Selects. Four programmable chip select lines are used on
the training board. Table 2–1 lists the chip select lines and how they are used.
For information on the memory mapping, refer to Memory Maps beginning on
page 2–22.
T able 2–1: Microprocessor chip select lines
Chip
select
CS0*Boot and system Flash ROM
CS1*User and system RAM
CS2*User and application ROM
CS3*Memory mapped input and output
Memory space usage
TLA QuickStart Technical Reference Manual
2–1
Hardware Features
Microprocessor Interrupts. Four external interrupts are used on the training board:
IRQ3*, IRQ5*, IRQ6*, and IRQ7*. You can assert the signals through the push
buttons on the training board or through the parallel control port.
Microprocessor Parallel Input/Output Port. The microprocessor has a general
purpose parallel input/output port (PORTA) that uses the upper eight address
lines. The port is used for general purpose (application defined) input and output
bits, serial clock bits, and serial data bits. Table 2–2 shows the bits of the port
and the corresponding signals. The PORTA signals are accessible on bus
interface connector (J180).
T able 2–2: PORTA signals
BitSignal nameFunction
0SCLSerial clock bit
1SDASerial data bit
2CNTLIN1Application defined input control bit
3CNTLIN2Application defined input control bit
4CNTLIN3Application defined input control bit
5CNTLOUT1Application defined output control bit
6CNTLOUT2Application defined output control bit
7CNTLOUT3Application defined output control bit
Microprocessor Output Bits. The microprocessor has an output port that shares
the signal lines with the signal lines of the dedicated serial ports (A and B). Two
of the bits have specific uses. The OP4 bit generates the clears the external
trigger input. The OP6 bit generates the trigger output signal (EXTRIGOUT).
Both signals are active low signals.
Delay Line Memory. The delay line memory is a 16-bit read and write register to
demonstrate setup and hold timing violations during read operations. Data can be
written and then read from the same memory location; the data read should equal
the written data. When you program the delay line with a small delay, a setup
violation occurs during the read operation and the data read back will be different
than the written data. When you program the delay line with a large delay, a hold
violation occurs during the read operation and the returned data will be different
than the written data.
2–2
TLA QuickStart Technical Reference Manual
Clockout
Dlyclksel0
Dlyclksel1
Data<0..15>
Delayed
read strobe
gen logic
Figure 2–1 shows a block diagram of the programmable delayed read memory.
Programmable Delay Clock Select. The programmable delay clock select consists
of a serial shift register clocked by the microprocessor system clock. The input to
the shift register is the delayed shift register read strobe which is delayed in
multiples of the clock period. The input read strobe and three output bits of the
shift register are routed to a four-bit input multiplexer. The multiplexer selects
one of the four read strobes.
Programmable Delay Line. The programmable setup and hold delay line is an
eight-bit register with 256 programmable delay settings. The delay line delays
the read strobe to the delay line memory to demonstrate setup and hold timing
violations. Each delay count increment is a 0.5 ns time delay. The minimum
delay is 00 and the maximum is FF.
OE
CLK
Data<0..7>
TLA QuickStart Technical Reference Manual
2–3
Hardware Features
Signal Sources Module
The signal sources module consists of the following groups of signals that can be
used to demonstrate logic analyzer and oscilloscope features:
Counter and pattern generator signals
Setup & Hold and trigger signals
Tapped delay line
Burst signal
Glitch signal
Metastable data and clock signals
Step signal
Runt pulse and missing pulse signal
Single-shot and narrow pulse signal
Staircase signal
Counter and Pattern Generator Signals. You can use the two 16-bit (or one 32-bit)
counter and pattern generators to demonstrate multiple logic analyzer and logic
scope capabilities. Both counter and pattern generators can be configured by
software. The counters can be programmed to count up or down. They can be
clocked by the 50 MHz oscillator or through an external trigger input.
Setup and Hold Trigger Signals. Use the setup and hold trigger signals to
demonstrate how logic analyzers can measure or trigger on setup and hold
signals. The setup and hold signals are generated by a four-bit counter. The
counter can be controlled by software to demonstrate setup violations or hold
violations.
T apped Delay Line. Use the tapped delay line as basic pattern generator to show
signal skew, timing resolution, and sampling rates.
Burst Signal. Use the burst signal to demonstrate logic analyzer transitional
timing.
Glitch Signal. Use the glitch signal to demonstrate logic analyzer and oscilloscope
triggering.
Metastable Data and Clock Signals. Use the metastable data and clock signals to
demonstrate logic analyzer and oscilloscope setup and hold triggering.
2–4
TLA QuickStart Technical Reference Manual
Hardware Features
Step Signal. Use the step signal to demonstrate analog bandwidth and triggering
of oscilloscopes and logic analyzers.
Runt Pulse and Missing Pulse Signal. Use the runt pulse and missing pulse signal
to demonstrate oscilloscope pulse triggering features. You can also use it to
demonstrate logic analyzer 4 ns counter/timers and time-qualified triggers.
Single-Shot Narrow Pulse Signal. Use the single-shot narrow pulse signal to
demonstrate analog bandwidths of oscilloscopes and logic analyzers. You can
also use this signal to demonstrate real-time sampling capabilities of the
oscilloscopes and logic analyzers.
Staircase Signal. Use the staircase signal to demonstrate the oscilloscope
acquisition modes and glitch detection.
User Interface Module
The user interface module consists of the following elements:
A two-line by 16-character LCD display
Four push-button switches
A reset switch
Two 10-segment LED indicators
LCD Display . The main display device is a two line by 16 character LCD display.
The readout is controlled by software and by the four push-button switches.
The microprocessor communicates with the display by placing the upper eight
bits on the data bus. The LCD display has a register select (RS) bit. When the
RS bit is low, it selects the instruction register; when the bit is high, it selects the
data register.
Push-button Switches. The four push-button switches connect to the four external
interrupt lines of the microcontroller. The switches select and control the
programs in the training board. The LCD readout displays the push-button
switch functions. The right-most switch halts the program and asserts a
nonmaskable interrupt (NMI) signal to IRQ7.
Reset Switch. The Reset switch is a momentary push-button switch that provides
a system reset to the microcontroller.
TLA QuickStart Technical Reference Manual
2–5
Hardware Features
LED Indicators. Two 10-segment LED indicators display bit patterns for various
software and hardware demonstrations. The first sixteen LED segments (labeled
0 through 15) represent data bits. Bits 16 and 17 represent the LAPort input and
output enable status. Bit 18 indicates whether the external trigger input is
enabled. Bit 19 shows the status of the Halt signal line.
Input and Output Connectors
The TLA 7QS Training Board has the following input and output port connectors:
Two serial ports
A logic analyzer control port
Two trigger BNC connectors
A background debug mode connector
A JTAG connector (pins not installed on board)
Power input connectors
Bus interface connector
These connectors and their pin information are described in the Theory of
Operation chapter beginning on page 4–9.
Serial Port Requirements
Serial Port B is the main serial port for connecting the training board to an
external host. It is also used to monitor programs and to download and execute
firmware. The serial port uses hardware handshaking to control communications
between the host and the training board.
In addition to the minimum RS-232 signals (RX, TX, and GND) for serial
communications, the handshaking signals (CTS and RTS) are required for
connection between a terminal (or computer) and the training board.
Serial Port B on the training board is designed as a DTE (data terminal equipment) device. Most terminals and personal computers with serial ports are also
configured as DTE devices. Therefore, the signal connections between the
terminal and Serial Port B on the training board may require an null modem
connection.
2–6
The left side of Figure 2–2 shows the standard full null modem connection. The
minimum null modem connection required for the training board is shown on the
right side of Figure 2–2.
TLA QuickStart Technical Reference Manual
Hardware Features
DTR
DSR
RTS
CTS
DCD
TXD
RXD
GND
Standard null modem connectionMinimum null modem connection
DTR
DSR
RTS
CTS
DCD
TXD
RXD
GND
DTR
DSR
RTS
CTS
DCD
TXD
RXD
GND
required for the training board
Figure 2–2: Null modem connections
Table 2–3 shows the connector pinouts for the DB9 and DB25 serial port
connectors.
T able 2–3: RS-232 connector pinouts
SignalNameDB9 pinsDB25 pins
DCDData carrier detect18
RXDReceive data23
DTR
DSR
RTS
CTS
DCD
TXD
RXD
GND
TXDTransmit data32
DTRData terminal ready420
GNDSignal ground57
DSRData set ready66
RTSRequest to send74
CTSClear to send85
RIRing indicator922
For more information on the serial ports on the training board refer to the Serial
Ports on page 4–11.
TLA QuickStart Technical Reference Manual
2–7
Software Features
This section describes software operation, embedded programs, and diagnostics
available with the TLA 7QS Training Board.
When you first apply power to the the training board, or when you press the
Reset button, the training board initializes the 68340 registers, runs the power-on
diagnostics, and then starts the normal operation.
Operating Modes
There are three modes of normal operation for the training board:
The software routines are available in both stand-alone operation and host
controlled mode (unless specified otherwise).
Stand-Alone Mode
Host-Controlled Mode
In the stand-alone mode, operation of the training board is controlled by the
button interface. All program information is sent to the liquid crystal display
(LCD). Menu selections are displayed on the LCD as well as the current function
of the four buttons mounted directly below the display.
You can scroll through the menu selection by pressing the UP or DN (down)
buttons. Pressing the RUN button starts the selected software routine. Pressing
the STOP button halts the selected routine. The display on the LCD may change
depending on the selected software routine. Refer to LCD User Interface on page
2–15 for more detailed information on controlling the training board in the
stand-alone mode.
In the host-controlled mode, the operation of the training board is controlled
through Serial Port B. You can connect the training board to a host (such as a PC
running an RS-232 application such as HyperTerminal). The menu selections are
the same as in the stand-alone mode; however, because of the larger display,
more verbose descriptions are possible.
TLA QuickStart Technical Reference Manual
2–9
Software Features
NOTE. You may need to use a null modem to connect the training board to your
PC. For information on using a null modem, refer to Serial Port Requirements
on page 2–6.
Additional menu choices are available that are not used in the stand-alone mode.
These choices include downloading an S-record file to user flash memory and
starting the SDS (Software Development Systems) target monitor program. A
list of embedded programs and routines is described in detail under EmbeddedPrograms beginning on page 2–10.
While the training board is connected to host, the training board operation can
still be controlled from the buttons and data will be displayed on the LCD as
well as on the remote menu.
Debug Mode
Main Software Routine
Embedded Programs
The debug mode is intended to be used during program development. While in
the debug mode, the training board runs a target monitor (a ROM resident
program) that communicates with the SDS SingleStep development software.
The debug mode lets you develop, download, and test programs before you
commit them to flash memory. The debug mode also provides direct access to
the hardware on the training board.
The main software routine is a message processor that runs in an endless loop.
User and instrument actions, such as pressing a button, generate messages which
are posted to a message stack. The routine continuously checks the stack for
messages and sends new messages to the appropriate action routine.
Most messages are generated by an interrupt service routine. The buttons,
timers, and RS-232 circuitry have individual interrupt service routines. When an
interrupt is serviced, the interrupt service routine posts the appropriate message
to the message stack and then returns control to the processor.
2–10
This section describes the embedded programs that are available with the current
version of the training board. The programs, routines, or tests described in this
subsection are available at product introduction. Others can be added by the user
as necessary.
The programs use several subroutines to provide logic analyzers a means of
demonstrating performance analysis. All initialized variables are mapped into
SRAM so values can be changed. The variables return to the default values at
power-on or when the training board is reset.
TLA QuickStart Technical Reference Manual
Software Features
LITES
STOP LITES
STRINGS
COUNTER
The Lites program strobes the LED segments from right to left and then left to
right. The program also writes the phrase “Making It Happen” to Serial Port B.
The Stop Lites program lights specific LEDs in a predetermined sequence. The
LEDs are lighted in a sequence to emulate two traffic lights (hence the name
Stop Lites). One set of lights change from green to amber to red. After the light
is red, a second set of lights cycles from green to amber to red. The sequence
continues until interrupted by the user.
The Strings program continuously sends the string “The quick brown fox jumped
over the lazy dog” to Serial Port B.
The Counter program controls the counter-pattern generator circuitry on the
training board (J840, J940, J830, and J930). Push the RUN button to start the
program and to display the current settings. To change any of the settings, push
the F1, F2, or F3 buttons. You can change the program settings by pushing the
appropriate buttons as described below:
Push the F1 button to select the counter size, 16 bits or 32 bits.
Push the F2 button to select the counter direction, up or down.
PATTERN GEN
SHOW CYCLES
Push the F3 button to select the counter clock source, internal or external.
Push the F4 button to accept the changes.
The Pattern Gen program controls the counter-pattern generator circuitry on the
training board (J840, J940, J830, and J930). Push the RUN button to start the
program and to display the current settings. To change any of the settings, Push
the F1, F2, or F3 buttons. You can change the program settings by pushing the
appropriate buttons as described below:
Push the F1 button to select the data pattern, A5 or F0.
Push the F2 button to select the clock speed, normal, divide-by-four,
divide-by-sixteen, or SIM timer module 2.
Push the F4 button to accept the changes.
The Show Cycle program routes the M68340 internal bus cycles to the external
bus. The logic analyzer can be set up to capture and analyze these bus cycles.
TLA QuickStart Technical Reference Manual
2–11
Software Features
WAIT STATE
INT LATENCY
PGM DELAY
The Wait State program varies the M68340 wait states from zero to three on CS2
and CS3. After starting the program, push the F1 button to select the number of
wait states. You can then use a logic analyzer to capture and analyze the impact
of the wait states on system performance.
The INT Latency program generates an interrupt at random intervals of time.
This program provides a means for logic analyzers to measure the time between
an INT assertion and an INT acknowledge. The LEDs strobe across the LED
display while the program runs.
The PGM Delay program controls the Setup and Hold circuitry on the training
board (J850). You can use the buttons to select the clock speed and to specify a
delay from 00 Hex to FF Hex.
When the program runs, it sends a value of 5555 Hex to a register and is then
read back. The read select line is delayed by the programmed amount. The
resulting value is displayed by the LED bank. If the displayed value is not
5555 Hex, then you know that an error occurred.
Push the RUN button to start the program and to display the current settings. To
change any of the settings, push the F1, F2, or F3 buttons. You can change the
program settings by pushing the appropriate buttons as described below:
AUTO DELAY
PULSE
Push the F1 button to select the clock, normal, divide-by-two, divide-by-
four, or divide-by-eight.
Push the F2 button to change the most-significant byte of the delay value.
Push the F3 button to change the least-significant byte of the delay value.
Push the F4 button to accept the changes.
The Auto Delay program is similar to the PGM Delay program except that the
clock and delay times are automatically sequenced through all possible values.
The Pulse program generates a monostable pulse when you press the F1 button.
The pulse is generated by SIM timer module 1. The 1 V pulse is sent to the
PULSE pins (J971-3 and J870-5, 6) in the Analog Signals section of the training
board. A TTL-level pulse is available on the C0-4 section (T1) of the microprocessor signals section on J750-5.
2–12
TLA QuickStart Technical Reference Manual
Software Features
SETUP/HOLD
PGM FLASH
The Setup/Hold program controls the Setup and Hold circuitry on the training
board (J850). The program sends a four bit count pattern to DATA pins 0–3
(J850-1 though J850-4). The same pattern is sent to the QOUT pins 0–3 (J850-5
through J850-8). However, the count data at the QOUT pins is skewed by a
specified amount of time.
Push the RUN button to start the program and to display the current settings. To
change any of the settings, Push the F1, F2, or F3 buttons. You can change the
program settings by pushing the appropriate buttons as described below:
Push the F1 button to select the clock, normal, Setup (CLK 2), or Hold
(CLK 1).
Push the F2 button to enable (YES) or disable (NO) a toggle feature. The
feature toggles the clock between Normal and Hold or between Setup and
Hold when a count of 0A H is reached.
Push the F4 button to accept the changes.
The PGM flash program provides a means for loading user programs into the
User area of the flash ROM. You can also use the program to bulk-erase the user
flash ROM. Any new user programs will be added to the menu display and can
be selected in the same manner as any other program. To use this program, you
must be operating in the host-controlled mode. Instructions for creating a new
user program are described in Creating Programs for the Training Board
beginning on page 2–29.
LAPORT ENABLE
CAUTION. Exiting or interrupting the program prematurely can corrupt the user
flash memory. Do not execute this program if you are not operating in the
host-controlled mode.
If you start the program from the training board, you will be asked to verify your
intentions (select YES to continue, NO to exit the program). You can only exit or
interrupt the program by pushing the Reset button on the training board.
The LAPort Enable program controls the LAPort functions of the training board.
The LAPort is normally enabled during reset or when you apply power to the
training board. This program allows you to enable or disable the port.
Push the RUN button to start the program and to display the current settings. To
change any of the settings, push the F1 button. You can change the program
settings by pushing the appropriate buttons as described below:
Push the F1 button to enable or disable the port.
Push the F2 button to count up to select the port lines.
TLA QuickStart Technical Reference Manual
2–13
Software Features
Push the F3 button to count down to select the port lines.
Push the F4 button to accept the changes.
The three LAPort lines are selected by binary values from the F2 or F3 buttons.
The value written to the output is displayed on the LCD as a binary number. For
example, to set the LAPort output line 1 high and others low, select the binary
value 010.
TRIG ENABLE
DIAGS
MONITOR
The Trig Enable program enables or disables the Trigger In or Trigger Out
features on the training board. When enabled, a Trigger In signal will generate an
IRQ7 interrupt and a Trigger Out signal will generate an IRQ6 interrupt.
When disabled, the Trigger In signal functions as an external clock for the
counters. The Trigger Out circuitry functions normally but does not assert an
IRQ6 interrupt.
Push the RUN button to start the program and to display the current settings.
Push the F2 button to enable or disable the Trigger In and Trigger Out feature.
Push the F1 button to manually generate a Trigger Out pulse; the training board
responds by displaying an asterisk on the LCD.
The Diags program executes the extended diagnostics. For more information on
diagnostics, see Diagnostics on page 2–16.
The Monitor program starts the SDS Target Monitor routine in preparation for
running the SDS SingleStep debugger. This selection is only useful if you have a
copy of the SDS SingleStep program running on a host computer. You will be
prompted to verify your intention to run this program. To exit this program, push
the Reset button.
Interrupt Service Routines
Interrupts 3, 5, 6, and 7 have individual handlers. Each handler posts a global
message that will be read by the main function. Timer 1, Timer 2, and RS-232
can also generate interrupts that will have their own interrupt service routines.
2–14
TLA QuickStart Technical Reference Manual
LCD User Interface
Software Features
The LCD Interface consists of the liquid crystal display and four buttons on the
training board. The UP, DN, RUN, and STOP images on the LCD correspond to
the buttons located directly below the display.
UP and DN Buttons
RUN Button
STOP Button
RS-232 Interface
Pushing either button causes interrupts. The interrupts post messages to the main
routine. Push the UP button to scroll backward through a list of programs. Push
the DN button to scroll forward through a list of programs.
Push the RUN button to start a program. While a program runs, the UP, DN, and
RUN images on the display are replaced by the prompt “RUNNING.” Other
buttons are ignored, except when the program prompts you to push a button.
Push the STOP button to halt a program. Pushing the STOP button while no
tests are running has no effect.
The RS-232 interface provides a means of controlling the training board from a
host. The host connects to the training board through RS-232 Serial Port B. The
interface displays a menu (see Figure 2–3) containing all of the tests programmed in the training board.
Figure 2–3: Remote menu
TLA QuickStart Technical Reference Manual
2–15
Software Features
Diagnostics
The interface runs at a baud rate of 9600 with hardware flow control. You should
use a terminal emulation program on a PC such as HyperTerminal.
The ANSI escape codes provide cursor control. Press an arrow key on the
terminal keyboard to move between highlight selections in the menu. If the
terminal does not have any arrow keys, press the J or K keys to change selections.
Press the Enter or Return key to start a program or test. The terminal displays the
following message:
Press any key to stop a test. The terminal returns control to the menu selections.
The diagnostics test the basic operation of the training board. The power-up
diagnostics run when power is applied to the training board or when the RESET
is asserted. Some of the extended diagnostics require human interaction.
LCD Test
Serial Port Tests
To start the extended diagnostics, select DIAGS on the display. Push the run
button to start the extended diagnostics. The diagnostics run automatically and
only require user interaction when connecting the RS-232 cables. The extended
diagnostics test the following areas of the training board:
LCD
Serial ports
ROM
RAM
Upon completing the diagnostics, the test results are temporarily listed on the
display.
The LCD is tested by displaying a pattern that illuminates all bits on the display.
Visually verify that all bits are illuminated.
The serial port test consists of two kinds of tests. The first test is an internal
loopback test. The test places the serial ports into the loopback mode. A
character is transmitted to the port, received, and compared. The test passes
when the received character matches the transmitted character.
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TLA QuickStart Technical Reference Manual
Software Features
The second test requires connecting a terminal to Serial Port A (9-pin subminiture D connector). The test pauses until you connect the cable and then push the
Run button to continue. The test string, “Testing serial port A,” is transmitted
through the port. The test passes when when you see the test string is on the
terminal screen.
The test is repeated for Serial Port B using a two by five shrouded square-pin
connector (see Table 4–8 on page 4–11 for pinout information).
ROM Test
RAM Test
The ROM test checks the read-only memory. The ROM is checked by reading a
specific location for a confidence word. If the returned value matches the
confidence word, the ROM is assumed to be good. A Pass/Fail condition is
displayed on the LCD at the completion of the tests.
The RAM is tested by writing a value and then reading the value. If the returned
value matches the written value, the test passes. A Pass/Fail condition is
displayed on the LCD at the completion of the tests.
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Memory Maps
This section provides information on the memory maps for the TLA 7QS
Training board. The first part of this section provides information on the memory
mapped input and output. The rest of this section lists the actual memory maps.
Memory Mapped Input and Output
The training board has 2 Mbytes of memory mapped input and output. The
memory is divided into eight equal segments. Table 2–4 lists the names and
addresses of the memory mapped input and output devices.
T able 2–4: Input and output device addresses
DeviceAddressInput/output typeMemory depth and width
LCD display$40 0000Read/write1 X 8
LED display$44 0000Write only1 X 16
Input control bits$48 0000Read only1 X 8
Output control bits$4C 0000Write only1 X 16
Setup and hold delay line$50 0000Write only1 X 8
Setup and hold memory$54 0000Read/write1 X 16
Low counter /pattern generator$58 0000Write only1 X 16
High counter/pattern generator$5C 0000Write only1 X 16
LCD Display
LED Displays
TLA QuickStart Technical Reference Manual
The liquid crystal display has two eight-bit registers selected by the register
select (RS) bit. When the RS bit is low, it selects the instruction register, when it
is high it selects the data register.
The training board has two 10-segment LED displays. The segments are used as
follows:
The first 16 segments connect directly to the 16-bit data lines and are used
for general purpose applications. Bit 0 is the right-most segment on DS880.
Bit 16 represents the LAPort input enable status. The input circuit uses a
flip-flop to clock in data by an external computer. The enable control bit
connects to the output enable of the flip-flop. When the LED is on (low
signal) the input is enabled and input signals are connected to the training
board.
2–19
Memory Maps
Bit 17 represents the LAPort output enable status. The output circuit uses a
transparent latch. When the LED is on (low signal), the output is enabled and
signal changes on the training board are sent to the output port. When the
LED is off, the output data is latched to last transmitted value (unknown at
power-on). The bit is inverted for proper polarity to the latch.
Bit 18 represents the external trigger input and output interrupt enable status.
When the LED is on, an external input or output trigger causes interrupts
IRQ7 and IRQ6 respectively.
The last bit represents the status of the Halt* signal. When the LED is on,
the Halt* line is asserted.
Input Control Bits
Register
The input control bits register is a general purpose register that monitors signals.
Table 2–5 lists the input control bits and the associated signals. The signals are
intended for diagnostic read-back purposes. See Figure 2–7 on 2–26 page for
memory mapping information.
T able 2–5: Input control bits
BitSignal nameFunction
0LAPORTIN*Control bit readback
1LAPORTOUT*Control bit readback
2TRIGGERINControl bit readback
3CNTRDIAGControl bit readback from Mux
4SIGCLK1Microprocessor timer 1 readback
5SIGCLK2Microprocessor timer 1 readback
6SCLSerial clock (PortA bit 0) readback
7SDASerial clock (PortA bit 1) readback
2–20
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Memory Maps
Output Control Bits
Register
The output control bits register is a 16-bit input register used to assert signals.
Table 2–6 lists the output control bits and the associated signals. See Figure 2–7
on 2–26 page for memory mapping information.
The programmable setup and hold delay line is an eight-bit register with 256
programmable delay settings. The delay line delays the read strobe to the delay
line memory to demonstrate setup and hold timing violations. Each delay count
increment is a 0.5 ns time delay. The minimum delay is 00 and the maximum
is FF.
The delay line memory is a 16-bit read and write register to demonstrate setup
and hold timing violations during read operations. Data can be written and then
read from the same memory location; the data read should equal the written data.
When you program the delay line with a small delay, a setup violation occurs
during the read operation and the data read back will be different than the written
data. When you program the delay line with a large delay, a hold violation occurs
during the read operation and the data will be different than the written data.
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2–21
Memory Maps
Low Counter Pattern
Generator Data
High Counter Pattern
Generator Data
Memory Maps
The low counter pattern generator data register is a 16-bit write-only register that
stores a data value in the low counter pattern generator.
The high counter pattern generator data register is a 16-bit write-only register
that stores a data value in the high counter pattern generator.
Figures 2–4 through 2–8 show the following memory maps for the TLA 7QS
Training board:
A full memory map
System and user static RAM
User EEPROM and flash
Input and output
System EEPROM and flash
2–22
TLA QuickStart Technical Reference Manual
Memory Maps
CS1
CS2
CS3
CS0
2 MB
User/System
SRAM
Space
2 MB
User
EEPROM/Flash
Space
2 MB
Input/Output
Space
2 MB
System
EEPROM/Flash
Space
8 MB
UNUSED
4 GB
Available on
Extender Bus
00 0000
$20 0000
$40 0000
$60 0000
$80 0000
$FF FFFF
$FFFF FFFF
On Board Memory Space
16 MB Address Space
24 Address Lines (A0—A23)
Extended Memory Space
4 GB Address Space
Available on Extender Bus using the upper
eight Address Lines (A24—A31)
Figure 2–4: Full Memory Map
TLA QuickStart Technical Reference Manual
2–23
Memory Maps
256K
256K
512K
512K
512K
128 K X 16 K
SRAM
128 K X 16 K
SRAM
Unused
Unused
Unused
$00 0000
$04 0000
$08 0000
$10 0000
$18 0000
1K
15K
16K
32K
196K
496K
Exception
Vectors
Monitor
Supervisor
Space
Supervisor
Stack Pointer
Space
User
Stack Pointer
Space
User
Program
Space
User
Program
Space
$00 0000
$00 03FF
$00 3FFF
$00 7FFF
$01 0000
$04 0000
$07 FFFF
$1F FFFF
Figure 2–5: System and user static RAM
2–24
TLA QuickStart Technical Reference Manual
$20 0000
Memory Maps
512K
512K
512K
512K
256K X 16
EEPROM/Flash
$28 0000
Unused
$30 0000
Unused
$38 0000
Unused
$3F FFFF
Figure 2–6: User EEPROM and Flash
TLA QuickStart Technical Reference Manual
2–25
Memory Maps
256K
256K
Input Control Bits
256K
Output Control Bits
256K
Programmable
256K
Delay Line Memory
256K
Pattern Generator
256K
Pattern Generator
256K
LCD Display
Output
Read/Write
LED Display
Output
Write Only
Read Only
Write Only
Delay Line
Write Only
Read/Write
Data
Write Only
Control
Write Only
$40 0000
$44 0000
$48 0000
$4C 0000
$50 0000
$54 0000
$58 0000
$5C 0000
$5F FFFF
Figure 2–7: Input and output
2–26
TLA QuickStart Technical Reference Manual
$60 0000
Memory Maps
512K
512K
512K
512K
256K X 16
EEPROM/Flash
$68 0000
Unused
$70 0000
Unused
$78 0000
Unused
$7F FFFF
Figure 2–8: System EEPROM and Flash
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2–27
Creating Programs for the Training Board
This section provides information on creating programs for use with the training
board. Information is provided under the following subsections:
Preparation
Writing the program
Compiling and linking code
Writing an image to the flash memory
Rebooting and running the program
Preparation
To create programs for the training board you will need the SDS CrossCode
C 68K software package from Software Development Systems (the C++ option
is not required) and some software tools from Tektronix. You will use these
packages to write the code and to download the programs to the training board.
Software Development
Systems Tools
Tektronix Software Tools
The SDS CrossCode C/C++ 68K package includes the C compiler, assembler,
linker, and other utilities necessary to convert your source code into 68K code.
Although not required, the SDS SingleStep debugger package may also prove to
be helpful.
The software packages come in several versions which vary mainly in the
connections to the target. The OnChip debugger connects to the background
Debug Mode (BDM) port on the training board through a cable adapter from the
PC printer port. The Target Monitor version connects through a standard serial
COM port to the SDS monitor program which is resident on the training board.
The Target Monitor version is easier to connect, but it is also slower than the
BDM version. The BDM version was used to develop the training board.
In addition to the software packages from Software Development Systems, you
will also need the object file (mongoose.obj) and the linker specification file
(combine.spc). If you intend to reuse some of the code already present on the
training board (such as the code to display strings on the LCD), you will also
need the include files for the training board.
Appendix A: Source Code contains examples of the combine.spc file and a list of
the Tektronix supplied software available with this technical reference manual.
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2–29
Creating Programs for the Training Board
Writing the Program
The following procedures provide information on writing the program code for
the training board. You may want to refer to Appendix A: Source Code for a
sample program. The procedures consist of the following steps:
Create the menu entry
Include the user header file
Create a dummy function
Write the code
Create the Menu Entry
Include the User Header
File
The menu for the training board is a linked list structure. The menu structure is
defined in the include file, menu.h. The file is type defined as MENU. You need
to define the following information in the structure:
The menu text to be displayed
The row location of the remote menu text
The column location of the remoter menu text
A pointer to the function to be executed
The following example shows how a sample menu entry with all of the
definitions provided.
MENU myItem = {
My Text",/*text that will be displayed on the menu */
3,/*row location of the remote menu item */
35,/*column location of the remote menu item */
mytestfunction /*pointer to the function to be executed */
};
You must include the user header file, user.h. This file declares a constant that is
located in a specific place in the user memory on the training board. The constant
is checked every time the training board is reset. If the header file finds the
constant, the software will look for menu entries to be added to the menu list.
Create a Dummy Function
2–30
You must include a dummy function to create the proper code and C frame. Do
not include any code in the function, the function must remain empty. The
dummy function is required to allow your code to be appended to the software
on the training board.
TLA QuickStart Technical Reference Manual
Creating Programs for the Training Board
Write the Code
Write your code using normal C or assembly language. You can use any of the
functions for the training board, or create your own functions. Refer to Appen-dix A: Source Code for a sample program. You may also want to refer to the code
supplied on the floppy disk accompanying this manual.
Compiling and Linking Code
The following procedure shows how to compile and link the code using the
CrossCode 68K application.
Compile the Code
Link the Code
Compile the code using commands and flags as shown below:
Although you may want to use other combinations of compiler flags, not all
combinations have been tested. However, the flags used in the above example
should work for your application.
After compiling the code, you must link the code. To link the code into an object
file, you will need the following items:
An object file (the output file from the compile operation)
The firmware object file (mongoose.obj)
A linker specification file (combine.spc)
The firmware object file is necessary because a successful link requires the
symbol table from the TLA 7QS software that is programmed in the system flash
ROM. For the symbol table to be valid, the firmware object file must be the
same revision as the firmware on the training board.
The linker specification file tells the linker file where to locate some specific
regions, such as your code, data, and constants. For more information about the
linker, regions, and partitions, refer to the SDS documentation on the linker
program.
Refer to Appendix A: Source Code for examples of the C program that will add a
menu item to the main menu on the training board. The program will display the
string “Time to Switch” on the display. The appendix also includes the linker
specification file and a batch file to compile, link, and convert the output to a
Motorola S-record file.
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2–31
Creating Programs for the Training Board
Writing an Image to the Flash Memory
Prepare to download the code into flash memory on the training board using a
downloader utility. The downloader utility will extract code bytes and convert
them into a Motorola S-record file. Make sure that you use the proper flags to
avoid ending up with an extremely large file.
Connect the training board to a PC running a terminal program such as HyperTerminal. Open up a session with the baud rate set to 9600 and with hardware
control flow. If you are unsure of the HyperTerminal settings, check the
configuration settings on the Property sheet under the File menu.
Complete the following steps to load the program in the flash memory:
1. Power on the training board and select PGM FLASH.
2. Start the PGM FLASH program and select YES when you are asked to
confirm your actions.
3. Select PGM from the menu to prepare to download the program.
Running the Program
4. When you see the prompt “Start file transfer now,” start the file transfer by
selecting Send Text File from the Transfer menu.
5. Enter the file name of the file created by the downloader program.
6. When the file transfer is complete, you will see the message “Verification is
Complete.”
After you have written the program to the flash memory, you must reset the
training board to activate the new menu. The new menu items should be
displayed after the SDS Monitor menu entry. You can now select and run the
new program using the buttons on the training board or by the cursor movement
keys on the remote menu.
2–32
TLA QuickStart Technical Reference Manual
Specifications
This chapter contains the specifications for the TLA 7QS Training Board. Within
each section, the specifications are arranged in functional groups such as:
Microprocessor System Characteristics, Signal Source Characteristics,
Hardware Characteristics, Power distribution, Mechanical Characteristics, and
Environmental Characteristics.
All specifications are warranted unless they are designated typical. Typical
characteristics describe typical or average performance and provide useful
reference information.
T able 3–1: Microprocessor signal characteristics
CharacteristicDescription
Microprocessor
Microprocessor componentMotorola M68340
Microprocessor clock rate16 MHz
System integration moduleProvides the external bus interface for the CPU32 and the DMA. Provides program-
mable circuits to perform address decoding and chip selects, wait-state insertion,
interrupt handling, clock generation, bus arbitration, watchdog timing, discrete I/O and
power-on reset timing.
DMA controller moduleThe DMA module consists of two independent programmable channels. Each channel
has separate request, acknowledge, and done signals. Each channel can operate in a
single-address or in a dual-address mode.
Serial moduleThe serial module contains a two-channel USART, an on-chip baud rate generator,
and is functionally equivalent to the MC68681/MC2681 DUART.
Timer moduleThe timer module consists of two general purpose counter/timers. Each timer consists
of a 16-bit countdown counter with an 8-bit countdown prescaler.
Parallel input/outputThe parallel port is part of the integrated external bus interface. It can function as a
bidirectional parallel port or as address lines A24 through A31.
Background debug mode
DescriptionThe background debug mode (BDM) is a special operating mode available in the
CPU32 where normal instruction execution is suspended while special on-chip
microcode performs the functions of a debugger.
InterfaceThe interface connector is a two-by-five shrouded square-pin header. Signals are
assigned to the pins using the standard Motorola and P&E Engineering format.
System memory
SRAM memory128 K by 16 (512 K total)
Flash ROM memorytwo banks of 128 K by 16 (256 K total)
Serial EEPROM NVRAMSerial 2 K by 8
TLA QuickStart Technical Reference Manual
3–1
Specifications
T able 3–1: Microprocessor signal characteristics (Cont.)
CharacteristicDescription
System reset signalThe reset signal is integrated into the M68340 microprocessor and connected to the
external button to reset the system.
External interrupt requestsIRQ3, IRQ4, IRQ6, IRQ7
Memory-mapped functions
Chip select decoderOne of eight chip select decoders to select memory-mapped functions
Input control bits registerAn eight-bit register to read input bits for monitoring system status and diagnostic
feedback
Output control bits registerA 16-bit register to write output bits to control circuit functions and to the LAPort output
control bits
Liquid crystal displayA two line by 16 character LCD readout used for system status and for application
program status
Ten-segment bar LED displayTwo 10-segment multicolor LED bar displays. LEDs labeled 0 through 15 represent
data bits and are used for application program output indicators. Three bits monitor
system status. The last bit indicates the status of the microprocessor HALT* line.
Memory read violation module
Memory read violation data registerOne 16-bit register
Read strobe coarse delay (typical)A four–to–one mulitplexer used to select one of four read strobes that are delayed by
clocked processor cycles
Read strobe fine delay (typical)256 steps from 10 ns to 137.5 ns
Delay line resolution (typical)0.5 ns
Logic analyzer probe connections
LASI-3 format processor probe
connections
LASI-4 format processor probe
connections
96 channels and six clocks with LASI-3 signal format
96 channels and six clocks with LASI-4 signal format
3–2
TLA QuickStart Technical Reference Manual
T able 3–2: Signal source characteristics
CharacteristicDescription
Counter/Pattern generator signals
Number of counter bitsOne 32-bit counter or two 16-bit counters
Counter clock frequency (typical)50 MHz
Number of pattern generator bits32
Pattern generator toggle bitsEight four-bit patterns
Pattern generator toggle frequency
(typical)
Counter/Pattern generator output
amplitude (typical)
Setup and hold counter signals
Counter data bits4
Latched data bits4
Normal setup and hold time (typical)> –2 ns setup time
Violation setup time (typical)< –2 ns setup time
Violation hold time (typical)> 2 ns hold time
Violation rate (typical)625 KHz
Clock frequency (typical)10 MHz
Signal amplitude (typical)3.1 V to 5.1 V maximum
Tapped Delay Signals
Output bits8
Delay time (typical)4 ns
Output amplitude (typical)3.1 V to 5.1 V maximum
Counter clock frequency (typical)10 MHz
Fast edge signal
Amplitude (typical)0.5 V high, 0 V low
Rise time (typical)< 2.0 ns
Frequency (typical)1.5 KHz to 3.5 KHz
Narrow pulse signal
Amplitude (typical)0.5 V to 1.0 V maximum
Pulse-width (typical)1.0 ns to 4.0 ns
Runt pulse and missing pulse signal
Normal pulse amplitude (typical)3.5 V to 5.5 V
Normal pulse frequency (typical)8 MHz to 12 MHz
Runt pulse amplitude (typical)2.0 V to 3.0 V
50 MHz, 10 MHz, 1.25 MHz, and programmable
3.5 V to 5.1 V maximum
0 V to 0.2 V minimum
0 V to 0.2 V minimum
0 V to 0.2 V minimum
Specifications
TLA QuickStart Technical Reference Manual
3–3
Specifications
T able 3–2: Signal source characteristics (Cont.)
CharacteristicDescription
Runt pulse frequency (typical)1.6 Hz to 2.5 Hz
Missing pulse frequency (typical)1.6 Hz to 2.5 Hz
Staircase signals source
Step intervals (typical)0.5 ms per step
Staircase interval (typical)8.0 ms per staircase
Amplitude (typical)900 mV
Metastable glitch signal
Clock frequency (typical)36 MHz to 44 MHz
Data frequency (typical)8 MHz to 12 MHz
Glitch amplitude (typical)±2 V minimum for largest glitches
Burst pulse signal
Data amplitude (typical)3.5 V to 5.1 V
Low frequency burst pulse modulation
rate (typical)
Mid frequency burst pulse modulation rate
(typical)
High frequency burst pulse modulation
rate (typical)
Signal sources probe connections
Counter and pattern generator
connections
Setup and hold counter connections2 by 8 square pin header and oscilloscope probe header
Digital signal connections2 by 8 square pin header and oscilloscope probe header
Analog signal connections2 by 8 square pin header and oscilloscope probe header
p-p
Single pulse at 763 Hz ± 75 Hz
Four pulses at 3.13 MHz ± 310 KHz
Eight pulses at 50 MHz ± 5 MHz
2 by 16 square pin headers
T able 3–3: Hardware characteristics
CharacteristicDescription
User interface
Halt indicator LEDOne LED connected to the microprocessor halt line. The LED is on when the halt line
is enabled (the microprocessor is in the halted state)
Trigger input enable LEDOne LED connected to the external trigger enable control bit. The LED is on when
external triggers are enabled.
LAPort output enable LEDOne LED connected to the LAPort output control bit. The LED is on when the LAPort
output is enabled.
3–4
TLA QuickStart Technical Reference Manual
T able 3–3: Hardware characteristics (Cont.)
CharacteristicDescription
LAPort input enable LEDOne LED connected to the LAPort input control bit. The LED is on when the LAPort
input is enabled.
Memory mapped LEDs16 memory mapped LEDs
Liquid crystal displayTwo line by 16 character LCD memory mapped display
External interrupt request switchesFour interrupt request signal switches for microprocessor signals IRQ3, IRQ4, IRQ6,
and IRQ7. The switches control the system software.
Reset switchOne microprocessor system reset switch
Power on/off switchApplies power to the circuit board
Power indicator LEDPower-on indicator LED
Signal input and output ports
Main serial port (Port B)One DB-9 connector
Auxiliary serial port (Port A)Two by five square-pin shrouded header
LAPort parallel control portDB-25 connector
Logic analyzer trigger outputBNC connector
Logic analyzer trigger intput
Background debug port connectorT wo by five square-pin shrouded header
JTAG PortOne by six square-pin connector (square pins not installed)
1
The logic analyzer trigger input BNC connector can also be used as the external clock input connector with for clock
frequencies up to 50 MHz.
1
BNC connector
Specifications
T able 3–4: Power distribution characteristics
CharacteristicDescription
Low voltage power supply
Power supply input voltage (typical)+8.0 V to +15.0 V
Power supply input voltage connector2 mm male connector with 3 A 24 V rating
Power supply output voltage (typical)+4.8 V to +5.2 V
Power supply output current (typical)1.0 A maximum
Input power supplies
North American120 VAC, 60 Hz input; +13.5 V, 1.5 A output
European220 VAC, 50 Hz input; +13.5 V, 1.3 A output
United Kingdom240 VAC, 50 Hz input; +12.0 V, 1.5 A output
Japan100 VAC, 50 Hz to 60 Hz input; +12.0 V, 1.5 A output
TLA QuickStart Technical Reference Manual
3–5
Specifications
T able 3–5: Mechanical characteristics
CharacteristicDescription
Construction material
Circuit boardGlass laminate
Physical Dimensions
Height1.0 in (2.54 cm)
Length8.1 in (20.57 cm)
Width5.3 in (13.46 cm)
Package Dimensions
Height3 in (7.62 cm)
Length12.9 in (32.77 cm)
Width11.4 in (28.96 cm)
Shipping weight4.5 lbs (2.03 kg)
3–6
TLA QuickStart Technical Reference Manual
Theory of Operation
This chapter provides the theory of operation of the TLA 7QS training board. It
provides information on the built-in circuit modules and on the connectors on the
training board.
Circuit Board Modules
The following circuit board modules are discussed in this section:
The microprocessor module (schematic sheets 2, 3, 4, 5, 6, 7, and 10) consists of
a Motorola M68340 microcontroller in a TQFP package, the associated static
memory, programmable memory, nonvolatile EEPROM memory, and a
read/write register.
Static Memory. The static memory consists of two banks of 128 K by 16 (memory
implemented) using two 128 K by eight memory components. The standard
training board is loaded with only one bank of static RAM for a total of
256 K bytes.
Programmable Memory. The programmable memory (PROM) is designed to be
either EEPROM or flash memory. The PROM consists of system PROM and
user PROM. Each bank can be implemented with two 128 K by eight parts, two
256 K by eight parts, or two 512 K by eight parts.
The standard training board has both banks or PROM loaded with 128 K flash
memory for a total of 256 Kbytes of system flash and 256 Kbytes of user flash.
The system flash contains the monitor program, board utilities, and a basic set of
application programs.
The system flash is programmed at the factory and can be upgraded through field
service upgrade kits. The user flash is provided for additional applications and is
intended to be modified or added to the product by users with the proper
software development tools.
TLA QuickStart Technical Reference Manual
4–1
Theory of Operation
EEPROM Memory . The EEPROM memory is implemented with a serial 2 K by
eight serial EEPROM. The EEPROM memory is intended to be used by user
applications to store miscellaneous data such as adjustment settings and bit
patterns for the pattern generators. The EEPROM uses the I2C two-wire serial
port for reading and writing data. The two-wire port consists of a clock and a
data line. The clock and data lines are connected to two of the microcontroller
input and output Port A bits. Software routines must be written by the user to
properly read and write serial data from the EEPROM in the correct format.
Read/Write Register . A one by 16 bit read/write register implemented with
D-flip-flops is used to create memory read errors. The read errors can be
demonstrated by writing data to the register and reading the data back. The read
strobe is set to provide timing for a proper read operation or to cause a read error.
The read strobe control consists of a coarse adjustment and a fine adjustment.
The coarse adjustment delays the strobe in increments of processor clock cycles
(62.5 ns) using a clock shift register and a multiplexer to select a specific output.
The fine strobe control adjusts the time delay in 256 increments of 0.5 ns steps
for a total range of 127 ns. The time adjustment is fine enough so that it can be
calibrated to be just on the threshold of creating a read error.
Signal Sources Module
You can use the high resolution (MagniVu) mode of the TLA 700 Series Logic
Analyzers to demonstrate and measure small changes in delay adjustments.
The signal sources module (schematic sheets 21, 22, 23,and 24) consists of
several groups of signals that can be used to demonstrate logic analyzer and
oscilloscope features.
Counter and Pattern Generator Signals. Two 16-bit counter and pattern generators
can be individually programmed to operate as counters, pattern generators, or
combined as a single 32-bit counter. The counters can be programmed to count
up or down. The counter-pattern generator is controlled by the output control bits
port of the microprocessor. Table 4–1 shows the output control bits.
bit 1
10LOCNTREN*Low counter count enable
11LOCNTRSEL*Low counter or pattern select
12LOCNTRUP*Low counter count up/down select
13HICNTREN*High counter count enable
14HICNTRSEL*High counter or pattern select
15HICNTRUP*High counter count up/down select
The output control bits port is a 16-bit input register used to assert signals. The
bit designations and signal names are listed in Table 4–1.
The two 16-bit counter-pattern generators operate the same. They can be
configured individually as counters or pattern generators using the LOCNTRSEL* and HICNTRSEL* bits. The count up and count down bits (LOCNTRUP*
and HICNTRUP*) control the count direction. The counters can be started or
stopped with the count enable control bits LOCNTREN* and HICNTREN*.
When the counter-pattern generators function as pattern generators with the
LOCNTRSEL* and HICNTRSEL* bits, you must select a pattern clock. The
pattern clock toggles the low and high nibble of each patten bytes. The clock
selection uses a four-to-one multiplexer which is controlled using pattern clock
select bits PATCLKSEL0 and PATCLKSEL1. Table 4–2 shows the clock select
truth table. Normal pattern generator operation includes disabling the counting so
that the pattern at the output is the pattern that was loaded.
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Theory of Operation
T able 4–2: Pattern generator clock select truth table
PATCLKSEL0PATCLKSEL1Clock select
00Sigclk2; Microprocessor timer2 used as clock
01TSTHD<3>; Setup and hold counter output
bit 3
10TSTHD<1>; Setup and hold counter output
bit 1
11CNTRCLK; Counter-pattern generator master
clock
The Sigclk2 clock is the microprocessor timer2 output which can be programmed to any frequency and duty cycle. It can also be programmed to stay
high or low, thus selecting the direct or alternate nibble of each byte. With the
Sigclk2 signal set low, the direct nibble is selected; the signal is high, the
alternate nibble is selected as shown in Table 4–3.
T able 4–3: Sigclk2 selections
Bit ValueCounter byte output nibble
0Direct nibble; counter bits 0–3 go to output bits 0–3
1Alternate nibble; counter bits 0–3 go to output bits 4–7
When the counters are used as pattern generators, the patterns can be loaded by
writing the 16-bit counter value to the appropriate address. The individual
counter load strobe is enabled with a write to the high counter-pattern generator
or to the low counter-pattern generator. Table 4–4 shows the counter addresses.
T able 4–4: Counter-pattern generator addresses
Memory mapped
device
Low Cntr/Pat Gen$58 000Write only1 X 16
High Cntr/Pat Gen$5C 000Write only1 X 16
Device
address
Input/output
type
Memory depth
and width
The 50 MHz oscillator is the master clock for the counter-pattern generators. An
external clock can be used to clock the counters. The external signal is a standard
TTL level signal into the Trigger-In BNC connector. The counter clock is
selected with the memory mapped external clock control bit EXTCLKEN (bit 6
of the 16-bit output control register at address 0X4C 0000.
4–4
TLA QuickStart Technical Reference Manual
Theory of Operation
Setup and Hold Trigger Signals. The setup and hold signals (schematic 25) are
generated by a four-bit counter clocked at a 50 MHz rate. The four bits of the
counter connect to four signal ground square pin pairs so they can be measured
by a logic analyzer or by an oscilloscope. The counter output bits are routed to a
latch which is clocked by a modified version of the 50 MHz clock counter clock.
The counter clock is delayed to create a setup violation or a hold violation. The
four output bits of the latch connect to four signal-ground square pin pairs. The
delayed clock signal also connects to a signal-ground square pin pair.
Figure 4–1 shows the block diagram of the setup and hold violation counter. You
may want to refer to this block diagram as you read the following paragraphs.
4–Bit
Counter
Mux
8-Bit
50 MHz
Oscillator
Locntrsel
Patclksel0
Patclksel1
tapped
delay
line
Setup/Hold control
Clock control
Clock control
Mux
Decode
logic
Figure 4–1: Setup and hold violation counter block diagram
4-Bin
Latch
Cntr0
Cntr1
Cntr2
Cntr3
Data0
Data1
Data2
Data3
Clock
The counter clock signal is delayed by an eight-bit tapped delay line. The clock
signal is derived from one of the middle taps so it is delayed approximately 12 ns. The signal is routed through a multiplexer for time delay matching
purposes. All four inputs of the multiplexer have the same clock signal so that
the clock input to the counter always has a steady clock signal.
The delayed counter clock is selected by the setup and hold clock multiplexer
(Mux). Three clock signals go to the four inputs of the Mux. A nominal delay
clock goes to two inputs of the Mux. A setup delay clock with less delay than the
counter clock and a hold delay with more delay than the counter clock are the
other two inputs to the Mux.
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Theory of Operation
The setup and hold violation counter operates in the following manner. The
four-bit counter has a continuous count at 50 MHz. The four output bits and the
clock can be measured. However, the clock is skewed in time at a specific
counter output bit pattern of 1010. The time skew can be in either direction,
positive or negative, compared to the counter clock. The time skew can be
measured and analyzed with a logic analyzer.
The counter output bits and the time-skewed clock are applied to the four-bit
latch. The time skew in the clock creates setup or hold violations when latching
the data. These violations should be apparent when capturing the four output bits
from the latch and measuring data errors at specific counts.
Three bits control the setup and hold violation counter operation (these bits also
control the counter-pattern generators). The two circuits are not intended to be
used at the same time. The LOCNTRSEL* bit selects either a setup clock or a
hold clock (see Table 4–5). The PATCLKSEL0* and PATCLKSEL1* bits
control the circuit operation as shown in Table 4–6.
T able 4–5: LOCNTRSEL bit operation
LOCNTRSEL bitSelection
0Selects the setup clock to cause a violation
1Selects the hold clock to cause a violation
T able 4–6: PATCLKSEL0 and PATCLKSEL1 bit operation
PATCLKSEL0 bitPA TCLKSEL1 bitSelection
00Set to skewed clock (setup or hold) don’t
toggle
01Set to norm clock (setup or hold) don’t toggle
10Set to skewed clock don’t toggle (same as 00)
11Run; toggle between norm and skewed clock
T apped Delay Line. The tapped delay line (schematic 25) is an eight-bit digital
delay with approximately 4 ns of delay between each bit. The on-board 100 MHz
clock the input source for the delay line.
Burst Signal. The burst signal (schematic 29) consists of multiple signals at
different frequencies from two different clock sources. The signals are combined
with combinational logic to create a gated pulse. View the burst signal with an
oscilloscope to see different features of the burst signal at different time base
settings.
4–6
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Theory of Operation
Glitch Signal. The glitch signal (schematic 28) is generated by gating the
microprocessor programmable timers. The timers can be changed in frequency
and duty cycle. The actual glitch signal is generated by delaying one of the timer
signals into an exclusive-or gate with a resistor-capacitor network. The time
difference of the two transitioning signals causes the glitch.
Metastable Data and Clock Signals. The metastable condition is created by
applying a 10 MHz clock into the data input of a latch and clocking the data with
an asynchronous 50 MHz clock (see schematic 26).
Step Signal. The step signal (schematic 28) is generated by rapidly turning off an
RF transistor with a drive transistor. This creates a low-to-high transition at the
collector of the output transistor. A resistor-capacitor-speedup network in the
base circuit of the RF transistor speeds up the switching time and provides a
method for high frequency compensation of the step signal.
Runt Pulse and Missing Pulse Signal. The runt pulse and missing pulse signals
(schematic 26) are created by applying a 2 Hz data clock to a D-flip-flop. The
flip-flop is clocked by a 10 MHz clock. The 2 Hz signal is divided by an
additional flip-flop and the outputs are gated together to create pulses that drive
one transistor that creates the runt pulses and another transistor that creates the
missing pulses.
Single-Shot Narrow Pulse Signal. The single-shot narrow pulse (schematic 28) is
created by applying a step signal to a gated resistor-capacitor network that
differentiates the step to create the pulse. The pulse input steps are generated
either from a 1 Hz continuous clock or from the processor timer number 1
(which is intended to be used for user initiated single-shot pulses).
Staircase Signal. The staircase (schematic 27) is generated by summing the
outputs of a four-bit counter to create the stairs. The stairs are combined with a
50 MHz clock to create noisy glitches.
Clock Signals. The following clock signals are present on the training board:
50 MHz system clock
An asynchronous 2 KHz clocks that is divided down to create lower
The user interface module (schematic sheets 8 and 9) provides a means to control
and observe the actions of the hardware features on the training board.
LCD Display . The main display device is a two by 16 character LCD display. The
readout is controlled by software and by the four push-button switches.
The microprocessor communicates with the display by placing the upper eight
bits on the data bus. The LCD display has a register select (RS) bit. When the
RS bit is low, it selects the instruction register; when the bit is high, it selects the
data register.
Push-button Switches. The four push-button switches connect to the four external
interrupt lines of the microcontroller. The switches select and control the
programs in the training board. The LCD readout displays the push-button
switch functions. The right-most switch halts the program and asserts a
nonmaskable interrupt (NMI) signal to IRQ7.
Reset Switch. The Reset switch is a momentary push-button switch that provides
a system reset to the microcontroller.
LED Indicators. Two 10-segment LED indicators display bit patterns for various
software and hardware demonstrations. The first sixteen LED segments (labeled
0 through 15) represent data bits. Bits 16 and 17 represent the LAPort input and
output enable status. Bit 18 indicates whether the external trigger input is
enabled. Bit 19 shows the status of the Halt signal line.
Power Supply Module
4–8
The power supply module (schematic 12) consists of a power input jack, fuse,
power switch, power LED indicator, and the power supply circuitry. The power
input jack accepts power from the wall mount power adapter. The battery input
pins allow battery operation from a 9 V to 15 V battery.
The power supply is a 1.5 A switching power supply that steps down voltages
between +15 V and +8 V to +5 V.
TLA QuickStart Technical Reference Manual
Input and Output Connectors
The TLA 7QS Training Board has the following input and output port connectors:
Two serial ports
A logic analyzer control port
Two external trigger BNC connectors
A background debug mode connector
A JTAG connector (pins not installed on board)
Power input connectors
Bus interface connector
Probe interfaces
Figure 4–2 shows the location of the connectors on the training board.
Theory of Operation
TLA QuickStart Technical Reference Manual
4–9
Theory of Operation
4–10
Figure 4–2: Input and output connector locations
TLA QuickStart Technical Reference Manual
Theory of Operation
Serial Ports
The main serial port, J500, (schematic 18) is a nine-pin subminiature D-connector that provides an RS-232 serial interface for controlling the computer system
and for reading program data. This serial port uses the integrated serial port B of
the M68340 microprocessor. The connector signals are compatible with a
standard PC serial port; Table 4–7 lists the main serial port signals.
T able 4–7: Serial Port B pinout (J500)
PinSignal
1Protective ground (shield)
2Transmit data (TXD)
3Receive data (RXD)
4–
5Ground
6–
7Clear to send (CTS)
8Ready to send (RTS)
9–
The secondary serial port, J600, (schematic 18) is a two by five shrouded
square-pin connector that provides an RS-232 serial interface for monitoring the
computer system and for software development. This serial port uses the
integrated serial port A of the M68340 microprocessor. The signals are assigned
to pins such that a standard nine-conductor ribbon cable subminiature D-connector can interface the port to a PC. Table 4–8 lists the secondary serial port
signals.
T able 4–8: Serial Port A pinout (J600)
PinSignal
1Protective ground (shield)
2–
3Transmit data (TXD)
4Clear to send (CTS)
5Receive data (RXD)
6Ready to Send (RTS)
7–
8–
9Ground
10–
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Theory of Operation
Logic Analyzer Control
Port
The logic analyzer control port (schematic 19) is a 25-pin subminiature
D-connector and provides parallel input and output control signals for monitoring and controlling the training board hardware and software. The port is
compatible with any version of the standard PC parallel interface port.
There are eight input lines, five output lines, and read and write handshaking
control signals. You can use any PC software capable of reading and writing
bytes to the parallel port with the control port. The electronic circuitry provides a
data register for writing data to the output port and a control/status register for
monitoring the port status.
Table 4–9 lists the control port pins, LAPort signal definitions, the PC parallel
port signal definitions, and the signal names.
T able 4–9: Logic analyzer control port signals (J400)
PinLAPort definitionParallel port definitionSignal name
1Write input strobe
2Data input bit 0Data0Reset*
3Data input bit 1Data1Cntlin1
4Data input bit 3Data2Cntlin2
5Data input bit 3Data3Cntlin3
1
Data input strobe
1
Write control strobe
6Data input bit 4Data4IRQ3*
7Data input bit 5Data5IRQ5
8Data input bit 6Data6IRQ6*
9Data input bit 7Data7IRQ7*
10Data output bit 0Ack* (status output bit 6)Power-on monitor
11Data output bit 1Busy (status output bit 7)Halt*
12Data output bit 2Error (status output bit 5)Cntlout1
13Data output bit 3Select (status output bit 4)Cntlout2
14No connectionAutofd* (Cntl input bit 1)–
15Data output bit 4Fault* (status output bit 3)Cntlout3
16No connectionInit* (Cntl input bit 2)–
17Read input strobe
18 –25GroundGroundGround
1
Active low signal
1
Select (Cntl input bit 3)Read control strobe
4–12
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Theory of Operation
External Trigger BNC
Connectors
Background Debug Mode
Connector
Two external trigger BNC connectors (schematic 20) provide input and output
trigger connections.
External Trigger Input Signal Connector (J700). This connector is an input for
TTL-level signals. The signal connects to the microprocessor interrupt request
level 5 input line and is gate-enabled through software control. This connector is
also used as the external clock input to the training board. You can use an
external clock frequency up to 50 Mhz.
External Trigger Output Signal Connector (J800). This connector is an output for
TTL-level signals. The signal connects to the microprocessor interrupt request
level 3 input line and is gate-enabled through software control.
The background debug port connector, J200, (schematic 20) is a right-angled,
two by five shrouded square-pin header array. The port connects to an external
serial software debugger that causes the microprocessor to run in the background
debug mode (BDM). The signal lines are compatible with the P&E Microsystems BDM interface cable that has a pseudo standard software that supports
BDM operation. Table 4–10 lists the pins and signals on the connector.
The JTAG port, J601, (schematic 20) does not have square pins installed. If
desired, you can install six square pins in the circuit board to connect a JTAG
tester to the microprocessor and to the programmable logic device (PLD) signal
generator. Table 4–11 lists the pins and signals on the connector.
T able 4–11: JTAG port (J601)
Pin (not installed)Signal
1TDO
2Ground
3TCK
4Ground
5TMS
6TDI
Two power connectors (schematic 12) are available on the training board; a
power-input jack (J111) and a battery header (J110). The inner connector is
positive and the outer connector is connected to ground. Use one of the wall
power adapters to connect to the power-input jack.
Bus Interface Connector
You can also connect a 9 V to 14 V battery; however, battery operation should
only be used when there are no other ways to power the training board. If you
use the battery connector, you need to install square pins to the J110 battery
header.
The Bus Interface connector, J180, (schematic 11) provides a means for
connecting the training board to other test fixtures. The connector is a standard 3
by 32 male receptacle DIN connector. Use a 3 by 32 female connector (Tektronix
part number 131–2950–00 or similar) to connect to this connector.
The connector allows you to add additional circuitry to the training board. Use
the schematics in this manual and the signals listed in Table 4–12 to design the
circuitry to add to the connector.
The training board provides connections for Tektronix logic analyzer probes
(schematic sheets 13, 14, 15, 16, and 17). The connectors comply with the
Tektronix LASI-3 (0.10-inch square pins) and LASI-4 (high-density) interfaces.
This provides connections for 96 data channels and six clock channels. The data
channels and clock channels connect to the 68340 microprocessor and the related
control lines. The signals are compatible with the Tektronix 68340 microprocessor control package.
The counter and pattern generator signals can be probed with standard logic
analyzer probes on two by eight square-pin headers. They can also be probed by
connecting to the high-density interface connectors.
The four-bit setup and hold counter can be probed on two by eight square-pin
headers or on two by eight oscilloscope probe headers. The same is true for the
analog and digital groups of signals on the training board.
4–16
TLA QuickStart Technical Reference Manual
Functional Verification Procedures
This chapter provides basic functional check procedures to verify that the TLA
7QS Training Board is operational beyond power-up diagnostics. There are no
specific performance verification procedures for the training board.
The basic functional verification is accomplished by performing the following
procedures:
Microprocessor circuitry check
Counter-pattern generator circuitry check
Digital and analog circuitry check
Equipment Required
Table 5–1 summarizes the test equipment required to complete the functional
check procedures.
T able 5–1: Test equipment
Item number and descriptionMinimum requirementsExample
2.Logic analyzer module102 channel or 136 channel TLA 700 Series Logic
Analyzer Module
3.Logic Analyzer Probes6 P6417 Probes and 3 P6434 Probes–
4.TLA 7QS SoftwareTLA 7QS Application software and TLA 7QS Microproces-
sor Analysis Files
5.Training ManualTLA 7QS QuickStart Training ManualIncluded with the TLA 7QS
6.Oscilloscope1 GHz analog bandwidthTektronix TDS 684B
7.Oscilloscope Probe1 GHz analog bandwidthTektronix P6245
TLA 7M3, TLA 7M4, TLA 7L3
or TLA 7L4
–
QuickStart Training Manual
TLA QuickStart Technical Reference Manual
5–1
Functional Verification Procedures
Microprocessor Circuitry Check
The following checks verify the functionality of the microprocessor circuitry on
the training board. This procedure is based on the microprocessor exercises in
the TLA 7QS Training Manual.
NOTE. To complete the functional check procedure, it is assumed that the
TLA 7QS application software and Microprocessor Analysis software files are
installed on the logic analyzer. If not, refer to the TLA 7QS Training Manual for
information on installing the software on the logic analyzer.
To perform the check, refer to the TLA 7QS Training Manual and perform the
following steps:
1. Connect the P6417 probes to the training board as indicated in the Micropro-
cessor Exercises Setup chapter.
2. Power on the training board.
3. Perform the steps under Microprocessor Exercise 1: Trigger on a Power-on
Reset and Capture the Controller Startup Code in the training manual.
4. Check that the Listing Data window shows disassembled data similar to that
in the exercise.
If the disassembled data is similar to that shown in the exercise example, you
have verified the functionality of the microprocessor circuitry for the P6417
probe connections.
5. Disconnect the P6417 probes from the training board and from the logic
analyzer and connect the P6434 probes.
6. Repeat the exercise using the P6434 probes.
If the disassembled data is similar to that shown in the exercise example, you
have verified the functionality of the microprocessor circuitry for the P6434
probe connections.
Counter-Pattern Generator Circuitry Check
The following procedure verifies the functionality of the counter-pattern
generator circuitry.
5–2
1. Disconnect the P6434 probe connected to the Group C connector on the
training board and connect the probe to the counter–pattern generator
connector (J820).
TLA QuickStart Technical Reference Manual
Functional Verification Procedures
2. Use the UP or DN buttons on the training board to select the PATTERN
GEN program.
3. Push the RUN button on the training board to start the pattern generator
program.
4. On the logic analyzer, restore the default setups (select Default System from
the File menu).
5. Open the Setup menu from the logic analyzer icon in the system menu.
6. Click on the Show Activity button to open the Activity monitor.
7. Check that the probe channels connected to the training board show activity
represented by up and down arrows for each channel.
Figure 5–1 shows an example of the Activity monitor with active signals for
the probes connected to the training board.
Figure 5–1: Sample Activity Monitor
If all signal channels show activity, you have verified the functionality of the
counter-pattern generator circuitry for the P6434 probe connections.
8. Disconnect the P6434 probes from the training board and from the logic
analyzer and connect the P6417 probes to the High Counter-Pattern
Generator and Low Counter-Pattern Generator connectors on the training
board (J840, J940, J830, and J930).
9. Check that the probe channels connected to the training board show activity
represented by up and down arrows for each channel.
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Functional Verification Procedures
If all signal channels show activity, you have verified the functionality of the
counter-pattern generator circuitry for the P6417 probe connections.
10. Disconnect one of the P6417 probes and connect one set of the 8-channel
lead sets to the Setup-Hold Signal connector (J850).
11. Connect the other set of 8-channel lead sets to the Tapped Delay connector
(J950)
12. Check that the probe channels connected to the training board show activity
on each channel.
If all signal channels show activity, you have verified the functionality of the
Setup-Hold Signal connector and the Tapped Delay connector.
13. Disconnect the logic analyzer probes from the training board.
Digital and Analog Circuitry Check
The procedures in this section check the following signals on the training board:
Runt pulse and missing pulse
Narrow pulse
Burst pulse
Fast edge signal
Metastable glitch signal
Staircase signal
To complete these checks, you will need a 1 GHz analog bandwidth oscilloscope
and an oscilloscope probe (Tektronix TDS 684B with a P6345 probe).
5–4
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Functional Verification Procedures
Runt Pulse and Missing
Pulse Check
Perform the followings steps to verify basic functionality of the runt pulse and
missing pulse.
1. Set up the vertical input of the oscilloscope to measure a 2 V pulse.
2. Set horizontal controls as follows:
Time/Div100 ns
PositionTrigger at center
Trigger position50%
3. Set up the trigger controls as follows:
TypePulse, Width, Neg, Trig Outside
15–128 ns
Level3.2 V
SourceCh1
PolarityPositive
Threshold220 mV
4. Connect the Channel 1 probe to the RUNT pin on the training board
(J870–3). Connect the probe ground lead to a nearby ground pin.
Narrow Pulse Check
5. Check for a series of pulses, with one of the pulses being a blinking runt
pulse.
Perform the followings steps to verify basic functionality of the narrow pulse
signal.
1. Set up the vertical input of the oscilloscope to measure a 500 mV signal.
2. Set horizontal controls as follows:
Time/Div2 ns
Trigger position50%
3. Set up the trigger controls as follows:
TypeEdge
SourceCh1
SlopeRising
Level500 mV
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Functional Verification Procedures
4. Connect the Channel 1 probe to the PULS pin on the training board
5. Adjust the trigger level control on the oscilloscope for a positive pulse (the
6. Check for a 0.5 ns – 6.0 ns pulse with an amplitude between 0.3 V and
(J870–5). Connect the probe ground lead to a nearby ground pin.
pulse may have some jitter).
2.0 V.
Burst Pulse Check
Perform the followings steps to verify basic functionality of the burst pulse
signal.
1. Set up the vertical input of the oscilloscope to measure a 2 V signal.
2. Set horizontal controls as follows:
Time/Div50 ns
Trigger position50%
3. Set up the trigger controls as follows:
TypeEdge
SourceCh1
SlopeRising
Level3.2 V
4. Connect the Channel 1 probe to the BURST pin on the training board
(J860–3). Connect the probe ground lead to a nearby ground pin.
5. Adjust the trigger level control on the oscilloscope for a stable signal.
6. Check for a signal with bursts of pulses.
Fast Edge Signal Check
5–6
Perform the followings steps to verify basic functionality of the fast edge signal.
1. Set up the vertical input of the oscilloscope to measure a 200 mV signal. Set
the position two divisions below the center graticule.
2. Set horizontal controls as follows:
Time/Div100 s
PositionTrigger at center
Trigger position50%
TLA QuickStart Technical Reference Manual
Functional Verification Procedures
3. Set up the trigger controls as follows:
TypeEdge
SourceCh1
SlopeRising
Level220 mV
4. Connect the Channel 1 probe to the EDGE pin on the training board
(J870–7). Connect the probe ground lead to a nearby ground pin.
5. Check for a signal from 250 mV to 1500 mV with a frequency from 1.5 KHz
to 3.5 KHz. The rise time should be from 0 to 300 ps.
Metastable Glitch Signal
Check
Perform the following steps to verify basic functionality of the metastable glitch
signal.
1. Set up the vertical input of the oscilloscope to measure a 2 V signal.
2. Set horizontal controls as follows:
Time/Div20 ns
PositionTrigger at center
Trigger position50%
3. Set up the trigger controls as follows:
TypeEdge
SourceCh1
SlopeRising
PolarityPositive
Level1.3 V
Threshold1.3 V
4. Connect the Channel 1 probe to the FF-D pin on the training board (J870–5).
Connect the probe ground lead to a nearby ground pin.
5. Check for a glitch in the square wave signal that is over 2 V.
TLA QuickStart Technical Reference Manual
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Functional Verification Procedures
Staircase Signal Check
Perform the followings steps to verify basic functionality of the staircase signal.
1. Set up the vertical input of the oscilloscope to measure a 200 mV signal.
Set the position two divisions below the center graticule.
2. Set horizontal controls as follows:
Time/Div1 ms
PositionTrigger at center
Trigger position90%
4. Connect the Channel 1 probe to the STEP pin on the training board
(J870–1). Connect the probe ground lead to a nearby ground pin.
5. Adjust the oscilloscope trigger level control for a stable staircase signal.
6. Check for a staircase signal with a peak-to-peak amplitude between 800 mV
and 1200 mV and a frequency between 63 Hz and 250 Hz.
7. Disconnect the probes from the training board.
8. Power off the training board.
5–8
TLA QuickStart Technical Reference Manual
Maintenance
Preventing ESD
This chapter contains the information needed for periodic and corrective
maintenance of the TLA 7QS Training Board. The following sections are
included:
Preventing ESD
Service Strategy
Inspection and Cleaning (see page 6–2)
Troubleshooting (see page 6–3)
Repackaging Instructions (see page 6–3)
When performing any service adhere to the following precautions to avoid
damaging internal modules and their components due to electrostatic discharge
(ESD).
Service Strategy
Warranty Repair Service
1. Minimize handling of static-sensitive components.
2. Transport and store static-sensitive components in their static protected
containers or on a metal rail. Label any package that contains static-sensitive
components.
3. Discharge the static voltage from your body by wearing a grounded antistatic
wrist strap while handling these components.
4. Nothing capable of generating or holding a static charge should be allowed
on the work station surface.
Tektronix provides service to cover repair under warranty as well as other
services that may provide a cost-effective answer to your service needs.
Tektronix warrants the training board for three months from the date of
shipment. Any failures will be replaced with an exchange module from the
Beaverton Exchange center. Tektronix technicians provide in-service center
warranty service at most Tektronix service locations worldwide. For the latest
information on Tektronix products, refer to the Tektronix Internet site at
http://www.tek.com.
TLA QuickStart Technical Reference Manual
6–1
Maintenance
Customer site service is also available from most of the same service locations.
Repair or Calibration
Service
Self Service
Tektronix offers several standard-priced adjustment (calibration) and repair
services:
A single repair and/or adjustment
Calibrations using equipment and procedures that meet the traceability
standards specific to national standards requirements (Calibrations do not
apply to the TLA 7QS QuickStart Training Board)
Annual prearranged service do not apply to the TLA 7QS QuickStart
Training Board
Of these services, the annual prearranged service offers a particularly cost-effective approach to service for many owners of the TLA 700 series logic analyzers.
Tektronix supports repair to the module level by providing Module Exchange.
Module Exchange. Use this service to reduce down time for repair by exchanging
circuit boards for remanufactured ones. Tektronix ships an updated and tested
exchange circuit board from the Beaverton, Oregon service center. Each circuit
board comes with a 90-day service warranty.
Inspection and Cleaning
For More Information. Contact your local Tektronix service center or sales
engineer for more information on any of the repair or adjustment services just
described.
This section describes how to inspect for dirt and damage, and how to clean the
training board. Inspection and cleaning are done as preventive maintenance.
Preventive maintenance, when done regularly, may prevent malfunctions and
enhance reliability.
Preventive maintenance consists of visually inspecting and cleaning the training
board, and using general care when operating it. How often to do maintenance
depends on the severity of the environment in which the training board is used.
Inspect and clean the training board as often as operating conditions require.
Collection of dirt on internal components can cause them to overheat and break
down. Dirt acts as an insulating blanket, preventing efficient heat dissipation.
Dirt also provides an electrical conduction path
under high-humidity conditions.
thatcan cause failures, especially
6–2
TLA QuickStart Technical Reference Manual
CAUTION. Avoid using chemical cleaning agents that might damage the plastics
and external labels used on the training board. Use a cloth dampened with water
to clean external surfaces. Before using any cleaner, consult your Tektronix
Service Center or representative.
To clean the exterior, perform the following steps:
1. Remove loose dust on the outside of the training board with a lint free cloth.
2. Remove remaining dirt with a lint free cloth dampened with water. Do not
use abrasive cleaners.
Troubleshooting Procedures
Most troubleshooting is accomplished by use of diagnostics and probing for
signals on the training board with an oscilloscope, a logic analyzer, or a logic
probe.
Maintenance
Diagnostics
Signal Tracing
Parts Replacement
Diagnostics run when you first apply power to the training board or when you
press the Reset button. You can also select the diagnostics from the menu in the
user interface. For information on diagnostics refer to page 2–16.
Use an oscilloscope or a logic probe to trace faults to specific areas on the
training board. Use the schematics in this manual to help isolate problems to a
component or connector.
Refer to the Replaceable Electrical Parts list for part numbers of all electrical
parts on the training board. Refer to the Replaceable Mechanical Parts list for
part numbers of all mechanical parts and accessories.
Repackaging Instructions
This section contains the information needed to repackage the training board for
shipment.
If at all possible, use the original packaging to ship or store the training board. If
the original packaging is not available, use a corrugated cardboard shipping
carton having a test strength of at least 275 pounds (125 kg) and with an inside
dimension at least six inches (15.25 cm) greater than the training board
dimensions. Add cushioning material to prevent the training board from moving
around in the shipping container.
TLA QuickStart Technical Reference Manual
6–3
Maintenance
If the training board is being shipped to a Tektronix Service Center, enclose the
following information:
The owner’s address
Name and phone number of a contact person
Type and serial number of the training board
Reason for returning
A complete description of the service required
Seal the shipping carton with an industrial stapler or strapping tape.
Mark the address of the Tektronix Service Center and also your own return
address on the shipping carton in two prominent locations.
6–4
TLA QuickStart Technical Reference Manual
Replaceable Electrical Parts
This section contains a list of the electrical components for the TLA 7QS
training board. Use this list to identify and order replacement parts.
Parts Ordering Information
Replacement parts are available through your local Tektronix field office or
representative.
Changes to Tektronix products are sometimes made to accommodate improved
components as they become available and to give you the benefit of the latest
improvements. Therefore, when ordering parts, it is important to include the
following information in your order:
Part number
Instrument type or model number
Instrument serial number
Instrument modification number, if applicable
If you order a part that has been replaced with a different or improved part, your
local Tektronix field office or representative will contact you concerning any
change in part number.
Change information, if any, is located at the rear of this manual.
Using the Replaceable Electrical Parts List
The tabular information in the Replaceable Electrical Parts List is arranged for
quick retrieval. Understanding the structure and features of the list will help you
find all of the information you need for ordering replacement parts. The
following table describes each column of the electrical parts list.
TLA QuickStart Technical Reference Manual
7–1
Replaceable Electrical Parts
Parts list column descriptions
ColumnColumn nameDescription
1Component numberThe component number appears on diagrams and circuit board illustrations, located in the diagrams
section. Assembly numbers are clearly marked on each diagram and circuit board illustration in the
Diagrams section, and on the mechanical exploded views in the Replaceable Mechanical Parts list
section. The component number is obtained by adding the assembly number prefix to the circuit
number (see Component Number illustration following this table).
The electrical parts list is arranged by assemblies in numerical sequence (A1, with its subassemblies and parts, precedes A2, with its subassemblies and parts).
Chassis-mounted parts have no assembly number prefix, and they are located at the end of the
electrical parts list.
2Tektronix part numberUse this part number when ordering replacement parts from Tektronix.
3 and 4Serial numberColumn three indicates the serial number at which the part was first effective. Column four indicates
the serial number at which the part was discontinued. No entry indicates the part is good for all
serial numbers.
5Name & descriptionAn item name is separated from the description by a colon (:). Because of space limitations, an item
name may sometimes appear as incomplete. Use the U.S. Federal Catalog handbook H6-1 for
further item name identification.
6Mfr. codeThis indicates the code number of the actual manufacturer of the part.
7Mfr. part numberThis indicates the actual manufacturer’s or vendor’s part number.
Abbreviations
Component Number
List of Assemblies
Chassis Parts
Mfr. Code to Manufacturer
Cross Index
Abbreviations conform to American National Standard ANSI Y1.1–1972.
Component Number
A23A2R1234 A23 R1234
Assembly numberCircuit Number
Read: Resistor 1234 (of Subassembly 2) of Assembly 23
A2
Subassembly Number
(optional)
A list of assemblies is located at the beginning of the electrical parts list. The
assemblies are listed in numerical order. When a part’s complete component
number is known, this list will identify the assembly in which the part is located.
Chassis-mounted parts and cable assemblies are located at the end of the
Replaceable Electrical Parts List.
The table titled Manufacturers Cross Index shows codes, names, and addresses
of manufacturers or vendors of components listed in the parts list.
7–2
TLA QuickStart Technical Reference Manual
Replaceable Electrical Parts
Manufacturers cross index
Mfr.
code
00779AMP INC.CUSTOMER SERVICE DEPT
01295TEXAS INSTRUMENTS INCSEMICONDUCTOR GROUP
04222AVX/KYOCERAPO BOX 867MYRTLE BEACH, SC 29577
04426ITW SWITCHESAN ILLINOIS TOOL WORKS CO.
04713MOTOROLA INCSEMICONDUCTOR PRODUCTS SECTOR
06090RAYCHEM CORP300 CONSTITUTION DRMENLO PARK, CA 94025–1111
09969DALE ELECTRONIC COMPONENTSEAST HWY 50
0B0A9DALLAS SEMICONDUCTOR4350 BELTWOOD PKWY SDALLAS, TX 75244
0HAF7EPSON AMERICA20770 MADRONA AVETORRANCE, CA 90503
0LUT2TOYOCOM USA INC617 E GOLF ROAD
1CH66PHILIPS SEMICONDUCTORS811 E ARQUES AVE
1ES66MAXIM INTEGRATED PRODUCTS INC120 SAN GABRIEL DRSUNNYVALE, CA 94086
27014NATIONAL SEMICONDUCTOR CORP2900 SEMICONDUCTOR DR
This section contains the troubleshooting procedures, block diagrams, circuit board
illustrations, component locator tables, waveform illustrations, and schematic diagrams.
Symbols
Graphic symbols and class designation letters are based on ANSI Standard Y32.2-1975.
Abbreviations are based on ANSI Y1.1-1972.
Logic symbology is based on ANSI/IEEE Standard 91-1984 in terms of positive logic.
Logic symbols depict the logic function performed and can differ from the manufacturer’s
data.
The tilde (~) or asterisk (*) preceding a signal name indicates that the signal performs its
intended function when in the low state.
Other standards used in the preparation of diagrams by Tektronix, Inc., include the
following:
Tektronix Standard 062-2476 Symbols and Practices for Schematic Drafting
ANSI Y14.159-1971 Interconnection Diagrams
ANSI Y32.16-1975 Reference Designations for Electronic Equipment
Locator Grid
Function Block Title
Internal Screw Adjustment
Onboard Jumper
Digital Ground
Refer to Assembly
& Diagram Number
Offboard Connector
Active Low Signal
Signal From
Another Diagram,
Same Board
A
B
12 3
Component Locator Diagrams
The schematic diagram and circuit board component location illustrations have grids
marked on them. The component lookup tables refer to these grids to help you locate a
component. The circuit board illustration appears only once; its lookup table lists the
diagram number of all diagrams on which the circuitry appears.
Some of the circuit board component location illustrations are expanded and divided into
several parts to make it easier for you to locate small components. To determine which
part of the whole locator diagram you are looking at, refer to the small locator key shown
below. The gray block, within the larger circuit board outline, shows where that part fits
in the whole locator diagram. Each part in the key is labeled with an identifying letter that
appears in the figure titles under component locator diagrams.
4
Power Termination
Component on back of board
Strap
Panel Control
Female Coaxial
Connector
Heat Sink
Decoupled Voltage
Diagram Number
Assembly Number
Diagram Name
MIL-HDBK-63038-1A Military Standard Technical Manual Writing Handbook
Component Values
Electrical components shown on the diagrams are in the following units unless noted
otherwise:
Capacitors:Values one or greater are in picofarads (pF).
Values less than one are in microfarads (F).
Resistors:Values are in Ohms ().
Graphic Items and Special Symbols Used in This Manual
Each assembly in the instrument is assigned an assembly number (for example A5). The
assembly number appears in the title on the diagram, in the lookup table for the schematic
diagram, and corresponding component locator illustration. The Replaceable Electrical
Parts list is arranged by assembly in numerical sequence; the components are listed by
component number.
Section of Circuit
Board Shown
TLA QuickStart Technical Reference Manual
123
A
J110
S110
J111
DS210
C
CR120
C130
R210
C210
CR220
C212
C
U231
R211
F220
C213C211
R212
J330
J340
R501
J500
U511
R513
J630
J640
C610
J620
Y610
R620
R621
J400
R500
J320
C411
L410L310
C421
R410
J420
R510
R511 R512
J430
J440J740
J540
J541J531
C600
J730J530
C622
R720
J600J200
C710
U710
C720
U720
R721
R710
R722
J601
R711
U712
U722
R730
R712
R723
R713
J731
J741
R714
R700
R715
C713
C723C712
U726
J700
CR800
R810
U821U723
U822
J830
J840
R811
C800
C810
C811
C820
CR801
J800
R900
R800
U812U810
C813
C822
U910
U920U824
C911
C921
J820
J930
J940
B
J180
R180
R181
S290
C150
C170C160
C180
U251
U261
U271
C282
U291
C285
U292
C350
Y360
C370
Y380
R390
J350
J450
R450
R454
R451
U371
R452
R453
R470
R480
C480
R550
TP5
R460
C470
C472
R471
R481
C482
R482
C471
J550
R551
R461
R483
C483
R552
U460
U471
U480
U461
C485
R484
R580
S590
C550
R560
C570C560
C580
R561
C572
C573
R570
R585
U560
J551
U563
U572
U580
C582
R581
R582
S591
C551
R562
C585
C565
C576
C584
U564
CR670
C586
R583
R584
U661
R670
R671
C671
C670
U681
R672
R673
C650
R660
R661
Q670
CR671
R674
S690S490
R675
C661
R662
C672
R676
R677
R678
R679
R680
C680
R663
Q671
Q672
Q673
Q680
R681
R682
J750
R750
R683
R684
R685
R751
R770
J770
R752
R771
R753
C770
R772
R760
J751J760
J771
U791
J850
J860
J870
C890
U890
J950J650
J960
J961
J970
J971
DS880DS780
C990
G9DĆ2234Ć00
COMPONENT NUMBER EXAMPLE
A23 A2 R1234
ChassisĆmounted components have no Assembly Number
prefixĊsee end of Replaceable Electrical Parts List.
STATIC
SENSITIVE
DEVICES
A01 TLA 7QS Quickstart Training Board (front)
TLA QuickStart Technical Reference Manual
123
A
U0911
U0921
C0910
C0920
U0813
U0825
C0812
C0821
U0811
U0823
U0820
C0714
C0725
C0724
U0713
U0724
C0711
U0725
C0721
C0722
U0711
U0721
C0612
C0621
R0611
U0610
C0611
C0660
C0620
U0660
R0610
U0565
C0564
R0564
C0563
U0510
U0562
C0521C0523 C0522
U0561
C0520
C0562
R0562
U0410
U0462
C0561
C0462
R0463
C0422
C0461
R0462
R0460
R0461
C0460
C0410
C0420
C
CR0310
R0310R0311
Q0310
U0360
U0210
C0260
C0214
U0230
C0240
U0250
C0151
U0260
B
R0890R0891
C0891
TLA QuickStart Technical Reference Manual
C0791
U0790
C0790
C0673
U0670
U0682
U0573
U0680
C0575
C0583
U0570
U0571
C0581
R0580
C0571
C0574
R0581
C0484
U0470
C0481
U0370
U0380
U0390
R0270
C0271
C0284
C0283
U0270
C0281
U0290
C0270
C0280
G9DĆ2234Ć00
COMPONENT NUMBER EXAMPLE
A23 A2 R1234
ChassisĆmounted components have no Assembly Number
prefixĊsee end of Replaceable Electrical Parts List.
STATIC
SENSITIVE
DEVICES
A01 TLA 7QS Quickstart Training board (back)
A01 TLA 7QS Quickstart Training Board Component Locator