Tait Electronics Limited
P.O. Box 1645
Christchurch
New Zealand
For the address and telephone number of regional
offices, refer to the TaitWorld website:
We b s it e : http://www.taitworld.com
Technical Support
For assistance with specific technical issues, contact
Technical Support:
E-mail: support@taitworld.com
We b s it e : http://support.taitworld.com
Intellectual Property Rights
This product may be protected by one or more patents
of Tait Electronics Limited together with their
international equivalents, pending patent applications
and registered trade marks: NZ338097, NZ 508054,
NZ508340, NZ508806, NZ 508807, NZ 509242,
NZ509640, NZ509959, NZ 510496, NZ 511155,
NZ511421, NZ516280/519742, NZ 519118,
NZ519344, NZ520650/537902, NZ 521450,
NZ524509, NZ524537, NZ 524630, NZ 530819,
NZ534475, NZ534692, NZ 535471, NZ 536945,
NZ537434, NZ534369, NZ 522236, NZ 524378,
AU2003281447, AU2002235062, AU2004216984,
CA2439018, EU03784706.8, EU 02701829.0,
EU04714053.8, GB23865476, GB 2386010,
GB0516094.0, GB0516092.4, US 09/847322, US60/
613748, US60/539617, US 10/520827, US10/468740,
US5,745,840, US 10/520827.
Copyright and Trademarks
All information contained in this manual is the property
of Tait Electronics Limited. All rights reserved.
This manual may not, in whole or in part, be copied,
photocopied, reproduced, translated, stored, or reduced
to any electronic medium or machine-readable form,
without prior written permission from Tait Electronics
Limited.
The word TAIT and the TAIT logo are trademarks of
Tait Electronics Limited.
All trade names referenced are the service mark,
trademark or registered trademark of the respective
manufacturers.
Disclaimer
There are no warranties extended or granted by this
manual. Tait Electronics Limited accepts no
responsibility for damage arising from use of the
information contained in the manual or of the
equipment and software it describes. It is the
responsibility of the user to ensure that use of such
information, equipment and software complies with the
laws, rules and regulations of the applicable
jurisdictions.
Enquiries and Comments
If you have any enquiries regarding this manual, or any
comments, suggestions and notifications of errors,
please contact Technical Support.
To Our European Customers
Tait Electronics Limited is an
environmentally responsible company
which supports waste minimization and
material recovery. The European Union’s
Waste Electrical and Electronic Equipment
Directive requires that this product be disposed of
separately from the general waste stream when its
service life is over. Please be environmentally
responsible and dispose through the original supplier,
your local municipal waste “separate collection” service,
or contact Tait Electronics Limited.
Updates of Manual and Equipment
In the interests of improving the performance, reliability
or servicing of the equipment, Tait Electronics Limited
reserves the right to update the equipment or this
manual or both without prior notice.
This manual contains information to service technicians for carrying out
level-1 and level-2 repairs of TM8100 and TM8200 radios and accessories.
Level-1 repairs entail the replacement of faulty parts and circuit boards;
level-2 repairs entail the repair of circuit boards, with the exception of
certain special items on the boards. The manual does not cover level-3
repairs, which entail the repair of the special items.
Hardware and Software Versions
This manual describes the following hardware and software versions.
The IPNs (internal part numbers) of the boards are listed below; the last two
digits in the IPN represent the issue of the board. The board information in
this manual covers all production-issue boards up to the issue listed below.
The characters xx represent the issue number of the documentation.
TM8100/TM8200 Main Board (B1) 25W
(board IPN 220-01700-05)
(boards after IPN 220-01700-05)
TM8100/TM8200 Main Board (H5/H6) 25W
(board IPN 220-01697-05)
(boards after IPN 220-01697-05)
(printed, pre-punched and shrink wrapped;
comprises MMA-00015-xx, MMA-00016-xx,
MMA-00020-xx, MMA-00021-xx, MMA-00031xx, MMA-00032-xx, MMA-00033-xx, MMA00034-xx, MMA-00035-xx, MMA-00050-xx and
MMA-00058-xx).
All available documentation is provided on the
TM8100/TM8200 Service CD, product code TMAA20-01.
Updates may also be published on the Tait support website.
3DK ManualsThe following manuals are mainly of concern to third-party developers.
The manuals are supplied on the 3DK (third-party developer’s kit)
resource CD.
■ MMA-00038-xxTM8100/TM8200 Computer-controlled Data
Publication Record
IssuePublication DateDescription
01March 2005first release
02May 2005update for 40W/50W radios
03August 2005update to board issue 10 (B1, H5 and H6 bands)
04June 2006include TM8200 3-digit-display control head, A4
Software Programmer’s Manual
Service Manual
Interface Protocol Definition
of 25W radios, incorporation of accessories
manual
and C0 bands, and information on issue -05 main
board for B1, H5 and H6 bands
Alert Notices
Within this manual, four types of alerts are given to the reader: warning,
caution, important and note. The following paragraphs illustrate each type
of alert and its associated symbol.
Warning!!This alert is used when there is a potential risk
of death or serious injury.
CautionThis alert is used when there is the risk of minor or
moderate injury to people.
ImportantThis alert is used to warn about the risk of equipment dam-
age or malfunction.
NoteThis alert is used to highlight information that is required to
The TM8100 and TM8200 series is a range of high-performance
microprocessor-controlled radios for analog voice and data communication.
The radios are designed for installation in vehicles but can also be used in
desktop, remote-monitoring and similar applications.
This manual includes the information required for servicing the radio and
its accessories.
This section describes the different options available for:
■ frequency bands
■ RF output power
■ accessories
■ product codes.
This section also gives an overview of the labels on the product and the
specifications.
Figure 1.1TM8200 mobile radios
TM8235 radio with 3-digit-display control head
TM8250 or TM8255 radio with graphical-display control head
The radios are available in the following frequency bands:
■ 66 to 88MHz (A4)
■ 136 to 174MHz (B1)
■ 174 to 225MHz (C0)
■ 216 to 266MHz (D1)
■ 400 to 470MHz (H5)
■ 450 to 530MHz (H6)
■ 450 to 520MHz (H7)
The frequency bands are implemented by different main boards in the radio
body. The control heads are identical for all frequency bands.
1.2RF Output Power
The radio bodies are available with 40W/50 W and 25W RF output power.
The two RF output power options are implemented by different main
boards in the radio body, mechanically different radio bodies, and different
power connectors. The control heads are identical for all RF output
power options.
The 40W/50W radio is available in the following frequency bands:
■ B1 (50W)
■ H5 (40W)
■ H7 (40W)
The 25W radio is available in the following frequency bands:
Tait offers a large variety of audio accessories, installation kits, internal
options boards and other accessories such as a desktop power supply.
For more information on these accessories refer to “Chapter 3 Accessories”
on page 447.
Audio AccessoriesThe radios allow for the connection of a comprehensive range of audio
accessories:
■ rugged microphone (standard)
■ DTMF microphone
■ keypad microphone
■ handset
■ concealed microphone (TM8200) and concealed microphone kit
(TM8100)
■ high-power remote speaker
■ remote PTT kit and hands-free kit.
Installation KitsThe radio is delivered with a vehicle installation kit, including a U-bracket.
Installation of the radio is described in the user’s guide or the installation
guide.
Optional installation kits are:
■ remote control-head kit for remote installation of the control head
■ security bracket for secure and quick-release installation
■ ignition-sense kit.
Internal Options
Boards
The radio provides space for an internal options board inside the radio body
connecting to an internal options connector. An aperture for an external
options connector is also provided.
Tait offers the following internal options boards:
■ line-interface board
■ RS-232 board
■ options-extender board.
Control-Head
Options Boards
The radio provides space for a control-head options board inside the blank
control head of the TM8105 and TM8252 radios.
Desktop Power
Supply
16IntroductionTM8100/TM8200 Service Manual
A desktop power supply including the parts for mounting the radio is
available for desktop installations.
This section describes the product codes used to identify products of the
TM8100 and TM8200 mobile radio product lines.
GeneralThe product codes of the TM8100 and TM8200 mobile radio product lines
have the format:
TMAabc–ddee
where:
■ a identifies the product category:
A=accessory, B =radio body, C =control head, S= software feature
■ b, c, dd and ee identify specific product features.
Radio BodiesThe product codes of the radio bodies have the format:
TMABbc–ddee
where:
■ b identifies the architecture of the digital board:
1=conventional analog
2=conventional analog (dual-mode capability)
3 identifies the digital boards of the digital TM9100 product line.
■ c identifies the RF output power:
2=25W, 3=25 W (trigger-base), 4=30 to 59 W,
5=30 to 59W (trigger-base).
■ dd identifies the frequency band:
A4=66 to 88MHz, B1 =136 to 174 MHz, C0 =174 to 225MHz,
D1=216 to 266MHz, H5 =400 to 470MHz, H6 =450 to 530MHz,
H7=450 to 520 MHz.
■ ee identifies any radio options:
00=BNC RF connector, 01=mini-UHF RF connector
Control HeadsThe product code of the control heads has the format:
TMACbc–dd
where:
■ b identifies the control-head type:
1=blank control head, 2=2-digit-display control head,
3=RJ45 control head, 4=graphical-display control head,
5=1-digit-display control head, 6= 3-digit-display control head.
■ c identifies the control-head configuration:
0=no options, 4=RS-485 option
1 identifies the control-head configuration of the digital TM9100
product line.
This section describes the mechanical design and architecture of the radio,
explains the operation of the transceiver and the control head, and gives
pinouts of the radio connectors.
2.1Mechanical Design
OverviewThe radio consists of the following main components:
■ control head B
■ radio body C.
Figure 2.1Components of the radio
C
B
D
E
3068z_01
The control head
where a seal
connects the control head to the radio body. Two dot-dash-dot marks at the
bottom of the radio body indicate the positions where a screwdriver is
applied to separate the control head from the radio body.
B clips firmly to the front face of the radio body C,
E provides IP54 class protection. A control-head loom D
OverviewThe radio body consists of the following main components (see Figure 2.2
on page 21):
■ cover B
■ lid D
■ internal options board (optional)
■ chassis G
■ main-board assembly F.
CoverThe black plastic cover B wraps over the top and sides of the radio body.
Apertures in the sides of the cover allow access to the four external screw
bosses of the radio body used for mounting the radio to the U-bracket.
LidThe aluminium lid D is attached to the chassis G with four M4x16 Torx-
head screws
provides for IP54 class protection. The rear of the lid has an aperture for an
external options connector, which may be fitted if an internal options board
is used. If no external options connector is used, the aperture is sealed with
a bung for IP54 class protection. The lid contains two of the four screw
bosses to attach the radio to the U-bracket of the installation kit.
C. A seal fitted inside a groove at the underside of the lid
Internal Options
Board (Optional)
On the inside of the lid, nine screw points are provided for mounting an
internal options board, which can be sized and shaped as required.
The internal options board connects to the internal options connector of
the main board. Tait offers a range of internal options board, which are
described in the accessories section of this manual. For more information on
how to create your own internal options board, contact Tait Electronics
Limited.
ChassisThe aluminium chassis g is different for the 40W/50W radio and the 25W
radio.
The chassis
five screws
G houses the main-board assembly F, which is attached with
E to screw bosses inside the chassis and with two screws I
through the rear of the chassis to the heat-transfer block.
The rear of the chassis has apertures for the RF, power and auxiliary
connectors of the main board. If the auxiliary connector is not used, the
aperture is sealed with a rubber bung
The RF connector has a rubber seal
The front of the chassis has an aperture for the control-head connector.
The control-head seal is fitted inside a groove around the flange at the front
face of the chassis and provides for IP54 class protection when the control
head is fitted. Two dot-dash-dot marks at the underside side of the chassis
indicate the leverage points for removing the control head from the
radio body.
The sides of the chassis contain two of the four screw bosses to attach the
radio to the U-bracket of the installation kit.
For heat dissipation, the chassis has heat fins at the rear, grooves at the
bottom, and holes in the front.
The heat fins at the rear of the 40W/50W radio are longer than those of the
25W radio. The grooves at the bottom of the 40W/50W radio are deeper
than those of the 25W radio.
For additional heat dissipation, the 40W/50W radio has an additional
L-shaped gap pad
The main board 1^ is attached to the heat-transfer block H with three
M3x10 Torx-head screws
auxiliary and RF connectors.
B and the fastening elements J, 1# and 1$ of the
The inner foam D-range seal
heat-transfer block. The power connector seal
against the heat-transfer block.
The power connector seal
the seal of the 25W radio (black).
Main BoardThe main board 1^ is a printed circuit board in SMT design with
components on the top and bottom sides. A digital board
soldered to the main board. Most components are shielded by metal cans.
There are different main boards for each frequency band and each RF
output power configuration.
The internal options connector
and the factory connector (not illustrated) for factory use are soldered to the
top side of the main board. The control-head connector
of the radio) and the auxiliary
the rear of the radio) are located on the bottom side of the main board.
The 40W/50W radio has a black power connector
has a white power connector.
G seals the auxiliary connector against the
1) seals the power connector
1) of the 40W/50W radio (blue) is different to
D is reflow-
E for connecting an internal options board
1& (facing the front
F, power 1! and RF 1% connectors (facing
1! and the 25W radio
For more information on the connectors, refer to “Connectors” on
page 36.
For heat dissipation, one of the screw bosses inside the chassis is in contact
with the underside of the main board. A larger copper plate at the underside
of the main board connects to the body of the heat-transfer block.
The 40W/50W radio has an additional gap pad between the heat-transfer
block and the main board
at the bottom side of the main board.
Heat-Transfer BlockThe aluminium heat-transfer block H dissipates heat from the main board
to the heat fins of the chassis. The heat-transfer block has a contact surface
to the larger copper plate at the underside of the main board
contact surface to the rear of the chassis. All contact surfaces are coated with
thermal paste.
Two self-adhesive foam seals
connector on either side of the heat-transfer block and the power connector
1) inside the aperture of the power connector are fitted to the heat-
OverviewThe control head can be divided into the following main areas:
■ front panel with control elements, indicators, LCD, speaker, and
concealed microphone (optional)
■ space-frame and seals
■ control-head board with SMT components, shielding cans, connectors,
and volume potentiometer
■ control-head loom with female-female adapter
■ adapter flange.
The circled numbers in this section refer to the items in Figure 2.4 on
page 27.
Front Panel
Assembly
The front panel assembly 1^ consists of an injection-moulded plastic part
with an integrated transparent light pipe element for the radio
STATUS LEDs,
a transparent lens which cannot be replaced, a cloth membrane which is
fixed to the speaker grille, and a foam seal inside a rectangular LCD recess
behind the lens. A label
1* with the radio model number is attached to the
front panel assembly with self-adhesive coating and can be replaced for
rebranding purposes.
Three clips on the rear side of the front panel assembly snap onto the spaceframe to hold the keypads
1# and 1#, the LCD assembly 1@ and the speaker
1! in place. The rear side of the front panel assembly also has four screw
bosses to fasten the control-head board
Knob for
Volume-Control
Potentiometer
KeypadsThe main keypad 1# (for the function, selection, and scroll keys) and the
The knob for the volume-control potentiometer 1& is fitted to the shaft of
the volume-control potentiometer, which is soldered to the control-head
board
F.
power keypad
1$ protrude through apertures in the front panel assembly 1^.
The rear sides of these keypads connect directly to the relevant contacts on
the control-head board
F.
F.
LCD AssemblyThe graphical-display LCD assembly 1@ sits on a foam seal inside a
rectangular recess of the front panel assembly
1^. Another foam seal is
attached to the rear of the LCD with self-adhesive coating. The LCD
assembly has a loom, which runs through a slot in the space-frame
connects to a connector on the rear side of the control-head board
SpeakerThe speaker 1! sits inside a round recess of the front panel assembly, where
a cloth membrane is fixed to the speaker grille. The speaker clamp
1) holds
the speaker in position. The speaker cable plugs into the speaker connector
on the rear side of the control-head board
F.
NoteIn some configurations the speaker may be disconnected.
Concealed
Microphone
(Optional)
A concealed microphone 1% consisting of the microphone capsule and a
rubber seal can be fitted in a round recess inside the front panel assembly
1^.
The microphone leads are soldered to two pads on the top side of the
control-head board. Before the microphone is fitted, a small hole is drilled
in the recess to provide an acoustic path to the microphone. The hole is
covered by the rubber seal to ensure that the control head remains sealed to
IP54 standards. For more information refer to “TMAA02-07 Concealed
Microphone” on page 501.
Space-FrameThe aluminium space-frame J snaps into the three clips of the front panel
assembly
1^. The front side of the space-frame holds the keypads, the LCD
assembly, and the speaker in place and at the same time allows access to their
electrical contacts. The rear side of the space-frame has four through-holes
for the screws
the adapter flange
E of the control-head board F and two screw bosses to fit
C. Two light pipes H and I are fitted in recesses in the
space-frame and direct light from LEDs on the control-head board to the
front panel. A slot at the top edge of the space-frame allows the loom of the
LCD assembly
SealsTwo identical ring seals G fitted to grooves around the perimeter of the
Control-Head BoardThe control-head board F is a printed circuit board in SMT design with
components on the top and bottom sides. Some SMT components are
shielded by metal cans.
The control-head board is fitted to the front panel assembly
space-frame
J with four 3x10 PT screws E.
1^ through the
The side facing the radio body has the connectors for the connection of the
control-head loom, the LCD loom, the speaker, an optional control-head
options board, and pads for the leads of the optional concealed microphone.
Figure 2.5Connectors of the control-head board
pads for leads of
concealed microphone
connector for
loom of LCD assembly
connector for control-head
options board
connector for speaker
connector for
control-head loom
The side facing the front panel has the volume-control potentiometer, the
microphone connector, the indicator and backlight LEDS, and the contacts
for the keypads.
Control-Head LoomThe control-head loom D connects the connector on the control-head
board to the control-head connector of the radio body. For more
information refer to “Control-Head Connectors” on page 42.
Adapter FlangeThe adapter flange C is an injection-moulded plastic part, which is fitted to
OverviewThe control heads with 1-, 2- or 3-digit display can be divided into the
following main areas:
■ front panel with control elements, indicators, speaker, and optional
concealed microphone
■ space-frame
■ control-head board with SMT components, shielding cans, connectors,
and volume potentiometer
■ control-head loom with female-female adapter.
The circled numbers in this section refer to the items in Figure 2.6 on
page 31.
Front Panel
Assembly
The front panel assembly H consists of an injection-moulded plastic part
with an integrated transparent light pipe element for the radio
STATUS LEDs,
a transparent lens which cannot be replaced, and a cloth membrane which
is fixed to the speaker grille. Depending on the type of control head, the
aperture on the lens is sized to display either one, two or three characters.
A label with the radio model number is attached to the front panel assembly
with self-adhesive coating and can be replaced for rebranding purposes.
Six clips on the space-frame
inside of the front panel assembly to hold the keypad
the speaker
Knob for
Volume-Control
Potentiometer
KeypadThe keypad 1@ protrudes through apertures in the front panel assembly H.
The knob for the volume-control potentiometer I is fitted to the shaft of
the volume-control potentiometer, which is soldered to the control-head
board
J in place.
F.
G snap into corresponding locations on the
1@, the LCD 1!, and
The rear side of each key connects directly to the relevant contact on the
control-head board
E. Four light pipes 1# and 1$ are fitted in the
appropriate recesses in the keypad and direct light from LEDs on the
control-head board to the front panel.
LCDThe LCD 1! sits inside a rectangular recess of the front panel assembly H
and is held in place by the space-frame
LCD and the control-head board is ensured by two elastomeric strips
G. Electrical contact between the
F
held in place by the space-frame.
SpeakerThe speaker J sits inside a round recess of the front panel assembly, where
a cloth membrane is fixed to the speaker grille. The space-frame
G holds
the speaker in position. The speaker cable plugs into the speaker connector
on the rear side of the control-head board
E.
NoteIn some configurations the speaker may be disconnected.
A concealed microphone 1) consisting of the microphone capsule and a
rubber seal can be fitted in a round recess inside the front panel assembly
The microphone leads are soldered to two pads on the top side of the
control-head board
E. Before the microphone is fitted a small hole is drilled
H.
in the recess to provide an acoustic path to the microphone. The hole is
covered by the rubber seal to ensure that the control head remains sealed to
IP54 standards. For more information refer to “TMAA02-06 Support Kit
for Concealed & Dynamic Microphones” on page 493.
Space-FrameThe plastic space-frame G clips into the six recesses inside the front panel
assembly
H. The front side of the space-frame holds the keypad (with the
four light pipes), the LCD, and the speaker in place and at the same time
allows access to their electrical contacts. The rear side of the space-frame has
three holes for the screws
Control-Head BoardThe control-head board E is a printed circuit board in SMT design with
D of the control-head board E.
components on the top and bottom sides. There are different boards for the
control heads with 1-, 2- and 3-digit display.s
The control-head board is clipped and then fitted to the space-frame
three 3x8 PT screws
D.
G with
The side facing the radio body has the connectors for the connection of the
control-head loom
B, the speaker, an optional control-head options board
C, and pads for the leads of the optional concealed microphone 1).
The side facing the front panel has the volume-control potentiometer, the
microphone connector, the indicator and backlight LEDs, the contacts for
the keypads, and the LCD.
Control-Head LoomThe control-head loom B with the female-female adapter connects the
connector on the control-head board
the radio body. For more information refer to “Control-Head Connectors”
Figure 2.9 shows the controls and indicators of the user interfaces. For more
information refer to the following user’s guides:
■ TM8100 (1-digit and 2-digit-display control head)
■ TM8250/TM8255 (graphical-display control head)
■ TM8235 (3-digit-display control head).
Some keys have functions assigned to both short and long key presses.
A short key press is less than one second, and a long key press is more than
one second.
OverviewThis section describes the specifications and pinouts of the connectors of the
radio body and the control head.
Figure 2.10 provides an overview of the connectors:
Figure 2.10Connectors (radio with graphical-display control head)
Volume
Control
Microphone
Connector
Keys
LCD
LEDs
Speaker
Control-Head
Options Connector
Control-Head
Options Board
Control-Head
Board
Pads for
Concealed
Microphone
Speaker
Connector
Speaker
Leads
Control-Head
Loom
Control-Head
Connector
Factory
Connector
(Factory Only)
Internal
Options
Loom
Main Board
Internal
Options
Connector
Internal
Options
Board
RF Connector
Power
Connector
Auxiliary
Connector
External
Options
Connector
Figure 2.11 shows the connectors of the radio body.
Figure 2.12 shows the connectors of the control head.
For information on the factory connector of the main board and the internal
connectors of the control head, refer to the PCB information of the main
boards and the control-head board.
The RF connector is the primary RF interface to the antenna. The RF
connector is a BNC connector or a mini-UHF connector with an
impedance of 50Ω.
ImportantThe maximum RF input level is +27dBm. Higher levels
may damage the radio.
Table 2.1RF connector - pins and signals
PinoutPinSignal NameSignal Type
1RFRF analog
B
C
rear view
2GNDRF ground
2.3.2Power Connector
The power connector is the interface for the primary 13.8 V power source
and the external speaker. The primary power source can be the vehicle
battery or a mains-fed DC power supply. There are different power
connectors for the 40W/50W and 25 W radios.
ImportantThe speaker load configuration is balanced; the speaker
output lines must not be connected to ground. Connecting
a speaker output line to ground will cause audio power
amplifier shutdown
Table 2.2Power connector (radio) – pins and signals
The auxiliary connector is the standard interface for external devices that are
typically connected to a radio. The auxiliary connector is a 15-way
standard-density D-range socket. The auxiliary connector provides a serial
port, three programmable input lines, four programmable digital I/O lines
and audio I/O.
The I/O lines can be programmed for a variety of functions, logic levels,
and in some cases, direction. Audio lines can also be programmed to tap
into, or out of, different points in the audio processing chain. For more
information refer to the online help of the programming application.
Table 2.3Auxiliary connector – pins and signals
PinoutPin Signal nameDescriptionSignal type
12AUX_GPI1General purpose digital input.
Programmable function.
B
J
C
1)
D
1!
E
1@
F
1#
G
1$
H
1%
I
rear view
a. For more information on hardware links refer to “Power-Sense Options” on page 83.
b. Can be switched or unswitched. For more information refer to “Connector Power Supply Options” on page 86.
5AUX_GPI2General purpose digital input.
Programmable function.
With LK3 fitted, GPI2 is an
emergency power sense input.
4AUX_GPI3General purpose digital input.
Programmable function.
With LK2 fitted, GPI3 is a power
sense input.
10AUX_GPIO4Programmable function and
2AUX_GPIO5
9AUX_GPIO6
1AUX_GPIO7
11AUX_TXDAsynchronous serial port -
3AUX_RXDAsynchronous serial port -
7AUD_TAP_INProgrammable tap point into the Rx
13AUD_TAP_OUT Programmable tap point out of the
14AUX_MIC_AUD Auxiliary microphone input.
6RSSIAnalog RSSI output. Analog
8+13V8_SW
15AGNDAnalog groundGround
direction.
Pads available to fit a higher power
driver transistor on GPIO4 line
Tran sm it d at a
Receive data
or Tx audio chain. DC-coupled.
Rx or Tx audio chain. DC-coupled.
Electret microphone biasing
provided. Dynamic microphones are
not supported.
b
Switched 13.8V supply. Supply is
switched off when radio body is
switched off.
a
a
Digital, 3V3 CMOS
Digital, 3V3 CMOS
Digital, 3V3 CMOS
Digital, 3V3 CMOS
input; open collector
output with pullup
When installing an internal options board, the internal options connector is
the electrical interface to the main board of the radio body.
The internal options connector provides similar I/O to the auxiliary
connector. The internal options connector is an 18-pin 0.1 inch pitch
Micro-MaTch connector.
ImportantThe digital I/O signals are intended to interface directly
with compatible logic signals only. Do not connect these
signals to external devices without appropriate signal conditioning and ESD protection.
Table 2.4Internal options connector – pins and signals
PinoutPinSignalDescriptionSignal type
113V8_SW
B
C
D
E
F
G
H
I
J
1)
1!
1@
1#
1$
1%
1^
1&
1*
top view
a. Can be switched or unswitched. For more information refer to “Connector Power Supply Options” on page 86.
b. For more information on hardware links refer to“Power-Sense Options” on page 83.
2AUD_TAP_OUT Programmable tap point out of the Rx or
6AUD_TAP_INProgrammable tap point into the Rx or Tx
7RX_AUDReceive audio output. Post volume
8RSSIAnalog RSSI output.Analog
9…15 IOP_GPIO1…7General-purpose port for input and
16DGNDDigital ground.Ground
17IOP_RXDAsynchronous serial port - Receive data.Digital.
18IOP_TXDAsynchronous serial port - Transmit data. Digital.
a
Switched 13V8 supply. Supply is switched
off when the Radio Body is switched off.
Tx audio chain. DC-coupled.
Electret microphone biasing provided.
Dynamic microphones are not supported.
audio chain. DC-coupled.
control. AC-coupled.
output of data. Programmable function
and direction. With LK4 fitted, GPIO7 is a
power sense input
b
.
Power
Analog
Analog
Analog
Analog
Digital.
3V3 CMOS
3V3 CMOS
3V3 CMOS
2.3.5Provision for External Options Connector
The radio has a mechanical interface for the external connector of an
internal options board. This external options connector can be a 9-way
standard-density or 15-way high-density D-range connector. If no internal
options board is installed (standard configuration), the hole for the external
options connector is sealed by a bung.
The microphone connector of the control head is an RJ45 socket.
When the control head is connected to the control-head connector of the
radio body using the loom provided, the microphone connector uses the
following eight control-head connector signals:
Table 2.6Microphone connector – pins and signals
PinoutPinSignal nameDescriptionSignal type
1MIC_RX_AUD Receive audio output.Analog
B
I
front view
a. Can be switched or unswitched. For more information refer to “Connector Power Supply Options” on page 86.
2+13V8
3MIC_TXDAsynchronous serial port -
4MIC_PTTPTT input from microphone. Also carries
5MIC_AUDFist microphone audio input.Analog
6AGNDAnalog ground.Analog ground
7MIC_RXDAsynchronous serial port - Receive data. 3.3 V CMOS
8MIC_GPIO1General purpose digital input/output.Open collector out
a
Power supply output. Switched off
when radio body is switched off.
Tran sm it d at a.
hookswitch signal.
Power
3.3V CMOS
Digital
3.3V CMOS in
2.3.8Programming Connector (RJ45 Control Head)
The programming connector of the RJ45 control head is an RJ45 socket.
When the RJ45 control head is connected to the radio body, the
programming connector uses the following signals.
Table 2.7Programming connector – pins and signals
PinoutPinSignal nameDescriptionSignal type
1PRG_RX_AUDReceive audio output.Analog
2+13V8
3PRG_TXDAsynchronous serial port -
I
B
front view
a. Can be switched or unswitched. For more information refer to “Connector Power Supply Options” on page 86.
4PRG_PTTPTT input from microphone.
5PRG_MIC_AUDFist microphone audio input.Analog
6AGNDAnalog groundGround
7PRG_RXDAsynchronous serial port -
8PRG_ON_OFFHardware power on/software-power
a
Power supply output. Switched off
when radio body is switched off.
OverviewThis section describes the hardware and software modules of the radio and
their interaction in the functioning of the radio.
2.4.1Hardware Architecture
The electrical hardware of the radio is implemented on a main board inside
the radio body and a control-head board inside the control head.
For a detailed description and block diagrams of individual circuits, refer to
“Circuit Descriptions” on page 19.
Main BoardThe main board inside the radio body includes the following circuitry:
■ transmitter
■ receiver
■ frequency synthesizer
■ digital board with a RISC processor and custom logic (implemented on
an FPGA), memory, and a DSP
■ CODEC and audio
■ interface
■ power supply.
The main board has an internal options connector which allows internal
options boards to access a variety of discrete and programmable signals.
For more information refer to “Internal Options Connector” on page 41.
For a basic block diagram of the main board, refer to Figure 2.14 on
page 46.
For a more detailed block diagram of the transceiver, refer to Figure 2.16 on
page 51.
Control-Head BoardThe control-head board of the control head with graphical display includes:
■ the circuitry needed for the controls and indicators on the front panel
■ with a RISC processor and custom logic (implemented on an FPGA),
and memory.
For a block diagram of this control-head board, refer to Figure 3.14 on
page 93.
The control head with graphical display may have a concealed microphone
inside the control head and also has provision for a separate circuit board that
may be designed to perform a variety of tasks including—but not limited
to—Bluetooth connectivity. No separate circuit board is required for a
dynamic microphone.
OverviewSoftware plays an important role in the functioning of the radio. Some radio
functions such as the graphical user interface, processing of the analog and
digital signals, and the implementation of radio applications are completely
implemented by software.
For a block diagram of the software architecture, refer to Figure 2.15 on
page 48.
Software ModulesThe following software modules are stored on the digital board of the main
board:
■ FPGA image, which includes the software-implemented RISC processor
and the custom logic (the custom logic executes additional digital signal
processing)
■ boot code
■ radio application code
■ digital signal processing
■ radio application database and radio calibration database.
The following software modules are stored on the control-head board with
graphical display:
■ FPGA image, which includes the software-implemented RISC processor
■ boot code
■ control-head application code
■ control-head application database.
Hardware and interface drivers are part of the boot code, the RISC code,
and—in the case of the main board—the DSP code.
Figure 2.15Software architecture (radio with graphical-display control head shown)
Serial
Flash
FPGA Image
RISC Proc.
FPGA Image
FPGA
Flash
Memory
Boot Code
Application Code
Boot Code
Control-Head Application Code
Database
FPGA
FPGA Image
RISC Processor
Boot Code
Radio Application
Code
Custom Logic
Additional Digital
Signal Processing
Serial Flash
FPGA Image
Flash Memory
Boot Code
Radio Application Code
Database
DSP Code
DSP
DSP Code
SRAM
Dynamic Memory
Dynamic
Memory
SRAM
Software Start-Up
When the radio is turned on, the following processes are carried out on the
main board:
NoteThis process describes the software start-up into normal radio
operation mode.
1.The FPGA image, which includes the RISC processor and the custom logic, is loaded from the serial flash to the FPGA.
2.The RISC processor executes the boot code, which carries out an
initialization and auto-calibration, and—in the case of a fault—
generates an error code for display on the control head.
3.Normal radio operation starts with:
■ the RISC processor executing the radio application code,
including application software
■ the DSP executing the DSP code for processing of digital signals
■ the custom logic executing additional digital signal processing.
When the radio is turned on, the following processes are carried out on the
control-head board of the control head with graphical display:
1.The FPGA image, which includes the RISC processor, is loaded from
the serial flash to the FPGA.
2.The RISC processor executes the boot code, which carries out an
initialization, and—in the case of a fault—generates an error code for
display on the control head.
3.Normal radio operation starts with the RISC processor executing
■ the graphical user interface
■ the I/O processing
■ the user interface processing.
During normal radio operation the radio body and control head
communicate via interface software, which is part of the radio and controlhead application software.
Software ShutdownOn shutdown, the programming and calibration data is stored in the
database, and power is removed from the radio.
ImportantOn power loss, any changes made to the programming or
calibration data may be lost.
Programming and
Calibration Files
One of the servicing tasks is the downloading and uploading of
programming and calibration files to the database. For more information,
refer to “Servicing Procedures” on page 149 and the online help of the
programming and calibration applications.
Software UpgradesDuring servicing it may become necessary to upload software to a
replacement main board, control head, or control head board using the
Tools>Options> Download command of the programming application.
For more information, refer to the online help of the programming
application and to the technical notes accompanying the software files.
PIN SwitchThe RF PIN switch circuitry selects the RF path to and from the antenna
to either the Tx or Rx circuitry of the radio. In addition to the switching
functionality, the PIN switch is used to provide attenuation to the Rx front
end in high signal-strength locations.
Front End and
First IF
Quadrature
Demodulator
Automatic Gain
Control
The front-end hardware amplifies and image-filters the received RF
spectrum, then down-converts the desired channel frequency to a first
intermediate frequency (IF1) of 21.4MHz (VHF) or 45.1 MHz (UHF)
where coarse channel filtering is performed. The first LO signal is obtained
from the frequency synthesizer and is injected on the low side of the desired
channel frequency for all bands. In receive mode, the modulation to the
frequency synthesizer is muted. See “Frequency Synthesizer” on page 57 for
a description of the frequency synthesizer. The output of the first IF is then
down-converted using an image-reject mixer to a low IF of 64kHz.
The LO for the image-reject mixer (quadrature demodulator) is synthesized
and uses the TCXO as a reference. This ensures good centring of the IF
filters and more consistent group-delay performance. The quadrature
demodulator device has an internal frequency division of 2 so the second
LO operates at 2 x (IF1+64kHz). The quadrature output from this mixer is
fed to a pair of ADCs with high dynamic range where it is oversampled at
256kHz and fed to the custom logic device.
The AGC is used to limit the maximum signal level applied to the imagereject mixer and ADCs in order to meet the requirements for
intermodulation and selectivity performance. Hardware gain control is
performed by a variable gain amplifier within the quadrature demodulator
device driven by a 10-bit DAC. Information about the signal level is
obtained from the IQ data output stream from the ADCs. The control loop
is completed within the custom logic. The AGC will begin to reduce gain
when the combined signal power of the wanted signal and first adjacent
channels is greater than about -70dBm. In the presence of a strong adjacentchannel signal it is therefore possible that the AGC may start acting when
the wanted signal is well below -70dBm.
Noise Blanking
(A4, B1 bands only)
With frequency bands between 66 and 174MHz, a noise blanker can be
selected to remove common sources of electrical interference such as vehicle
ignition noise. The noise blanker functions by sampling the RF input to the
receiver for impulse noise and momentarily disconnecting the first LO for
the duration of the impulse. The response time of the noise blanker is very
fast (tens of nanoseconds) and is quicker than the time taken for the RF
signal to pass through the front-end hardware, so that the LO is disabled
before the impulse reaches the IF stage where it could cause crystal
filter ring.
Custom LogicThe remainder of the receiver processing up to demodulation is performed
by custom logic. The digitized quadrature signal from the RF hardware is
digitally down-converted to a zero IF and channel filtering is performed at
baseband. Different filter shapes are possible to accommodate the various
channel spacings and data requirements. These filters provide the bulk of
adjacent channel selectivity for narrow-band operation. The filters have
linear phase response so that good group-delay performance for data is
achieved. The filters also decimate the sample rate down to 48kHz.
Custom logic also performs demodulation, which is multiplexed along with
AGC and amplitude data and fed via a single synchronous serial port to the
DSP. The stream is demultiplexed and the demodulation data used as an
input for further audio processing.
Noise SquelchThe noise squelch process resides in the DSP. The noise content above and
adjacent to the voice band is measured and compared with a preset
threshold. When a wanted signal is present, out-of-band noise content is
reduced and, if below the preset threshold, is indicated as a valid wanted
signal.
RSSIReceive signal strength is measured by a process resident in the DSP.
This process obtains its input from the demodulator (RF signal magnitude
value) and from the AGC (present gain value). With these two inputs and a
calibration factor, the RF signal strength at the antenna can be accurately
calculated.
CalibrationThe following items within the receiver path are factory-calibrated:
■ front-end tuning
■ AGC
■ noise squelch
■ RSSI.
Information on the calibration of these items is given in the on-line help
facility of the calibration application.
Audio ProcessingRaw demodulated data from the receiver is processed within the DSP.
The sample rate at this point is 48kHz with signal bandwidth limited only
by the IF filtering. Scaling (dependent on the bandwidth of the RF channel)
is then applied to normalize the signal level for the remaining audio
processing. The sample rate is decimated to 8 kHz and 0.3 to 3kHz bandpass
audio filtering is applied. De-emphasis is then applied to cancel out the
receive signals pre-emphasized response and improve signal to noise
performance. Optional processing such as decryption or companding is then
applied if applicable.
Data and Signalling
Decoders
The data and signalling decoders obtain their signals from various points
within the audio processing chain. The point used depends on the decoders’
bandwidth and whether de-emphasis is required. Several decoders may be
active simultaneously.
Side TonesSide tones are summed in at the end of the audio processing chain. These are
tones that provide some form of alert or give the user confidence an action
has been performed. The confidence tones may be generated in receive or
transmit mode. The sidetone level is a fixed proportion (in the order of
-10dB) relative to full scale in the receive path.
CODECThe combined audio and side-tone signal is converted to analog form by a
16-bit DAC with integral anti-alias filtering. This is followed by a
programmable-gain amplifier with 45dB range in 1.5 dB steps, that performs
primary volume control and muting. The DAC and primary volume control
are part of the same CODEC device (AD6521).
Output to SpeakersThe output of the CODEC is fed to an audio power amplifier via a
secondary volume control (not TM8100 radios) and to the control head via
a buffer amplifier. The output configuration of the audio power amplifier is
balanced and drives an internal speaker in non-remote control-head
configuration and, optionally, an external speaker. The speaker loads are
connected in parallel rather than being switched. The power delivered to
each speaker is limited by its impedance. The internal speaker has 16Ω
impedance whereas the external speaker can be as low as 4Ω.
Volume Control
Configurations
There are two volume controls in the TM8200 radio but only one is active
at any time when audio is being output to the speaker(s). The inactive
volume control is set to maximum. For non-remote control-head
configuration, the primary volume control is active. For remote controlhead configuration, the secondary volume control is active. This enables
fixed level audio feed to the remote control head, and independent volume
control of the external speaker and the speaker of the remote control head.
Microphone InputThe input to the transmitter path begins at the microphone input. There are
two microphone sources: a fist microphone connected to the control head
and an auxiliary microphone connected via the auxiliary or external options
connector. Only electret-type microphones are supported. Support for
optional dynamic fist microphones is facilitated by a hardware amplifier and
filter in the control head, and must be activated in the programming
software.
Analog Processing
of the Microphone
Input
Automatic Level
Control
DSP Audio
Processing
The CODEC (AD6521) performs microphone selection and amplification.
The microphone amplifier consists of a fixed gain amplifier of 16dB
followed by a programmable-gain amplifier with 0 to 22dB gain.
The amplified microphone signal is converted to a digital stream by a 16-bit
ADC with integral anti-alias filtering (0.1 to 3.2 kHz). The digital stream is
transported to the DSP for further audio processing.
The ALC follows and is used to effectively increase dynamic range by
boosting the gain of the microphone pre-amplifier under quiet conditions
and reducing the gain under noisy acoustic conditions. The ALC function
resides in the DSP and controls the microphone-programmable gain
amplifier in the CODEC. The ALC has a fast-attack (about 10ms) and
slow-decay (up to 2 s) gain characteristic. This characteristic ensures that the
peak signal level is regulated near full scale to maximize dynamic range.
The output of the automatic level control provides the input to the DSP
audio processing chain at a sample rate of 8kHz. Optional processing such
as encryption or companding is done first if applicable. Pre-emphasis, if
required, is then applied. The pre-emphasized signal is hard limited to
prevent overdeviation and filtered to remove high frequency components.
The sample rate is then interpolated up to 48 kHz and scaled to be suitable
for the frequency synthesizer.
Data and Signalling
Encoders
The data and signalling encoders inject their signals into various points
within the audio processing chain. The injection point depends on the
encoders bandwidth and whether pre-emphasis is required.
The FCL provides the reference frequency for the RF PLL. The FCL
generates a high-stability reference frequency that can be both modulated
and offset in fine resolution steps.
RF PLL■ The RF PLL consists of the following:
■ RF PLL device
■ loop filter
■ VCO
■ VCO output switch.
The RF PLL has fast-locking capability but coarse frequency resolution.
This combination of control loops creates improved frequency generation
and acquisition capabilities.
Note that patents are pending for several aspects of the synthesizer design.
Operation of
Control Loop
The RF PLL is a conventional integer-N-type design with frequency
resolution of 25kHz. In transmit mode, the loop locks to the transmit
frequency, whereas in receive mode, it locks to the receive frequency minus
the first IF frequency.
Initially, the VCO generates an unregulated frequency in the required range.
This is fed to the PLL device (ADF4111) and divided down by a
programmed ratio to approximately 25 kHz. The reference frequency input
from the FCL is also divided down to approximately 25kHz. The phase of
the two signals is compared and the error translated into a DC voltage by a
programmable charge pump and dual-bandwidth loop filter. This DC signal
is used to control the VCO frequency and reduce the initial error. The loop
eventually settles to a point that minimizes the phase error between divided
down reference and VCO frequencies. The net result is that the loop
“locks” to a programmed multiple of the reference frequency.
The FCL generates an output of 13.012 MHz±4kHz. Initially, a VCXO
(voltage controlled crystal oscillator) produces a quasi-regulated frequency in
the required range. The VCXO output is fed to a mixer where it is mixed
with the 13.000MHz TCXO frequency. The mixer, after low-pass filtering
to remove unwanted products, produces a frequency of 12kHz nominally.
This is converted to digital form and transported to the frequency control
block in the custom logic.
The frequency control block compares the mixer output frequency to a
reference generated by the digital clock and creates a DC error signal.
A programmed offset is also added. This error signal is converted to analog
form and used to control the VCXO frequency and reduce the initial error.
Once settled, the loop “locks” to the TCXO frequency with a programmed
offset frequency. The FCL output therefore acquires the TCXO's
frequency stability.
ModulationThe full bandwidth modulation signal is obtained from the DSP in digital
form at a sample rate of 48kHz. In traditional dual-point modulation
systems the modulation is applied, in analog form, to both the frequency
reference and the VCO in the RF PLL, combining to produce a flat
modulation response down to DC. Reference modulation is usually applied
directly to the TCXO.
Frequency
Generation
Fast Frequency
Settling
In the system employed in the radio, the frequency reference is generated by
the FCL, which itself requires dual-point modulation injection to allow
modulation down to DC. With another modulation point required in the
RF PLL, this system therefore requires triple-point modulation.
The modulation signals applied to the FCL are in digital form while for the
RF PLL (VCO) the modulation signal is applied in analog form.
The modulation cross-over points occur at approximately 30 and 300Hz as
determined by the closed loop bandwidths of the FCL and RF PLL
respectively.
The RF PLL has a frequency resolution of 25kHz. Higher resolution
cannot be achieved owing to acquisition-time requirements and so for any
given frequency the error could be as high as ±12.5kHz. This error is
corrected by altering the reference frequency to the RF PLL. The FCL
supplies the reference frequency and is able to adjust it up to ± 300 ppm with
better than 0.1ppm resolution (equivalent to better than 50 Hz resolution at
the RF frequency). The FCL offset will usually be different for receive and
transmit modes.
Both the FCL and RF PLL employ frequency-acquisition speed-up
techniques to achieve fast frequency settling. The frequency-acquisition
process of the FCL and RF PLL is able to occur concurrently with minimal
loop interaction owing to the very large difference in frequency step size
between the loops.
In the RF PLL the loop bandwidth is initially set to high by increasing the
charge-pump current and reducing time constants in the loop filter.
As a result, settling to within 1kHz of the final value occurs in under 4 ms.
In order to meet noise performance requirements the loop parameters are
then switched to reduce the loop bandwidth. There is a small frequency kick
as the loop bandwidth is reduced. Total settling time is under 4.5ms.
Frequency
Acquisition of FCL
The FCL utilizes self-calibration techniques that enable it to rapidly settle
close to the final value while the loop is open. The loop is then closed and
settling to the final value occurs with an associated reduction in noise.
The total settling time is typically less than 4ms.
CalibrationThe following items are calibrated in the frequency synthesizer:
■ nominal frequency
■ KVCO
■ KVCXO
■ VCO deviation.
Calibration of the nominal frequency is achieved by adding a fixed offset to
the FCL nominal frequency; the TCXO frequency itself is not adjusted.
The items KVCO and KVCXO are the control sensitivities of the RF VCO
(in MHz/V) and VCXO (in kHz/V) respectively. The latter has
temperature compensation.
2.6.3RF Transmitter
RF Power Amplifier
and Switching
(50W/40W Radio)
The RF power amplifier and exciter of the 40W/50 W radio is a five-stage
line-up with approximately 40dB of power gain. The output of the
frequency synthesizer is first buffered to reduce kick during power ramping.
The buffer output goes to a discrete exciter that produces approximately 300
to 400mW output. This is followed by an LDMOS driver producing up to
8W output that is power-controlled. The final stage consists of two parallel
LDMOS devices producing enough power to provide 40 to 50W at
the antenna.
RF Power Amplifier
and Switching
(25W Radio)
The RF power amplifier of the 25W radio is a four-stage line-up with
approximately 37dB of power gain. The output of the frequency synthesizer
is first buffered to reduce kick during power ramping. The buffer output
goes to a broad-band exciter IC that produces approximately 200mW
output. This is followed by an LDMOS driver producing up to 2W output
that is power-controlled. The final stage consists of two parallel LDMOS
devices producing enough power to provide 25W at the antenna.
Output of RF Power
Amplifier
The output of the RF power amplifier passes through a dual-directional
coupler, used for power control and monitoring, to the PIN switch.
The PIN switch toggles the antenna path between the receiver and
transmitter in receive and transmit modes respectively. Finally, the output is
low-pass-filtered to bring harmonic levels within specification.
Power ControlThe steady-state power output of the transmitter is regulated using a
hardware control loop. With the 40 W/50 W radio, the sum of the forward
power output from the RF power amplifier and reverse power reflected from
the load is sensed by the directional coupler and fed back to the power
control loop. With the 25W radio, the forward power output from the RF
power amplifier is sensed by the directional coupler and fed back to the
power control loop. The PA output power is controlled by varying driver
gate bias voltage that has a calibrated maximum limit to prevent overdrive.
The power control signal is supplied by a 13-bit DAC driven by
custom logic.
RampingPower ramp-up consists of two stages:
■ bias
■ power ramping.
The timing between these two stages is critical to achieving the correct
overall wave shape in order to meet the specification for transient ACP
(adjacent channel power). A typical ramping waveform is shown in
Figure 2.17.
Figure 2.17Typical ramping waveforms
Power
Power
Bias
Power
ramp
ramp
High power
powerLow
Bias Ramp-UpThe steady-state final-stage bias level is supplied by an 8-bit DAC
ramp
Bias
ramp
Time
programmed prior to ramp-up but held to zero by a switch on the DAC
output under the control of a
release by the
TXINHIBIT signal with the ramping shape being determined by
TXINHIBIT signal. Bias ramp-up begins upon
a low-pass filter. Owing to power leakage through the PA chain, ramping
the bias takes the PA output power from less than –20dBm for the
40W/50W or –10dBm for the 25 W radio to approximately 25dB below
steady-state power.
Power Ramp-UpThe power ramp signal is supplied by a 13-bit DAC that is controlled by
custom logic. The ramp is generated using a look-up table in custom logic
memory that is played back at the correct rate to the DAC to produce the
desired waveform. The ramp-up and ramp-down waveforms are produced
by playing back the look-up table in forward and reverse order respectively.
For a given power level the look-up table values are scaled by a steady-state
power constant so that the ramp waveform shape remains the same for all
power levels.
PIN SwitchThe RF PIN switch circuitry selects the RF path to and from the antenna
to either the Tx or Rx circuitry of the radio. In addition to the switching
functionality, the PIN switch is used to provide attenuation to the Rx front
end in high signal-strength locations.
IntroductionFor a block diagram of the transmitter circuitry, refer to Figure 3.2.
The transmitter circuitry is different for the 40W/50W radios and the 25 W
radios, and the different bands.
ExciterWith the 40 W/50 W radio, the discrete-component exciter is designed for
specific bands (UHF or VHF). It is made up of Q3501, Q3502, and Q3505,
which amplify the signal provided by the frequency synthesizer from its level
of 7 to 10dBm up to 24dBm for the frequency bands 136 to 174MHz and
400 to 520MHz.
With the 25W radio, the broadband exciter is a common element in all the
bands, as it operates across all frequencies from 66 to 530MHz. It is made
up of Q300 and Q303, which amplify the signal provided by the frequency
synthesizer from its level of 7 to 10dBm up to 24.5dBm for the frequency
band from 66 to 530MHz.
The exciter operates in full saturation, thereby maintaining a constant
output power independent of the varying input power level supplied by the
synthesizer.
Power AmplifierThe power amplifier comprises the driver amplifier Q306 and two paralleled
final devices Q309 and Q310.
With the 40W/50W radio, the signal from the exciter is amplified by Q306
to a power level of approximately 2W (VHF) using a PD55003 and about
3W (UHF) using a PD55008. The resulting signal is then amplified by
Q309 and Q310 to produce a typical output power of 90W at 155 MHz and
65W across the UHF band, when measured after the series capacitors
(C348, C349, C350) at the start of the directional coupler.
With the 25W radio, the 24.5dBm signal from the exciter is reduced by a
band-dependent pi-attenuator and is amplified by Q306. The resulting
signal is then amplified a second time by Q309 and Q310 to produce a
typical output power of 40W when measured after the series capacitors
(C348, C349, C350) at the start of the directional coupler.
The high-level RF signal passes via the directional coupler, the transmitreceive PIN switch, and the LPF, through to the antenna. The LPF is used
to attenuate unwanted harmonic frequencies.
Power Control LoopCalibration is used to adjust the power control loop, thus setting the output
of the transmitter to one of four preferred power levels:
■ 10, 15, 25, and 50 watts (VHF), and
10, 15, 20, and 40 watts (UHF) for 40W/50W radios
■ 1, 5, 12 and 25 watts (all bands) for 25W radios.
The loop maintains these power settings under changing environmental
conditions. The control mechanism for this loop is via the DAC IC204 and
one of the operational amplifiers making up IC301. The power control loop
will be inhibited if for any reason an out-of-lock signal is detected from the
synthesizer. This ensures that no erroneous signals are transmitted at
any time.
With the 40W/50W radio, the power control loop processes the voltages
from the forward and reverse power sensors in the directional coupler.
This signal is fed to the buffer and a band-limited operational amplifier back
to the gate of Q306. In this way, the transmitter is protected against bad
mismatches.
With the 25W radio, the power control loop senses the forward power by
means of the diode D304. This signal is fed to the buffer and a band-limited
operational amplifier back to the gate of Q306.
A voltage clamp (one of the operational amplifiers of IC301) for Q306 limits
the maximum control-loop voltage applied to its gate.
Directional
Coupler
With the 40W/50W radio, the directional coupler actively senses the
forward power and the reverse power, and feeds them back to the powercontrol circuit.
With the 25W radio, the directional coupler actively senses the forward
power and feeds it back to the power-control circuit. If the directional
coupler detects too much reverse power, indicating a badly matched
antenna, the transmitter will be reduced to the lowest power setting.
Temperature SensorFor added protection, a temperature sensor ensures that the transmitter
power is reduced to very low levels should a temperature threshold be
exceeded. If the temperature does not decrease, the transmitter is
switched off.
IntroductionFor a block diagram of the receiver circuitry, refer to Figure 3.3 (B1, H5,
H6 bands, 05 issue PCBs) and Figure 3.4 (other bands and later issue PCBs).
The receiver is of the triple-conversion superheterodyne type. The first two
IF stages are implemented in hardware; the third stage is implemented in the
FPGA (Field-Programmable Gate Array) of the digital board. The FPGA
also carries out the demodulation of the received signals.
Front-End CircuitryThe front-end circuitry is a standard varicap-tuned singlet (band-pass filter),
followed by an LNA (low-noise amplifier), and then a varicap-tuned
doublet (image filter). The varicap tuning voltage
by a DAC, with voltages calculated from a calibration table stored in nonvolatile memory. The two varicap-tuned filters need to be calibrated to
ensure that maximum sensitivity is achieved.
First MixerThe first mixer is a standard diode-ring mixer with SMD (surface-mount
device) baluns and a quadruple SMD diode. For the bands between 66 and
174MHz, the receiver includes a circuit for suppressing ignition noise.
This circuit momentarily removes the LO signal from the mixer when an
ignition noise pulse is detected. The ignition-noise suppressor is selectable
on a per-channel basis when the radio is programmed.
CDCRXFE TUNE is provided
First IF Stage and
Second Mixer
The first IF stage consists of a crystal channel filter (BPF1), followed by an
IF amplifier, and then another crystal filter (BPF2). The second mixer is an
IC quadrature mixer with an internal AGC amplifier. This IC has a divideby-two function on the LO input in order to provide the quadrature LO
frequencies required internally. The second LO frequency is synthesized by
an integer PLL (IC403), which uses the TCXO frequency
SYNRXOSC
(13.0000 MHz) as its reference.
Frequencies
of IF Stages
The frequency of the first IF stage depends as follows on the frequency band
of the radio:
■ VHF bands: 21.400029MHz
■ UHF bands: 45.100134MHz.
The above are nominal values; the actual frequency will differ by a small
amount depending on the exact initial frequency of the TCXO.
The frequency of the second IF stage will always be precisely 64.000kHz
once the TCXO calibration has been completed. (The TCXO calibration
does not adjust the TCXO frequency, but instead adjusts the VCXO
frequency, which in turn adjusts the VCO or first LO frequency as well as
the frequency of the first IF stage. The second LO frequency remains fixed.)
The third IF stage is completely within the FPGA and is not accessible.
DemodulationDemodulation takes place within the FPGA. Demodulated audio is passed
to the DSP of the digital board for processing of the receiver audio signal.
Raw demodulated audio can be tapped out from the DSP for use with an
external modem. The modem may be connected to the auxiliary connector
or to the external options connector when an internal options board
is fitted.
68Circuit DescriptionsTM8100/TM8200 Service Manual
The receiver has an AGC circuit to enable it to cover a large signal range.
Most of the circuit functions are implemented in the FPGA. The FPGA
passes the AGC signal to the CODEC IC204 for output from pin 14
(
IDACOUT) and then via IC201 as the signal CDCRXAGC to pin 23 of the
quadrature mixer IC400. As the antenna signal increases, the AGC voltage
decreases.
Channel FilteringThe channel filtering is split between the first and third IF stages.
The channel filtering circuit in the first IF stage comprises a pair of two-pole
crystal filters. The first filter has a 3dB bandwidth of 12kHz, and the second
a 3dB bandwidth of 15kHz. Most of the channel filtering, however, is
implemented in the FPGA. When the radio is programmed, the different
filters are selected as assigned by the channel programming. The selectable
filters plus the fixed crystal filters result in the following total IF 3dB
bandwidths:
■ wide channel spacing: 12.6 kHz
■ medium channel spacing: 12.0kHz
■ narrow channel spacing : 7.8 kHz.
(The FPGA runs from the
DIGSYSCLK signal, which has a frequency of
12.288MHz.) The receiver requires the TCXO calibration to be completed
to ensure that the channel filtering is centred, thereby minimizing
distortion.
Received Signal
Strength Indication
Front-End AGC
Control
Noise Blanker (A4,
B1 bands only)
The RSSI is calculated in the FPGA and DSP, and can be passed as an analog
voltage to the internal options interface and the external auxiliary interface.
To obtain an accurate estimate of the RSSI (over the signal level and
frequency), it is necessary to calibrate the AGC characteristic of the receiver
and the front-end gain versus the receive frequency.
The receiver has a front-end AGC circuit to enable it to handle large
receiver signals with minimal receiver distortion. This is very important for
the correct operation of the THSD modem (Tait High-Speed Data). It
enables THSD to maintain residual BER of < 10
-4
. The front-end AGC is
controlled by an algorithm which monitors the RSSI and configures the
DAC to turn on the front-end attenuation via the receive pin diode of the
PIN switch.
If the frequency band is between 66 and 174MHz, a noise blanker can be
selected to remove common sources of electrical interference such as vehicle
ignition noise. The noise blanker functions by sampling the RF input to the
receiver for impulse noise and momentarily disconnecting the first LO for
the duration of the impulse. The response time of the noise blanker is very
fast (tens of nanoseconds) and is quicker than the time taken for the RF
signal to pass through the front-end hardware, so that the LO is disabled
before the impulse reaches the IF stage where it could cause crystal
filter ring.
IntroductionFor a block diagram of the frequency synthesizer circuitry, refer to
Figure 3.5 and Figure 3.6 (FCL for the A4 band).
The frequency synthesizer includes an active loop filter, one or two VCOs
and buffer amplifiers, and a PLL IC. The last-named uses conventional
integer-N frequency division and includes a built-in charge pump. Speedup techniques ensure a transmit-receive settling time of less than 4.5ms
while retaining low noise characteristics in static operation.
Power SuppliesSeveral power supplies are used by the frequency synthesizer owing to a
combination of performance requirements and the availability of suitable
components. The PLL IC includes analog and digital circuitry and uses
separate power supplies for each section. The digital section is run on 3V,
while the analog section is run on approximately 5V. The VCOs and buffer
amplifiers run off a supply of about 5.3V. The active loop filter requires a
supply of 14 to 15V, and a reference voltage of approximately 2.5V.
Performance
Requirements
Effect of Tuning
Range
Switch-mode Power
Supply
Low noise and good regulation of the power supply are essential to the
performance of the synthesizer. A 6V regulator IC provides good line
regulation of the 9V supply and good load regulation. Good regulation of
the power-supply line and load is essential for meeting the transient ACP
requirements. The regulator output voltage is electrically noisy, however,
and filtering is essential. Filtering of the power supply is achieved with two
capacitance multipliers (Q508 and C585 for the VCO supply, and Q512 and
C579 for the PLL and loop-filter supply). The VCO (or VCOs) use a
separate capacitance multiplier because these multipliers have poor load
regulation and the VCOs impart sufficient load transients to warrant a
separate supply.
For reasons of noise performance, the VCOs are designed to be tuned
within a range of 2 to 12V. Active tuning circuitry is required. An active
loop filter incorporating an IC operational amplifier achieves this range with
a suitable power supply voltage. Normal synthesizer switching behaviour
involves overshoot, which dictates that the tuning voltage range must extend
above and below the range of 2 to 12V. The 14V limit is a result of limits
on the working supply voltage of the IC operational amplifier.
The power supply VCLSUPPLY for the active loop filter is provided by a
SMPS, which is in turn powered by 9V. The SMPS consists of an oscillator
(switching circuit) and a detector. The output voltage is monitored by a
feedback circuit that controls the DC bias of the switching circuit to
maintain a constant output voltage.
Synthesizer
Circuitry
The essential function of the PLL frequency synthesizer is to multiply a
25kHz reference frequency (30kHz for A4 band) to give any desired
frequency that is an integer multiple of 25 kHz (30 kHz for A4 band). There
are some constraints imposed by the capabilities of the synthesizer hardware,
especially the tuning range of the VCOs.
72Circuit DescriptionsTM8100/TM8200 Service Manual
Figure 3.6Block diagram of the frequency control loop circuitry—A4 band
÷4
÷ 4
Buffer
Buffer
Amplifier
Amplifier
÷4
÷ 4
FCL
FCL
Reference
Frequency
The approximately 25kHz (30kHz for A4) reference is obtained by dividing
the approximately 13MHz (2.612 kHz for A4) output of the FCL. Any error
in the FCL output frequency will be multiplied by the synthesizer.
Therefore, if the synthesizer is locked but not the FCL, then the synthesizer
output frequency will be wrong. The FCL frequency division is performed
by a digital counter inside the PLL IC. The divider setting is constant.
VCO Frequency and
Output Power
The output frequency from the synthesizer is generated by a VCO.
The VCO frequency is tuned across the frequency range of the radio by
means of a DC control voltage, typically between 2V and 12V. The VCO
output power is amplified by a buffer amplifier. The power is low and varies
from band to band. The buffer output power depends on which mode—
receive or transmit—is used. In receive mode the output power should be
about 7dBm, whereas in transmit mode it should be about 9 dBm.
Dual VCOsSome variants of the synthesizer use two VCOs: one for receive and one for
transmit. Synthesizers with two VCOs share the same tuning signal.
Only one VCO is switched on at a time, and so the PLL IC will see only
one output frequency to tune. A portion of the RF output from the VCOs
is fed to the RF input of the PLL IC. The RF signal is divided by an integer
that gives 25kHz (30kHz for A4) if the output frequency is correct.
Phase-locked LoopThe PLL IC compares the 25kHz reference (30kHz for A4) and the divided
VCO signal, and the error is used to control the internal charge pump.
The charge pump is a current source that can sink or source current in
proportion to the frequency or phase error. The output is a series of 25kHz
pulses (30kHz for A4) with a width that is dependent on the phase error.
When the output frequency of the synthesizer is correct, there is no error
and the charge pump output will become open circuit.
74Circuit DescriptionsTM8100/TM8200 Service Manual
Active Loop FilterThe loop filter continuously integrates the current pulses from the charge
pump and produces a steady DC output voltage that tunes the VCO
(or VCOs). When the VCO frequency is correct, there is no frequency
error and therefore no charge-pump output, and so the loop filter’s output
voltage remains constant. If the frequency is too high or too low, the error
will result in the output of charge-pump current pulses (negative or positive
depending on the sign of the error). The loop filter’s output voltage will
change accordingly, causing the VCO frequency to change in proportion.
The synthesizer design is such that normally the VCO frequency will be
automatically corrected.
Re-tuning of VCO
Frequency
Speed-up
Te ch n iq ue s
When the radio changes channels or switches between receive and transmit,
the VCO frequency must be changed. The rate at which the VCO is retuned is dependent on many factors, of which the loop filter is the main
factor. The loop filter is an integrator built around an operational amplifier.
The resistors and capacitors of the filter affect both the switching time and
the stability of the synthesizer; the values of these components have been
carefully selected to give optimum control characteristics.
To reduce the change-over time between transmit and receive, part-time
speed-up techniques have been implemented. Speed-up involves changing
some resistor values while simultaneously changing the PLL IC settings.
This process is implemented in hardware under software control in
conjunction with use of the synthesized reference input. The result is a
transmit-receive settling time of less than 4.5ms. (The switching time is
measured for a frequency change equal to the first IF plus 10MHz or 1MHz,
depending on the repeater offsets used for the band. This implies a
synthesizer transmit-receive change-over plus an offset of 1MHz or 10 MHz
in less than 4.5ms. The ramp-up and ramp-down of the transmitter, which
totals 1ms, extends this change-over time to 5.5ms.)
IntroductionThe FCL is included in the block diagram of the frequency synthesizer
(see Figure 3.5 and Figure 3.6).
The FCL forms part of the frequency-synthesizer module. The basis of the
FCL is a VCXO, which generates the reference frequency required by the
main PLL of the synthesizer.
Elements of
FCL Circuitry
The FCL is a simple frequency-locked loop. The circuitry consists of the
following elements:
■ VCXO (XL501, Q501, Q503)
■ TCXO (XL500)
■ buffer amplifier (IC500)
■ mixer (IC501)
■ low-pass filter (IC502, pins 5 to 7)
■ modulator buffer amplifier (IC502, pins 1 to 3).
The A4 band has additional circuitry:
■ 2.612MHz mixer (IC506)
■ amplifiers (Q504, IC509)
■ TCXO divide by 4 (IC508)
The TCXO supplies a reference frequency of 13.0000MHz (10.4MHz for
the A4 band), which is extremely stable, regardless of the temperature.
The VCXO runs at a nominal frequency of 13.0120MHz, and is frequencylocked to the TCXO reference frequency.
Circuit OperationThe VCXO is mixed with the TCXO output to create a nominal difference
(or offset) frequency of 12kHz
SYN CDC FCL. In A4 band radios, there is
additional circuitry and the VCXO is mixed with the TCXO to produce
2.612MHz. This is then mixed with 2.6MHz (TCXO divided by 4) to
produce the 12kHz
SYN CDC FCL.
The signal
SYN CDCFCL is fed via the CODEC IC502 in the CODEC
circuitry to the FPGA on the digital board. The FPGA detects the offset
frequency, compares it with the programmed offset frequency, and outputs
a corresponding feedback signal
CDCVCXOMOD via IC205. The feedback
signal is amplified and inverted by the modulator buffer amplifier and output
as the loop voltage for the VCXO. With this design the VCXO frequency
can be adjusted by very small precise amounts, and because the loop is
locked, the VCXO inherits the temperature stability of the TCXO.
ModulationThe FCL modulation is implemented within the FPGA and appears at the
output of IC205, and therefore on the VCXO loop voltage. Consequently,
the VCXO is frequency modulated directly by the relevant modulation
information. The latter may be the microphone audio, an audio tap-in
signal, internal modem signals, or any combination of these.
76Circuit DescriptionsTM8100/TM8200 Service Manual
IntroductionFor a block diagram of the CODEC and audio circuitry, refer to Figure 3.7.
A/D and D/A
Conversion
Device IC203IC203 is an eight-channel DAC that provides control of transmitter biasing,
The analog-to-digital conversion and digital-to-analog conversion is
performed by the devices IC203, IC204 and IC205.
front-end AGC, front-end tuning, and the output of analog RSSI signals.
The digital input data are fed to IC203 in synchronous serial form. Three of
the DAC channels are not used.
Device IC205IC205 contains two CODECs. One is used by the FCL. The second is used
for auxiliary audio (input) and VCO modulation (output). The digital
section communicates with this device via a four-wire synchronous serial
interface.
Device IC204IC204 contains base-band, voice-band and auxiliary CODECs and some
analog signal conditioning. The reference voltage (nominally 1.2V) for
these CODECs is provided internally by IC204 but is decoupled externally
by C228.
Base-band CODECThe base-band CODEC handles the I and Q outputs (IRXP, IRXN, QRXP and
QRXN balls) of the receiver’s second IF stage. The analog signals are
differential and biased at 1.2V nominally. The digital section communicates
with this CODEC via a two-wire synchronous serial interface (
BSOFS balls). The digital-to-analog conversion section of the base-band
BSDO and
CODEC is not used.
Voice-band CODECThe voice-band CODEC handles the microphone and speaker signals.
The digital section communicates with this CODEC via a three-wire
synchronous serial interface (
VSFS, VSDO and VSDI balls). IC204 also contains
voice-band filtering, pre-amplification and volume control.
Auxiliary CODECThe auxiliary CODEC handles transmitter power control, receiver gain
control, auxiliary audio output and general analog monitoring functions.
The digital section communicates with this CODEC via a three-wire
synchronous serial interface (
receiver gain control (
IDACOUT ball) is a current output type. Current-to-
ASFS, ASDI and ASDO balls). The DAC used for
voltage conversion is performed by R238. The full-scale output of 1.2 V is
amplified by IC201 to approximately 3V as required by the receiver.
Audio CircuitryThe audio circuitry performs four functions:
The sections of the circuitry concerned with these functions are described
below.
Audio Signal
for Speaker
The audio signal for the speaker is generated by IC204 (VOUTAUXP ball).
This signal is post-volume-control and has a pre-emphasized frequency
response. The signal is then processed by R218, R217 and C231 (C205) to
restore a flat frequency response and reduce the signal level to that required
by the audio power amplifier.
Summing CircuitThe top of C231 (C205) is where side tones are summed in and the CDCRX
AUD signal is obtained. C201 and R211 pre-emphasize and attenuate the
side-tone signal to give a flat side-tone frequency response and reduce the
input to an appropriate level.
Buffer AmplifierIC201 (pins 8 to 10) amplifies the signal at the top of C231 (C205) by 19dB
and drives the
CDCRXAUD system interface line via C212 and R225.
The capacitor C212 provides AC output coupling and R225 ensures
stability. The DC bias for this amplifier is derived from IC204.
Audio Power
Amplifier
The signal at the top of C231 (C205) is fed via C204 to the audio power
amplifier IC202. IC202 has 46dB of gain and a differential output
configuration. C209, C211, R252 and R253 ensure stability of the amplifier
at high frequencies. When operational, the output bias voltage for IC202 is
approximately half the radio supply voltage. When not operational, the
output becomes high impedance.
Control of Audio
Power Amplifier
Power up, power down, and muting of IC202 is controlled by two signals
from the digital section,
DIG AUD PA EN1 and DIG AUD PA EN2. The network
consisting of Q200, Q201, R200 to R206, R210 and R250 converts the
two digital signals to the single three-level analog signal required by IC202.
Microphone SignalsThere are two microphone source signals:
■ ITF AUX MIC AUD from auxiliary or internal options connector
■ ITF CH MIC AUD from control head.
The biasing for electret microphones is provided by a filtered 3.0V supply
via R226 and R227. The components R209 and C202 provide the supply
filtering. The microphone inputs to IC204 (
VINNORN balls) are differential. The negative inputs are decoupled to the
filtered 3.0V supply by C215 and C216. The positive inputs are biased to
approximately 1.5 V by R229, R232, R230 and R233. AC coupling and
DC input protection is provided by C213 and C214.
Auxiliary Audio
Input
The auxiliary audio input signal ITFAUDTAPIN is DC-coupled to the ADC
input of IC205. R241 combined with internal clamping diodes in IC205
provide DC protection for the ADC input. IC205 provides the input biasing
of approximately 1.5V.
The source for the auxiliary audio output signal CDCAUDTAPOUT is provided
by IC204 (
RAMPDAC ball). The DAC output of IC204 is low-pass filtered to
remove high-frequency artefacts. The low-pass filter, formed by IC201
(pins 1 to 3), R219, R220, R221, R224, C206, C208 and C210, is a thirdorder Butterworth type with a cut frequency of approximately 12kHz.
The output of the low-pass filter is amplified by 6dB by a buffer amplifier,
IC201 (pins 5 to 7), and fed via R207 and R208 to drive the
OUT interf ace line. The DC bias for this signal pa th is provided by IC204 and
is approximately 1.2V when operational. The offset at
CDCAUDTAPOUT is
CDCAUDTAP
approximately 2.4V owing to the gain of the buffer amplifier.
80Circuit DescriptionsTM8100/TM8200 Service Manual
IntroductionFor a block diagram of the power supply circuitry, refer to Figure 3.8.
The power-supply circuitry consists of the following main sections:
■ supply protection
■ supervisory circuit
■ internal power supplies
■ control of internal power supplies
■ control of external power supply.
Supply ProtectionElectrical protection to the radio is provided by the clamping diode D600
and by 20A fuses (for the 40W/50 W radios) and 10A fuses (for the 25W
radios) in the positive and negative leads of the power cable. This provides
protection from reverse voltages, positive transients greater than 30V, and all
negative transients. An ADC monitors the supply and is responsible for the
protection of internal devices, which have an operating voltage of less than
30V. The ADC also ensures protection if the radio operates outside its
specified voltage range of 10.8V to 16 V.
Supervisory CircuitThe supervisory circuit comprises a reset and watchdog timer. The circuit
PSUSYSRST to the digital section, which in turn
DIGWDKICK required by the supervisory circuit.
V8 BATT.
Internal Power
Supplies
provides the reset signal
provides the watchdog signal
There are eight internal power supplies:
■ one SMPS (+3V3)
■ four linear regulators (+9V0, +6V0, +3V0 AN, +2V5 CDC)
■ three switched supplies (+9V0 TX, +3V0 RX, +13V8 SW).
The SMPS is used to regulate to 3.3V from the external supply +13
The four lower voltages required are then further stepped down with linear
regulators. These all take advantage of the efficiency gain of the SMPS.
The 9V regulator and the 13.8V switched supply are connected to +13
BATT. The two remaining switched supplies (9V and 3V) use P-channel
V8
MOSFETs.
Control of Internal
Power Supplies
The radio can be switched on using the ON/OFF key on the control head or
by means of external signals. For the latter case hardware links are required
and there are several power-sense options; these are discussed below. Some
internal power supplies can be controlled by means of digital lines
depending on the mode in which the radio is operating.
The radio allows the configuration of different power-sense options to
control how the radio is powered up and down:
■ battery power sense
■ auxiliary power sense (ignition sense)
■ internal-options power sense
■ no power sense
■ emergency power sense.
The emergency power-sense option can be used in conjunction with any of
the other four options.
The different power-sense options have to be facilitated by hardware means,
as the software cannot act before it is powered up. The radio provides four
hardware links (LK1 to LK4) on the top-side of the main board which can
be configured to attain the power-sense option desired.
Figure 3.9 shows a block diagram of the hardware links LK1 to LK4.
Figure 3.9Block diagram of hardware links LK1 to LK4
ON/OFF Key
13V8 BATT
LK1
13.8V Battery
Power Sense
LK2
AUX GPI3
Auxiliary Power Sense
(Ignition Sense)
13V8 BATT
Power-up
Circuit
LK3
AUX GPI2
Emergency
Sense
LK4
IOP GPIO7
Internal Options
Power Sense
The radio can be programmed to be either on, or to return to its previous
state when the power sense signal is removed. For information on
programming the power-on mode refer to the online help of the
programming software.
The
ON/OFF key can be used with any of the of the power-sense options to
Table 3.1 shows the configuration of the hardware links LK1, LK2 and LK4
for the individual power-sense options. It also lists the dependence of the
power-sense options with respect to the GPI lines, which can or cannot be
used.
Table 3.1Configuration of hardware links and GPI lines for power-sense options
Power-sense option
13.8V battery power
sense
Links
required
LK1 inLK2 in:
Configuration of remaining links and
use of AUX GPI3 and IOP GPIO7
AUX GPI3 must be left floating.
LK2 out:
AUX GPI3 can be used as GPI
a
.
Voltages
required
≤ supply≤ 16V
10.8V
LK4 outIOP GPIO7 can be used as GPIO.
auxiliary power sense
(ignition sense)
LK2 inLK1 in:
Input line must sink >1mA from
AUX GPI3 (which is pulled to 13.8V by a
Ω resistor). The impedance between
33k
AUX GPI3
AUX GPI3
ignition-sense tolerant to
3.3V, 5 V and 12 V
≤0.7V off
≥2.6V high (active)
the vehicle ignition signal and ground
must be ≤1k
LK1 out:
Input line must be active high
Ω.
b
.
LK4 outIOP GPIO7 can be used as GPIO.
internal power senseLK1 outIOP GPIO7
LK2 outAUX GPI3 can be used as GPI.
LK4 inWith LK4 in, the input line must be active
high
c
.
IOP GPIO7≥ 2.6V high
(active)
ignition-sense tolerant to
3.3V and 5V only
≤0.7V off
no power senseLK1 out10.8V ≤ supply ≤16V
LK2 outAUX GPI3 can be used as GPI.
LK4 outIOP GPIO7 can be used as GPIO.
a. If LK2 is out and AUX GPIO is not used, R775 (33k) should be placed to ensure that AUX GPI3 does not float
(R775 is not placed by factory default).
b. If LK1 is out and R775 is placed, AUX GPI3 should be driven low as well.
c. If LK 4 is in and R723 is placed, IOP GPIO7 should be driven low as well. (R723 is placed by factory default.)
Table 3.2 shows the configuration of ‘emergency power sense’. ‘Emergency
power sense’ can be configured with any of the above power sense options.
Table 3.2Configuration of hardware link LK3 and AUX GPI2 for ‘emergency power sense’
External push-button
or toggle switch
required to enter
emergency mode
YesLK3 inAUX GPI2 must be connected to an
NoLK3 inAUX GPI2 must be left floating
84Circuit DescriptionsTM8100/TM8200 Service Manual
Links
required
Implications on AUX GPI2Voltages required
external (hidden) push-button or toggle
switch, which connects it to ground.
With this option, link LK1 connects +13V8 BATT of the power connector to
the power-up circuitry. With this option, when a 13.8 V supply is connected
to the radio, the radio enters the programmed power-on mode. The
ON/OFF
key can then be used to switch the radio on and off. This option has the
disadvantage that the radio still draws about 50mA after being switched off
using the
ON/OFF key. The reason is that the radio enters the stand-by mode
and does not shut down completely.
Auxiliary Power
Sense
(Ignition Sense)
This option uses the digital input line AUXGPI3 of the auxiliary connector to
power the radio up and down. Link LK2 is required to connect the line to
the power-up circuitry. The line is active high; it is on when the level
exceeds 2.6V and off when the level falls below 0.7V; the line tolerates
maximum inputs equal to the radio supply voltage. When the line becomes
active, the radio enters the programmed power-on mode. The
ON/OFF key
can then be used to switch the radio on and off. With the radio off and the
line active, the radio draws about 50mA. When the line becomes inactive,
the radio is shut down completely regardless of whether it was on or in
stand-by mode. With the line inactive the radio draws less than 1mA.
In a vehicle installation this avoids flattening the battery when the ignition
key is off.
Internal-Options
Power Sense
This option is similar to the auxiliary power-sense option, except that the
IOP GPIO7 line of the internal options connector is used. Link LK4 is required
to connect the line to the power-up circuitry. This line is active high; it is
on when the level exceeds 2.6V and off when the level falls below 0.7V;
the line tolerates maximum inputs of 5V. The behaviour of the
ON/OFF key
is the same as with the auxiliary power-sense option.
No Power SenseIf no power-sense option is selected, the radio can only be powered up and
powered down by means of the
ON/OFF key. For this option, the links LK1,
LK2 and LK4 must be removed. The advantage of this option over the
battery power-sense option is that the radio draws less than 1 mA when it is
switched off.
Emergency
Power Sense
This option uses the AUXGPI2 line of the auxiliary connector. Externally, this
line is typically connected to a hidden switch. Internally, link LK3 is
required to connect the line to the power-up circuitry. The line is active low
and has an internal pull-up resistor to the external supply voltage. The line
is on when the level falls below 0.7V. When the line becomes active (when
the hidden switch is pressed for two seconds) the radio enters the emergency
mode. This mode can also be activated by making an emergency call or by
pressing a key that has been programmed appropriately. The concealed
microphone is typically fitted when the emergency power-sense option is
selected.
If the radio is off when the emergency mode is activated, the radio is
powered up but the display on the control head is not switched on. If the
radio is on when the mode is activated, the display is frozen. In the latter
case, if the
ON/OFF key is pressed, the display is switched off but the radio
remains in the emergency mode. While in this mode the radio cycles
between transmit and receive. To exit the emergency mode, the
ON/OFF key
needs to be pressed again.
Connector Power
Supply Options
Power from the radio’s primary power source is fed to the auxiliary, internal
options, control head and microphone connectors. Whether power to these
connectors is unswitched, switched or not supplied is determined by
hardware links LK5 to LK8 on the top side of the main board, as shown in
Figure 3.10 and Table 3.3.
Unswitched power means that power will always be supplied to the
connector while the primary power source is connected to the radio and is
alive. The supply to the connector is not affected by the state of the radio.
Switched power means that when the radio is off or in standby mode, the
power to the connector is switched off. The power will also be switched off
if the primary power source voltage is outside the radio’s operating range.
The combined switched current drawn by the internal options connector,
the auxiliary connector and the control-head connector must not exceed
1A.
NoteThe switched output is protected. Short-circuiting the switched
power on any connector will not damage the radio. In the event
of a short circuit, the current folds back to protect the switch
device and connectors.
Figure 3.10Connector power supply options
Internal
Options
1
Connector
LK7
(R787)
LK5
LK6
+13V8
Auxiliary
Connector
8
Control-
2
Connector
Head
Microphone
Connector
2
Primary
Power
Source
Power
Connector
LK8
(R786)
+13V8 BATT
NoteThe links LK7 and LK8 have the alternative designations R787
and R786 respectively. The factory-default setting is with LK5
and LK7 inserted and LK6 and LK8 omitted.
86Circuit DescriptionsTM8100/TM8200 Service Manual
IntroductionFor a block diagram of the interfaces circuitry, refer to Figure 3.11.
For more on the connector pinouts, refer to “Connectors” on page 36.
Bi-directional LinesBi-directional lines are provided on four pins of the auxiliary connector,
AUXGPIO4 to AUXGPIO7) one on the control-head connector (CH GPIO1), and
(
seven on the internal options connector (
the auxiliary and control-head connectors are formed by combining two
uni-directional lines. For example, the line
auxiliary connector is formed from
The circuitry is the same in all five cases and is explained below for the case
AUXGPIO4.
of
IOPGPIO1 to IOP GPIO7). Those on
AUXGPIO4 at pin 10 of the
ITF AUX GPI4 and DIGAUXGPO4.
Output Signals
(e.g. AUX GPIO4)
An output on the line AUX GPIO4 originates as the 3.3V signal DIG AUX GPO4
from the digital section. The signal is first inverted by Q703 (pins 3 to 5) and
the output divided down to 1.6V by R748 and R753 to drive the base of
Q703 (pins 1, 2 and 6). When the latter’s collector current is low, the base
current is a maximum and creates a small voltage drop across R761, causing
the collector emitter to saturate. As the collector current increases, the base
current decreases proportionally until the voltage across R761 reaches 1V.
At this point the base-emitter begins to turn off and the base current
diminishes rapidly. The net effect is a current-limiting action. The current
limit value is approximately 18mA (the inverse of the value of R761).
The output configuration is open-collector with a pull-up to 3.3 V by
default. Pull-up options to 5V and 13.8 V are also available. On
AUX GPIO4
only, the optional MOSFET Q707, which has a high current drive, may be
fitted. If Q707 is fitted, R768 must be removed.
5-Volt RegulatorThe 5V supply mentioned above is provided by a simple buffered zener
regulator formed by Q702, D721, R721 and R722. The resistor R722
limits the current to about 25 mA under short-circuit conditions.
An input signal applied to AUXGPIO4 is coupled via R757 to ITF AUX GPI4 and
fed to the digital section. As the input signal may exceed the maximum
allowed by the digital section, it is clamped by D711 and a shunt regulator.
The shunt regulator consists of Q708, R719 and R720 and begins to turn
on at approximately 2.7V. In combination with D711, the input to
ITF AUX GPI4 is therefore clamped to 3.3V nominally. The value of R757 is
made large to minimize the loading effect on the output pull-up resistors.
Input Signals
(AUX GPI1 to AUX GPI3)
Dedicated inputs are provided on three pins of the auxiliary connector
AUX GPI1 to AUX GPI3). AUXGPI1 is a general-purpose input with strong
(
protection of the same type used for
AUX GPIO4. AUX GPI2 is normally a
dedicated emergency input but can be made a general-purpose input like
AUX GPI1 by removing the link LK3 in the power supply area. AUX GPI3 is
normally a dedicated ignition-sense input but can be made a generalpurpose input like
AUXGPI1 by removing the link LK2 in the power supply
area and fitting the 33kΩ resistor R775.
ESD ProtectionOn exposed inputs of the auxiliary and control-head connectors ESD
(electrostatic discharge) protection is provided by a 470pF capacitor and by
clamping diodes to ground and to 13.8V. For example, on
consists of D713 and C725. The lines
IOP GPIO1 to IOP GPIO7 are intended for
AUX GPIO4 this
connection to internal digital devices and so these have relatively light
protection.
Hookswitch
Detection
Hookswitch detection is performed by Q700, R709, R706 and R712.
When the resistance to ground on the PTT line is less than 13.2kΩ, Q700
will turn on and drive the
ITFCHHOOK line high; this indicates either that the
microphone is on hook or that the PTT (press-to-talk) switch is pressed.
3.8Digital Board
IntroductionDifferent digital boards are used for the TM8200 and TM8100 radios.
For a block diagram of the digital board of the TM8200 radios, refer to
Figure 3.12. For a block diagram of the digital board of the TM8100 radios,
refer to Figure 3.13.
The digital board is not serviceable at level-2 and is not described in this
manual.
IntroductionThis section describes the control-head board for the control head with
graphical display.
For a block diagram of the digital circuitry, refer to Figure 3.14.
Most signals (except power on/off, speaker and microphone) to and from
the radio body are processed by a RISC processor, which is implemented on
an FPGA on the control-head board. For more information on the RISC
processor and the FPGA, refer to “Software Architecture” on page 47.
User InterfaceThe control-head board includes the circuitry for the following control
elements:
■ ON/OFF key
■ volume potentiometer
■ main keypad (with four functions keys, two scroll keys and
two selection keys)
■ LCD module (with backlighting and optional heating element)
■ three status LEDs
■ two function key LEDs (for function keys F1 and F4)
■ keypad backlighting LEDs
■ speaker.
ConnectorsThe control-head board includes the circuitry for the following connectors:
ON/OFF KeyWhen battery power (13.8V) is applied to the radio, a press of the ON/OFF key
will create an active low signal (
CH ON OFF) back to the radio body to initiate
the power-on or power-off sequence. This key-press will also be detected
by the FPGA of the control head through Q611 as an active high signal.
For more information on the start-up process, refer to “Software
Architecture” on page 47.
92Circuit DescriptionsTM8100/TM8200 Service Manual
Power SupplyA 3.3V regulator (U1) converts the switched 13.8V supply from the radio
body to 3.3V. A 1.5V regulator (U203) converts the 3.3V to 1.5V.
A power-sense module (U202) verifies the outputs of the voltage regulators
and—in the case of a fault—creates a power reset signal which is processed
by the FPGA.
Volume ControlThe voltage level of the volume control potentiometer is converted to a
digital signal by an analog/digital converter (U601), processed by the FPGA
and transmitted to the radio body.
Main KeypadThe eight keys of the main keypad (function, scroll and selection keys) are
connected to the FPGA by an array of 3 columns and 3 rows. During idle
operation, the
KEY ROW signals are driven low by the FPGA and the KEY COL
signals (pulled high by an external resistor) are monitored for activity by the
FPGA. A key-press will generate a high-to-low transition on the associated
column
levels on the
LCD ModuleThe LCD module is connected to the control-head board via the LCD
KEY COL signal. This, in turn, will initiate a sequence of high output
KEY ROW signals to identify which key was pressed.
connector. The LCD module display is contro lled by a se r ial data link to the
FPGA. The backlighting and the optional heating element incorporated in
the LCD module are controlled by a data line each from the FPGA, which
switch two transistors on MOSFET Q102. A temperature signal from the
LCD module is converted to a digital signal by an analog/digital converter
(U601) and processed by the FPGA.
Function Key LEDs
and Status LEDs
The function key LEDs (F1 and F4) and the red, green and amber status
LEDs each are controlled by an FPGA signal and a transistor (Q604 to
Q608). The brightness level is controlled by two FPGA signals, resulting in
four intensity levels (off, low, medium and high).
Keypad
Backlighting
The keypad backlighting LEDs are controlled by two FPGA signals and two
transistors (Q2), resulting in four intensity levels (off, low, medium and
high). The keypad backlighting LEDs are arranged in two groups for the
main keypad and one group for the power button keypad, each group
consisting of three LEDs.
SpeakerThe two speaker lines (SPK+ and SPK–) are connected to the speaker
connector (J104) which is joined to the control-head connector (J103)
through two ferrite beads (L105 and L106).
Microphone and
Concealed
Microphone
(Optional)
The audio signals from the microphone connector or the soldering pads of
the optional concealed microphone are routed to a switching and preamplifier circuit. If a dynamic microphone is required, the pre-amplifier is
engaged. The switching logic is used to select either the standard
microphone input or the concealed microphone signal. The dynamic
microphone must be activated in the programming software.
PTTThe PTT signal from the microphone connector is connected to the FPGA
via a resistor (R25) and relayed to the radio as a digital command.
94Circuit DescriptionsTM8100/TM8200 Service Manual
3.10Control-Head Board with 1-, 2- or 3-Digit Display
IntroductionThis section describes the circuitry of the control-head boards for the
control heads with 1-, 2- or 3-digit display. The boards differ in their layouts
but the components are virtually identical. The circuit description given
below is sufficiently general to be applicable to all boards.
User InterfaceThe control-head board includes the circuitry for the following control
elements:
■ ON/OFF key
■ volume potentiometer
■ keypad (with four functions keys and two scroll keys)
■ LCD
■ three status LEDs
■ four function key LEDs (for function keys F1 to F4)
■ keypad backlighting LEDs
■ speaker.
ConnectorsThe control-head board includes the circuitry for the following connectors:
The optional circuit board is installed when a dynamic microphone is used
or a concealed microphone is fitted.
Basic CircuitryThe LCD driver is based on IC2, IC5 and IC7. Electrical contact between
the control head and the LCD itself is via two elastomeric strips as described
in “Control Heads with 1-, 2- or 3-Digit Display” on page 29. There are
pads on the board for the seven keys—four function keys, two channelselection keys, and the
ON/OFF key. The device IC4 reads the status of the
function and channel-selection keys. Of the 18 LEDs, there are red, orange
and green
STATUS LEDs, and four green LEDs for the function keys, as well
as 11 green LEDs for back-lighting—one for each key and four for the LCD.
The four dual switching transistors Q1 to Q4 control the switching of the
LEDs; the transistors are driven by IC3.
The control-head board uses an SPI (serial peripheral interface) to control
the display on the LCD, turn back-lighting on and off, control the
STATUS
LEDs, and read the status of the keys. The interface consists of the following
four lines at the control-head connector:
■ pin 11: data out CHSPIDO
■ pin 12: latch line CHLE
■ pin 15: data in CHSPIDI
■ pin 16: clock CHSPICLK.
Data Input and
Output
Data that are input to the control head are clocked through the LCD driver
and daisy-chained to a shift register. Once all the data have been clocked in,
the latch line is driven low. On this falling edge all the outputs (LEDs and
LCD segments) are driven to their new state. When the latch line is driven
high, the state of each key is latched into another shift register. The data are
then clocked out back to the radio body so that the radio can respond
accordingly.
LCD DriverAn oscillator is used to run the LCD. It oscillates at about 60Hz and employs
a Schmitt trigger and D flip-flop to ensure a 50% duty cycle to the LCD.
A reset circuit is required because the reset from the main board is not routed
to the control head. The reset circuit also employs a Schmitt trigger.
Volume ControlThe volume-control potentiometer is linear and passes the DC voltage signal
VOL WIP DC to the radio body. The signal is read by an ADC on the main