SUPER
X7DBU
X7DGU
®
USER’S MANUAL
Revision 1.0c
The information in this User’s Manual has been carefully reviewed and is believed to be accurate.
The vendor assumes no responsibility for any inaccuracies that may be contained in this document,
makes no commitment to update or to keep current the information in this manual, or to notify any
person or organization of the updates. Please Note: For the most up-to-date version of this
manual, please see our web site at www.supermicro.com.
Super Micro Computer, Inc. ("Supermicro") reserves the right to make changes to the product
described in this manual at any time and without notice. This product, including software, if any,
and documentation may not, in whole or in part, be copied, photocopied, reproduced, translated or
reduced to any medium or machine without prior written consent.
IN NO EVENT WILL SUPER MICRO COMPUTER, INC. BE LIABLE FOR DIRECT, INDIRECT,
SPECIAL, INCIDENTAL, SPECULATIVE OR CONSEQUENTIAL DAMAGES ARISING FROM THE
USE OR INABILITY TO USE THIS PRODUCT OR DOCUMENTATION, EVEN IF ADVISED OF
THE POSSIBILITY OF SUCH DAMAGES. IN PARTICULAR, SUPER MICRO COMPUTER, INC.
SHALL NOT HAVE LIABILITY FOR ANY HARDWARE, SOFTWARE, OR DATA ST ORED OR USED
WITH THE PRODUCT, INCLUDING THE COSTS OF REPAIRING, REPLACING, INTEGRATING,
INSTALLING OR RECOVERING SUCH HARDWARE, SOFTWARE, OR DATA.
Any disputes arising between manufacturer and customer shall be governed by the laws of Santa
Clara County in the State of California, USA. The State of California, County of Santa Clara shall
be the exclusive venue for the resolution of any such disputes. Super Micro's total liability for all
claims will not exceed the price paid for the hardware product.
FCC Statement: This equipment has been tested and found to comply with the limits for a Class
A digital device pursuant to Part 15 of the FCC Rules. These limits are designed to provide
reasonable protection against harmful interference when the equipment is operated in a commercial
environment. This equipment generates, uses, and can radiate radio frequency energy and, if not
installed and used in accordance with the manufacturer’s instruction manual, may cause harmful
interference with radio communications. Operation of this equipment in a residential area is likely
to cause harmful interference, in which case you will be required to correct the interference at your
own expense.
California Best Management Practices Regulations for Perchlorate Materials: This Perchlorate
warning applies only to products containing CR (Manganese Dioxide) Lithium coin cells. “Perchlorate
Material-special handling may apply. See www.dtsc.ca.gov/hazardouswaste/perchlorate”
WARNING: Handling of lead solder materials used in this
product may expose you to lead, a chemical known to
the State of California to cause birth defects and other
reproductive harm.
Manual Revision 1.0c
Release Date: June 16, 2009
Unless you request and receive written permission from Super Micro Computer, Inc., you may not
copy any part of this document.
Information in this document is subject to change without notice. Other products and companies
referred to herein are trademarks or registered trademarks of their respective companies or mark
holders.
Copyright © 2009 by Super Micro Computer, Inc.
All rights reserved.
Printed in the United States of America
Preface
About This Manual
This manual is written for system integrators, PC technicians and
knowledgeable PC users. It provides information for the installation and use of the
X7DBU/X7DGU motherboard. The X7DBU/X7DGU supports dual
Intel
XEON 64-bit Quad-core/Dual-core processors at a front side bus speed of 1.333
GHz/1.066 GHz/667 MHz. With dual 64-bit Xeon Quad-core/Dual-core processors,
the 5000 chipset, and 8 DDR2 FBD 667/533 memory modules built-in, the X7DBU/
X7DGU offers substantial functionality and performance enhancements to the motherboards based on the Core microarchitecture while remaining compatible with the
32-bit based software. The features include Virtualization Technology, Execution
Trace Cache, Thermal Monitor 2 (TM2), Enhanced Intel SpeedStep technology, Advanced Dynamic Execution, Advanced Transfer Cache, Streaming SIMD Extensions
3 (SSE3) and Extended Memory 64 Technology (EM64T). These features allow the
motherboard to operate at much higher speeds with better power management in
much safer environments than the traditional motherboards. The X7DBU/X7DGU
is ideal for high performance dual processor (DP) enterprise server environments.
This product is intended to be professionally installed.
Preface
Manual Organization
Chapter 1 describes the features, specifi cations and performance of the mainboard
and provides detailed information about the chipset.
Chapter 2 provides hardware installation instructions. Read this chapter when
installing the processor, memory modules and other hardware components into the
system. If you encounter any problems, see Chapter 3, which describes troubleshooting procedures for video, memory and system setup stored in the CMOS.
Chapter 4 includes an introduction to the BIOS and provides detailed information
on the CMOS Setup utility.
Appendix A provides BIOS POST Error Beep Codes. Appendix B, and Appendix
C list OS and Software Installation Instructions.
Conventions Used in the Manual:
Special attention should be given to the following symbols for proper installation and
to prevent damage done to the components or injury to yourself:
Warning: Important information given to ensure proper system installation
or to prevent damage to the components.
Note: Additional Information given to differentiate various models or to ensure correct system setup.
iii
X7DBU/X7DGU User's Manual
Table of Contents
Preface
About This Manual ...................................................................................................... iii
Manual Organization ................................................................................................... iii
Conventions Used in the Manual ..................................................................................iii
Chapter 1: Introduction
1-1 Overview ......................................................................................................... 1-1
Checklist ................................................................................................... 1-1
Contacting Supermicro ............................................................................. 1-2
X7DBU/X7DGU Image ............................................................... 1-3
X7DBU/X7DGU Layout ............................................................... 1-4
Quick Reference ...................................................................................... 1-5
Motherboard Features ................................................................................ 1-6
Intel 5000 Chipset: System Block Diagram ............................................. 1-8
1-2 Chipset Overview ........................................................................................... 1-9
1-3 Special Features ........................................................................................... 1-10
1-4 PC Health Monitoring .................................................................................... 1-10
1-5 ACPI Features .............................................................................................. 1-11
1-6 Power Supply ............................................................................................... 1-12
1-7 Super I/O ........................................................................................................1-13
Chapter 2: Installation
2-1 Static-Sensitive Devices ................................................................................. 2-1
Precautions ................................................................................................ 2-1
Unpacking ................................................................................................ 2-1
2-2 Processor and Heatsink Installation ............................................................... 2-2
2-3 Installing DIMMs ............................................................................................. 2-6
2-4 Control Panel Connectors and IO Ports ......................................................... 2-8
A. Back Panel Connectors/IO Ports .............................................................. 2-8
B. Front Control Panel ...................................................................................2-9
C. Front Control Panel Pin Defi nitions ........................................................2-10
NMI Button .............................................................................................2-10
Power LED ............................................................................................. 2-10
HDD LED/FP UID Switch ........................................................................ 2-11
NIC1/NIC2 LEDs ................................................................................... 2-11
Overheat/Fan Fail LED/PWR Fail/FP UID LED .................................... 2-12
Power Fail LED ........................................................................................2-12
Reset Button ......................................................................................... 2-13
iv
Table of Contents
Power Button .......................................................................................... 2-13
2-5 Connecting Cables ......................................................................................... 2-14
ATX Power Connector .......................................................................... 2-14
Processor Power Connector ................................................................. 2-14
Universal Serial Bus ................................................................................ 2-15
Chassis Intrusion .................................................................................... 2-15
Fan Headers .......................................................................................... 2-16
Keylock .................................................................................................... 2-16
ATX PS/2 Keyboard and Mouse Ports .....................................................2-17
Serial Ports ............................................................................................. 2-17
Wake-On-Ring ..........................................................................................2-18
Wake-On-LAN ..........................................................................................2-18
GLAN 1/2 (Ethernet Ports) ....................................................................... 2-19
Speaker/Power LED Header .................................................................. 2-19
Overheat LED/Fan Fail ............................................................................ 2-20
SMB Connector ........................................................................................ 2-20
SMB Power Connector .............................................................................2-21
VGA Connector ........................................................................................2-21
Unit Identifi cation Switches ......................................................................2-22
SGPIO Headers ....................................................................................... 2-22
2-6 Jumper Settings .............................................................................................. 2-23
Explanation of Jumpers ......................................................................... 2-23
GLAN Enable/Disable ............................................................................ 2-23
Clear CMOS ............................................................................................. 2-24
Watch Dog ................................................................................................2-24
VGA Enable/Disable .................................................................................2-25
I2C Bus to PCI Slots ................................................................................ 2-26
2-7 Onboard Indicators .......................................................................................... 2-27
GLAN LEDs .............................................................................................. 2-27
Onboard Power LED ................................................................................ 2-28
2-8 Floppy, Hard Disk Drive, SIMSO-DIMM IPMI and SCSI Connections ............ 2-29
Floppy Connector .................................................................................... 2-29
SIMSO Slot .............................................................................................. 2-30
IDE Connectors ....................................................................................... 2-31
SXB1/SXB2 Slots .................................................................................... 2-32
Chapter 3: Troubleshooting
3-1 Troubleshooting Procedures ........................................................................... 3-1
Before Power On ....................................................................................... 3-1
v
X7DBU/X7DGU User's Manual
No Power ................................................................................................... 3-1
No Video .................................................................................................. 3-1
Losing the System’s Setup Confi guration ................................................ 3-1
Memory Errors ........................................................................................... 3-2
3-2 Technical Support Procedures ........................................................................ 3-2
3-3 Frequently Asked Questions ........................................................................... 3-3
3-4 Returning Merchandise for Service ................................................................. 3-4
Chapter 4: BIOS
4-1 Introduction .......................................................................................................4-1
4-2 Running Setup ................................................................................................. 4-2
4-3 Main BIOS Setup .............................................................................................4-3
4-4 Advanced Setup ............................................................................................... 4-6
4-5 Security Setup ............................................................................................... 4-23
4-6 Boot Setup ......................................................................................................4-24
4-7 Exit ..................................................................................................................4-25
Appendices:
Appendix A: BIOS POST Beep Codes ...................................................................... A-1
Appendix B: Installing the Windows OS ....................................................................B-1
Appendix C: Installing Other Software Programs and Drivers...................................C-1
vi
Chapter 1: Introduction
Chapter 1
Introduction
1-1 Overview
Checklist
Congratulations on purchasing your computer motherboard from an acknowledged
leader in the industry. Supermicro boards are designed with the utmost attention to
detail to provide you with the highest standards in quality and performance. Check
that the following items have all been included with your motherboard. If anything
listed here is damaged or missing, contact your retailer.
All the following items are included in the Retail Box.
One (1) Supermicro Mainboard
One (1) ribbon cable for IDE devices (CBL-036L-02)
One (1) fl oppy ribbon cable (CBL-022)
One (1) Supermicro CD containing drivers and utilities
One (1) User's/BIOS Manual
1-1
X7DBU/X7DGU User's Manual
Contacting Supermicro
Headquarters
Address: Super Micro Computer, Inc.
980 Rock Ave.
San Jose, CA 95131 U.S.A.
Tel: +1 (408) 503-8000
Fax: +1 (408) 503-8008
Email: marketing@supermicro.com (General Information)
support@supermicro.com (Technical Support)
Web Site: www.supermicro.com
Europe
Address: Super Micro Computer B.V.
Het Sterrenbeeld 28, 5215 ML
's-Hertogenbosch, The Netherlands
Tel: +31 (0) 73-6400390
Fax: +31 (0) 73-6416525
Email: sales@supermicro.nl (General Information)
support@supermicro.nl (Technical Support)
rma@supermicro.nl (Customer Support)
Asia-Pacifi c
Address: Super Micro Computer, Taiwan
4F, No. 232-1 Liancheng Road
Chung-Ho 235, Taipei Hsien, Taiwan, R.O.C.
Tel: +886-(2) 8226-3990
Fax: +886-(2) 8226-3991
Web Site: www.supermicro.com.tw
Technical Support:
Email: support@supermicro.com.tw
Tel: 886-2-8228-1366, ext.132 or 139
1-2
X7DBU/X7DGU Image
Chapter 1: Introduction
Note 1: The drawings and pictures shown in this manual were based on PCB
Revision 1.02, the latest revision available at the time of publishing of the manual.
The motherboard you’ve received may or may not look exactly the same as the
graphics shown in the manual.
Note 2: X7DGU is for OEM only.
1-3
X7DBU/X7DGU User's Manual
JD1
F
n
2
X7DBU/X7DGU Motherboard Layout
(not drawn to scale)
Buzzer
SP1
Intel 5000
(North Bridge)
I2C1
I2C2
J27
J28
X7DBU
SXB2: PCI-E x8
SXB1: PCI-E x16
KB/MS
USB 0/1
COM1
JCOM1
VGA
J15
LAN1
JLAN1
LAN2
JLAN2
LE2
JKM1
Rear UID
SW1
UIO PWR
Battery
J11
Bank4
Bank3
Bank2
Bank1
LAN
CTRL
Fan6
J7B3
J7B2
J7B1
J14
Fan5
J9B2
J9B1
J8B3
J8B2
J8B1
PCI-X 133 MHz
Fan7
CPU Fan1
DIMM4B
DIMM4A
DIMM3B
DIMM3A
DIMM2B
DIMM2A
DIMM1B
DIMM1A
PWR SMB
J9
J17
J5
Intel ESB2
(South Bridge)
JWOR1
JPG1
ES1000
Video CTRL
COM2
4-Pin PWR
8-Pin PWR
JPW2
JPW1
20-Pin Main PWR
JPW3
Fa
J
CPU1
FP CTRL
Fan2
LE1
JOH1
JP1
CPU2
I-SATA4
I-SATA3
I-SATA2
I-SATA1
I-SATA0
SGPIO1
J29
J30
SGPIO2
BIOS
JBT1
J7
Video Memory
JWD
JK1
JWOL1
JPL2
USB4
JPL1
I-SATA5
S I/O
USB2/3
Fan8
CPU FAN2
J18
SMB
JL1
Fan
IDE#1
SIMSO
Floppy
J
Fan4
Notes:
1. Jumpers not indicated are for test purposes only.
2. See Chapter 2 for detailed information on jumpers, I/O ports and JF1 front panel
connections.
3. " ", "
" and " " indicate Pin 1 locations.
4. The X7DBU uses the Intel 5000P chip and the X7DGU uses the Intel 5000X
chip.
5. The X7DGU model is for OEM only.
6. When LE1 is on, make sure to remove the power cable before removing or
installing components.
7. All SXB1 (J5), SXB2 (J9) and PCI-X 133 MHz (J14) slots are designed to be
used with riser cards. When used with riser cards, the left IO slot (SXB1) supports
one PCI-E x8 and one UIO devices, while the right IO slots (SXB2, PC1-X: J14)
can support a PCI-E x8 or a PCI-X 133 MHz device.
1-4
Chapter 1: Introduction
Quick Reference ( X7DBU/X7DGU)
Jumper Description Default Setting
JBT1 CMOS Clear See Chapter 2
2
JI
C1 (J27) SMBBus to PCI-X/PCI-E Slots Off (Disabled)
JI2C2 (J28) SMBBus to PCI-X/PCI-E Slots Off (Disabled)
JPG1 VGA Enable Pins 1-2 (Enabled)
JPL1/ JPL2 GLAN1/GLAN2 Enable Pins 1-2 (Enabled)
JWD Watch Dog Pins 1-2 (Reset)
Connector Description
ATX PWR (JPW1) Primary 20-Pin ATX PWR Connector
Aux. PWR/CPU PWR +12V 4-pin PWR (JWP2)/+12V 8-pin PWR(JPW3)
UIO PWR (J11) Power Connector for the Universal IO slots
Buzzer (SP1) Internal Speaker
Chassis Intrusion (JL1) Chassis Intrusion Header
COM1/COM2 COM1(JCOM1)/COM2(JCOM2) Serial Port Connectors
DIMM#1A-DIMM#4B Memory DDR2 Fully Buffered (FBD) Slots
FAN 1-8 Fans 1-6 (System Fans), Fans 7-8: CPU Fans
(Fans 1-4: 3-pin Fans, Fans 5-8: 4-pin Fans)
Floppy (J22) Floppy Disk Drive Connector
FP CTRL (JF1) Front Control Panel Connector
GLAN 1/2 (JLAN1/2) G-bit Ethernet Ports
IDE#1 (JIDE1) IDE#1 Hard Drive
Keylock (JK1) Keylock Header
OH LED (JOH1) Overheat LED Indicator
PCI-X (J14) PCI-X 133MHz Slot (*See Note 7 on Page 1-4)
PWR LED/SPKR (JD1) PWR LED(pins1-3)/Speaker Header (pins 4-7)
PWR SMB (J17) Power System Management (I
SATA0-SATA5 Intel SATA 0-5 Connectors
SGPIO1/2 (J29, J30) Serial General Purpose Input/Output Headers
SIMSO SIM SO-DIMM IPMI Slot
SMB (J18) System Management Bus Header
SXB1 (J5) PCI-Exp x16 slot (*See Note 7 on Page 1-4)
SXB2 (J9) PCI-Exp x8 slot (*See Note 7 on Page 1-4)
UID (SW1) Rear Unit Identifi cation Switch
USB 0/1 Back Panel USB Ports 0/1
USB 2/3,USB4 Front Panel USB Connectors 2/3, FP USB Connector 4
VGA (J15) (Note) VGA Connector
WOL (JWOL1) Wake-on-LAN Header
WOR (JWOR1) Wake-on-Ring Header
2
C) Header
LE Indicators Description
LE1 Onboard Power LED Indicator
LE2 Unit Identifi cation (UID) LED Indicator
Note: The X7DGU model is for OEM only.
1-5
X7DBU/X7DGU User's Manual
Motherboard Features
CPU
®
• Dual Intel
bus speed of 1.333 GHz/1.066 GHz/667 MHz
Memory
• 8 240-pin DIMM sockets with support up to 32 GB DDR2 Fully Buffered (FBD)
ECC 667/533 Memory (*See Section 2-3 in Chapter 2 for DIMM Slot Population.)
Chipset
*X7DBU:
• Intel 5000P chipset, including: the 5000P Memory Control Hub (MCH) and the
Enterprise South Bridge 2 (ESB2).
64-bit Xeon LGA 771 Quad-core/Dual-core processors at a front side
*X7DGU:
• Intel 5000X chipset, including: the 5000X Memory Control Hub (MCH) and the
Enterprise South Bridge 2 (ESB2).
Expansion Slots
*X7DBU:
• Two PCI-Express slots (SXB1: PCI-E x8 + x8 Single Slot, SXB2: PCI-E x8)
• One 64-bit PCI-X 133 MHz slot (J14)
*X7DGU (for OEM only):
• Two PCI-Express slots (SXB1: PCI-E x16, SXB2: PCI-E x8)
• One 64-bit PCI-X 133 MHz slot (J14)
BIOS
• 8 Mb Phoenix
®
Flash ROM
• DMI 2.3, PCI 2.2, ACPI 1.0/2.0, Plug and Play (PnP), SMBIOS 2.3 and USB
Keyboard support
PC Health Monitoring
• Onboard voltage monitors for CPU cores, chipset voltage, memory voltage,
HT voltage, +1.8V, +3.3V, +5V, 12V, 12V, +3.3V Standby, +5V standby and
VBAT
• Fan status monitor with fi rmware control
• CPU/chassis temperature monitors
• Low noise fan speed control
1-6
Chapter 1: Introduction
• Platform Environment Control Interface (PECI) ready
2
• I
C temperature sensing logic
• Thermal Monitor 2 (TM2) support
• CPU slow-down on temperature overheat
• CPU thermal trip support for processor protection
• Power-up mode control for recovery from AC power loss
• Pulse Width Modulation Fan Control (Fans 5-8)
• Auto-switching voltage regulator for CPU cores
• System overheat/Fan Fail LED Indicator and control
• Chassis intrusion detection
• System resource alert via Supero Doctor III
ACPI Features
• Slow blinking LED for suspend state indicator
• Main switch override mechanism
• ACPI Power Management
• Power-on mode for power recovery
Onboard I/O
• Six SATA ports (supporting RAID0, RAID1, RAID10 and RAID5)
• One SIMSO IPMI socket (AOC-SIMSO)
• Two Giga-bit LAN ports with IOAT Technology
• One IDE w/two devices supported
• One fl oppy port interface
• Two COM ports(1 header, 1 port)
• Up to fi ve USB 2.0 (Universal Serial Bus) (2 ports, 2 Headers)
• ATI ES1000 16MB Graphic Controller
• Super I/O: Winbond W83627HG w/Hardware Monitor support: W83793G
Other
• External modem ring-on
• Wake-on-LAN (WOL)
• Wake-on-Ring (WOR)
• Console redirection
• Onboard Fan Speed Control by Thermal Management via BIOS
• SDDC support
CD/Diskette Utilities
• BIOS fl ash upgrade utility and device drivers
Dimensions
• Proprietary 13.035" (L) x 12.075" (W) (331.09mm x 306.71mm)
1-7
X7DBU/X7DGU User's Manual
VGA
CONN
VRM
J9
J14
PCIX SLOT
VGA
ES1000
PROCESSOR#2
1067/1333
J5
PCI-E X16 SLOT
PWR
36PIN
PCI-EX8
PCI-EXP X8 SLOT
PCI-X133
PCI32
/33MMZ
PCI-EX8
PCI-EX8
MT/S
PORT
#4,5
(Intel 5000)
PORT
#6,7
PCIE X8
PORT
#1,2
MCH
PORT PORT
#0#2,3
PORT PORT
#4 #3
ESB2
PROCESSOR#1
1067/1333
MT/S
FBD CHNL0
FBD CHNL1
FBD CHNL2
FBD CHNL3
PCIE X4
ATA100
3.0Gb/S
USB2.0
VRM
#1B #2B #3B
#1A
#2A #3A
FBD DIMM
FBD DIMM
IDE CONN
#5
#4
#3
#2
#1
#0
SATA
#4
#3
#2
#1
#0
USB
#4B
#4A
FBD DIMM
FBD DIMM
HF
LPC
FWH
DDR
RJ45
KUMERAN
GB LAN
GILGAL
SIO
W83627
RJ45
FDD
MS
KB
COM1
COM2
System Block Diagram for the X7DBU
Note: This is a general chipset block diagram. Please see the previous Motherboard
Features pages for details on the features of each motherboard.
1-8
Chapter 1: Introduction
1-2 Chipset Overview
Built upon the functionality and the capability of the 5000P/5000X chipset, the
X7DBU/X7DGU motherboard provides the performance and feature set required
for dual processor-based servers with confi guration options optimized for com-
munications, presentation, storage, computation or database applications. The
5000P/5000X chipset supports a single or dual Intel 64-bit Quad-core/Dual-core
processor(s) with front side bus speeds of up to 1.333 GHz. The chipset consists
of the 5000P/5000X Memory Controller Hub (MCH) and the Enterprise South Bridge
2 (ESB2),
The 5000P/5000X MCH chipset is designed for symmetric multiprocessing across
two independent front side bus interfaces. Each front side bus uses a 64-bit wide,
1333 MHz data bus that transfers data at 10.7 GB/sec. The MCH chipset connects
up to 8 Fully Buffered DIMM modules, providing up to 32 GB of DDR2 FBD ECC
memory. The MCH chipset also provides three x8 PCI-Express interface to the
ESB2. In addition, the 5000P/5000X chipset offers a wide range of RAS features,
including memory interface ECC, x4/x8 Single Device Data Correction, CRC, parity
protection, memory mirroring and memory sparing.
Xeon Quad-core/Dual-core Processor Features
Designed to be used with conjunction of the 5000P/5000X chipset, the Xeon Quadcore/Dual-core Processor provides a feature set as follows:
The Xeon Quad-core/Dual-core Processor
*L1 Cache Size: Instruction Cache (32KB/16KB), Data Cache (32KB/24KB)
*L2 Cache Size: 4MB/2MB (per core)
*Data Bus Transfer Rate: 8.5 GB/s
*Package: FC-LGA6/FC-LGA4, 771 Lands
1-9
X7DBU/X7DGU User's Manual
1-3 Special Features
Recovery from AC Power Loss
BIOS provides a setting for you to determine how the system will respond when
AC power is lost and then restored to the system. You can choose for the system
to remain powered off (in which case you must hit the power switch to turn it back
on) or for it to automatically return to a power- on state. See the Power Lost Control setting in the Advanced section (Boot Features) to change this setting. (Note:
Default: Last State).
1-4 PC Health Monitoring
This section describes the PC health monitoring features of the X7DBU/X7DGU.
All have an onboard System Hardware Monitor chip that supports PC health monitoring.
Onboard Voltage Monitors for CPU Cores, Memory, Chipset, HT,
+1.8V, +3.3V, +5V, +12V, −12V, +3.3V Standby, +5V standby and
VBAT
An onboard voltage monitor will scan these voltages continuously. Once a voltage
becomes unstable, a warning is given or an error message is sent to the screen.
Users can adjust the voltage thresholds to defi ne the sensitivity of the voltage
monitor.
Fan Status Monitor with Firmware Control
The PC health monitor can check the RPM status of the cooling fans. The onboard
CPU and chassis fans are controlled by Thermal Management via BIOS (under
Hardware Monitoring in the Advanced Setting).
Environmental Temperature Control
The thermal control sensor monitors the CPU temperature in real time and will turn
on the thermal control fan whenever the CPU temperature exceeds a user-defi ned
threshold. The overheat circuitry runs independently from the CPU. Once it detects
that the CPU temperature is too high, it will automatically turn on the thermal fan
control to prevent any overheat damage to the CPU. The onboard chassis thermal
circuitry can monitor the overall system temperature and alert users when the chassis temperature is too high.
1-10
Chapter 1: Introduction
System Resource Alert
This feature is available when used with Supero Doctor III in the Windows OS
environment or used with Supero Doctor II in Linux. Supero Doctor is used to
notify the user of certain system events. For example, if the system is running low
on virtual memory and there is insuffi cient hard drive space for saving the data,
you can be alerted of the potential problem. You can also confi gure Supero Doctor
to provide you with warnings when the system temperature goes beyond a predefi ned range.
1-5 ACPI Features
ACPI stands for Advanced Confi guration and Power Interface. The ACPI specifi -
cation defi nes a fl exible and abstract hardware interface that provides a standard
way to integrate power management features throughout a PC system, including
its hardware, operating system and application software. This enables the system
to automatically turn on and off peripherals such as CD-ROMs, network cards, hard
disk drives and printers. This also includes consumer devices connected to the PC
such as VCRs, TVs, telephones and stereos.
In addition to enabling operating system-directed power management, ACPI
provides a generic system event mechanism for Plug and Play and an operating
system-independent interface for confi guration control. ACPI leverages the Plug
and Play BIOS data structures while providing a processor architecture-independent
implementation that is compatible with Windows 2000, Windows XP and Windows
2003 Server Operating Systems.
Slow Blinking LED for Suspend-State Indicator
When the CPU goes into a suspend state, the chassis power LED will start blinking
to indicate that the CPU is in suspend mode. When the user presses any key, the
CPU will wake-up and the LED will automatically stop blinking and remain on.
Main Switch Override Mechanism
When an ATX power supply is used, the power button can function as a system suspend button to make the system enter a SoftOff state. The monitor will be suspended
and the hard drive will spin down. Pressing the power button again to "wake-up" the
whole system. During the SoftOff state, the ATX power supply provides power to
keep the required circuitry in the system "alive." In case the system malfunctions and
you want to turn off the power, just press and hold the power button for 4 seconds.
This option can be set in the Power section of the BIOS Setup routine.
1-11
X7DBU/X7DGU User's Manual
External Modem Ring-On
Wake-up events can be triggered by a device such as the external modem ringing
when the system is in the SoftOff state. Note that external modem ring-on can only
be used with an ATX 2.01 (or above) compliant power supply.
Wake-On-LAN (WOL)
Wake-On-LAN is defi ned as the ability of a management application to remotely
power up a computer that is powered off. Remote PC setup, up-dates and asset
tracking can occur after hours and on weekends so that daily LAN traffi c is kept
to a minimum and users are not interrupted. The motherboard has a 3-pin header
(WOL) to connect to the 3-pin header on a Network Interface Card (NIC) that has
WOL capability. In addition, an onboard LAN controller can also support WOL
without any connection to the WOL header. The 3-pin WOL header is to be used
with a LAN add-on card only.
Note: Wake-On-LAN requires an ATX 2.01 (or above) compliant power supply.
1-6 Power Supply
As with all computer products, a stable power source is necessary for proper and
reliable operation. It is even more important for processors that have high CPU
clock rates.
The X7DBU/X7DGU can only accommodate 20-pin ATX power supplies. Although
most power supplies generally meet the specifi cations required by the CPU, some
are inadequate. The 12V 4-pin and the 12V 8-pin power connections are also required to ensure adequate power supply to the system. In addition, the UIO power
connector, located at J11, is required to supply power to Universal IO slots. Also
your power supply must supply 1.5A for the Ethernet ports.
It is strongly recommended that you use a high quality power supply that meets ATX
power supply Specifi cation 2.01 or above. It must also be SSI compliant (info at
http://www.ssiforum.org/). Additionally, in areas where noisy power transmission is
present, you may choose to install a line fi lter to shield the computer from noise. It
is recommended that you also install a power surge protector to help avoid problems
caused by power surges.
1-12
Chapter 1: Introduction
1-7 Super I/O
The disk drive adapter functions of the Super I/O chip include a fl oppy disk drive
controller that is compatible with industry standard 82077/765, a data separator,
write pre-compensation circuitry, decode logic, data rate selection, a clock generator, drive interface control logic and interrupt and DMA logic. The wide range of
functions integrated onto the Super I/O greatly reduces the number of components
required for interfacing with fl oppy disk drives. The Super I/O supports 360 K, 720
K, 1.2 M, 1.44 M or 2.88 M disk drives and data transfer rates of 250 Kb/s, 500 Kb/s
or 1 Mb/s. It also provides two high-speed, 16550 compatible serial communication
ports (UARTs). Each UART includes a 16-byte send/receive FIFO, a programmable
baud rate generator, complete modem control capability and a processor interrupt
system. Both UARTs provide legacy speed with baud rate of up to 115.2 Kbps
as well as an advanced speed with baud rates of 250 K, 500 K, or 1 Mb/s, which
support higher speed modems.
The Super I/O provides functions that comply with ACPI (Advanced Confi guration
and Power Interface), which includes support of legacy and ACPI power management through an SMI or SCI function pin. It also features auto power management
to reduce power consumption.
The IRQs, DMAs and I/O space resources of the Super I/O can fl exibly adjust
to meet ISA PnP requirements, which support ACPI and APM (Advanced Power
Management).
1-13
X7DBU/X7DGU User's Manual
Notes
1-14
Chapter 2: Installation
Chapter 2
Installation
2-1 Static-Sensitive Devices
Electro-Static-Discharge (ESD) can damage electronic com ponents. To prevent
damage to your system board, it is important to handle it very carefully . The following
measures are generally suffi cient to protect your equipment from ESD.
Precautions
• Use a grounded wrist strap designed to prevent static discharge.
• Touch a grounded metal object before removing the board from the antistatic
bag.
• Handle the board by its edges only; do not touch its components, peripheral
chips, memory modules or gold contacts.
• When handling chips or modules, avoid touching their pins.
• Put the motherboard and peripherals back into their antistatic bags when not in
use.
• For grounding purposes, make sure your computer chassis provides excellent
conductivity between the power supply, the case, the mounting fasteners and
the motherboard.
• Use only the correct type of onboard CMOS battery as specifi ed by the manu-
facturer. Do not install the onboard battery upside down to avoid possible explosion.
Unpacking
The motherboard is shipped in antistatic packaging to avoid static damage. When
unpacking the board, make sure the person handling it is static protected.
2-1
X7DBU/X7DGU User's Manual
!
2-2 Processor and Heatsink Installation
When handling the processor package, avoid placing
direct pressure on the label area of the fan.
(Notes: 1. Always connect the power cord last and always remove it before adding,
removing or changing any components. Make sure that you install the processor
into the CPU socket before you install the CPU heatsink.
2. Intel's boxed Xeon CPU package contains the CPU fan and heatsink assembly.
If you buy a CPU separately, make sure that you use only Intel-certifi ed multi-di-
rectional heatsink and fan.
3. Make sure to install the motherboard into the chassis before you install the CPU
heatsink and fan.
4. When purchasing an LGA 771 CPU or when receiving a motherboard with an LGA
771 CPU pre-installed, make sure that the CPU plastic cap is in place and none of
the CPU pins are bent; otherwise, contact the retailer immediately.
5. Refer to the MB Features Section for more details on CPU support.
Installation of the LGA771 Processor
Socket Clip
Load Plate
1. Press the socket clip to release
the load plate, which covers the CPU
socket, from its locking position.
2. Gently lift the socket clip to open the
load plate.
Load Plate
2-2
3. Use your thumb and your index fi nger
!
to hold the CPU at the North Center
Edge and the South Center Edge of
the CPU.
4. Align CPU Pin1 (the CPU corner
marked with a triangle) against the
socket corner that is marked with a
triangle cutout.
5. Align the CPU key that is the semi-
circle cutout below a gold dot against the
socket key , the notch on the same side of
the triangle cutout on the socket.
6. Once aligned, carefully lower the CPU
straight down to the socket. (**Do not
drop the CPU on the socket. Do not
move the CPU horizontally or vertically.
Do not rub the CPU against the surface
or against any pins of the socket to avoid
damage to the CPU or the socket.)
North Center Edge
South Center Edge
Socket Key
(Socket Notch)
CPU Key
(semi-circle
cutout) below
the circle.
Corner with a
triangle cutout
Chapter 2: Installation
gold dot
CPU Pin1
7. With the CPU inside the socket,
inspect the four corners of the CPU
to make sure that the CPU is properly
installed.
8. Use your thumb to gently push the
socket clip down to the clip lock.
9. If the CPU is properly installed into
the socket, the plastic cap will be automatically released from the load plate
when the clip is pushed into the clip
lock. Remove the plastic cap from the
motherboard.
(Warning: Please keep the plastic
cap. The motherboard and the CPU
must be shipped with the plastic cap
properly installed to protect the CPU
pins. Shipment without the CPU plastic
cap properly installed will void the warranty.)
Socket clip
CPU in the CPU socket
Plastic cap
is released
from the
load plate
if the CPU
is properly
installed.
2-3
X7DBU/X7DGU User's Manual
!
Installation of the Heatsink
CEK Heatsink Installation
1. Do not apply any thermal grease to
the heatsink or the CPU die-the required
amount has already been applied.
2. Place the heatsink on top of the CPU so
that the four mounting holes are aligned with
those on the retention mechanism.
3. Screw in two diagonal screws (ie the #1
and the #2 screws) until just snug. Do not
fully tighten the screws to avoid possible
damage to the CPU.
4. Finish the installation by fully tightening
all four screws.
CEK Passive Heatsink
Screw#1
Screw#1
Screw#2
To Un-install the Heatsink
(Warning: We do not recommend that
the CPU or the heatsink be removed.
However, if you do need to uninstall
the heatsink, please follow the instructions below to uninstall the heatsink to
avoid damage done to the CPU or the
CPU socket.)
Screw#2
2-4
Chapter 2: Installation
1. Unscrew and remove the heatsink screws
from the motherboard in the sequence as show
in the picture on the right.
2. Hold the heatsink as shown in the picture
on the right and gently wiggle the heatsink to
loosen it from the CPU. (Do not use excessive
force when wiggling the heatsink!!)
3. Once the heatsink is loosened, remove the
heatsink from the CPU socket.
4. Clean the surface of the CPU and the
heatsink to get rid of the old thermal grease.
Reapply the proper amount of thermal grease
on the surface before you re-install the CPU
and the heatsink.
Screw#1
Screw#4
Screw#3
Screw#2
Mounting the Motherboard in the Chassis
All motherboards have standard mounting holes to fi t different types of chas-
sis. Make sure that the locations of all the mounting holes for both motherboard
and chassis match. Make sure that the metal standoffs click in or are screwed in
tightly. Then, use a screwdriver to secure the motherboard onto the motherboard
tray. (Note: some components are very close to the mounting holes. Please take
precautionary measures to prevent damage done to these components when you
install the motherboard to the chassis.)
2-5
X7DBU/X7DGU User's Manual
2-3 Installing DIMMs
Note: Check the Supermicro web site for recommended memory modules.
CAUTION
Exercise extreme care when installing or removing DIMM
modules to prevent any possible damage. Also note that the
memory is interleaved to improve performance (see step 1).
DIMM Installation
1. Insert the desired number of DIMMs into the memory slots, starting with DIMM
#1A. The memory scheme is interleaved so you must install two modules
at a time, beginning with DIMM #1A, then DIMM #2A and so on. (*See the
Memory Installation Table Below.)
2. Insert each DIMM module vertically into its slot. Pay attention to the notch along
the bottom of the module to prevent inserting the DIMM module incorrectly.
3. Gently press down on the DIMM module until it snaps into place in the slot.
Repeat for all modules (see step 1 above).
Memory Support
The X7DBU/X7DGU supports up to 32 GB fully buffered (FBD) ECC DDR2 667/533
in 8 DIMMs. Populating DIMM modules with pairs of memory modules of the
same size and same type will result in Interleaved Memory which will increase
memory performance.
Optimized DIMM Population Configurations
Branch 0 Branch 1
Number of
DIMMs
2 DIMMs 1A --- 2A --- --- --- --- --4 DIMMs 1A --- 2A --- 3A --- 4A --6 DIMMs 1A 1B 2A 2B 3A --- 4A --8 DIMMs 1A 1B 2A 2B 3A 3B 4A 4B
(*Notes: i. DIMM slot# specified: DIMM slot to be populated; “--
-“: DIMM slot not to be populated. ii. Both FBD 533 MHz and
667MHz DIMMs are supported; however, you need to use the
memory modules of the same speed and of the same type on a
motherboard. iii. Interleaved memory is supported when pairs
of DIMM modules are installed. For best performance, please
install memory modules in both
memory to work properly, you need to follow the restrictions
listed above. )
Bank 1
(Channel 0)
Bank 2
(Channel 1)
Bank 3
(Channel 2)
Branch 0 and Branch 1. iv. For
Bank 4
(Channel 3)
Note 1: Due to OS limitations, some operating systems may not show more than
4 GB of memory.
Note 2: Due to memory allocation to system devices, memory remaining available
for operational use will be reduced when 4 GB of RAM is used. The reduction in
memory availability is disproportional. (Refer to the Memory Availability Table on
the next page for details.)
2-6
D
D lot
Possible System Memory Allocation & Availability
Chapter 2: Installation
System Device Size Physical Memory
Remaining (-Available)
(4 GB Total System Memory)
Firmware Hub fl ash memory
1 MB 3.99
(System BIOS)
Local APIC 4 KB 3.99
Area Reserved for the
2 MB 3.99
chipset
I/O APIC (4 Kbytes) 4 KB 3.99
PCI Enumeration Area 1 256 MB 3.76
PCI Express (256 MB) 256 MB 3.51
PCI Enumeration Area 2
512 MB 3.01
(if needed) -Aligned on
256-MB boundary-
VGA Memory 16 MB 2.85
TSEG 1 MB 2.84
Memory available to System
2.84
BIOS & OS applications
7
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Intel 5000
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Use your thumbs to gently
push the release tabs near
both ends of the module.
This should release it from
the slot.
Installing and Removing DIMMs
R
R
W
W
P
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in
in
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4
3
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CPU2
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To Install: Insert module vertically and press down until it
snaps into place. Pay attention to the alignment notch at
the bottom.
2-7
X7DBU/X7DGU User's Manual
1
2
3
4
5
6
7
8
9
2-4 Control Panel Connectors/IO Ports
The I/O ports are color coded in conformance with the PC 99 specifi cation. See the
fi gure below for the colors and locations of the various I/O ports.
A. Back Panel Connectors/IO Ports
R
R
W
W
P
P
in
in
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-P
8
7
n7
Fa
1
Intel 5000
(North Bridge)
2
XB
S
1
B
SX
J1
B
M
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R
PW
1
an
F
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B
4
M
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4
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3B
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A
3
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B
2
M
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A
2
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1B
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D
A
1
M
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C
: P
J9
J5
6
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: P
Intel ESB2
(South Bridge)
1
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Back Panel I/O Port Locations and Defi nitions
Back Panel Connectors
1. Keyboard (Purple)
2. PS/2 Mouse (Green)
3. Back Panel USB Port 0
4. Back Panel USB Port 1
5. COM Port 1 (Turquoise)
6. VGA Port (Blue) 7. Gigabit LAN 1
8. Gigabit LAN 2
9. Rear UID Switch
(See Section 2-5 for details.)
2-8
Chapter 2: Installation
o
o
B. Front Control Panel
JF1 contains header pins for various buttons and indicators that are normally located
on a control panel at the front of the chassis. These connectors are designed specifi -
cally for use with Supermicro server chassis. See the fi gure for the descriptions of
the various control panel buttons and LED indicators. Refer to the following section
for descriptions and pin defi nitions.
JF1 Header Pins
R
R
4-Pin PW
8-Pin PW
Fan7
Intel 5000
(North Bridge)
SXB2: PCI-E x8
SXB1: PCI-E x16
J17
B
PWR SM
Fan1
CPU
4B
M
DIM
4A
DIMM
3B
DIMM
3A
M
DIM
2B
DIMM
DIM
DIMM
DIM
CPU1
M2A
1B
1A
M
CPU2
J9
J5
I-SATA0
SGPIO1
J29
Intel ESB2
J30
SGPIO2
(South Bridge)
JBT1
ory
J7
OR1
JW
em
JPG1
ES1000
Video M
Video CTRL
D
JW
JK1
OL1
JW
COM2
JPL2
JPL1
PCI-X 133 M
Buzzer
SP1
I2C1
I2C2
J27
J28
Hz
X7DBU
S
Fan6
Fan5
KB/M
JKM1
J9B2
Bank4
J9B1
USB 0/1
J8B3
Bank3
J8B2
COM1
J8B1
Bank2
1
JCOM
J7B3
Battery
J7B2
Bank1
VGA
J7B1
J15
LAN1
1
JLAN
LAN2
JLAN2
LAN
1
CTRL
Rear UID
LE2
SW
J14
J11
R
UIO PW
3
2
JPW
JPW
1
JPW
R
ain PW
20-Pin M
Fan1
JF1
FP CTRL
Fan2
JD1
LE1
JOH1
JP1
Fan3
Fan8
FAN2
CPU
I-SATA4
I-SATA2
I-SATA3
I-SATA5
I-SATA1
E#1
ID
SIMSO
BIOS
SB4
U
Floppy
J18
J22
B
SM
S I/O
OH/Fan Fail/
JL1
USB2/3
Fan4
PWR Fail/UID LED
Ground
X
Power LED
HDD LED
NIC1 LED
NIC2 LED
PWR Fail LED
Ground
Ground
1920
NMI
X
Vcc
UID Switch/Vcc
Vcc
Vcc
Blue_LED_Cathode
(UID)/Vcc
Vcc
Reset
PWR
1
2
FP Reset Butt
FP Power Butt
2-9
X7DBU/X7DGU User's Manual
o
o
C. Front Control Panel Pin Defi nitions
NMI Button
The non-maskable interrupt button
header is located on pins 19 and 20
of JF1. Refer to the table on the right
for pin defi nitions.
Power LED
The Power LED connection is located
on pins 15 and 16 of JF1. Refer to the
table on the right for pin defi nitions.
NMI Button
Pin Defi nitions (JF1)
Pin# Defi nition
19 Control
20 Ground
Power LED
Pin Defi nitions (JF1)
Pin# Defi nition
15 +5V
16 Ground
A. NMI
8-Pin PWR
Fan7
Fan5
Fan6
KB/MS
JKM1
J9B2
Bank4
J9B1
USB 0/1
J8B3
Bank3
J8B2
COM1
J8B1
Bank2
JCOM1
J7B3
Battery
J7B2
Bank1
VGA
J7B1
J15
LAN1
JLAN1
LAN2
JLAN2
LAN
CTRL
Rear UID
LE2
SW1
UIO PWR
PCI-X 133 MHz
J14
J11
Buzzer
SP1
Intel 5000
(North Bridge)
I2C1
I2C2
J27
J28
X7DBU
SXB2: PCI-E x8
SXB1: PCI-E x16
CPU Fan1
DIMM4B
DIMM4A
DIMM3B
DIMM3A
DIMM2B
DIMM2A
DIMM1B
DIMM1A
PWR SMB
J17
J9
JWOR1
JPG1
COM2
J5
Intel ESB2
(South Bridge)
ES1000
Video CTRL
JBT1
J7
JPL1
4-Pin PWR
JPW3
JPW2
JPW1
20-Pin Main PWR
Fan1
I-SATA4
USB2/3
I-SATA5
CPU FAN2
SMB
JF1
FP CTRL
B
Fan2
JD1
LE1
JOH1
JP1
Fan3
Fan8
IDE#1
SIMSO
Floppy
J18
J22
JL1
Fan4
OH/Fan Fail/
PWR Fail/UID LED
CPU1
CPU2
I-SATA3
I-SATA2
I-SATA1
I-SATA0
SGPIO1
J29
J30
SGPIO2
BIOS
Video Memory
JWD
JK1
S I/O
JWOL1
JPL2
USB4
Ground
X
Power LED
HDD LED
NIC1 LED
NIC2 LED
PWR Fail LED
Ground
Ground
2-10
B. PWR LED
1920
NMI
X
Vcc
UID Switch/Vcc
Vcc
Vcc
Blue_LED_Cathode
(UID)/Vcc
Vcc
Reset
PWR
1
2
A
FP Reset Butt
FP Power Butt
Chapter 2: Installation
o
o
D
HDD LED/FP UID Switch
The Front Panel UID Switch connection is
located on pin 13 of JF1. Connect a cable
with a switch attached to pin 13 of JF1 to
provide Unit Identifi cation to your system.
(*For more information on the UID Switches, please refer to UID Switches on Page
2-22.) The HDD LED connection is located
on pins 13 (Vcc) and 14 of JF1. Attach the
hard drive LED cable here to display disk
activity (for any hard drives on the system,
including Serial ATA and IDE). See the table
on the right for pin defi nitions.
NIC1/NIC2 LED Indicators
The NIC (Network Interface Controller) LED
connection for GLAN port1 is located on
pins 11 and 12 of JF1 and the LED connection for GLAN Port2 is on Pins 9 and
10. Attach the NIC LED cables to display
network activity. Refer to the table on the
right for pin defi nitions.
HDD LED
Pin Defi nitions (JF1)
Pin# Defi nition
13 UID Switch/+5V (for HDD
Act)
14 HD Active
GLAN1/2 LED
Pin Defi nitions (JF1)
Pin# Defi nition
9/11 Vcc
10/12 PWR Fail
A. FP UID Switch
B. HDD LED
C. NIC1 LED
D. NIC2 LED
R
R
W
W
P
P
in
in
-P
-P
8
7
Fan7
1
r
e
z
uz
Fan5
Fan6
KB/MS
KM1
J
J9B2
Bank4
J9B1
USB 0/1
J8B3
Bank3
J8B2
COM1
J8B1
Bank2
M1
O
C
J
J7B3
ry
atte
B
J7B2
Bank1
VGA
J7B1
5
1
J
LAN1
1
N
A
L
J
LAN2
2
N
LA
J
N
LA
L
R
T
C
Rear UID
LE2
SW1
W
P
UIO
I-X
C
P
J14
J11
R
B
1
SP
nte
I
(North Brid
1
C
I2
2
C
I2
7
2
J
8
2
J
Hz
M
3
3
1
X7DBU
SX
XB1
S
J
B
SM
R
W
P
Fan1
U
P
C
B
IMM4
D
A
IMM4
D
B
IMM3
D
A
IMM3
D
B
M2
M
I
D
A
IMM2
D
B
IMM1
D
A
IMM1
D
0
0
0
5
l
)
e
g
8
x
I-E
C
P
:
2
B
9
J
5
J
6
1
x
I-E
C
P
:
2
B
S
E
l
e
t
In
)
e
ridg
B
th
u
o
S
(
B
J
7
J
1
R
O
W
J
G1
P
J
0
0
0
1
ES
L
R
T
C
o
Vide
M2
O
C
P
J
4
3
2
W
W
P
P
J
J
1
W
P
J
R
W
P
Main
in
P
-
0
2
Fan1
F1
J
L
R
1
PU
C
2
PU
C
2
3
1
A
A
A
T
T
T
A
A
A
-S
-S
I-S
I
I
0
A
T
I-SA
1
SGPIO
9
2
J
0
3
J
2
SGPIO
S
BIO
1
T
emory
M
Video
D
W
J
O
I/
K1
J
S
L1
O
W
J
L2
P
J
4
B
S
U
L1
T
C
FP
Fan2
1
D
J
1
LE
H1
O
J
B
1
P
J
Fan3
C
Fan8
2
N
FA
U
P
C
4
5
A
A
T
T
I-SA
I-SA
1
OH/Fan Fail/
E#
ID
PWR Fail/UID LED
SIMSO
Floppy
8
1
J
2
2
J
SMB
L1
J
3
/
USB2
Fan4
Ground
X
Power LED
HDD LED
NIC1 LED
NIC2 LED
PWR Fail LED
Ground
Ground
1920
NMI
X
Vcc
UID Switch/Vcc
A
Vcc
Vcc
Blue_LED_Cathode
(UID)/Vcc
Vcc
Reset
FP Reset Butt
FP Power Butt
PWR
1
2
2-11
X7DBU/X7DGU User's Manual
o
o
Overheat (OH)/Fan Fail/PWR
Fail/FP UID LED
Connect an LED to the Overheat/Fan
Fail/PWR Fail/UID (Unit ID) LED
connection on pins 7 and 8 of JF1 to
provide advanced warnings of chassis overheating, power failure or fan
failure in addition to providing unit
identifi cation for your system. (*For
more information on UID Switches,
please refer to Pages 2-11 and 2-22.)
Refer to the table on the right for pin
defi nitions.
OH/Fan Fail/PWR Fail/FP UID LED
Pin Defi nitions (JF1)
Pin# Defi nition
7 Blue_LED_Cathode (UID)
8 OH_Fan Fail_PWR
Fail_UID
OH/Fan Fail/PWR Fail/FP UID Indica-
tor Status
State Defi nition
Off System Normal
Red On Overheat
Red Flashing Fan Fail/PWR Fail
Blue On FP UID
Power Fail LED
The Power Fail LED connection is
located on pins 5 and 6 of JF1. Refer to the table on the right for pin
defi nitions.
7
Fan7
1
r
e
z
uz
Fan5
Fan6
KB/MS
KM1
J
J9B2
Bank4
J9B1
USB 0/1
J8B3
Bank3
J8B2
COM1
J8B1
Bank2
M1
O
C
J
J7B3
ry
Batte
J7B2
Bank1
VGA
J7B1
5
1
J
LAN1
1
N
A
L
J
LAN2
2
N
LA
J
N
LA
L
R
T
C
Rear UID
LE2
SW1
W
P
UIO
I-X
C
P
J14
J11
R
B
1
SP
nte
I
(North Brid
1
C
I2
2
C
I2
7
2
J
8
2
J
Hz
M
3
3
1
X7DBU
SX
SXB1
J
B
SM
R
W
P
Fan1
U
P
C
B
IMM4
D
A
IMM4
D
B
IMM3
D
A
IMM3
D
B
M2
M
I
D
A
IMM2
D
B
IMM1
D
A
IMM1
D
0
0
0
5
l
)
e
g
8
x
I-E
C
P
:
2
B
9
J
6
1
x
I-E
C
P
:
O
W
J
G1
P
J
C
1
PU
C
2
PU
C
5
J
2
J
2
B
S
E
l
e
t
In
3
J
)
e
ridg
B
th
u
o
S
(
1
T
B
J
7
J
1
R
0
0
0
1
ES
L
R
T
C
o
Vide
O
W
J
K1
J
O
W
J
M2
L1
P
J
PWR Fail LED
Pin Defi nitions (JF1)
Pin# Defi nition
5 Vcc
6 Ground
A. OH/Fan Fail/PWR Fail/UIE LED
B. PWR Supply Fail
R
R
W
W
P
P
in
in
-P
-P
8
4
3
2
W
W
P
P
J
J
1
W
P
J
R
W
P
Main
in
P
-
0
2
Fan1
F1
J
TRL
C
FP
Fan2
1
D
J
1
LE
H1
O
J
1
P
J
Fan3
Fan8
2
N
FA
U
P
C
4
2
3
5
1
A
A
A
A
A
T
T
T
T
T
A
A
A
-S
-S
I-SA
I-S
I
I-SA
I
0
A
T
I-SA
1
SGPIO
9
0
2
SGPIO
S
IO
B
ry
Memo
ideo
V
D
O
I/
S
L1
USB2
L2
P
J
4
B
S
U
OH/Fan Fail/
A
1
E#
PWR Fail/UID LED
ID
SIMSO
B
Floppy
8
1
J
2
2
J
SMB
L1
J
3
/
Fan4
Ground
X
Power LED
HDD LED
NIC1 LED
NIC2 LED
PWR Fail LED
Ground
Ground
1920
NMI
X
Vcc
UID Switch/Vcc
Vcc
Vcc
Blue_LED_Cathode
(UID)/Vcc
Vcc
Reset
FP Reset Butt
FP Power Butt
PWR
1
2
2-12
Chapter 2: Installation
o
o
Reset Button
The Reset Button connection is located
on pins 3 and 4 of JF1. Attach it to the
hardware reset switch on the computer
case. Refer to the table on the right for
pin defi nitions.
Power Button
The Power Button connection is located
on pins 1 and 2 of JF1. Momentarily
contacting both pins will power on/off
the system. This button can also be
confi gured to function as a suspend but-
ton (with a setting in BIOS - see Chapter
4). To turn off the power when set to
suspend mode, press the button for at
least 4 seconds. Refer to the table on
the right for pin defi nitions.
Reset Button
Pin Defi nitions (JF1)
Pin# Defi nition
3 Reset
4 Ground
Power Button
Pin Defi nitions (JF1)
Pin# Defi nition
1 Signal
2 +3V Standby
A. Reset Button
B. PWR Button
R
R
W
W
P
P
in
in
-P
-P
8
7
Fan7
1
r
e
Fan5
Fan6
KB/MS
M1
K
J
J9B2
Bank4
J9B1
USB 0/1
J8B3
Bank3
J8B2
COM1
J8B1
Bank2
1
M
O
C
J
J7B3
ry
e
att
B
J7B2
Bank1
VGA
J7B1
5
1
J
LAN1
1
N
LA
J
LAN2
2
N
LA
J
N
LA
L
R
T
C
Rear UID
LE2
SW1
W
P
UIO
I-X
C
P
J14
J11
R
Buzz
SP1
nte
I
th Bri
(Nor
1
C
I2
2
C
I2
7
2
J
8
2
J
MHz
3
3
1
X7DBU
SXB2
SXB1
J
SMB
R
W
P
Fan1
U
P
C
B
IMM4
D
A
IMM4
D
B
IMM3
D
A
IMM3
D
B
IMM2
D
A
IMM2
D
B
IMM1
D
A
IMM1
D
0
0
0
5
l
)
ge
d
x8
E
-
I
C
P
:
9
J
5
J
6
x1
I-E
C
P
:
2
B
S
E
tel
n
I
e)
g
rid
B
th
u
So
(
BT1
J
7
J
1
R
O
W
J
G1
P
J
0
0
0
1
S
E
L
R
T
C
o
ide
V
M2
O
C
P
J
4
3
2
W
W
P
P
J
J
1
W
P
J
R
W
P
Main
n
i
-P
0
2
Fan1
F1
J
L
R
1
PU
C
2
PU
C
2
3
1
A
A
A
T
T
T
A
A
A
-S
-S
I-S
I
I
0
A
T
I-SA
1
IO
GP
S
9
2
J
0
3
J
2
IO
GP
S
S
BIO
ry
Memo
Video
D
W
J
O
I/
1
K
J
S
L1
O
W
J
L2
P
J
4
B
US
L1
T
C
FP
Fan2
1
D
J
LE1
H1
O
J
1
P
J
Fan3
Fan8
2
N
A
F
U
P
C
4
5
A
A
T
T
I-SA
I-SA
OH/Fan Fail/
1
E#
PWR Fail/UID LED
ID
SIMSO
Floppy
8
1
J
2
2
J
MB
S
L1
J
3
/
USB2
Fan4
Ground
X
Power LED
HDD LED
NIC1 LED
NIC2 LED
PWR Fail LED
Ground
Ground
1920
NMI
X
Vcc
UID Switch/Vcc
Vcc
Vcc
Blue_LED_Cathode
(UID)/Vcc
Vcc
A
Reset
FP Reset Butt
FP Power Butt
PWR
1
2
B
2-13
X7DBU/X7DGU User's Manual
D
2-5 Connecting Cables
ATX Power Connector
There are a 20-pin main power supply
connector(JPW1) and an 8-pin CPU
PWR connector (JPW3) on the motherboard. These power connectors
meet the SSI EPS 12V specifi cation.
The 4-pin 12V PWR supply is required
to provide adequate power to the system. The UIO PWR, located at J11, is
also required for the UIO slots. For the
8-pin PWR (JPW3), please refer to the
item listed below. See the table on the
right for pin defi nitions.
Processor Power Connector
In addition to the Primary ATX power
connector (above), the 12V 8-pin CPU
PWR connector at JPW3 must also
be connected to your power supply.
See the table on the right for pin
defi nitions.
7
an
COM
J
VGA
15
J
J
LA
J
KB/MS
USB 0/1
COM1
LAN1
LA
LAN2
LE2
P1
S
X7DBU
Nor
(
ntel 500
I
h Br
t
XB2:
S
XB1:
S
F
idge)
PCI-E
PCI-E
r
e
zz
J
N
N2
UI
J9B2
Bank4
J9B1
J8B3
Bank3
J8B2
J8B1
Bank2
1
J7B3
y
r
e
Batt
J7B2
Bank1
J7B1
1
N
LA
RL
T
C
Rear UID
SW1
J11
R
PW
O
133 M
PCI-X
J14
5
n
Fa
6
n
Fa
KM1
Bu
I2C1
I2C2
27
J
28
J
Hz
17
J
B
M
S
R
PW
1
an
F
CPU
4B
IMM
D
4A
IMM
D
B
3
IMM
D
3A
IMM
D
2B
IMM
D
2A
IMM
D
1B
IMM
D
1A
M
IM
D
0
x8
9
J
5
J
x16
Inte
outh B
(S
OR1
W
J
PG1
J
10
S
E
e
id
V
2
M
CO
ATX Power 20-pin Connector
Pin Defi nitions
Pin# Defi nition Pin # Defi nition
11 +3.3V 1 +3.3V
12 -12V 2 +3.3V
13 COM 3 COM
14 PS_ON 4 +5V
15 COM 5 COM
16 COM 6 +5V
17 COM 7 COM
18 Res (NC) 8 PWR_OK
19 +5V 9 5VSB
20 +5V 10 +12V
12V 4-pin Power Con-
nector
Pin Defi nitions
Pins Defi nition
1 and 2 Ground
3 and 4 +12V
Required Connection
12V 8-pin Power CPU
Connector
Pin Defi nitions
Pins Defi nition
1 through 4 Ground
B
C
PW
4-Pin
2
PW
J
1
PW
J
-P
20
A
U1
P
C
U2
P
C
4
3
2
5
1
A
A
A
A
A
T
T
T
T
T
A
A
A
S
S
I-SA
I-
I-SA
I-
I-S
0
A
T
A
I-S
1
GPIO
S
29
J
2
B
S
E
l
00
CT
o
RL
ridge
30
J
GPIO2
S
)
S
IO
B
y
r
1
BT
J
o
7
J
m
e
M
o
e
Vid
D
W
J
I/O
K1
J
S
OL1
W
J
PL2
J
PL1
J
B2/3
US
4
B
US
5 through 8 +12V
R
R
PW
8-Pin
3
JPW
R
PW
in
a
M
in
Fan1
1
F
J
RL
CT
P
F
2
an
F
1
D
J
1
LE
OH1
J
P1
J
3
an
F
8
an
F
N2
A
F
CPU
1
#
E
ID
O
S
IM
S
y
p
p
lo
F
8
1
J
22
J
MB
S
L1
J
4
an
F
A. ATX Main PWR
B. 8-pin Processor PWR
C. 4-pin PWR
D. UIO PWR
2-14
Chapter 2: Installation
D
Universal Serial Bus (USB)
There are fi ve USB 2.0 (Universal
Serial Bus) ports/headers on the
motherboard. Two of them are Back
Panel USB ports (USB#0/1), and the
other are Front Panel USB headers
(USB#2/3, USB#4). See the tables on
the right for pin defi nitions.
Chassis Intrusion
A Chassis Intrusion header is located
at JL1. Attach the appropriate cable
from the chassis to inform you of a
chassis intrusion when the chassis
is opened.
Back Panel USB
(USB 0/1)
Pin# Defi nitions
1 +5V
2 PO3 PO+
4 Ground
5 N/A
Front Panel USB
Pin Defi nitions (USB 2/3/4)
USB2/4
Pin # Defi nition
USB3
Pin # Defi nition
1 +5V 1 +5V
2 PO- 2 PO3 PO+ 3 PO+
4 Ground 4 Ground
5 Key 5 No connection
Chassis Intrusion
Pin Defi nitions (JL1)
Pin# Defi nition
1 Intrusion Input
2 Ground
R
R
PW
PW
4-Pin
8-Pin
P1
S
X7DBU
ntel 5000
I
Nor
(
S
F
dge)
i
h Br
t
PCI-E
XB2:
PCI-E
XB1:
S
r
e
zz
5
n
Fa
6
n
a
KB/MS
USB 0/1
COM1
COM
J
VGA
15
J
LAN1
LA
J
LAN2
LA
J
LE2
F
KM1
J
N
N2
SW1
UI
1
1
O
Rear UID
PW
J9B2
Bank4
J9B1
A
J8B3
Bank3
J8B2
J8B1
Bank2
J7B3
y
r
e
Batt
J7B2
Bank1
J7B1
N
LA
RL
T
C
133 M
PCI-X
J14
J11
R
Bu
I2C1
I2C2
27
J
28
J
Hz
J17
B
M
S
R
PW
1
an
F
CPU
4B
IMM
D
4A
IMM
D
B
3
IMM
D
3A
IMM
D
2B
IMM
D
2A
IMM
D
1B
IMM
D
1A
M
IM
D
x8
9
J
5
J
x16
Inte
outh B
(S
OR1
W
J
PG1
J
S
E
e
id
V
2
M
CO
U1
P
C
U2
P
C
29
J
2
B
S
E
l
30
J
)
ridge
1
BT
J
7
J
0
0
10
RL
CT
o
W
J
K1
J
OL1
W
J
PL1
J
JPW1
4
3
2
1
A
A
A
A
T
T
T
T
A
A
A
S
I-SA
I-
I-S
I-S
0
A
T
A
-S
I
1
GPIO
S
GPIO2
S
S
IO
B
y
r
o
m
e
M
o
e
Vid
D
I/O
S
C
PL2
J
B4
US
7
an
3
2
PW
J
PW
in
a
M
in
-P
20
F
F
F
CPU
5
A
T
A
S
I-
B
M
S
B
L1
J
/3
2
B
US
A. Backpanel USB 0/1
PW
J
B. Front Panel USB 2/3
R
C. Front Panel USB 4
1
an
F
1
F
J
D. Chassis Intrusion
RL
CT
P
F
2
an
1
D
J
1
LE
OH1
J
P1
J
3
an
F
8
an
N2
A
1
#
E
ID
O
S
IM
S
y
p
p
lo
F
8
1
J
22
J
4
an
F
2-15
X7DBU/X7DGU User's Manual
G
F
E
D
H
I
Fan Headers
The X7DBU/X7DGU has eight chassis/system
fan headers (Fan1 to Fan8.) Fan1-Fan6 are
chassis/system fans, while Fan7 and Fan8 are
CPU fans. Fan5-Fan8 are 4-pin fan headers.
Pins 1-3 of the 4-pin fan headers are backward
compatible with the traditional 3-pin fans. The
fan speeds for the 4-pin fans are controlled
by Thermal Management via BIOS Hardware
Monitor in the Advanced Setting. The default
setting is Disabled. See the table on the right
for pin defi nitions. (*Note: all these fans are
4-pin fan connectors. However, Pins 1-3 of
the fan headers are backward compatible with
the traditional 3-pin fans.)
Keylock
The keyboard lock connection is designated
JK1. Utilizing this header allows you to inhibit
any actions made on the keyboard, effectively
"locking" it.
3-Pin Fan Header
Pin Defi nitions
Pin# Defi nition
1 Ground
2 +12V
3 Tachometer
4-Pin Fan Header
Pin Defi nitions
Pin# Defi nition
1 Ground
2 +12V
3 Tachometer
4 PWM Signals
Keylock
Pin Defi nitions
Pin# Defi nition
1 Ground
2 Keylock R-N
COM
J
VGA
15
J
J
LA
J
KB/MS
USB 0/1
COM1
LAN1
LA
LAN2
LE2
R
R
PW
PW
4-Pin
8-Pin
P1
S
X7DBU
Nor
(
ntel 500
I
h Br
t
XB2:
S
XB1:
S
F
idge)
PCI-E
PCI-E
r
e
zz
J
N
N2
UI
J9B2
Bank4
J9B1
J8B3
Bank3
J8B2
J8B1
Bank2
1
J7B3
y
r
e
Batt
J7B2
Bank1
J7B1
1
N
LA
RL
T
C
Rear UID
SW1
J11
R
PW
O
133 M
PCI-X
J14
5
n
Fa
6
n
Fa
KM1
Bu
I2C1
I2C2
27
J
28
J
Hz
17
J
B
M
S
R
PW
1
an
F
CPU
4B
IMM
D
4A
IMM
D
B
3
IMM
D
3A
IMM
D
2B
IMM
D
2A
IMM
D
1B
IMM
D
1A
M
IM
D
0
x8
9
J
5
J
x16
Inte
outh B
(S
OR1
W
J
PG1
J
S
E
e
id
V
2
M
CO
U1
P
C
U2
P
C
29
J
2
B
S
E
l
00
10
CT
o
RL
ridge
30
J
)
1
BT
J
7
J
W
J
K1
J
OL1
W
J
PL1
J
1
PW
J
4
3
2
1
A
A
A
A
T
T
T
T
A
A
S
I-SA
I-
I-SA
I-S
0
A
T
A
I-S
1
GPIO
S
GPIO2
S
S
IO
B
y
r
o
m
e
M
o
e
Vid
D
I/O
S
PL2
J
4
B
US
7
an
3
2
PW
JPW
J
R
PW
in
a
M
in
-P
20
Fan1
A
1
F
J
RL
CT
P
F
2
an
F
B
1
D
J
1
LE
OH1
J
P1
J
3
an
F
8
an
F
N2
A
F
CPU
5
A
T
A
S
I-
1
#
E
ID
O
S
IM
S
y
p
p
lo
F
8
1
J
22
J
MB
S
L1
J
B2/3
US
4
an
F
A. Fan1
B. Fan2
C. Fan3
D. Fan4
E. Fan5
F. Fan6
G.Fan7(CPU Fan1)
H.Fan8(CPU Fan2)
C
K.Keylock
2-16
Chapter 2: Installation
ATX PS/2 Keyboard and
PS/2 Mouse Ports
The ATX PS/2 keyboard and the PS/2
mouse ports are located at JKM1. See
the table on the right for pin defi ni-
tions. See the table on the right for
pin defi nitions.
Serial Ports
COM1 (JCOM1) is a connector located on the IO Backpanel and COM2 is
a header located at JCOM2 to provide
front access. See the table on the right
for pin defi nitions.
PS/2 Keyboard and
Mouse Port Pin
Defi nitions
Pin# Defi nition
1 Data
2NC
3 Ground
4 VCC
5 Clock
6NC
Serial Port Pin Defi nitions
(COM1/COM2)
Pin # Defi nition Pin # Defi nition
1 CD 6 DSR
2RD 7RTS
3 TD 8 CTS
4 DTR 9 RI
5 Ground 10 NC
(Pin 10 is available on COM2
only. NC: No Connection.)
R
R
PW
PW
4-Pin
8-Pin
P1
S
X7DBU
F
00
el 50
t
n
I
dg
i
h Br
t
Nor
(
PCI-E
2:
B
X
S
PCI-E
XB1:
S
r
e
z
z
JKM1
USB 0/1
COM1
JCOM
VGA
15
J
LAN1
N
LA
J
LAN2
N2
LA
J
LE2
SW1
U
1
IO
1
Rear UID
PW
J9B2
Bank4
J9B1
J8B3
Bank3
J8B2
B
J8B1
Bank2
J7B3
y
r
e
Batt
J7B2
Bank1
J7B1
N
LA
RL
T
C
J11
R
33 M
1
PCI-X
J14
5
n
a
F
6
n
a
F
A
KB/MS
Bu
I2C1
I2C2
27
J
28
J
Hz
J17
B
M
S
R
PW
1
an
F
CPU
4B
IMM
D
4A
IMM
D
3B
IMM
D
3A
M
IM
D
B
2
IMM
D
2A
IMM
D
1B
IMM
D
1A
M
IM
D
)
e
8
x
9
J
5
J
16
x
Inte
outh B
(S
OR1
W
J
G1
P
J
S
E
e
id
V
C
M2
CO
U1
P
C
2
U
P
C
29
J
2
B
S
E
l
30
J
)
ridge
BT1
J
7
J
0
0
10
RL
CT
o
JW
K1
J
O
W
J
PL1
J
JPW1
4
3
2
1
A
A
A
A
T
T
T
T
A
A
A
S
I-SA
I-
I-S
I-S
0
A
T
A
-S
I
GPIO1
S
GPIO2
S
S
IO
B
y
r
o
m
e
M
o
e
Vid
D
I/O
S
L1
PL2
J
B4
US
7
an
3
2
PW
PW
J
J
A. KB/Mouse
R
PW
Main
Pin
-
20
B. COM1
1
n
a
F
1
F
J
C. COM2
RL
CT
P
F
an2
F
1
D
J
1
LE
OH1
J
P1
J
3
an
F
8
an
F
N2
A
F
PU
C
5
A
T
A
S
I-
1
#
E
ID
O
S
IM
S
y
p
p
lo
F
8
1
J
2
2
J
B
M
S
L1
J
B2/3
US
4
an
F
2-17
X7DBU/X7DGU User's Manual
Wake-On-Ring
The Wake-On-Ring header is designated JWOR1. This function allows
your computer to receive and be
"awakened" by an incoming call to
the modem when the system is in
the suspend state. See the table on
the right for pin defi nitions. You must
have a Wake-On-Ring card and cable
to use this feature. Please make sure
to enable this function in the BIOS.
Wake-On-LAN
The Wake-On-LAN header is located
at JWOL1 on the motherboard. See
the table on the right for pin defi ni-
tions. (Y ou must also have a LAN card
with a Wake-On-LAN connector and
cable to use this feature.)
Wake-On-Ring
Pin Defi nitions
Pin# Defi nition
1 Ground
2 Wake-up
Wake-On-LAN
Pin Defi nitions
Pin# Defi nition
1 +5V Standby
2 Ground
3 Wake-up
VGA
JCOM
J
J
J
15
LA
LA
KB/MS
JKM1
USB 0/1
COM1
LAN1
N
LAN2
N2
LE2
UI
1
SW1
1
O
Batt
Rear UID
R
PW
R
R
PW
PW
4-Pin
P1
S
X7DBU
(
ntel 500
I
Nor
S
S
F
dge)
i
h Br
t
PCI-E
XB2:
PCI-E
XB1:
r
e
zz
5
n
Fa
6
n
a
F
J9B2
Bank4
J9B1
J8B3
Bank3
J8B2
J8B1
Bank2
J7B3
y
r
e
J7B2
Bank1
J7B1
N
LA
RL
T
C
133 M
PCI-X
J14
J11
Bu
I2C1
I2C2
27
J
28
J
Hz
1
J
B
M
S
R
PW
1
an
F
CPU
4B
IMM
D
4A
IMM
D
B
3
IMM
D
3A
IMM
D
2B
IMM
D
2A
IMM
D
1B
IMM
D
1A
M
IM
D
U1
P
C
0
U2
P
C
1
A
T
x8
9
J
5
J
x16
2
B
S
E
l
Inte
ridge
outh B
(S
A
7
J
R1
O
W
J
PG1
J
0
0
10
S
E
RL
CT
o
e
id
V
2
COM
A
S
I0
A
T
I-SA
1
GPIO
S
29
J
30
J
GPIO2
S
)
IOS
B
y
JBT1
mor
e
M
o
e
Vid
D
W
J
K1
J
B
L1
O
W
J
PL2
J
B4
US
JPL1
7
7
an
8-Pin
3
2
PW
PW
J
J
1
PW
J
R
PW
in
a
M
in
-P
20
an
F
F
J
RL
T
C
P
F
2
an
F
1
D
J
1
LE
OH1
J
P1
J
Fan3
8
an
F
N2
A
F
CPU
4
3
2
5
A
A
A
A
T
T
T
T
A
A
A
S
I-
I-S
I-SA
I-S
1
#
E
D
I
IMSO
S
y
p
p
Flo
18
I/O
S
J
J22
B
M
S
L1
J
B2/3
US
4
an
F
A. WOR
B. WOL
1
1
2-18
GLAN 1/2 (Giga-bit Ethernet
Ports)
Two G-bit Ethernet ports are designated JLAN1 and JLAN2 on the IO
backplane. This port accepts RJ45
type cables.
Power LED/Speaker
Chapter 2: Installation
GLAN1 GLAN2
On the JD1 header, pins 1-3 are for
a power LED, and pins 4-7 are for the
speaker. See the table on the right
for speaker pin defi nitions. *Note:
The speaker connector pins are for
use with an external speaker. If you
wish to use the onboard speaker, you
should close pins 6-7 with a jumper.
7
an
P1
S
X7DBU
Nor
(
ntel 500
I
h Br
t
XB2:
S
B1:
X
S
F
PW
1
an
F
CPU
IMM
D
IMM
D
IMM
D
IMM
D
IMM
D
IMM
D
IMM
D
M
IM
D
0
idge)
x8
PCI-E
x16
PCI-E
r
e
zz
5
n
Fa
6
n
a
KB/MS
USB 0/1
COM1
JCOM
VGA
15
J
LAN1
LA
J
LAN2
LA
J
LE2
F
JKM1
N
N2
SW1
UI
1
1
O
Rear UID
PW
J9B2
Bank4
J9B1
J8B3
Bank3
J8B2
J8B1
Bank2
J7B3
y
r
e
Batt
J7B2
Bank1
J7B1
A
B
N
LA
RL
T
C
133 M
PCI-X
J14
J11
R
Bu
I2C1
I2C2
27
J
28
J
Hz
Speaker Connector
Pin Defi nitions
Pin Setting Defi nition
Pins 6-7 Internal Speaker
Pins 4-7 External Speaker
R
R
PW
PW
4-Pin
8-Pin
3
PL2
GPIO
GPIO2
2
PW
PW
J
J
JPW1
R
PW
in
a
M
in
-P
20
2
an
F
LE
OH1
J
8
an
F
N2
A
F
CPU
4
3
2
5
1
A
A
A
A
A
T
T
T
T
T
A
A
A
A
S
S
I-SA
I-
I-S
I-
I-S
1
O
S
IM
S
IO
B
I/O
S
B4
US
S
18
J
MB
S
L1
J
B2/3
US
an
F
A. GLAN1
B. GLAN2
C. PWR LED/Speaker
1
an
F
1
F
J
RL
CT
P
F
1
D
C
J
1
P1
J
Fan3
1
#
E
ID
y
p
p
lo
F
J22
4
17
J
B
M
S
R
4B
4A
B
3
3A
2B
2A
1B
1A
9
J
5
J
Inte
outh B
(S
R1
O
W
J
PG1
J
S
E
e
id
V
2
COM
U1
P
C
U2
P
C
0
A
T
A
-S
I
S
29
J
2
B
S
E
l
30
J
S
)
ridge
y
r
JBT1
o
7
J
m
e
M
o
0
0
10
RL
CT
o
e
Vid
D
W
J
K1
J
L1
O
W
J
J
JPL1
2-19
X7DBU/X7DGU User's Manual
Overheat LED/Fan Fail
(JOH1)
The JOH1 header is used to connect
an LED to provide warnings of chassis overheating. This LED will blink
to indicate a fan failure. Refer to the
table on right for pin defi nitions.
SMB
A System Management Bus header is
located at J18. Connect the appropriate cable here to utilize SMB on your
system.
Overheat LED
Pin Defi nitions
Pin# Defi nition
1 5vDC
2 OH Active
OH/Fan Fail LED
Pin Defi nitions
State Message
Solid Overheat
Blinking Fan Fail
SMB Header
Pin Defi nitions
Pin# Defi nition
1 Data
2 Ground
3 Clock
4 No Connection
JCOM
VGA
15
J
J
LA
J
KB/MS
USB 0/1
COM1
LAN1
LA
LAN2
LE2
R
R
PW
PW
4-Pin
8-Pin
P1
S
X7DBU
Nor
(
ntel 500
I
h Br
t
XB2:
S
B1:
X
S
F
idge)
PCI-E
PCI-E
r
e
zz
JKM1
N
N2
UI
J9B2
Bank4
J9B1
J8B3
Bank3
J8B2
J8B1
Bank2
1
J7B3
y
r
e
Batt
J7B2
Bank1
J7B1
1
N
LA
RL
T
C
Rear UID
SW1
J11
R
PW
O
133 M
PCI-X
J14
5
n
Fa
6
n
a
F
Bu
I2C1
I2C2
27
J
28
J
Hz
17
J
B
M
S
R
PW
1
an
F
CPU
4B
IMM
D
4A
IMM
D
B
3
IMM
D
3A
IMM
D
2B
IMM
D
2A
IMM
D
1B
IMM
D
1A
M
IM
D
U1
P
C
1
PW
J
0
U2
P
C
4
3
2
1
A
A
A
A
T
T
T
T
x8
9
J
5
J
x16
2
B
S
E
l
Inte
)
ridge
outh B
(S
JBT1
7
J
R1
O
W
J
PG1
J
0
0
10
S
E
RL
CT
o
e
id
V
2
COM
J
JPL1
A
S
I-SA
I-
I-SA
I-SA
0
A
T
A
I-S
1
GPIO
S
29
J
30
J
GPIO2
S
S
IO
B
y
r
o
m
e
M
o
e
Vid
D
W
J
I/O
K1
J
L1
O
W
J
B
S
PL2
B4
US
7
an
3
2
PW
PW
J
J
R
PW
in
a
M
in
-P
20
an
F
F1
J
RL
CT
P
F
2
an
F
1
D
J
1
LE
OH1
J
P1
J
Fan3
8
an
F
N2
A
F
CPU
5
A
T
A
S
I-
1
#
E
ID
O
S
IM
S
y
p
p
Flo
18
J
J22
MB
S
L1
J
B2/3
US
4
an
F
A. OH/Fan Fail LED
B. SMB Header
1
A
2-20
Chapter 2: Installation
Power SMB (I2 C) Connector
Power SMB (I2 C) Connector (J17)
monitors onboard power supply, fan
speeds and system temperatures.
See the table on the right for pin
defi nitions.
VGA Connector
A VGA connector (J15) is located next
to the GLAN2 port on the IO backplane.
Refer to the board layout below for
the location.
PWR SMB
Pin Defi nitions
Pin# Defi nition
1 Clock
2 Data
3 PWR Fail
4 Ground
5 +3.3V
A
7
an
P1
S
X7DBU
Nor
(
ntel 500
I
h Br
t
XB2:
S
B1:
X
S
F
idge)
PCI-E
PCI-E
r
e
zz
5
n
Fa
6
n
a
KB/MS
USB 0/1
COM1
JCOM
VGA
15
J
LAN1
LA
J
LAN2
LA
J
LE2
F
JKM1
N
N2
SW1
UI
1
1
O
B
Rear UID
PW
J9B2
Bank4
J9B1
J8B3
Bank3
J8B2
J8B1
Bank2
J7B3
y
r
e
Batt
J7B2
Bank1
J7B1
N
LA
RL
T
C
133 M
PCI-X
J14
J11
R
Bu
I2C1
I2C2
27
J
28
J
Hz
17
J
B
M
S
R
PW
1
an
F
CPU
4B
IMM
D
4A
IMM
D
B
3
IMM
D
3A
IMM
D
2B
IMM
D
2A
IMM
D
1B
IMM
D
1A
M
IM
D
U1
P
C
0
U2
P
C
x8
9
J
5
J
x16
E
l
Inte
outh B
(S
R1
O
W
J
PG1
J
0
0
10
S
E
RL
CT
o
e
id
V
2
COM
B
S
ridge
0
A
T
A
-S
I
GPIO
S
29
J
2
30
J
GPIO2
S
)
y
r
JBT1
o
7
J
m
e
M
o
e
Vid
D
W
J
K1
J
L1
O
W
J
PL2
J
US
JPL1
R
R
PW
PW
4-Pin
8-Pin
3
2
PW
PW
J
J
JPW1
R
PW
in
a
M
in
-P
20
F
2
an
F
1
LE
OH1
J
J
Fan3
8
an
F
N2
A
F
CPU
4
3
2
5
1
A
A
A
A
A
T
T
T
T
T
A
A
A
A
S
S
I-SA
I-
I-S
I-
I-S
1
O
S
IM
S
IO
B
I/O
S
B4
S
18
J
MB
S
L1
J
B2/3
US
an
F
1
an
1
F
J
RL
CT
P
F
1
D
J
P1
1
#
E
ID
y
p
p
lo
F
J22
4
A. PWR SMB
B. VGA
2-21
X7DBU/X7DGU User's Manual
Unit Identifi cation Switches
There are two Unit Identifi cation (UID) Switches
on the motherboard. The Front Panel UID
Switch is connected to Pin 13 of the Front
Control Panel. The Rear UID Switch (SW1)
is located next to LAN Port2. When you
push the UID Switch on the Front Control
Panel, both Rear UID and FP UID Indicators
will turn on. Push the FP UID Switch (or the
Rear UID Switch-SW1) again to turn off both
Indicators. These UID Indicators provide easy
identifi cation of a system unit that may be in
need of service. (*For more information on
the FP UID Switch, please refer to FP UID
Switch on Page 2-11.)
SGPIO Headers
There are two SGPIO (Serial General Purpose
Input/Output) headers (J29, J30) located on
the motherboard. These headers are used to
"talk to" the AMI Chip on the backplane. See
the table on the right for pin defi nitions. Refer
to the board layout below for the locations of
the headers.
7
an
JCOM
VGA
15
J
J
LA
J
KB/MS
USB 0/1
COM1
LAN1
LA
LAN2
LE2
P1
S
X7DBU
Nor
(
ntel 500
I
h Br
t
XB2:
S
B1:
X
S
F
idge)
PCI-E
PCI-E
r
e
zz
JKM1
N
N2
UI
J9B2
Bank4
J9B1
J8B3
Bank3
J8B2
J8B1
Bank2
1
J7B3
y
r
e
Batt
J7B2
Bank1
J7B1
1
N
LA
RL
T
C
A
Rear UID
SW1
J11
R
PW
O
133 M
PCI-X
J14
5
n
Fa
6
n
a
F
Bu
I2C1
I2C2
27
J
28
J
Hz
17
J
B
M
S
R
PW
1
an
F
CPU
4B
IMM
D
4A
IMM
D
B
3
IMM
D
3A
IMM
D
2B
IMM
D
2A
IMM
D
1B
IMM
D
1A
M
IM
D
0
x8
9
J
5
J
x16
B
S
E
l
Inte
ridge
outh B
(S
R1
O
W
J
PG1
J
0
0
10
S
E
RL
CT
o
e
id
V
2
COM
SGPIO
Pin Defi nitions
Pin# Defi nition Pin Defi nition
1 *NC 2 *NC
3 Ground 4 Data
5 Load 6 Ground
7 *NC 8 *NC
Note: NC= No Connections
R
R
PW
PW
4-Pin
8-Pin
3
2
PW
PW
J
J
1
PW
J
R
PW
in
a
M
in
-P
20
an
F
J
U1
P
C
U2
P
C
4
3
2
1
A
A
A
A
T
T
T
T
A
S
I-SA
I-
I-SA
I-SA
0
A
T
A
I-S
B
1
GPIO
S
29
J
2
30
J
GPIO2
S
)
S
C
IO
B
y
r
JBT1
o
7
J
m
e
M
o
e
Vid
D
W
J
I/O
K1
J
S
L1
O
W
J
PL2
J
JPL1
US
B4
US
RL
CT
P
F
2
an
F
1
LE
OH1
J
P1
J
Fan3
8
an
F
N2
A
F
CPU
5
A
T
A
S
I-
1
#
E
ID
O
S
IM
S
y
p
p
Flo
18
J
J22
MB
S
L1
J
B2/3
4
an
F
A. UID Switch
B. SGPIO1
C. SGPIO2
1
F1
1
D
J
2-22
2-6 Jumper Settings
Connector
Pins
Jumper
Cap
Setting
Explanation of
Jumpers
To modify the operation of the
motherboard, jumpers can be used
to choose between optional settings.
Jumpers create shorts between two
pins to change the function of the
connector. Pin 1 is identifi ed with a
square solder pad on the printed circuit
board. See the motherboard layout
pages for jumper locations.
Note: On two pin jumpers, "Closed"
means the jumper is on and "Open"
means the jumper is off the pins.
Chapter 2: Installation
3 2 1
3 2 1
Pin 1-2 short
GLAN Enable/Disable
JPL1/JPL2 enable or disable the
GLAN Port1/GLAN Port2 on the motherboard. See the table on the right for
jumper settings. The default setting
is enabled.
7
an
P1
S
X7DBU
ntel 5000
I
Nor
(
S
F
PW
1
an
F
CPU
IMM
D
IMM
D
IMM
D
IMM
D
IMM
D
IMM
D
IMM
D
M
IM
D
dge)
i
h Br
t
x8
PCI-E
XB2:
x16
PCI-E
XB1:
S
r
e
zz
5
n
Fa
6
n
a
KB/MS
USB 0/1
COM1
COM
J
VGA
15
J
LAN1
LA
J
LAN2
LA
J
LE2
F
KM1
J
N
N2
SW1
UI
1
1
O
Rear UID
PW
J9B2
Bank4
J9B1
J8B3
Bank3
J8B2
J8B1
Bank2
J7B3
y
r
e
Batt
J7B2
Bank1
J7B1
N
LA
RL
T
C
133 M
PCI-X
J14
J11
R
Bu
I2C1
I2C2
27
J
28
J
Hz
GLAN Enable
Jumper Settings
Pin# Defi nition
1-2 Enabled (*default)
2-3 Disabled
R
R
PW
PW
4-Pin
8-Pin
3
PL2
GPIO
GPIO2
2
PW
J
JPW1
PW
in
a
M
in
-P
20
an
F
an
F
A
F
CPU
4
3
2
5
1
A
A
A
A
A
T
T
T
T
T
A
A
A
A
S
S
I-SA
I-
I-S
I-
I-S
1
S
IO
B
1
I/O
S
B4
US
B
J
B
M
S
L1
J
/3
2
B
US
A. GLAN Port1 Enable
PW
J
B. GLAN Port2 Enable
R
1
an
F
1
F
J
RL
CT
P
F
2
1
D
J
1
LE
OH1
J
P1
J
3
an
F
8
N2
1
#
E
ID
O
S
IM
S
y
p
p
lo
F
8
22
J
4
an
F
J17
B
M
S
R
4B
4A
B
3
3A
2B
2A
1B
1A
9
J
5
J
Inte
outh B
(S
OR1
W
J
PG1
J
S
E
e
id
V
2
M
CO
U1
P
C
U2
P
C
0
A
T
A
-S
I
S
29
J
2
B
S
E
l
30
J
S
)
ridge
y
r
1
BT
J
o
7
J
m
e
M
o
0
0
10
RL
CT
o
e
Vid
D
W
J
K1
J
OL1
W
J
J
A
PL1
J
2-23
X7DBU/X7DGU User's Manual
CMOS Clear
JBT1 is used to clear CMOS. Instead of pins, this "jumper" consists of contact
pads to prevent the accidental clearing of CMOS. To clear CMOS, use a metal
object such as a small screwdriver to touch both pads at the same time to short
the connection. Always remove the AC power cord from the system before clearing
CMOS. Note: For an ATX power supply, you must completely shut down the system,
remove the AC power cord and then short JBT1 to clear CMOS.
Watch Dog Enable/Disable
Watch Dog is a sy stem moni tor that c an reb oot
the system w hen a sof tware a pplicat ion hang s.
Close Pins 1-2 to reset the system if an application hangs. Close Pins 2-3 to generate a
non-maskable interrupt signal for the application
that hangs. See the table on the right for jumper
settings. Watch Dog must also be enabled in the
BIOS.
Jumper Setting Defi nition
Pins 1-2 Reset
Pins 2-3 NMI
Open Disabled
Watch Dog
Jumper Settings (JWD)
(*default)
COM
J
VGA
15
J
J
LA
J
KB/MS
USB 0/1
COM1
LAN1
LA
LAN2
LE2
R
R
PW
PW
4-Pin
8-Pin
P1
S
X7DBU
Nor
(
ntel 500
I
h Br
t
XB2:
S
XB1:
S
F
idge)
PCI-E
PCI-E
r
e
zz
J
N
N2
UI
J9B2
Bank4
J9B1
J8B3
Bank3
J8B2
J8B1
Bank2
1
J7B3
y
r
e
Batt
J7B2
Bank1
J7B1
1
N
LA
RL
T
C
Rear UID
SW1
J11
R
PW
O
133 M
PCI-X
J14
5
n
Fa
6
n
a
F
KM1
Bu
I2C1
I2C2
27
J
28
J
Hz
17
J
B
M
S
R
PW
1
an
F
CPU
4B
IMM
D
4A
IMM
D
B
3
IMM
D
3A
IMM
D
2B
IMM
D
2A
IMM
D
1B
IMM
D
1A
M
IM
D
U1
P
C
1
PW
J
0
U2
P
C
4
3
2
1
A
A
A
A
T
T
T
T
x8
9
J
5
J
x16
2
B
S
E
l
Inte
)
ridge
outh B
(S
A
1
BT
J
7
J
OR1
W
J
PG1
J
00
10
S
E
RL
CT
o
e
id
V
2
M
CO
J
PL1
J
A
S
I-SA
I-
I-SA
I-SA
0
A
T
A
I-S
1
GPIO
S
29
J
30
J
GPIO2
S
S
IO
B
y
r
o
m
e
M
o
e
Vid
D
W
J
B
I/O
K1
J
S
OL1
W
PL2
J
B4
US
7
an
3
2
PW
J
a
M
in
-P
20
CPU
5
A
T
A
S
I-
MB
S
/3
2
B
US
A. Clear CMOS
PW
J
B. Watch Dog Enable
R
PW
in
1
an
F
1
F
J
RL
CT
P
F
2
an
F
1
D
J
1
LE
OH1
J
P1
J
3
an
F
8
an
F
N2
A
F
1
#
E
ID
O
S
IM
S
y
p
p
lo
F
8
1
J
22
J
L1
J
4
an
F
2-24
Chapter 2: Installation
VGA Enable/Disable
JPG1 allows you to enable or disable the
VGA port. The default position is on pins
1 and 2 to enable VGA. See the table on
the right for jumper settings.
VGA Enable/Disable
Jumper Settings (JPG1)
Both Jumpers Defi nition
*Pins 1-2 Enabled
Pins 2-3 Disabled
R
R
PW
PW
4-Pin
8-Pin
P1
S
X7DBU
Nor
(
ntel 500
I
h Br
t
XB2:
S
B1:
X
S
F
idge)
PCI-E
PCI-E
r
e
zz
5
n
Fa
6
n
a
KB/MS
USB 0/1
COM1
JCOM
VGA
15
J
LAN1
LA
J
LAN2
LA
J
LE2
F
JKM1
N
N2
SW1
UI
1
1
O
Rear UID
PW
J9B2
Bank4
J9B1
J8B3
Bank3
J8B2
J8B1
Bank2
J7B3
y
r
e
Batt
J7B2
Bank1
J7B1
N
LA
RL
T
C
133 M
PCI-X
J14
J11
R
Bu
I2C1
I2C2
27
J
28
J
Hz
17
J
B
M
S
R
PW
1
an
F
CPU
4B
IMM
D
4A
IMM
D
B
3
IMM
D
3A
IMM
D
2B
IMM
D
2A
IMM
D
1B
IMM
D
1A
M
IM
D
U1
P
C
JPW1
0
U2
P
C
4
3
2
1
A
A
A
A
T
T
T
T
A
A
x8
9
J
5
J
x16
2
B
S
E
l
Inte
ridge
outh B
(S
7
J
R1
O
W
J
PG1
J
A
0
0
10
S
E
RL
CT
o
e
id
V
2
COM
A
S
I-SA
I-
I-S
I-S
0
A
T
A
-S
I
1
GPIO
S
29
J
30
J
GPIO2
S
)
S
IO
B
y
r
JBT1
o
m
e
M
o
e
Vid
D
W
J
I/O
K1
J
S
L1
O
W
J
PL2
J
B4
US
JPL1
7
an
3
2
PW
PW
J
J
R
PW
in
a
M
in
-P
20
2
an
F
1
LE
OH1
J
J
Fan3
8
an
F
N2
A
F
CPU
5
A
T
A
S
I-
O
S
IM
S
18
J
MB
S
L1
J
B2/3
US
an
F
A. VGA Enabled
1
an
F
1
F
J
RL
CT
P
F
1
D
J
P1
1
#
E
ID
y
p
p
lo
F
J22
4
2-25
X7DBU/X7DGU User's Manual
I2C Bus to PCI Slots 1/2
JI2C1 (J27)/JI2C2 (J28) allow you to enable I2C Bus to PCI-X/PCI-E slots. See
the table on the right for jumper settings. The default setting is Disabled.
I2C Bus to PCI Slots
Jumper Settings
Jumper Defi nition
1-2 Enabled
Off Disabled (De-
fault)
JCOM
VGA
15
J
J
LA
J
KB/MS
USB 0/1
COM1
LAN1
LA
LAN2
LE2
R
R
PW
PW
4-Pin
8-Pin
P1
S
X7DBU
Nor
(
ntel 500
I
h Br
t
XB2:
S
B1:
X
S
F
idge)
PCI-E
PCI-E
r
e
zz
JKM1
N
N2
UI
J9B2
Bank4
J9B1
J8B3
Bank3
J8B2
J8B1
Bank2
1
J7B3
y
r
e
Batt
J7B2
Bank1
J7B1
1
N
LA
RL
T
C
Rear UID
SW1
J11
R
PW
O
133 M
PCI-X
J14
5
n
Fa
6
n
a
F
Bu
I2C1
I2C2
27
J
A
28
J
Hz
B
17
J
B
M
S
R
PW
1
an
F
CPU
4B
IMM
D
4A
IMM
D
B
3
IMM
D
3A
IMM
D
2B
IMM
D
2A
IMM
D
1B
IMM
D
1A
M
IM
D
U1
P
C
1
PW
J
0
U2
P
C
4
3
2
1
A
A
A
A
T
T
T
T
x8
9
J
5
J
x16
2
B
S
E
l
Inte
)
ridge
outh B
(S
JBT1
7
J
R1
O
W
J
PG1
J
0
0
10
S
E
RL
CT
o
e
id
V
2
COM
J
JPL1
A
S
I-SA
I-
I-SA
I-SA
0
A
T
A
I-S
1
GPIO
S
29
J
30
J
GPIO2
S
S
IO
B
y
r
o
m
e
M
o
e
Vid
D
W
J
I/O
K1
J
S
L1
O
W
PL2
J
B4
US
7
an
3
2
PW
PW
J
J
R
PW
in
a
M
in
-P
20
F
2
an
F
1
LE
OH1
J
J
Fan3
8
an
F
N2
A
F
CPU
5
A
T
A
S
I-
O
S
IM
S
18
J
MB
S
L1
J
B2/3
US
an
F
A. JI2C1
B. JI2C2
1
an
F1
J
RL
CT
P
F
1
D
J
P1
1
#
E
ID
y
p
p
Flo
J22
4
2-26
Chapter 2: Installation
2-7 Onboard Indicators
GLAN LEDs
There are two GLAN ports on the motherboard. Each Gigabit Ethernet LAN port
has two LEDs. The yellow LED indicates
activity , while the Link LED may be green,
amber or off to indicate the speed of the
connection. See the tables at right for
more information.
Link
LED
Activity
LED
(Rear View: When viewing from
the rear side of the system)
GLAN Activity Indicator
Jumper Settings
LED Color Defi nition
Off Not Active
Y ellow Blinking: Active
GLAN Link Indicator
Jumper Settings
LED Color Defi nition
Off No Connection or 10 Mbps
Green 100 Mbps
Amber 1 Gbps
R
R
PW
PW
4-Pin
8-Pin
P1
S
X7DBU
Nor
(
ntel 500
I
h Br
t
XB2:
S
B1:
X
S
F
idge)
PCI-E
PCI-E
r
e
zz
5
n
Fa
6
n
a
KB/MS
USB 0/1
COM1
JCOM
VGA
15
J
LAN1
LA
J
LAN2
LA
J
LE2
F
JKM1
N
N2
SW1
UI
1
1
O
Rear UID
PW
J9B2
Bank4
J9B1
J8B3
Bank3
J8B2
J8B1
Bank2
J7B3
y
r
e
Batt
J7B2
Bank1
J7B1
A
B
N
LA
RL
T
C
133 M
PCI-X
J14
J11
R
Bu
I2C1
I2C2
27
J
28
J
Hz
17
J
B
M
S
R
PW
1
an
F
CPU
4B
IMM
D
4A
IMM
D
B
3
IMM
D
3A
IMM
D
2B
IMM
D
2A
IMM
D
1B
IMM
D
1A
M
IM
D
U1
P
C
JPW1
0
U2
P
C
4
3
2
1
A
A
A
A
T
T
T
T
A
A
x8
9
J
5
J
x16
2
B
S
E
l
Inte
ridge
outh B
(S
7
J
R1
O
W
J
PG1
J
0
0
10
S
E
RL
CT
o
e
id
V
2
COM
A
S
I-SA
I-
I-S
I-S
0
A
T
A
-S
I
1
GPIO
S
29
J
30
J
GPIO2
S
)
S
IO
B
y
r
JBT1
o
m
e
M
o
e
Vid
D
W
J
I/O
K1
J
S
L1
O
W
J
PL2
J
B4
US
JPL1
7
an
3
2
PW
J
PW
in
a
M
in
-P
20
2
an
F
LE
8
an
F
N2
A
F
CPU
5
A
T
A
S
I-
O
S
IM
S
18
J
MB
S
L1
J
B2/3
US
F
A. GLAN Port1 LEDs
PW
J
B. GLAN Port2 LEDs
R
1
an
F
1
F
J
RL
CT
P
F
1
D
J
1
OH1
J
P1
J
Fan3
1
#
E
ID
y
p
p
lo
F
J22
4
an
2-27
X7DBU/X7DGU User's Manual
Onboard Power LED (LE1)
There is an Onboard Power LED (LE1)
located on the motherboard. When LE1
is off, the system is off. When the green
light is on, the system is on. See the layout
below for the LED location.
Onboard PWR LED Indicator (LE1)
LED Color Defi nition
Off System Off (*PWR cable
not connected)
Green System On
Green:
ACPI S1 State
Flashing
Quickly
Green:
ACPI S3 (STR) State
Flashing
Slowly
JCOM
VGA
15
J
J
LA
J
KB/MS
USB 0/1
COM1
LAN1
LA
LAN2
LE2
R
R
PW
PW
4-Pin
8-Pin
P1
S
X7DBU
Nor
(
ntel 500
I
h Br
t
XB2:
S
B1:
X
S
F
idge)
PCI-E
PCI-E
r
e
zz
JKM1
N
N2
UI
J9B2
Bank4
J9B1
J8B3
Bank3
J8B2
J8B1
Bank2
1
J7B3
y
r
e
Batt
J7B2
Bank1
J7B1
1
N
LA
RL
T
C
Rear UID
SW1
J11
R
PW
O
133 M
PCI-X
J14
5
n
Fa
6
n
a
F
Bu
I2C1
I2C2
27
J
28
J
Hz
17
J
B
M
S
R
PW
1
an
F
CPU
4B
IMM
D
4A
IMM
D
B
3
IMM
D
3A
IMM
D
2B
IMM
D
2A
IMM
D
1B
IMM
D
1A
M
IM
D
U1
P
C
1
PW
J
0
U2
P
C
4
3
2
1
A
A
A
A
T
T
T
T
x8
9
J
5
J
x16
2
B
S
E
l
Inte
)
ridge
outh B
(S
JBT1
7
J
R1
O
W
J
PG1
J
0
0
10
S
E
RL
CT
o
e
id
V
2
COM
J
JPL1
A
S
I-SA
I-
I-SA
I-SA
0
A
T
A
I-S
1
GPIO
S
29
J
30
J
GPIO2
S
S
IO
B
y
r
o
m
e
M
o
e
Vid
D
W
J
I/O
K1
J
S
L1
O
W
PL2
J
B4
US
7
an
3
2
PW
PW
J
J
R
PW
in
a
M
in
-P
20
1
an
F
F1
J
RL
CT
P
F
2
an
F
1
D
J
1
LE
A
OH1
J
P1
J
Fan3
8
an
F
N2
A
F
CPU
5
A
T
A
S
I-
1
#
E
ID
O
S
IM
S
y
p
p
Flo
18
J
J22
MB
S
L1
J
B2/3
US
4
an
F
A. PWR LED
2-28
Chapter 2: Installation
2-8 Floppy Drive, Hard Disk Drive, SIMSO-DIMM IPMI
and SCSI Connections
Note the following when connecting the fl oppy and hard disk drive cables:
• The fl oppy disk drive cable has seven twisted wires.
• A red mark on a wire typically designates the location of pin 1.
• A single fl oppy disk drive ribbon cable has two connectors to provide for two
fl oppy disk drives. The connector with twisted wires always connects to drive
A, and the connector that does not have twisted wires always connects to drive
B.
Floppy Drive Connector
Pin Defi nitions (Floppy)
Pin# Defi nition Pin # Defi nition
1 Ground 2 FDHDIN
Floppy Connector
The fl oppy connector is located at
J22. See the table below for pin
defi nitions.
3 Ground 4 Reserved
5 Key 6 FDEDIN
7 Ground 8 Index
9 Ground 10 Motor Enable
11 Ground 12 Drive Select B
13 Ground 14 Drive Select B
15 Ground 16 Motor Enable
17 Ground 18 DIR
19 Ground 20 STEP
21 Ground 22 Write Data
23 Ground 24 Write Gate
25 Ground 26 Track 00
27 Ground 28 Write Protect
29 Ground 30 Read Data
31 Ground 32 Side 1 Select
33 Ground 34 Diskette
WR
WR
P
P
n
n
i
i
P
P
-
-
4
7
n
a
F
17
zer
z
u
5
n
a
F
6
n
a
F
KB/MS
1
M
K
J
J9B2
Bank4
J9B1
USB 0/1
J8B3
Bank3
J8B2
COM1
J8B1
Bank2
1
M
O
C
J
J7B3
ttery
a
B
J7B2
Bank1
VGA
J7B1
5
1
J
LAN1
1
N
A
L
J
LAN2
2
N
A
L
J
N
A
L
CTRL
Rear UID
LE2
SW1
IO
U
CI-
P
J14
J11
WR
P
B
SP1
n
I
(No
I2C1
I2C2
27
J
28
J
z
H
M
3
13
X
X7DBU
SX
S
J
B
M
S
WR
P
1
n
a
F
CPU
B
4
M
M
DI
4A
M
DIM
3B
M
DIM
3A
M
DIM
2B
M
DIM
2A
M
DIM
1B
M
DIM
1A
M
DIM
0
el 500
t
e)
dg
i
r
B
h
t
r
8
x
E
-
I
C
P
2:
B
9
J
16
x
E
CI-
P
1:
B
X
J
U1
CP
U2
CP
5
J
SATA0
I-
SG
29
J
B2
S
E
l
nte
I
0
3
J
)
e
g
d
uth Bri
o
S
(
y
r
1
T
B
J
o
7
J
1
WOR
1
G
P
J
V
COM
m
e
M
o
e
d
S1000
E
i
V
CTRL
eo
d
i
WD
J
1
K
J
WOL
J
2
J
1
L
P
J
8
W3
W2
P
P
J
J
W1
P
J
WR
P
n
i
a
M
n
i
P
20-
n
a
F
F
J
CTRL
P
F
2
n
a
F
D1
J
1
E
L
OH1
J
1
P
J
3
n
a
F
8
n
a
F
2
N
A
F
CPU
4
5
A
T
A
SATA
SATA2
SATA3
S
SATA1
-
I-
I
I-
I-
I-
IO1
P
2
O
I
P
SG
IOS
B
I/O
S
1
2
L
P
4
SB
U
IDE#1
SO
M
SI
y
p
p
o
l
F
18
J
22
J
B
SM
1
L
J
2/3
SB
U
4
n
a
F
1
1
A
A. Floppy Port
2-29
X7DBU/X7DGU User's Manual
SIMSO IPMI Slot
There is a SIM SO-DIMM IPMI
(Intelligent Platform Management Interface) Slot on the
motherboard. Refer to the
layout below for the location
of SIMSO slot.
VGA
COM
J
15
J
LA
J
LA
J
KB/MS
JKM1
USB 0/1
COM1
LAN1
N
LAN2
N2
LE2
UI
R
R
PW
PW
4-Pin
8-Pin
P1
S
X7DBU
I
Nor
(
S
ntel 5000
h Br
t
PCI-E
XB2:
PCI-E
B1:
X
S
F
dge)
i
r
e
zz
5
n
Fa
6
n
a
F
J9B2
Bank4
J9B1
J8B3
Bank3
J8B2
J8B1
Bank2
1
J7B3
y
r
e
Batt
J7B2
Bank1
J7B1
1
N
LA
RL
T
C
Rear UID
SW1
J11
R
PW
O
133 M
PCI-X
J14
Bu
I2C1
I2C2
27
J
28
J
Hz
17
J
B
M
S
R
PW
1
an
F
CPU
4B
IMM
D
4A
IMM
D
B
3
IMM
D
3A
IMM
D
2B
IMM
D
2A
IMM
D
1B
IMM
D
1A
M
IM
D
x8
9
J
5
J
x16
Inte
o
(S
R1
O
W
J
PG1
J
S
E
e
id
V
2
COM
uth B
10
o
U1
P
C
U2
P
C
29
J
2
B
S
E
l
30
J
)
ridge
JBT1
7
J
0
0
RL
CT
W
J
K1
J
O
W
J
JPL1
1
PW
J
4
3
2
1
A
A
A
A
T
T
T
T
A
A
-S
I-SA
I
I-SA
I-S
0
A
T
A
I-S
1
GPIO
S
GPIO2
S
S
IO
B
y
mor
e
M
o
e
Vid
D
I/O
S
L1
PL2
J
B4
US
7
an
3
2
PW
PW
J
J
in
a
M
in
-P
20
CPU
5
A
T
A
S
I-
A
MB
S
B2/3
US
R
PW
1
an
F
1
F
J
RL
CT
P
F
2
an
F
1
D
J
1
LE
OH1
J
P1
J
Fan3
8
an
F
N2
A
F
1
#
E
ID
O
S
IM
S
y
p
p
lo
F
18
J
J22
L1
J
4
an
F
A. SIMSO Slot
2-30
Chapter 2: Installation
IDE Connector
An IDE Connector is located at JIDE1on
the motherboard. See the table on the
right for pin defi nitions.
IDE Drive Connectors
Pin Defi nitions
Pin# Defi nition Pin # Defi nition
1 Reset IDE 2 Ground
3 Host Data 7 4 Host Data 8
5 Host Data 6 6 Host Data 9
7 Host Data 5 8 Host Data 10
9 Host Data 4 10 Host Data 11
11 Host Data 3 12 Host Data 12
13 Host Data 2 14 Host Data 13
15 Host Data 1 16 Host Data 14
17 Host Data 0 18 Host Data 15
19 Ground 20 Key
21 DRQ3 22 Ground
23 I/O Write 24 Ground
25 I/O Read 26 Ground
27 IOCHRDY 28 BALE
29 DACK3 30 Ground
31 IRQ14 32 IOCS16
33 Addr1 34 Ground
35 Addr0 36 Addr2
37 Chip Select 0 38 Chip Select 1
39 Activity 40 Ground
R
R
PW
PW
4-Pin
P1
S
X7DBU
Fa
el 50
Int
i
h Br
t
Nor
(
PCI
:
2
XB
S
PCI
:
1
B
X
S
r
e
z
z
5
an
F
6
an
KB/MS
USB 0/1
COM1
OM1
C
J
VGA
15
J
LAN1
LA
J
LAN2
LA
J
LE2
F
1
M
K
J
N1
N2
SW1
UIO
Batt
Rear UID
PW
J9B2
Bank4
J9B1
J8B3
Bank3
J8B2
J8B1
Bank2
J7B3
y
r
e
J7B2
Bank1
J7B1
N
LA
RL
CT
J14
J11
R
PCI-X
M
33
1
Bu
C1
I2
I2C2
27
J
28
J
Hz
1
J
B
M
S
R
PW
1
an
F
CPU
4B
IMM
D
A
4
IMM
D
M3B
IM
D
M3A
IM
D
B
2
IMM
D
A
2
IMM
D
B
IMM1
D
1A
IMM
D
U1
P
C
00
e)
dg
U2
P
C
1
A
T
8
x
-E
9
J
5
J
16
x
-E
2
B
S
Intel E
ridge
B
uth
o
(S
7
J
R1
O
JW
PG1
J
0
0
10
S
E
RL
CT
o
e
id
V
2
COM
A
S
I0
A
T
A
I-S
GPIO1
S
29
J
30
J
GPIO2
S
)
IOS
B
y
JBT1
mor
e
M
o
e
Vid
D
W
J
K1
J
1
L
O
W
J
PL2
J
B4
US
PL1
J
7
7
n
8-Pin
3
2
PW
PW
J
J
1
PW
J
R
PW
ain
M
20-Pin
1
n
Fa
1
F
J
RL
T
C
P
F
2
n
a
F
1
D
J
1
LE
OH1
J
P1
J
3
an
F
8
an
F
N2
A
F
U
P
C
4
3
2
5
A
A
A
A
T
T
T
T
A
A
A
S
I-
I-S
I-SA
I-S
1
#
E
D
I
A
IMSO
S
py
p
lo
F
8
1
I/O
S
J
2
2
J
B
M
S
L1
J
/3
2
B
US
4
n
a
F
A. IDE#1
2-31
X7DBU/X7DGU User's Manual
SXB1/SXB2 Slots
SXB1(J5) and SXB2 (J9) are specially
designed for Supermicro's riser cards.
These two slots are to be used with
riser cards. When used with riser
cards, the left IO slot (SXB1) supports
one PCI-E x8 and one UIO devices;
while the right IO slots (PCI-X: J14
and SXB2) can support a PCI-E x8 or
a PCI-X 133MHz device. Refer to the
layout below for the location.
8-Pin PWR
Fan7
Intel 5000
(North Bridge)
SXB2: PCI-E x8
SXB1: PCI-E x16
CPU Fan1
J17
PWR SMB
DIMM4B
DIMM4A
DIMM3B
DIMM3A
DIMM2B
DIMM2A
DIMM1B
DIMM1A
B
J9
J5
A
Intel ESB2
(South Bridge)
JWOR1
JPG1
ES1000
Video CTRL
COM2
PCI-X 133 MHz
Buzzer
SP1
I2C1
I2C2
J27
J28
X7DBU
Fan6
Fan5
KB/MS
JKM1
J9B2
Bank4
J9B1
USB 0/1
J8B3
Bank3
J8B2
COM1
J8B1
Bank2
JCOM1
J7B3
Battery
J7B2
Bank1
VGA
J7B1
J15
LAN1
JLAN1
LAN2
JLAN2
LAN
CTRL
Rear UID
LE2
SW1
J14
J11
UIO PWR
4-Pin PWR
JPW3
JPW2
JPW1
20-Pin Main PWR
Fan1
CPU1
CPU2
I-SATA1
I-SATA0
SGPIO1
J29
J30
SGPIO2
BIOS
ry
JBT1
o
J7
m
e
M
eo
id
V
JWD
JK1
JWOL1
JPL2
USB4
JPL1
JF1
FP CTRL
Fan2
JD1
LE1
JOH1
JP1
Fan3
Fan8
CPU FAN2
I-SATA4
I-SATA3
I-SATA2
I-SATA5
IDE#1
SIMSO
Floppy
J18
J22
SMB
S I/O
JL1
USB2/3
Fan4
A. SXB1 (the left slot)
B. SXB2 (the right slots)
2-32
Chapter 3: Troubleshooting
Chapter 3
Troubleshooting
3-1 Troubleshooting Procedures
Use the following procedures to troubleshoot your system. If you have followed all
of the procedures below and still need assistance, refer to the ‘Technical Support
Procedures’ and/or ‘Returning Merchandise for Service’ section(s) in this chapter.
Note: Always disconnect the power cord before adding, changing or installing
any hardware components.
Before Power On
1. Make sure that there are no short circuits between the motherboard and chassis.
2. Disconnect all ribbon/wire cables from the motherboard, including those for the
keyboard and mouse.
3. Remove all add-on cards.
4. Install one CPU (making sure it is fully seated) and connect the chassis speaker
and the power LED to the motherboard. (Check all jumper settings as well.)
5. Use only the correct type of CMOS onboard battery as recommended by the
Manufacturer. Do not install the onboard battery upside down to avoid possible explosion.
No Power
1. Make sure that there are no short circuits between the motherboard and chassis.
2. Verify that all jumpers are set to their default positions.
3. Check that the 115V/230V switch on the power supply is properly set.
4. Turn the power switch on and off to test the system.
5. The battery on your motherboard may be old. Check to verify that it still supplies
~3VDC. If it does not, replace it with a new one.
No Video
1. If the power is on but you have no video, remove all the add-on cards and
memory modules.
2. Use the speaker to determine if any beep codes exist. Refer to Appendix A and
Appendix B for details on beep codes.
Losing the System’s Setup Confi guration
1. Make sure that you are using a high quality power supply. A poor quality power
supply may cause the system to lose the CMOS setup information. Refer to
Section 1-6 for details on recommended power supplies.
3-1
X7DBU/X7DGU User's Manual
2. The battery on your motherboard may be old. Check to verify that it still supplies
~3VDC. If it does not, replace it with a new one.
3. If the above steps do not fi x the Setup Confi guration problem, contact your
vendor for repairs.
NOTE
If you are a system integrator, VAR or OEM, a POST diagnostics
card is recommended. For I/O port 80h codes, refer to App. B.
Memory Errors
1. Make sure that the DIMM modules are properly and fully installed.
2. Determine if different speeds of DIMMs have been installed and verify that the
BIOS setup is confi gured for the fastest speed of RAM used. It is recom-
mended that you use the same RAM speed for all DIMMs in the system.
3. Make sure that you are using the correct type of DDR2 FBD (Fully Buffered) ECC
667/533 SDRAM (*recommended by the manufacturer.)
4. Check for bad DIMM modules or slots by swapping a single module between
four slots and noting the results.
5. Make sure that all memory modules are fully seated in their slots. To install memory modules, begin with Branch 1, then Branch 2, and so on (see Page 2-6).
3-2 Technical Support Procedures
Before contacting Technical Support, please take the following steps. Also, note
that as a motherboard manufacturer, Super Micro does not sell directly to end-users, so it is best to fi rst check with your distributor or reseller for troubleshooting
services. They should know of any possible problem(s) with the specifi c system
confi guration that was sold to you.
1. Please go through the ‘Troubleshooting Procedures’ and 'Frequently Asked Question' (FAQ) sections in this chapter or see the FAQs on our web site (
www.supermicro.com/support/faqs/
2. BIOS upgrades can be downloaded from our web site at
com/support/bios/
)
) before contacting Technical Support.
(http://www.supermicro.
http://
Note: Not all BIOS can be fl ashed; it depends on the modifi cations to the
boot block code.
3. If you still cannot resolve the problem, include the following information when
3-2
Chapter 3: Troubleshooting
contacting Super Micro for technical support:
• Motherboard model and PCB revision number
• BIOS release date/version (this can be seen on the initial display when your
system fi rst boots up)
•System confi guration
An example of a Technical Support form is on our web site at
supermicro.com/support/contact.cfm).
4. Distributors: For immediate assistance, please have your account number ready
when placing a call to our technical support department. We can be reached
by e-mail at support@supermicro.com or by fax at: (408) 503-8000, option
2.
(http://www.
3-3 Frequently Asked Questions
Question: What are the various types of memory that my motherboard can
support?
Answer: The X7DBU/X7DGU has eight 240-pin DIMM slots that support DDR2
FBD ECC 667/533 SDRAM modules. It is strongly recommended that you do not
mix memory modules of different speeds and sizes.
Question: How do I update my BIOS?
Answer: It is recommended that you do not upgrade your BIOS if you are not
experiencing any problems with your system. Updated BIOS fi les are located on
our web site at http://www.supermicro.com/support/bios/. Please check our BIOS
warning message and the information on how to update your BIOS on our web
site. Select your motherboard model and download the BIOS fi le to your computer.
Also, check the current BIOS revision and make sure that it is newer than your
BIOS before downloading. You can choose from the zip fi le and the .exe fi le. If you
choose the zip BIOS fi le, please unzip the BIOS fi le onto a bootable device or a USB
pen. Run the batch fi le using the format fl ash.bat fi lename.rom from your bootable
device or USB pen to fl ash the BIOS. Then, your system will automatically reboot.
If you choose the .exe fi le, please run the .exe fi le under Windows to create the
BIOS fl ash fl oppy disk. Insert the fl oppy disk into the system you wish to fl ash the
BIOS. Then, bootup the system to the fl oppy disk. The BIOS utility will automati-
cally fl ash the BIOS without any prompts. Please note that this process may take
a few minutes to complete. Do not be concerned if the screen is paused for a few
minutes.
(
*Warning: Do not shut down or reset the system while updating BIOS to
prevent possible system boot failure!)
3-3
X7DBU/X7DGU User's Manual
Question: What's on the CD that came with my motherboard?
Answer: The supplied compact disc has quite a few drivers and programs that will
greatly enhance your system. We recommend that you review the CD and install
the applications you need. Applications on the CD include chipset drivers for the
Windows OS, security and audio drivers.
3-4 Returning Merchandise for Service
A receipt or copy of your invoice marked with the date of purchase is required before any warranty service will be rendered. You can obtain service by calling your
vendor for a Returned Merchandise Authorization (RMA) number. When returning
to the manufacturer, the RMA number should be prominently displayed on the
outside of the shipping carton, and mailed prepaid or hand-carried. Shipping and
handling charges will be applied for all orders that must be mailed when service is
complete. For faster service, RMA authorizations may be requested online (http://
www.supermicro.com/support/rma).
This warranty only covers normal consumer use and does not cover damages incurred in shipping or from failure due to the alternation, misuse, abuse or improper
maintenance of products.
During the warranty period, contact your distributor fi rst for any product problems.
3-4
Chapter 4: BIOS
Chapter 4
BIOS
4-1 Introduction
This chapter describes the Phoenix BIOS™ Setup utility for the X7DBU/X7DGU.
The Phoenix ROM BIOS is stored in a fl ash chip and can be easily upgraded using
a fl oppy disk-based program.
Note: Due to periodic changes to the BIOS, some settings may have been added
or deleted and might not yet be recorded in this manual. Please refer to the Manual
Download area of the Supermicro web site <http://www.supermicro.com> for any
changes to the BIOS that may not be refl ected in this manual.
System BIOS
The BIOS is the Basic Input Output System used in all IBM® PC, XT™, AT®, and
PS/2® compatible computers. The Phoenix BIOS stores the system parameters,
types of disk drives, video displays, etc. in the CMOS. The CMOS memory requires
very little electrical power. When the computer is turned off, a backup battery provides power to the CMOS Logic, enabling it to retain system parameters. Each time
the computer is powered on the computer is confi gured with the values stored in
the CMOS Logic by the system BIOS, which gains control at boot up.
How To Change the Confi guration Data
The CMOS information that determines the system parameters may be changed by
entering the BIOS Setup utility. This Setup utility can be accessed by pressing the
<Delete> key at the appropriate time during system boot. (See below.)
Starting the Setup Utility
Normally , the only visible POST (Power On Self Test) routine is the memory test. As
the memory is being tested, press the <Delete> key to enter the main menu of the
BIOS Setup utility. From the main menu, you can access the other setup screens,
such as the Security and Power menus. Beginning with Section 4-3, detailed descriptions are given for each parameter setting in the Setup utility.
Warning: Do not shut down or reset the system while updating BIOS
to prevent possible boot failure.
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X7DBU/X7DGU User's Manual
4-2 Running Setup
*Default settings are in bold text unless otherwise noted.
The BIOS setup options described in this section are selected by choosing the appropriate text from the main BIOS Setup screen. All displayed text is described in
this section, although the screen display is often all you need to understand how
to set the options (See the next page).
When you fi rst power on the computer, the Phoenix BIOS™ is immediately acti-
vated.
While the BIOS is in control, the Setup program can be activated in one of two
ways:
1. By pressing <Delete> immediately after turning the system on, or
2. When the message shown below appears briefl y at the bottom of the screen
during the POST (Power On Self-Test), press the <Delete> key to activate the
main Setup menu:
Press the <Delete> key to enter Setup
4-3 Main BIOS Setup
All main Setup options are described in this section. The main BIOS Setup screen
is displayed below.
Use the Up/Down arrow keys to move among the different settings in each menu.
Use the Left/Right arrow keys to change the options for each setting.
Press the <Esc> key to exit the CMOS Setup Menu. The next section describes in
detail how to navigate through the menus.
Items that use submenus are indicated with the
press the <Enter> key to access the submenu.
icon. With the item highlighted,
4-2
Main BIOS Setup Menu
Main Setup Features
System Time
Chapter 4: BIOS
To set the system date and time, key in the correct information in the appropriate
fi elds. Then press the <Enter> key to save the data.
System Date
Using the arrow keys, highlight the month, day and year fi elds, and enter the correct
data. Press the <Enter> key to save the data.
BIOS Version
This fi eld displays the version number of current BIOS.
BIOS Date
This fi eld displays the date when this version of BIOS was built.
Legacy Diskette A
This setting allows the user to set the type of fl oppy disk drive installed as diskette A.
The options are Disabled, 360Kb 5.25 in, 1.2MB 5.25 in, 720Kb 3.5 in, 1.44/1.25MB,
3.5 in and 2.88MB 3.5 in.
IDE Channel 0 Master/Slave and Secondary IDE Master/Slave
These settings allow the user to set the parameters of IDE Channel 0 Master/Slave
and Secondary IDE Master/Slave slots. Press <Enter> to activate the following
submenu items for detailed options. Set the correct confi gurations accordingly.
The items included in the submenu are:
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X7DBU/X7DGU User's Manual
Type
Selects the type of IDE hard drive. The option Auto will allow the BIOS to
automatically confi gure the parameters of the HDD installed at the connection.
Enter a number between 1 to 39 to select a predetermined HDD type. Select
User to allow the user to enter the parameters of the HDD installed. Select
CDROM if a CDROM drive is installed. Select ATAPI if a removable disk drive
is installed.
Multi-Sector Transfers
This item allows the user to specify the number of sectors per block to be used
in multi-sector transfer. The options are Disabled, 4 Sectors, 8 Sectors, and
16 Sectors.
LBA Mode Control
This item determines whether the Phoenix BIOS will access the IDE Channel 0
Master Device via the LBA mode. The options are Enabled and Disabled.
32 Bit I/O
This option allows the user to enable or disable the function of 32-bit data transfer.
The options are Enabled and Disabled.
Transfer Mode
This option allows the user to set the transfer mode. The options are Standard,
Fast PIO1, Fast PIO2, Fast PIO3, Fast PIO4, FPIO3/DMA1 and FPIO4/DMA2.
Ultra DMA Mode
This option allows the user to select Ultra DMA Mode. The options are Disabled,
Mode 0, Mode 1, Mode 2, Mode 3, Mode 4, and Mode 5.
Parallel ATA
This setting allows the user to enable or disable the function of Parallel ATA. The
options are Enabled and Disabled.
Serial ATA
This setting allows the user to enable or disable the function of Serial ATA. The
options are Disabled and Enabled.
Native Mode Operation (Available when the item-SATA Controller
Mode Operation indicated is set to Compatible.)
Select the native mode for the HDD drives. The options are: Serial ATA,
and Auto.
SATA Controller Mode
Select Compatible to allow the SATA and PATA drives to be automatically-detected
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Chapter 4: BIOS
and be placed in the Legacy Mode by the BIOS. Select Enhanced to allow the
SATA and PATA drives to be to be automatically-detected and be placed in the
Native IDE Mode. (Note: The Enhanced mode is supported by the Windows
2000 OS or a later version.)
When the SATA Controller Mode is set to Enhanced, the following items will
display:
SATA RAID Enable (Available when the item-SATA Controller Mode
Operation indicated is set to Enhanced.)
Select Enable to enable Serial ATA RAID Functions. (*For the Windows OS
environment, use the RAID driver if this feature is set to Enabled. When this item
is set to Enabled, the item: "ICH RAID Code Base" will be available for you to select
either Intel or Adaptec Host RAID fi rmware. If this item is set to Disabled, the item-
SATA AHCI Enable will be available.) The options are Enabled and Disabled.
ICH RAID Code Base (Available when SATA RAID is Enabled.)
Select Intel to enable Intel's SATA RAID fi rmware. Select Adaptec to use Adaptec's
HostRAID fi rmware. The options are Intel and Adaptec.
SATA AHCI (Available when SATA RAID is Disabled.)
Select Enable to enable the function of Serial ATA Advanced Host Interface. (*Take
caution when using this function. This feature is for advanced programmers only.
The options are Enabled and Disabled.)
System Memory
This display informs you how much system memory is detected by the BIOS.
Extended Memory
This display informs you how much extended memory is detected by the BIOS.
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X7DBU/X7DGU User's Manual
4-4 Advanced Setup
Choose Advanced from the Phoenix BIOS Setup Utility main menu with the arrow
keys. Y ou should see the following display . The items with a triangle beside them have
submenus that can be accessed by highlighting the item and pressing <Enter>.
Boot Features
Access the submenu to make changes to the following settings.
QuickBoot Mode
If enabled, this feature will speed up the POST (Power On Self Test) routine by
skipping certain tests after the computer is turned on. The settings are Enabled
and Disabled. If Disabled, the POST routine will run at normal speed.
QuietBoot Mode
This setting allows you to Enable or Disable the graphic logo screen during bootup.
POST Errors
Set to Enabled to display POST Error Messages if an error occurs during bootup.
If set to Disabled, the system will continue to boot without displaying any error
messages even when a boot error occurs.
ACPI Mode
Use the setting to determine if you want to employ ACPI (Advanced Confi guration
and Power Interface) power management on your system. The options are Yes
and No.
Power Button Behavior
If set to Instant-Off, the system will power off immediately as soon as the user hits
the power button. If set to 4-sec., the system will power off when the user
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Chapter 4: BIOS
presses the power button for 4 seconds or longer. The options are instant-off and
4-sec override.
Resume On Modem Ring
Select On to “wake your system up” when an incoming call is received by your
modem. The options are On and Off.
Power Loss Control
This setting allows you to choose how the system will react when power returns
after an unexpected loss of power. The options are Stay Off, Power On, and Last
State.
Watch Dog
If enabled, this option will automatically reset the system if the system is not active
for more than 5 minutes. he options are Enabled and Disabled.
Summary Screen
This setting allows you to Enable or Disable the summary screen which displays
the system confi guration during bootup.
Memory Cache
Cache System BIOS Area
This setting allows you to designate a reserve area in the system memory to be used
as a System BIOS buffer to allow the BIOS to write (cache) data into this reserved
memory area. Select Write Protect to enable this function, and this area will be
reserved for BIOS ROM access only. Select Uncached to disable this function and
make this area available for other devices.
Cache Video BIOS Area
This setting allows you to designate a reserve area in the system memory to be
used as a Video BIOS buffer to allow the BIOS to write (cache) data into this
reserved memory area. Select Write Protect to enable the function and this area
will be reserved for Video BIOS ROM access only. Select Uncached to disable this
function and make this area available for other devices.
Cache Base 0-512K
If enabled, this feature will allow the data stored in the base memory area: block
0-512K to be cached (written) into a buffer , a storage area in Static DROM (SDROM)
or to be written into L1, L2 cache inside the CPU to speed up CPU operations.
Select Uncached to disable this function. Select Write Through to allow data to be
cached into the buffer and written into the system memory at the same time.
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X7DBU/X7DGU User's Manual
Select Write Protect to prevent data from being written into the base memory area
of Block 0-512K. Select Write Back to allow CPU to write data back directly from
the buffer without writing data to the System Memory for fast CPU data processing
and operation. The options are Uncached, Write Through, Write Protect, and Write
Back.
Cache Base 512K-640K
If enabled, this feature will allow the data stored in the memory area: 512K-640K
to be cached (written) into a buffer, a storage area in the Static DROM (SDROM)
or written into L1, L2, L3 cache inside the CPU to speed up CPU operations.
Select Uncached to disable this function. Select Write Through to allow data to
be cached into the buffer and written into the system memory at the same time.
Select Write Protect to prevent data from being written into the base memory area
of Block 512-640K. Select Write Back to allow CPU to write data back directly from
the buffer without writing data to the System Memory for fast CPU data processing
and operation. The options are Uncached, Write Through, Write Protect, and
Write Back.
Cache Extended Memory
If enabled, this feature will allow the data stored in the extended memory area
to be cached (written) into a buffer, a storage area in Static DROM (SDROM) or
written into L1, L2, L3 cache inside the CPU to speed up CPU operations. Select
Uncached to disable this function. Select Write Through to allow data to be cached
into the buffer and written into the system memory at the same time. Select Write
Protect to prevent data from being written into the system memory area above 1MB.
Select Write Back to allow CPU to write data back directly from the buffer without
writing data to the System Memory for fast CPU data processing and operation.
The options are Uncached, Write Through, Write Protect, and Write Back.
Discrete MTRR Allocation
If enabled, MTRRs (-Memory Type Range Registers) are confi gured as distinct, separate
units and cannot be overlapped. Set to Enabled to enhance graphic performance
when using a Linux graphic driver that requires write-combining confi guration with
4GB or more memory. The options are Enabled and Disabled.
PCI Confi guration
Access the submenu to make changes to the following settings for PCI devices.
Onboard GLAN1/Onboard GLAN2 (Gigabit- LAN) OPROM Confi gure
Enabling this option provides the capability to boot from the GLAN port specifi ed.
The options are Disabled and Enabled.
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Chapter 4: BIOS
Default Primary Video Adapter
This feature allows the user to specify which video adapter to be used as the
default primary video adapter--the onboard video adapter or others. The options
are Other and Onboard Video.
Emulated IRQ Solutions
When this item is set to Enabled, Emulated IRQ Scheme allows PCI devices to
run on legacy operating systems that use the MSI mechanism to generate INTX
compatible interrupts. The options are Disabled and Enabled.
PCI-Exp. I/O Performance
Some add-on cards perform faster with the coalesce feature, which limits the
payload size to 128 Bytes; while others perform faster with a payload size of 256
Bytes which inhibits coalesce features. Please refer to your add-on card user
guide for the desired setting. The options are Payload (256 Bytes) and Coalesce
Enabled (128 Bytes).
PCI Parity Error Forwarding
The feature allows SERR and PERR errors detected in PCI slots to be sent
(forwarded) to the BIOS DMI Event Log for the user to review. The options are
Enabled and Disabled.
ROM Scan Ordering
This feature allows the user to decide which Option ROM to be activated fi rst. The
options are Onboard fi rst and Add-On fi rst.
PCI Fast Delayed Transaction
Enable this function to improve DMA data transfer rate for a PCI 32-bit multimedia
card. The options are Enable and Disabled.
Reset Confi guration Data
If set to Yes, this setting clears the Extended System Confi guration Data- (ESCD)
area. The options are Yes and No.
Frequency for PCI-X#2
This option allows the user to change the bus frequency for the devices installed
in the slot indicated. The options are Auto, PCI 33 MHz, PCI 66 MHz, PCI-X 66
MHz, PCI-X 100 MHz and PCI-X 133 MHz.
L1 Blue Slot PCI-Exp. x8, L2 Slot PCI-Exp. x8, R1 Slot PCI-X 133
MHz, R2 Slot PCI-Exp. x8/x4 and R3 Slot PCI-Exp. x4
Access the submenu for each of the settings above to make changes to the
following:
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X7DBU/X7DGU User's Manual
Option ROM Scan
When enabled, this setting will initialize the device expansion ROM. The options
are Enabled and Disabled.
Enable Master
This setting allows you to enable the selected device as the PCI bus master.
The options are Enabled and Disabled.
Latency Timer
This setting allows you to set the clock rate for Bus Master. A high-priority, highthroughout device may benefi t from a greater clock rate. The options are Default,
0020h, 0040h, 0060h, 0080h, 00A0h, 00C0h, and 00E0h. For Unix, Novell and
other Operating Systems, please select the option: other. If a drive fails after
the installation of a new software, you might want to change this setting and
try again. A different OS requires a different Bus Master clock rate.
Large Disk Access Mode
This setting determines how large hard drives are to be accessed. The options are
DOS or Other (for Unix, Novelle NetWare and other operating systems).
Advanced Chipset Control
Access the submenu to make changes to the following settings.
Warning: Take caution when changing the Advanced settings. An incorrect
setting, a very high DRAM frequency or an incorrect DRAM timing may cause
the system to become unstable. When this occurs, reset the setting to the
default setting.
SERR Signal Condition
This setting specifi es the ECC Error conditions that an SERR# is to be asserted.
The options are None, Single Bit, Multiple Bit, and Both.
J5 Slot Link Width
Use this feature to confi gure Link Width settings for the devices connected to
PCI-E Slot J5. After changing the Link Width setting, please reboot the system for
the new Link Width setting to take effect. The options are One (Connection) in x
16 and Two in x 8.
4GB PCI Hole Granularity
This feature allows you to select the granularity of PCI hole for PCI slots. If MTRRs
are not enough, this option may be used to reduce MTRR occupation. The options
are: 256 MB, 512 MB, 1GB and 2GB.
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Chapter 4: BIOS
Memory Branch Mode
This option determines how the two memory branches operate. System address
space can either be interleaved between the two branches or Sequential from one
branch to another. Mirror mode allows data correction by maintaining two copies
of data in two branches. Single Channel 0 allows a single DIMM population during
system manufacturing. The options are Interleave, Sequential, Mirroring, and
Single Channel 0.
Branch 0/1 Rank Interleaving & Sparing
Select enable to enable the functions of Memory Interleaving and Memory Sparing
for Branch 0/1 Rank. The options for Memory Interleaving are 1:1, 2:1 and 4:1. The
options for Sparing are Enabled and Disabled.
Enhanced x8 Detection
Select Enabled to enable Enhanced x8 DRAM UC Error Detection. The options
are Disabled and Enabled.
High Temperature DRAM Operation
When set to Enabled, the BIOS will refer to the SPD table to set the maximum
DRAM temperature. If disabled, the BIOS will set the maximum DRAM temperature
based on a predefi ned value. The options are Enabled and Disabled.
AMB Thermal Sensor
Select Enabled to activate the thermal sensor embedded in the Advanced Memory
Buffer on a fully buffered memory module for thermal monitoring. The options are
Disabled and Enabled.
Thermal Throttle
Select Enabled to enable closed-loop thermal throttling on a fully buffered (FBD)
memory module. In the closed-loop thermal environment, thermal throttling will be
activated when the temperature of the FBD DIMM module exceeds a predefi ned
threshold. The options are Enabled and Disabled.
Global Activation Throttle
Select Enabled to enable open-loop global thermal throttling on a fully buffered
(FBD) memory module to make it active whenever the number of activate control
exceeds a predefi ned number. The options are Enabled and Disabled.
Crystal Beach Features
This feature was designed to implement Intel's I/O AT (Acceleration Technology) to
accelerate the performance of TOE devices. (Note: A TOE device is a specialized,
dedicated processor that is installed on an add-on card or a network card to handle
some or all packet processing of the add-on card. For this motherboard, the TOE
device is built inside the ESB 2 South Bridge chip.) The options are Enabled and
Disabled.
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X7DBU/X7DGU User's Manual
Route Port 80h Cycles to
This feature allows the user to decide which bus to send debug information to.
The options are PCI and LPC.
Clock Spectrum Feature
If Enabled, the BIOS will monitor the level of Electromagnetic Interference caused
by the components and will attempt to decrease the interference whenever needed.
The options are Enabled and Disabled.
High Precision Event Time
Select Yes to activate the High Precision Event Timer (HPET), which is capable of
producing periodic interrupts at a much higher frequency than a Real-time Clock
(RTC) can in synchronizing multimedia streams, providing smooth playback and
reducing the dependency on other timestamp calculation devices, such as an x86
RDTSC Instruction embedded in a CPU. The High Precision Event Timer is used to
replace the 8254 Programmable Interval Timer. The options are Yes and No.
USB Function
Select Enabled to enable the function of USB devices specifi ed. The settings are
Enabled and Disabled.
Legacy USB Support
This setting allows you to enable support for Legacy USB devices. The settings
are Enabled and Disabled.
Advanced Processor Options
Access the submenu to make changes to the following settings.
CPU Speed
This is a display that indicates the speed of the installed processor.
Frequency Ratio (Available when supported by the CPU.)
The feature allows the user to set the internal frequency multiplier for the CPU.
The options are: Default and x12.
Core-Multi-Processing (Available when supported by the CPU.)
Set to Enabled to use a processor's Second Core and beyond. (Please refer to Intel's
website for more information.) The options are Disabled and Enabled.
Machine Checking (Available when supported by the CPU.)
Set to Enabled to use this function which will allow the CPU to detect and report
hardware (machine) errors via a set of model-specifi c registers (MSRs). The options
are Disabled and Enabled.
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Chapter 4: BIOS
Thermal Management 2 (Available if supported by the CPU.)
Set to Enabled to use Thermal Management 2 (TM2) which will lower CPU voltage
and frequency when the CPU temperature reaches a predefi ned overheat threshold.
Set to Disabled to use Thermal Manager 1 (TM1), allowing CPU clocking to be
regulated via CPU Internal Clock modulation when the CPU temperature reaches
the overheat threshold. The options are Disabled and Enabled.
C1 Enhanced Mode (Available when supported by the CPU.)
Set to Enabled to enable Enhanced Halt State to lower CPU voltage/frequency to
prevent overheat. The options are Enabled and Disabled. (Note: please refer to
Intel’s web site for detailed information.)
Execute Disable Bit (Available when supported by the CPU.)
Set to Enabled to allow the processor to classify areas in memory where an
application code can execute and where it cannot, and thus preventing a worm or
a virus from inserting and creating a fl ood of codes to overwhelm the processor
or damage the system during an attack. (Note: this feature is available when your
OS and your CPU support the function of Execute Disable Bit.) The options are
Disabled and Enabled. (Note: For more information regarding hardware/software
support for this function, please refer to Intel's and Microsoft's web sites.)
Adjacent Cache Line Prefetch (Available when supported by the
CPU.)
The CPU fetches the cache line for 64 bytes if this option is set to Disabled. The
CPU fetches both cache lines for 128 bytes as comprised if Enabled. The default
settings are Disabled for the Intel 5100 Series Processors and Enable for the
5000 Series Processors.
Hardware Prefetcher (Available when supported by the CPU.)
Set to Enabled to activate the hardware components that are used in conjunction
with software programs to prefetch data in order to shorten execution cycles and
maximize data processing effi ciency. The options are Disabled and Enabled.
Direct Cache Access (Available when supported by the CPU.)
Set to Enable to route inbound network IO traffi c directly into processor caches to
reduce memory latency and improve network performance. The options are Enabled
and Disabled. If this item is set to Enabled, the following item will display.
DCA Delay Clocks (Available if supported by the CPU.)
This feature allows the user to set the clock delay setting from snoop to prefetch
for Direct Cache Access. Select a setting from 8 (bus cycles) to 120 (bus cycles)
(in 8 -cyc le inc rement). Th e default s etti ng is 32 (bus cycles).
4-13
X7DBU/X7DGU User's Manual
Intel <R> Virtualization Technology (Available when supported by
the CPU.)
Select Enabled to use the feature of Virtualization Technology to allow one platform
to run multiple operating systems and applications in independent partitions, creating
multiple "virtual" systems in one physical computer. The options are Enabled and
Disabled. (Note: If there is any change to this setting, you will need to power off
and restart the system for the change to take effect.) Please refer to Intel’s web
site for detailed information.
Intel EIST Support (Available when supported by the CPU.)
Select Enabled to use the Enhanced Intel SpeedStep Technology and allow the
system to automatically adjust processor voltage and core frequency in an effort
to reduce power consumption and heat dissipation. The options are Enabled and
Disabled. Please refer to Intel’s web site for detailed information.
I/O Device Confi guration
Access the submenu to make changes to the following settings.
KBC Clock Input
This setting allows you to select clock frequency for the Keyboard Controller. The
options are 6MHz, 8MHz, 12MHz, and 16MHz.
Serial Port A
This setting allows you to decide how Serial Port A is controlled by the system.
The options are Enabled (user defined), Disabled, and Auto (BIOS- or OScontrolled).
Base I/O Address
This setting allows you to select the base I/O address for Serial Port A. The
options are 3F8, 2F8, 3E8, and 2E8.
Interrupt
This setting allows you to select the IRQ (interrupt request) for Serial Port A.
The options are IRQ3 and IRQ4.
Serial Port B
This setting allows you to decide how Serial Port B is controlled by the system.
The options are Enabled (user defi ned), Disabled, Auto (BIOS controlled) and OS
Controlled.
Mode
This setting allows you to set the type of device that will be connected to Serial
Port B. The options are Normal and IR (for an infrared device).
4-14
Chapter 4: BIOS
Base I/O Address
This setting allows you to select the base I/O address for Serial Port B. The
options are 3F8, 2F8, 3E8 and 2E8.
Interrupt
This setting allows you to select the IRQ (interrupt request) for Serial Port B.
The options are IRQ3 and IRQ4.
Floppy Disk Controller
This setting allows you to decide how Floppy Disk Controller is managed by the
system. The options are Enabled (user defi ned), Disabled, and Auto (BIOS and
OS controlled).
Base I/O Address
This setting allows you to select the base I/O address for the Floppy port. The
options are Primary and Secondary.
DMI Event Logging
Access the submenu to make changes to the following settings.
Event Log Validity
This is a display to inform you of the event log validity. It is not a setting.
Event Log Capacity
This is a display to inform you of the event log capacity. It is not a setting.
View DMI Event Log
Highlight this item and press <Enter> to view the contents of the event log.
Event Logging
This setting allows you to Enable or Disable event logging.
ECC Event Logging
This setting allows you to Enable or Disable ECC event logging.
Mark DMI Events as Read
Highlight this item and press <Enter> to mark the DMI events as read.
Clear All DMI Event Logs
Select Yes and press <Enter> to clear all DMI event logs. The options are Yes
and No.
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X7DBU/X7DGU User's Manual
Console Redirection
Access the submenu to make changes to the following settings.
COM Port Address
This item allows you to specify which COM port to direct the remote console to:
Onboard COM A or Onboard COM B. This setting can also be Disabled.
BAUD Rate
This item allows you to set the BAUD rate for console redirection. The options are
300, 1200, 2400, 9600, 19.2K, 38.4K, 57.6K, and 115.2K.
Console Type
This item allows you to set console redirection type. The options are VT100,
VT100,8bit, PC-ANSI, 7bit, PC ANSI, VT100+, VT-UTF8 and ASCII.
Flow Control
This item allows you to select the fl ow control option for console redirection. The
options are: None, XON/XOFF, and CTS/RTS.
Console Connection
This item allows you to decide how console redirection is to be connected: either
Direct or Via Modem.
Continue CR after POST
This item allows you to decide if you want to continue with console redirection
after the POST routine. The options are On and Off.
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Chapter 4: BIOS
Hardware Monitor
This feature allows the user to monitor system health and review the status of each
item as displayed.
Overheat Alarm
This option allows the user to select the CPU Overheat Alarm setting which determines when the CPU OH alarm will be activated to provide warning of possible
CPU overheat.
Warning! 1.Any temperature that exceeds the CPU threshold temperature
predefi ned by the CPU manufacturer may result in CPU overheat or system
instability. When the CPU temperature reaches this predefi ned threshold,
the CPU and system cooling fans will run at full speed.
2. To avoid possible system overheating, please be sure to provide adequate airfl ow to your system.
The options are:
Early Alarm: Select this setting if you want the CPU overheat alarm (including the
•
LED and the buzzer) to be triggered as soon as the CPU temperature reaches
the CPU overheat threshold as predefi ned by the CPU manufacturer.
Default Alarm
• : Select this setting if you want the CPU overheat alarm (in-
cluding the LED and the buzzer) to be triggered when the CPU temperature
reaches about 5
manufacturer to give the CPU and system fans additional time needed for CPU
and system cooling. In both the alarms above, please take immediate action
as shown below.
PEC
I Agent 1/2 (Temperatures)/System Temperature
Note: The following item display temperature readings for the PECI Agents and
the system. These items are displayed for your reference only.
PECI (Platform Environment Control Interface) Agent 1/PECI Agent 2
o
C above the threshold temperature as predefi ned by the CPU
These features will display the temperature readings for PECI Agent 1 and PECI
Agent 2 as detected by the BIOS:
Low – This level is considered as the ‘normal’ operating state. The PECI Agent
temperature is well below its ‘T emperature Tolerance’. The cooling fans and PECI
Agent will run normally as confi gured in the BIOS (Fan Speed Control). User
intervention: No action required.
Medium – The PECI Agent is running warmer. This is a ‘precautionary’ level and
generally means that there may be factors contributing to this condition, but
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X7DBU/X7DGU User's Manual
the PECI Agent is still within its normal operating state and below its ‘Temperature
T olerance’. The cooling fans will run normally as confi gured in the BIOS. The fans
may adjust to a faster speed depending on the Fan Speed Control settings.
User intervention: No action is required. However, consider checking the cooling
fans and the chassis ventilation for blockage.
High – The PECI Agent is running hot. This is a ‘caution’ level since the PECI
Agent ’s ‘Temperature Tolerance’ has been reached (or has been exceeded) and
may activate an overheat alarm. The system may shut down if it continues for
a long period to prevent damage to the PECI Agent.
User intervention: If the system buzzer and Overheat LED has activated, take
action immediately by checking the system fans, chassis ventilation and room
temperature to correct any problems.
System Temperature
This item displays the absolute system temperature status as detected by the
BIOS:
Fan1-Fan8 Speeds
If the feature of Auto Fan Control is enabled, the BIOS will automatically display
the status of the fans indicated in this item.
Fan Speed Control Modes
This feature allows the user to decide how the system controls the speeds of the
onboard fans. The CPU temperature and the fan speed are correlative. When the
CPU on-die temperature increases, the fan speed will also increase, and vise versa.
If the option is set to 3-pin fan, the fan speed is controlled by voltage. If the option
is set to 4-pin, the fan speed will be controlled by Pulse Width Modulation (PWM).
Select 3-pin if your chassis came with 3-pin fan headers. Select 4-pin if your chassis came with 4-pin fan headers. Select Workstation if your system is used as a
Workstation. Select Server if your system is used as a Server. Select Disable to
disable fan speed control and allow the onboard fans to constantly run at full speed
(12V). The Options are: 1. Disable (running@Full Speed), 2. 3-pin (Server), 3.
3-pin (Workstation), 4. 4-pin (Server) and 5. 4-pin (Workstation).
Voltage Monitoring
The following items will be monitored and displayed:
Vcore A/Vcore B, -12V/+12V, P1V5/CPU_VTT/Vbat, +3.3V, 5Vsb/5VDD
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Chapter 4: BIOS
IPMI (The option is available only when an IPMI card is installed
in the system.)
IPMI Specifi cation Version:
This item displays the current IPMI Version.
Firmware Version: This item displays the current Firmware Version.
System Event Logging
Select Enabled to enable IPMI Event Logging. When this function is set to Disabled,
the system will continue to log events received via system interface. The options
are Enabled and Disabled.
Clear System Event Logging
Enabling this function to force the BIOS to clear the system event logs during the
next cold boot. The options are Enabled and Disabled.
Existing Event Log Number
This item displays the number of the existing event log.
Event Log Control
System Firmware Progress
Enabling this function to log POST progress. The options are Enabled and
Disabled.
BIOS POST Errors
Enabling this function to log POST errors. The options are Enabled and
Disabled.
BIOS POST Watch Dog
Set to Enabled to use the POST Watch Dog timer. The options are Enabled and
Disabled.
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X7DBU/X7DGU User's Manual
OS Boot Watch Dog
Set to Enabled to enable OS Boot Watch Dog support.The options are Enabled
and Disabled.
Timer for Loading OS (Minutes)
This feature allows the user to set the time value (in minutes) for the previous
item: OS Boot Watch Dog by keying-in a desired number in the blank. The
default setting is 10 (minutes.) (Please ignore this option when OS Boot Watch
Dog is set to Disabled.)
Time Out Option
This feature allows the user to determine what action to take in an event of a
system boot failure. The options are No Action, Reset, Power Off and Power
Cycles.
System Event Log/System Event Log (List Mode)
These options display the System Event (SEL) Log and System Event (SEL) Log
in List Mode. Items include: SEL (System Event Log) Entry Number, SEL Record
ID, SEL Record Type, Time Stamp, Generator ID, SEL Message Revision, Sensor
Type, Sensor Number, SEL Event Type, Event Description, and SEL Event Data.
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Chapter 4: BIOS
Realtime Sensor Data
This feature display information from motherboard sensors, such as temperatures,
fan speeds and voltages of various components.
IPMI LAN Confi guration
The following features allow the user to confi gure and monitor IPMI LAN settings.
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X7DBU/X7DGU User's Manual
VLAN Tagging
Select Enabled to enable Virtual LAN(s) for IPMI connections and allow the user
to confi gure VLAN settings. The options are Enabled and Disabled.
VLAN ID
If VLAN Tagging above is set to Enabled, this item allows the user to change
the VLAN ID. If VLAN Tagging is disabled, this item will be ignored by the
fi rmware.
IP Address Source
Select the source of this machine's IP address. If Static is selected, you will need
to know and enter manually the IP address of this machine below. If DHCP is
selected, the BIOS will search for a DHCP (Dynamic Host Confi guration Protocol)
server in the network it is attached to, and request the next available IP address.
The options are DHCP and Static.
IP Address
This item displays the IP address for the IPMI connection detected.
IP Subnet Mask
This item displays the IP Subnet Mask for the IPMI connection detected.
Default Gateway
This item displays the Default Gateway for the IPMI connection detected.
MAC Address
This item displays the MAC Address for the IPMI connection detected.
Update LAN Settings
This item saves the IPMI Lan Confi guration settings into memory. If you wish
to change any of the settings, select Yes and press F10 to save your settings.
Otherwise, leave this setting to its default setting of No.
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Chapter 4: BIOS
4-5 Security
Choose Security from the Phoenix BIOS Setup Utility main menu with the arrow
keys. You should see the following display. Security setting options are displayed by
highlighting the setting using the arrow keys and pressing <Enter>. All Security BIOS
settings are described in this section.
Supervisor Password Is:
This feature indicates if a supervisor password has been entered to the system.
Clear means such a password has not been used, and Set means a supervisor
password has been entered.
User Password Is:
This feature indicates if a user password has been entered to the system. Clear
means such a password has not been used, and Set means a user password has
been entered.
Set Supervisor Password
When the item Set "Supervisor Password" is highlighted, hit the <Enter> key . When
prompted, type the Supervisor's password in the dialogue box to set or to change
supervisor's password, which allows access to the BIOS.
Set User Password
When the item "Set User Password" is highlighted, hit the <Enter> key. When
prompted, type the user's password in the dialogue box to set or to change the
user's password, which allows access to the system at boot-up.
Password on Boot
This setting allows you to determine if a password is required for a user to enter
the system at system boot. The options are Enabled (password required) and
Disabled (password not required).
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X7DBU/X7DGU User's Manual
4-6 Boot
Choose Boot from the Phoenix BIOS Setup Utility main menu with the arrow keys.
You should see the following display. See details on how to change the order and
specs of boot devices in the Item Specifi c Help window. All Boot BIOS settings are
described in this section.
Boot List
Candidate
List
Boot Priority Order/Excluded from Boot Orders
The devices included in the boot list section (above) are bootable devices listed in
the sequence of boot order as specifi ed. The boot functions for the devices included
in the candidate list (above) are currently disabled. Use a <+> key or a <-> key to
move the device up or down. Use the <f> key or the <r> key to specify the type of
an USB device, either fi xed or removable. You can select one item from the boot
list and hit the <x> key to remove it from the list of bootable devices (to make its
resource available for other bootable devices). Subsequently , you can select an item
from the candidate list and hit the <x> key to remove it from the candidate list and
put it in the boot list. This item will then become a bootable device. See details on
changing the boot priority order of a device in the "Item Specifi c Help" window.
4-24
Chapter 4: BIOS
4-7 Exit
Choose Exit from the Phoenix BIOS Setup Utility main menu with the arrow keys. Y ou
should see the following display. All Exit BIOS settings are described in this section.
Exit Saving Changes
Highlight this item and hit <Enter> to save any changes you've made and to exit
the BIOS Setup utility.
Exit Discarding Changes
Highlight this item and hit <Enter> to exit the BIOS Setup utility without saving any
changes you may have made.
Load Setup Defaults
Highlight this item and hit <Enter> to load the default settings for all items in the
BIOS Setup. These are the safest settings to use.
Discard Changes
Highlight this item and hit <Enter> to discard (cancel) any changes you've made.
You will remain in the Setup utility.
Save Changes
Highlight this item and hit <Enter> to save any changes you've made. You will
remain in the Setup utility.
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X7DBU/X7DGU User's Manual
Notes
4-26
Appendix A: POST Error Beep Codes
Appendix A
POST Error Beep Codes
This section lists POST (Power On Self Test) error beep codes for the Phoenix BIOS.
POST error beep codes are divided into two categories: recoverable and terminal.
This section lists Beep Codes for recoverable POST errors.
Recoverable POST Error Beep Codes
When a re cove rab le t yp e of er r or oc c ur s dur ing P OST, BIOS will d isp lay a PO ST
code t hat desc ri bes th e prob lem. BI OS may al so iss ue one of t he fol lowin g beep
codes:
1 long and t wo sh or t beeps - v ideo c onfi guration error
1 repetit ive lon g beep - no m emor y detec ted
1 conti nuous be ep with Fro nt Panel Ove rheat L ED on - system ove rheat
A-1
X7DBU/X7DGU User's Manual
Notes
A-2
Appendix B: Installing the Windows OS
Appendix B
Installing the Windows OS
After all hardware components have been installed, you must fi rst confi gure Intel
South Bridge RAID Settings before you install the Windows OS and other software
drivers. To confi gure Intel or Adaptec HostRAID settings, please refer to RAID
Confi guration User Guides posted on our website at www.supermicro.com/support/
manuals.
B-1 Installing the Windows XP/2000/2003 OS for
Systems with RAID Functions
Insert Microsoft's Windows XP/2000/2003 Setup CD in the CD Driver, and the 1.
system will start booting up from CD.
Press the <F6> key when the message-" Press F6 if you need to install a 2.
third party SCSI or RAID driver" displays.
When the Windows XP/2000/2003 Setup screen appears, press "S" to specify 3.
additional device(s).
Insert the driver diskette-"Intel AA RAID XP/2000/2003 Driver for ESB2" into 4.
Drive A: and press the <Enter> key.
Choose the Intel(R) ESB2 5. SATA RAID Controller from the list indicated in the
XP/2000/2003 Setup Screen, and press the <Enter> key.
Press the <Enter> key to continue the installation process. (If you need to 6.
specify any additional devices to be installed, do it at this time.) Once all
devices are specifi ed, press the <Enter> key to continue with the installation.
From the Windows XP/2000/2003 Setup screen, press the <Enter> key. The 7.
XP/2000/2003 Setup will automatically load all device fi les and then, continue
the Windows XP/2000/2003 installation.
After the Windows XP/2000/2003 OS Installation is completed, the system will 8.
automatically reboot.
Insert the Supermicro Setup CD that came with your motherboard into the CD 9.
Drive during system boot, and the main screen as shown on Page C-1 will
display. Follow the instructions given in Appendix C to complete other driver/
software installation.
B-1
X7DBU/X7DGU User's Manual
B-2 Installing the Windows XP/2000/2003 OS for
Systems without RAID Functions
Insert Microsoft's Windows XP/2000/2003 Setup CD in the CD Drive, and the 1.
system will start booting up from CD.
Continue with the OS installation. The Windows OS Setup screen will display.2.
From the Windows XP/2000/2003 Setup screen, press the <Enter> key. The 3.
XP/2000/2003 Setup will automatically load all device fi les and then continue
with the Windows XP/2000/2003 installation.
After the Windows XP/2000/2003 OS Installation is completed, the system will 4.
automatically reboot.
Insert the Supermicro Setup CD that came with your motherboard into the 5.
CD Drive during system boot, and the main screen as shown on Page C-1
will display. Follow the instructions given in Appendix C to complete other
driver/software installation.
B-2
Appendix C: Installing Other Software Programs and Drivers
Appendix C
Installing Other Software Programs and Drivers
C-1 Installing other Software Programs and Drivers
After you've installed the Windows Operating System, a screen as shown below
will appear. You are ready to install software programs and drivers that have not
yet been installed. To install these software programs and drivers, click the icons
to the right of these items.
Driver/Tool Installation Display Screen
Notes:
1. Click the icons showing a hand writing on the paper to view the readme
fi les for each item. Click on a computer icon to the right of an item to
install an item (from top to the bottom) one at a time. After installing each
item, you must reboot the system before proceeding with the next item
on the list. The bottom icon with a CD on it allows you to view the entire
contents of the CD.
2. When making a SATA storage driver disk by booting into a Driver CD,
please set the SATA Confi guration to "Compatible Mode" and confi gure
SATA as IDE in the BIOS Setup. After making the driver diskette, be sure
to change the SATA settings back to your original settings.
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X7DBU/X7DGU User's Manual
C-2 Confi guring Supero Doctor III
The Supero Doctor III program is a web-base management tool that supports
remote management capability. It includes Remote and Local Management tools.
The local management is called the SD III Client. The Supero Doctor III program
included on the CDROM that came with your motherboard allows you to monitor
the environment and operations of your system. Supero Doctor III displays crucial
system information such as CPU temperature, system voltages and fan status. See
the Figure below for a display of the Supero Doctor III interface.
Note 1: The default user name and password are ADMIN.
Note 2: In the Windows OS environment, the Supero Doctor III settings take pre-
cedence over the BIOS settings. When fi rst installed, Supero Doctor III adopts the
temperature threshold settings previously set in the BIOS. Any subsequent changes
to these thresholds must be made within Supero Doctor, since the SD III settings
override the BIOS settings. For the Windows OS to adopt the BIOS temperature
threshold settings, please change the SDIII settings to be the same as those set
in the BIOS.
Supero Doctor III Interface Display Screen-I (Health Information)
C-2
Appendix C: Installing Other Software Programs and Drivers
Supero Doctor III Interface Display Screen-II (Remote Control)
Note: SD III Software Revision 1.0 can be downloaded from our Web site at: ftp://
ftp.supermicro.com/utility/Supero_Doctor_III/. You can also download SDIII User's
Guide at: http://www.supermicro.com/PRODUCT/Manuals/SDIII/UserGuide.pdf. For
Linux, we will still recommend that you use Supero Doctor II.
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X7DBU/X7DGU User's Manual
Notes
C-4
(Disclaimer Continued)
The products sold by Supermicro are not intended for and will not be used in life support systems, medical equipment, nuclear facilities or systems, aircraft, aircraft devices,
aircraft/emergency communication devices or other critical systems whose failure to perform be reasonably expected to result in signifi cant injury or loss of life or catastrophic
property damage. Accordingly, Supermicro disclaims any and all liability, and should buyer use or sell such products for use in such ultra-hazardous applications, it does so
entirely at its own risk. Furthermore, buyer agrees to fully indemnify, defend and hold Supermicro harmless for and against any and all claims, demands, actions, litigation, and
proceedings of any kind arising out of or related to such ultra-hazardous use or sale.
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