The information in this User’s Manual has been carefully reviewed and is believed to be accurate.
The vendor assumes no responsibility for any inaccuracies that may be contained in this document,
makes no commitment to update or to keep current the information in this manual, or to notify any
person or organization of the updates. Please Note: For the most up-to-date version of this
manual, please see our web site at www.supermicro.com.
Super Micro Computer, Inc. ("Supermicro") reserves the right to make changes to the product
described in this manual at any time and without notice. This product, including software, if any,
and documentation may not, in whole or in part, be copied, photocopied, reproduced, translated or
reduced to any medium or machine without prior written consent.
IN NO EVENT WILL SUPERMICRO BE LIABLE FOR DIRECT, INDIRECT, SPECIAL, INCIDENTAL,
SPECULATIVE OR CONSEQUENTIAL DAMAGES ARISING FROM THE USE OR INABILITY TO
USE THIS PRODUCT OR DOCUMENTATION, EVEN IF ADVISED OF THE POSSIBILITY OF
SUCH DAMAGES. IN PARTICULAR, SUPERMICRO SHALL NOT HAVE LIABILITY FOR ANY
HARDWARE, SOFTWARE, OR DATA STORED OR USED WITH THE PRODUCT, INCLUDING THE
COSTS OF REPAIRING, REPLACING, INTEGRATING, INSTALLING OR RECOVERING SUCH
HARDWARE, SOFTWARE, OR DATA.
Any disputes arising between manufacturer and customer shall be governed by the laws of Santa
Clara County in the State of California, USA. The State of California, County of Santa Clara shall
be the exclusive venue for the resolution of any such disputes. Supermicro's total liability for all
claims will not exceed the price paid for the hardware product.
FCC Statement: This equipment has been tested and found to comply with the limits for a Class B
digital device pursuant to Part 15 of the FCC Rules. These limits are designed to provide reasonable
protection against harmful interference in a residential installation. This equipment generates,
uses, and can radiate radio frequency energy and, if not installed and used in accordance with the
manufacturer’s instruction manual, may cause interference with radio communications. However,
there is no guarantee that interference will not occur in a particular installation. If this equipment
does cause harmful interference to radio or television reception, which can be determined by turning
the equipment off and on, you are encouraged to try to correct the interference by one or more
of the following measures: Reorient or relocate the receiving antenna. Increase the separation
between the equipment and the receiver. Connect the equipment into an outlet on a circuit different
from that to which the receiver is connected. Consult the dealer or an experienced radio/television
technician for help.
California Best Management Practices Regulations for Perchlorate Materials: This Perchlorate
warning applies only to products containing CR (Manganese Dioxide) Lithium coin cells. “Perchlorate
Material-special handling may apply. See www.dtsc.ca.gov/hazardouswaste/perchlorate”
WARNING: Handling of lead solder materials used
in this product may expose you to lead, a chemical
known to the State of California to cause birth defects
and other reproductive harm.
Manual Revision: Rev. 1.0a
Release Date: April 4, 2008
Unless you request and receive written permission from Super Micro Computer, Inc., you may not
copy any part of this document.
Information in this document is subject to change without notice. Other products and companies
referred to herein are trademarks or registered trademarks of their respective companies or mark
holders.
Note:The drawings and pictures shown in this manual were based on the latest
PCB Revision available at the time of publishing of the manual. The motherboard
you’ve received may or may not look exactly the same as the graphics shown in
the manual.
1-3
X7DA3+ User's Manual
X7DA3+ Motherboard Layout
(not drawn to scale)
KB/
Mouse
JKM1
US
1/2/3
JUSB1
OM1
C
LAN1/2
HD
Audio
/
0
B
J
Parrallel
Port
JLAN1
J21
JC1
GLAN
R
CTL
COM1
JLA
Slot
Fan6
J9B2
1
J9B
J8B3
2
J8B
J8B1
B3
J7
7B2
J
J7B1
UPER X7DA3+
S
N
1
Audio
CTRL
7
SIM LP IPMI
6
Slot
PCI-Exp x16
Slot5
PCI-33MHz
2
C
JI
lot4
S
P
JWD
Slot3
PCI-X 133
JPL1
2
Slot
PCI-X 133
WOR
J
1
Slot
PCI
PWR
DIMM 4B (Bank 4)
DIMM 4A (Bank 4)
D
DIMM 3A (Bank 3)
D
DIMM 2A (Bank 2)
DIMM 1B
DIMM 1A (Bank 1)
CD1
2
C4
JI
3
4
x
p
CI-Ex
MHz
2
JPL
MHz
2
JI
00 MH
-X 1
4-Pin
Fan5
24-Pin
JPW2
IMM 3B (Bank
IMM 2B (Bank
(Ban
®
2
C2
I
J
C1
reen
ZCR (G
z
ATX PWR
3
2
k 1)
Battery
Slot)
JPW1
)
)
reencree
G
North Bridge
JL
1
SATA0
CPU
Fan 1
JS
k
SMB
1
Fan7
J3P
JBT1
PX
SATA1
JS2
J17
JAR
H
USB4/5
SATA4
JS5
SATA2
J
PSF
S
8-pin PWR
JPW3
1
Fan
JF1
Floppy
T
4-7
0-3
SAS4-7
SAS0-3
SPK
PW LED
LE1
SGPIO1
J29
J30
SGPIO2
Compact Flash
JIDE2
JSM2
JSM1
Fan4
FP Control
Fan2
JD1
JOH1
DE1
I
IDE1
J
CPU1
CPU2
CPU
Fan2
Fan3
Fan8
F1
JW
JCF1
South
Bridge
SAS
Controller
JUSB2
A5
T
SA
JS6
A3
T
SA
WOL
J
JS4
3
IOS
B
22
J
AC
ACT
JPS1
S10
J
SAS ACT4-7 LEDs
SAS ACT0-3 LEDs
Notes:
1. Jumpers not indicated are for test purposes only.
2. See Chapter 2 for detailed information on jumpers, I/O ports and JF1 front panel
connections.
3. " " indicates the location of Pin 1.
4. Please install the ZCR card on the green slot for it to work properly.
5. The drawings and pictures shown in this manual were based on the latest
PCB Revision available at the time of publishing of the manual. The motherboard
you’ve received may or may not look exactly the same as the graphics shown in
the manual.
1-4
Chapter 1: Introduction
Quick Reference (X7DA3+)
Jumper Description Default Setting
J3P 3rd PWR Failure Detect
JAR Alarm Reset Off (Disabled)
JBT1 CMOS Clear See Chapter 2
JCF1 Compact Card Master/Slave Select On (Master)
JI2C1/JI2C2 SMB to PCI-X Slots Pins 2-3 (Disabled)
JI2C3/JI2C4 SMB to PCI-E Slots Pins 2-3 (Disabled)
(*Notes: i. DIMM slot# specified: DIMM slot to be populated; “---“: DIMM slot not to
be populated. ii. Both FBD 533 MHz and 667MHz DIMMs are supported; however,
you need to use the memory modules of the same speed and of the same type on a
motherboard. iii. Interleaved memory is supported when pairs of DIMM modules are
installed. To optimize memory performance, please install pairs of DIMMs in bothBranch 0 and Branch 1. iv. For memory to work properly, you need to follow the
restrictions listed above. )
Bank 1
(Channel 0)
Bank 2
(Channel 1)
Bank 3
(Channel 2)
Bank 4
(Channel 3)
Note 2: Due to memory allocation to system devices, memory remaining available
for operational use will be reduced when 4 GB of RAM is used. The reduction in
memory availability is disproportional. (Refer to the following Memory Availability
Table for details.)
2-6
DDR2 FBD DIMM
Possible System Memory Allocation & Availability
Chapter 2: Installation
System DeviceSizePhysical Memory
Remaining (-Available)
(4 GB Total System Memory)
Firmware Hub fl ash memory (System
1 MB3.99
BIOS)
Local APIC4 KB3.99
Area Reserved for the chipset2 MB3.99
I/O APIC (4 Kbytes)4 KB3.99
PCI Enumeration Area 1256 MB3.76
PCI Express (256 MB)256 MB3.51
PCI Enumeration Area 2 (if needed)
512 MB3.01
-Aligned on 256-MB boundary-
VGA Memory16 MB2.85
TSEG1 MB2.84
Memory available to OS and other ap-
2.84
plications
Installing and Removing DIMMs
JLAN1
®
3+
A
X7D
R
PE
U
S
To Remove:
Use your thumbs
to gently push
the release tabs
near both ends of
the module. This
should release it
from the slot.
DDR2 FBD
To Install: Insert module vertically and press down until it
snaps into place. Pay attention to the alignment notch at
the bottom.
Top View of DDR2 FBD Slot
Top View of DDR2 FBD
2-7
X7DA3+ User's Manual
1
2
3
4
5
6
789
2-5 Control Panel Connectors/IO Ports
The I/O ports are color coded in conformance with the PC 99 specifi cation. See
Figure 2-3 below for the colors and locations of the various I/O ports.
Back Panel Connectors/IO Ports
JLAN1
®
3+
A
X7D
R
PE
U
S
13
10
12
16
15
Back Panel I/O Port Locations and Defi nitions
Back Panel Connectors
1. Keyboard (Purple)
2. PS/2 Mouse (Green)
3. Back Panel USB Port 0
4. Back Panel USB Port 1
5. Back Panel USB Port 2
6. Back Panel USB Port 3
7. COM Port 1 (Turquoise)
8. Parallel Port (Printer)
9. Gigabit LAN 2
10. Gigabit LAN 1
11. Side_Surround (Grey)
12. Back_Surround (Black)
13. CEN/LFE (Orange)
14. Microphone-In (Pink)
15. Front (Green)
16. Line-In (Blue)
(See Section 2-5 for details.)
11
14
2-8
Chapter 2: Installation
Front Control Panel
JF1 contains header pins for various buttons and indicators that are normally located
on a control panel at the front of the chassis. These connectors are designed specifi -
cally for use with Supermicro server chassis. See Figure 2-4 for the descriptions of
the various control panel buttons and LED indicators. Refer to the following section
for descriptions and pin defi nitions.
JF1 Header Pins
1920
Ground
NMI
JLAN1
®
UPER X7DA3+
S
X
Power LED
HDD LED
NIC1 LED
NIC2 LED
OH/Fan Fail LED
PWR Fail LED
Ground
Ground
X
Vcc
Vcc
Vcc
Vcc
Vcc
Vcc
Reset
PWR
2
1
Reset Button
Power Button
2-9
X7DA3+ User's Manual
Front Control Panel Pin Defi nitions
NMI Button
The non-maskable interrupt button
header is located on pins 19 and 20
of JF1. Refer to the table on the right
for pin defi nitions.
Power LED
NMI Button
Pin Defi nitions (JF1)
Pin# Defi nition
19Control
20Ground
The Power LED connection is located
on pins 15 and 16 of JF1. Refer to the
table on the right for pin defi nitions.
A. NMI
B. PWR LED
KB/
Mouse
USB 0/
/2/3
1
COM1
LAN1/2
HD
Audio
Parrallel
Port
JLAN1
LAN
G
TLR
C
S
Audio
CTRL
ank
CPU
PWR
X
T
A
Fan 1
JPW1
k
4)
4
)
k
3)
3
)
1)
Greencreek
ridg
B
h
Nort
attery
B
lot)
S
JL1
SATA
4-Pin
4-Pin
2
5
Fan
6
Fan
WR
P
JPW2
DIMM
4B (Ban
DIMM
4
A (
Bank
DIMM
3B (Ban
DIMM
3
A (
Bank
DIMM
2B (Bank 2)
DIMM
2A (Bank 2)
DIMM 1
B (B
DI
MM
1A (Bank 1)
®
A3+
D
X7
R
UPE
S
CD1
7
lot
SIM LP IPMI
lot6
S
PCI-Exp x16
5
Slot
PCI-33MHz
2
2
C4
I
J
3
C
I
J
4
Slot
4
x
p
x
-E
CI
P
WD
J
3
Slot
Slot
JW
Slot
z
H
M
33
1
X
-
CI
P
JPL2
JPL1
2
z
H
M
33
1
X
-
CI
P
2
2
C2
I
J
1
C
I
J
OR
1
-
CI
P
reen
G
(
CR
Z
z
MH
00
1
X
PSF
7
Fan
J17
J3P
JAR
e
JBT1
PXH
MB
S
0
SATA
South
Bridge
/5
4
B
S
U
5
A
T
4
SA
SATA
3
2
SATA
1
SATA
Power LED
Pin Defi nitions (JF1)
Pin# Defi nition
15+5V
16Ground
8-pin PWR
JPW3
1
Fan
Ground
JF1
L
E1
SGP
SGP
FP Control
Fan2
SPK
PW LED
JOH1
I
O1
I
O
2
B
Power LED
HDD LED
NIC1 LED
X
1
U
P
C
2
PU
C
NIC2 LED
CPU
Fan2
Fan8
Fan3
ct Flash
IDE1
1
AC
ACT0-3
JS10
Floppy
T4
ompa
C
-7
SAS4-7
SAS0-3
Fan4
OH/Fan Fail LED
PWR Fail LED
Ground
Ground
WF
J
F1
JC
S
O
I
B
J
PS1
SAS
Controller
OL
W
J
1920
NMI
A
X
Vcc
Vcc
Vcc
Vcc
Vcc
Vcc
Reset
Reset Button
Power Button
PWR
2
1
2-10
HDD LED
The HDD LED connection is located
on pins 13 and 14 of JF1. Attach the
hard drive LED cable here to display
disk activity (for any hard drives on
the system, including SAS, Serial ATA
and IDE). See the table on the right
for pin defi nitions.
NIC1/NIC2 LED Indicators
The NIC (Network Interface Control-
ler) LED connection for GLAN port1 is
located on pins 11 and 12 of JF1 and
the LED connection for GLAN Port2
is on Pins 9 and 10. Attach the NIC
LED cables to display network activity.
Refer to the table on the right for pin
defi nitions.
Chapter 2: Installation
HDD LED
Pin Defi nitions (JF1)
Pin# Defi nition
13+5V
14HD Active
GLAN1/2 LED
Pin Defi nitions (JF1)
Pin# Defi nition
9/11Vcc
10/12Ground
A. HDD LED
B. NIC1 LED
C. NIC2 LED
USB 0/
/2/3
1
COM1
LAN1/2
Parrallel
HD
Audio
G
C
Port
JLAN1
LAN
TLR
S
Audio
CTRL
lot
Fan
S
7
lot
S
5
Slot
Slot
3
Slot
2
Slot
OR
JW
1
Slot
KB/
Mouse
Fan
6
UPER
CD1
SIM LP IPMI
6
PCI-Exp x16
PCI-33MHz
2
3
C
I
J
4
-E
CI
P
WD
J
X
-
CI
P
JPL2
JPL1
X
-
CI
P
X
-
CI
P
CPU
4-Pin
4-Pin
2
PWR
X
T
WR
P
DIMM
DIMM
DIMM
DIMM
DIMM
DIMM
DIMM 1
DI
MM
®
4
z
H
M
z
H
M
2
1
C
I
z
JPW2
4B (Ban
4
A (
3B (Ban
3
A (
2B (Bank 2)
2A (Bank 2)
B (B
1A (Bank 1)
A3+
D
2
C2
I
J
reen
G
(
CR
Z
Bank
Bank
ank
A
JPW1
k
4)
4
)
k
3)
3)
1)
Greencreek
ridg
B
h
Nort
attery
B
lot)
S
JL1
SATA
5
X7
2
C4
I
J
x
p
x
33
1
33
1
J
MH
00
1
PSF
7
Fan
J17
Fan 1
J3P
JAR
1
U
P
C
2
U
P
e
JBT1
PXH
MB
S
0
SATA
C
South
Bridge
SAS
Controller
/5
4
B
S
U
5
A
T
4
SA
SATA
3
2
SATA
1
SATA
OL
W
J
8-pin PWR
JPW3
Fan1
JF1
FP Control
Fan2
SPK
PW LED
L
E1
JOH1
SGP
I
O1
SGP
I
O
2
CPU
Fan2
Fan8
Fan3
y
ct Flash
IDE1
1
WF
J
F1
JC
Flopp
ompa
C
ACT0
AC
T4
-7
-3
SAS4-7
SAS0-3
JS10
Fan4
OH/Fan Fail LED
S
O
I
B
J
PS1
Ground
Power LED
HDD LED
A
B
NIC1 LED
NIC2 LED
C
PWR Fail LED
X
Ground
Ground
1920
NMI
X
Vcc
Vcc
Vcc
Vcc
Vcc
Vcc
Reset
Reset Button
Power Button
PWR
2
1
2-11
X7DA3+ User's Manual
Overheat/Fan Fail LED (OH)
Connect an LED to the OH/Fan Fail
connection on pins 7 and 8 of JF1 to
provide advanced warning of chassis
overheating or fan failure. Refer to the
table on the right for pin defi nitions.
Power Fail LED
The Power Fail LED connection is
located on pins 5 and 6 of JF1. Re-
fer to the table on the right for pin
defi nitions.
OH/Fan Fail LED
Pin Defi nitions (JF1)
Pin# Defi nition
7Vcc
8Ground
OH/Fan Fail Indicator
Status
State Defi nition
OffNormal
OnOverheat
Flash-
Fan Fail
ing
PWR Fail LED
Pin Defi nitions (JF1)
Pin# Defi nition
5Vcc
6Ground
A. OH/Fan Fail LED
B. PWR Supply Fail
4-Pin
5
Fan
6
USB 0/
/2/3
1
COM1
LAN1/2
HD
Audio
Parrallel
Port
JLAN1
LA
G
TLR
C
S
Audio
CTRL
7
Slot
N
Slot
Slot
Slot
lot
S
Slot
JW
Slot
Fan
WR
P
DIMM 4
DIMM
DIMM 3B (
DIMM
DIMM 2
DIMM
DIMM 1B (Bank 1)
DIMM 1A (
®
PER X7DA3+
U
CD1
SIM LP IPMI
6
PCI-Exp x16
5
PCI-33MHz
2
2
4
C
I
J
3
C
I
J
4
4
x
p
x
E
-
CI
P
WD
J
3
z
H
M
33
1
X
CI-
P
JPL2
JPL1
2
z
H
M
33
1
X
CI-
P
2
1
C
I
J
OR
1
Z
z
H
M
00
1
X
-
CI
P
KB/
Mouse
24
JPW2
B
(
Bank
4A (Bank 4)
Bank 3
3A (Bank 3)
B (B
2A (Bank 2)
2
2
C
I
J
reen S
G
(
CR
-Pin
B
A
ank
ank 1)
lot)
T
B
attery
PWR
X
4)
2)
JPW1
)
Greencree
North Brid
JL1
CPU
PSF
7
Fan
J17
Fan 1
J3P
JAR
1
PU
C
k
e
g
JBT1
XH
P
SA
MB
S
0
1
SA
A
A
T
T
SA
SA
2
U
P
C
South
ge
Brid
SAS
Controller
/5
4
B
S
U
5
4
SATA
A
T
3
A
T
2
SA
A
T
L
O
W
J
8-pin PWR
JPW3
1
Fan
Ground
JF1
FP Control
2
Fan
SPK
Power LED
PW LED
L
E1
JOH1
HDD LED
SGP
I
O1
NIC1 LED
SGP
I
O
2
h
CPU
Fan2
Fan3
Fan8
1
DE
I
1
WF
J
1
F
JC
I
B
Floppy
S
O
ACT4
AC
T0-3
J
PS1
SAS
0
JS1
OH/Fan Fail LED
ompact Flas
C
PWR Fail LED
-7
-7
4
SAS0-3
Fan4
X
NIC2 LED
A
B
Ground
Ground
1920
NMI
X
Vcc
Vcc
Vcc
Vcc
Vcc
Vcc
Reset
Reset Button
Power Button
PWR
2
1
2-12
Chapter 2: Installation
Reset Button
The Reset Button connection is located
on pins 3 and 4 of JF1. Attach it to the
hardware reset switch on the computer
case. Refer to the table on the right for
pin defi nitions.
Power Button
The Power Button connection is located
on pins 1 and 2 of JF1. Momentarily
contacting both pins will power on/off
the system. This button can also be con-
fi gured to function as a suspend button
(with a setting in BIOS - see Chapter 4).
To turn off the power when set to suspend
mode, press the button for at least 4
seconds. Refer to the table on the right
for pin defi nitions.
Reset Button
Pin Defi nitions (JF1)
Pin# Defi nition
3Reset
4Ground
Power Button
Pin Defi nitions (JF1)
Pin# Defi nition
1Signal
2+3V Standby
A. Reset Button
B. PWR Button
6
USB 0/
/2
1
C
LAN1/2
/
OM1
Parrallel
HD
Audio
3
G
C
Port
JLAN1
LAN
TLR
Fan
UPER X7DA3+
S
Audio
CTRL
7
Slot
6
Slot
5
Slot
2
I
J
4
Slot
P
3
Slot
P
JPL1
2
Slot
P
OR
JW
1
lot
S
P
KB/
Mouse
5
Fan
CD1
SIM LP IPMI
PCI-Exp x16
PCI-33MHz
2
C
I
J
C3
p
x
-E
CI
WD
J
33
1
X
CI-
JPL2
33
1
X
-
CI
00
1
X
-
CI
4
4
x
M
M
J
M
4-Pin
24-Pin
A
WR
P
JPW2
DIMM
4B (Bank 4)
DIMM 4A (Bank 4)
DIMM
3B (Bank 3)
DIMM
3A (Bank 3)
D
I
MM 2B (Bank 2)
DIMM
2
A
(Bank 2
DIMM
1B (Bank 1)
DIMM
1A (Bank 1)
®
B
z
H
z
H
2
2
2
C
I
J
1
C
I
lot
reen S
G
(
CR
Z
z
H
PWR
X
T
)
atter
)
JPW1
Greencreek
North Bridg
y
JL
1
SATA
CPU
PSF
7
Fan
J17
Fan 1
J3P
JAR
1
PU
C
2
U
P
SATA
SATA
C
South
Bridge
SAS
Controller
/5
4
B
S
U
5
4
SATA
3
2
SATA
WOL
J
e
T1
JB
PXH
MB
S
0
1
SATA
8-pin PWR
JPW3
1
Fan
Ground
JF1
FP Control
Fan2
SPK
Power LED
PW LED
L
E1
JOH1
SGP
I
O1
SGP
CPU
Fan2
Fan8
Fan3
ct Flash
1
WF
J
F1
JC
Floppy
ompa
C
S
O
I
B
AC
T4-7
ACT0
-
3
J
PS
1
SAS4-7
SAS0-3
JS10
NIC1 LED
I
O
2
IDE1
OH/Fan Fail LED
PWR Fail LED
Fan4
X
HDD LED
NIC2 LED
Ground
Ground
1920
NMI
X
Vcc
Vcc
Vcc
Vcc
Vcc
Vcc
Reset
Reset Button
A
Power Button
PWR
2
1
B
2-13
X7DA3+ User's Manual
2-6 Connectors and Headers
ATX Power Connector
There are a 24-pin main power supply
connector(JPW1) and an 8-pin CPU
PWR connector (JPW3) on the moth-
erboard. These power connectors
meet the SSI EPS 12V specifi cation.
The 4-pin 12V PWR supply located at
JPW2 is also required to provide ad-
equate power to the system. See the
table on the right for pin defi nitions.
For the 8-pin PWR (JPW3), please
refer to the item listed below.
Processor Power Connector
In addition to the Primary ATX power
connector (above), the 12V 8-pin CPU
PWR connector at JPW3 must also
be connected to your power supply.
See the table on the right for pin
defi nitions.
ATX Power 24-pin Connector
Pin Defi nitions
Pin# Defi nition Pin # Defi nition
13+3.3V1+3.3V
14-12V2+3.3V
15COM3COM
16PS_ON4+5V
17COM5COM
18COM6+5V
19COM7COM
20Res (NC)8PWR_OK
21+5V95VSB
22+5V10+12V
23+5V11+12V
24COM12+3.3V
Required Connection
12V 4-pin Power
Connector
Pin Defi nitions
Pins Defi nition
1 and 2Ground
3 and 4+12V
12V 8-pin Power Con-
Pins Defi nition
1 through 4Ground
5 through 8+12V
Required Connection
nector
Pin Defi nitions
KB/
M
USB
1/2/3
ouse
COM1
0
Parrallel
LAN1/2
HD
Audio
G
C
/
Port
JLAN1
AN
L
TLR
5
Fan
6
Fan
UPER X7DA3+
S
CD1
Audio
CTRL
7
Slot
SIM LP IPMI
6
Slot
PCI-Exp x16
5
Slot
PCI-33MHz
2
2
C4
I
J
C3
I
J
4
Slot
Exp x
PCI-
JWD
3
Slot
133 M
CI-X
P
JPL2
JPL1
2
Slot
133
-X
CI
P
WOR
J
1
Slot
100 M
CI-X
P
C
-Pin
-Pin
4
4
2
WR
P
JPW2
D
I
MM
4B
(B
D
IMM 4
A
(B
DIMM 3B (Bank
D
IMM 3A
(B
DIMM
2B
(Bank
D
IMM 2A
(B
D
IMM
1B (Ban
D
I
MM
1
A
(B
®
4
Hz
Hz
M
2
2
C2
I
J
C1
I
J
(Green
CR
Hz Z
T
A
ank
ank 4)
an
k
an
k 2
k
an
k 1
B
lot)
S
A
X PWR
4)
3)
3)
2)
1)
atter
)
)
G
North
y
JL
JPW1
reencree
Brid
1
SA
CPU
Fan 1
TA
J17
J3P
JAR
CPU1
k
e
g
JBT1
H
X
P
SATA4
SMB
0
1
SATA2
TA
SA
USB4/
SATA5
SA
2
U
CP
South
ge
rid
B
SAS
Controller
5
TA3
WOL
J
CPU
8-pin PWR
JPW3
Fan1
F1
J
FP Control
2
Fan
SPK
PW LED
LE1
JOH1
SG
P
IO1
SG
P
IO2
Fan2
Fan3
Fan8
Flash
y
ct
DE1
JWF1
F1
C
J
OS
I
B
JP
I
Flopp
ompa
C
ACT4-
7
AC
T
0-3
S
1
7
-
4
SAS
SAS0-3
0
S1
J
Fan4
A. 24-pin ATX PWR
B. 8-pin Processor PWR
C. 4-pin PWR
PSF
B
7
Fan
2-14
Chapter 2: Installation
Universal Serial Bus (USB)
There are six USB 2.0 (Universal Se-
rial Bus) ports/headers on the mother-
board. Four of them are Back Panel
USB ports (USB#0/1/2/3: JUSB1),
and the other two are Front Panel
USB headers (USB#4/5:JUSB2).
See the tables on the right for pin
defi nitions.
Chassis Intrusion
A Chassis Intrusion header is located
at JL1 on the motherboard. Attach the
appropriate cable from the chassis to
inform you of a chassis intrusion when
the chassis is opened.
Back Panel USB
(USB0/1/2/3)
Pin# Defi nitions
1+5V
2PO-
3PO+
4Ground
5N/A
Front Panel USB
Pin Defi nitions (USB4)
USB4
Pin # Defi nition
USB5
Pin # Defi nition
1+5V1+5V
2PO-2PO-
3PO+ 3PO+
4Ground4Ground
5Key5No connection
Chassis Intrusion
Pin Defi nitions (JL1)
Pin# Defi nition
1Intrusion Input
2Ground
KB/
M
USB
1/2/3
ouse
COM1
LAN1/2
HD
Audio
/
0
Parrallel
Port
JLAN1
AN
L
G
TLR
C
5
Fan
6
Fan
A
UPER X7DA3+
S
CD1
Audio
CTRL
7
Slot
SIM LP IPMI
6
Slot
PCI-Exp x16
5
Slot
PCI-33MHz
2
2
C4
I
J
C3
I
J
4
Slot
Exp x
PCI-
JWD
3
Slot
133 M
CI-X
P
JPL2
JPL1
2
Slot
133
-X
CI
P
WOR
J
1
Slot
100 M
CI-X
P
-Pin
-Pin
4
4
2
WR
P
JPW2
D
I
MM
4B
(B
D
IMM 4
A
(B
DIMM 3B (Bank
D
IMM 3A
(B
DIMM
2B
(Bank
D
IMM 2A
(B
D
IMM
1B (Ban
D
I
MM
1
A
(B
®
4
Hz
Hz
M
2
2
C2
I
J
C1
I
J
(Green S
CR
Hz Z
A
ank
ank 4)
an
k
an
k 2
k
an
k 1
B
lot)
X PWR
T
4)
3)
3)
2)
1)
atter
C
)
)
G
North
y
JL
JPW1
reencree
Brid
1
SA
CPU
Fan 1
TA
PSF
7
Fan
J17
J3P
JAR
CPU1
k
e
g
JBT1
H
X
P
SATA4
SMB
0
1
SATA2
TA
SA
B
USB4/
SATA5
SA
2
U
CP
South
ge
rid
B
SAS
Controller
5
TA3
WOL
J
CPU
8-pin PWR
JPW3
Fan1
1
F
J
FP Control
2
Fan
SPK
PW LED
LE1
JOH1
SG
P
IO1
SG
P
IO2
Fan2
Fan3
Fan8
Flash
ct
JWF1
F1
C
J
OS
I
B
JP
IDE1
Floppy
ompa
C
ACT4-
7
AC
T
0-3
S
1
7
-
4
SAS
SAS0-3
0
S1
J
Fan4
A. Back panel USB Ports
01/2/3
B. Front Panel USB 4/5
C. Chassis Intrusion
2-15
X7DA3+ User's Manual
G
F
E
D
H
Fan Headers
The X7DA3+ has eight chassis/system
fan headers (Fan1 to Fan8), including
two CPU Fans (Fans 7/8). (Note: Pins
1-3 of 4-pin fan headers are backward
compatible with the traditional 3-pin
fans). See the table on the right for pin
defi nitions. (The onboard fan speeds
are controlled by Thermal Manage-
ment via BIOS Hardware Monitor
in the Advanced Setting
Manufacturer Default is set to Dis-
abled to allow the fans to constantly
run at the full speed. When using
Thermal Management setting, please
use all 3-pin fans or all 4-pin fans on
the motherboard.)
. Note: The
Fan Header
Pin Defi nitions (Fan1-8)
Pin# Defi nition
1Ground
2+12V
3Tachometer
4Pulse Width Modulation
KB/
M
USB
1/2/3
ouse
COM1
Parrallel
LAN1/2
HD
Audio
0
Port
JLAN1
L
G
TLR
C
Fan
/
S
Audio
CTRL
7
Slot
AN
Slot
5
Slot
Slot
3
Slot
2
Slot
WOR
J
1
Slot
-Pin
-Pin
4
4
WR
P
D
D
JPW2
I
MM
IMM 4
4B
2
(B
A
(B
5
Fan
6
DIMM 3B (Bank
D
IMM 3A
(B
DIMM
2B
(Bank
D
IMM 2A
(B
D
IMM
1B (Ban
D
I
MM
1
A
(B
®
UPER X7DA3+
CD1
SIM LP IPMI
6
PCI-Exp x16
PCI-33MHz
2
2
C4
I
J
C3
I
J
4
4
Exp x
PCI-
JWD
Hz
133 M
CI-X
P
JPL2
JPL1
Hz
M
133
-X
CI
P
CI-X
P
100 M
2
2
C2
I
J
C1
I
J
(Green S
CR
Hz Z
T
A
ank
ank 4)
an
k
an
k 2
k
an
k 1
B
lot)
X PWR
4)
3)
3)
2)
atter
1)
)
)
G
North
y
JL
JPW1
reencree
Brid
1
SA
TA
CPU
Fan 1
PSF
7
Fan
J17
J3P
JAR
CPU1
k
e
g
JBT1
H
PX
SATA4
SMB
0
1
SATA2
TA
SA
USB4/
SAT
SA
2
U
CP
South
ge
rid
B
SAS
Controller
5
5
A
TA3
WOL
J
CPU
8-pin PWR
A
JPW3
Fan1
1
B
JF
FP Control
2
Fan
SPK
PW LED
LE1
JOH1
SG
P
IO1
SG
P
IO2
C
Fan2
F1
C
J
B
h
Fan3
Fan8
y
DE1
JWF1
OS
I
JP
I
Flopp
ompact Flas
C
ACT4-
7
AC
T
0-3
S
1
7
-
4
SAS
SAS0-3
0
S1
J
Fan4
A. Fan 1
B. Fan 2
C. Fan 3
D. Fan 4
E. Fan 5
F. Fan 6
G. Fan 7 (CPU Fan 1)
H. Fan 8 (CPU Fan 2)
2-16
Chapter 2: Installation
ATX PS/2 Keyboard and
PS/2 Mouse Ports
The ATX PS/2 keyboard and the PS/2
mouse are located at JKM1. See the
table on the right for pin defi nitions.
(The mouse port is above the key-
board port. See the table on the right
for pin defi nitions.)
Serial Port
COM1 is a connector located at
JCOM1 on the IO Backpanel. See the
table on the right for pin defi nitions.
PS/2 Keyboard and
Mouse Port Pin
Defi nitions
Pin# Defi nition
1Data
2NC
3Ground
4VCC
5Clock
6NC
Serial Port Pin Defi nitions
(COM1)
Pin # Defi nitionPin # Defi nition
1CD6DSR
2RD7RTS
3TD8CTS
4DTR9 RI
5Ground10NC
KB
M
U
1/2/3
COM1
/
ouse
B
S
Parrallel
LAN1/2
HD
Audio
G
CTLR
0
Port
JLAN1
L
Fan
A
/
B
UPER X7DA3+
S
Audio
CTRL
7
Slot
AN
Slot
5
lot
S
Slot
3
Slot
2
Slot
WOR
J
1
Slot
Fan
6
CD1
SIM LP IPMI
6
PCI-Exp x16
PCI-33MHz
2
J
C3
I
J
4
Exp x4
PCI-
JWD
CI-X
P
JPL2
JPL1
X
-
CI
P
CI-X
P
5
I
133
133 M
1
2
C4
00
-Pin
4
WR
P
JPW2
DIMM
D
IMM 4A
DIMM 3
D
IMM 3A (B
D
IMM
D
IMM 2A (B
DIMM 1B
D
IMM 1A (B
®
Hz
M
Hz
2
I
J
C1
I
J
CR
Z
Hz
M
4B
B (Bank
2B (Ban
2
C2
(G
-Pin
4
2
(Bank
(
B
an
ank 3)
ank 2)
(Bank 1)
ank 1)
S
reen
( NC: No Connection.)
CPU
PWR
X
AT
Fan 1
JPW1
4)
k
4)
3
)
k
2)
reencreek
G
e
g
Brid
h
Nort
attery
B
lot)
JL
1
TA0
SA
SMB
PSF
7
Fan
J17
J3P
JAR
1
U
CP
CPU2
JBT1
H
X
P
TA1
SA
South
Bridge
SAS
Controller
USB4/5
5
TA
4
SA
TA
SA
3
A
T
SA
TA2
SA
WOL
J
CPU
8-pin PWR
JPW3
Fan1
1
F
J
FP Control
2
Fan
SPK
A. Keyboard/Mouse
PW LED
B. COM1
LE
1
JOH1
SG
P
IO1
SG
P
IO2
Fan2
Fan3
Fan8
Flash
ct
DE1
JWF1
1
F
C
J
S
O
I
B
JP
I
Floppy
ompa
C
AC
T
4-7
ACT0
-3
S
1
SAS4-7
SAS0-3
0
S1
J
Fan4
2-17
X7DA3+ User's Manual
Wake-On-Ring
The Wake-On-Ring header is des-
ignated JWOR. This function allows
your computer to receive and be
"woken up" by an incoming call to
the modem when the system is in
the suspend state. See the table on
the right for pin defi nitions. You must
have a Wake-On-Ring card and cable
to use this feature.
Wake-On-LAN
The Wake-On-LAN header is located
at JWOL on the motherboard. See the
table on the right for pin defi nitions.
(You must also have a LAN card with
a Wake-On-LAN connector and cable
to use this feature.)
Wake-On-Ring
Pin Defi nitions
(JWOR)
Pin# Defi nition
1Ground
2Wake-up
Wake-On-LAN
Pin Defi nitions
(JWOL)
Pin# Defi nition
1+5V Standby
2Ground
3Wake-up
KB/
M
USB
1/2/3
ouse
C
0
OM1
Parrallel
LAN1/2
HD
Audio
G
CTLR
/
Port
JLAN1
LAN
5
Fan
6
Fan
UPER X7DA3+
S
CD1
Audio
CTRL
7
Slot
SIM LP IPMI
6
Slot
PCI-Exp x16
5
Slot
PCI-33MHz
2
2
C4
I
J
C3
I
J
4
Slot
p
Ex
PCI-
D
JW
3
Slot
133
-X
CI
P
JPL2
JPL1
lot2
S
133 M
CI-X
P
WOR
J
A
1
Slot
100 M
CI-X
P
-Pin
4
WR
P
JPW2
DIMM
D
IMM 4A (B
DIMM
D
IMM 3A
DIMM 2B
D
IMM 2
D
I
MM
D
IMM 1
®
4
x
Hz
M
Hz
2
C1
I
J
Hz ZCR
4
3B (Ban
1B (Ban
2
C2
I
J
-Pin
4
2
B (Bank
ank 4)
(B
an
(Bank
A
(B
an
A (Ban
(Green S
CPU
X PWR
T
A
Fan 1
JPW1
4)
k
3)
k
3)
2)
k 2
)
k
1)
k 1)
reencreek
G
e
g
Brid
North
attery
B
lot)
JL1
0
TA
SA
SMB
Fan
SA
J3P
JBT1
PSF
7
J17
JAR
CPU1
CPU2
outh
S
ge
Brid
H
PX
U
SATA5
SATA4
2
SA
A
1
SAT
TA
SAS
Controller
5
4/
B
S
B
TA3
WOL
J
CPU
8-pin PWR
JPW3
Fan1
F1
J
FP Control
2
Fan
SPK
PW LED
LE1
JOH1
SG
P
IO1
SG
P
IO2
Fan2
Fan3
Fan8
Flash
y
ct
DE1
S
ACT0-3
1
ACT4
S1
J
Flopp
-7
SAS4-7
SAS0-
0
ompa
C
I
3
Fan4
JWF1
F1
C
J
OS
I
B
JP
A. WOR
B. WOL
2-18
Chapter 2: Installation
GLAN 1/2 (Giga-bit Ethernet
Ports)
Two G-bit Ethernet ports are located
at JLAN1 on the IO backplane. This
port accepts RJ45 type cables.
Power LED/Speaker
On the JD1 header, pins 1-3 are for
a power LED and pins 4-7 are for the
speaker. See the table on the right
for speaker pin defi nitions. Note: The
speaker connector pins are to be
used with an external speaker. If you
wish to use the onboard speaker, you
should close pins 6-7 with a jumper.
GLAN1
GLAN2
Speaker Connector
Pin Setting Defi nition
Pins 6-7Internal Speaker
Pins 4-7External Speaker
KB/
M
USB
1/2/3
COM1
ouse
Parrallel
LAN1/2
HD
Audio
G
C
0
Port
JLAN1
L
TLR
Fan
/
UPER X7DA3+
S
A
Audio
CTRL
7
Slot
AN
Slot
5
Slot
Slot
3
Slot
2
Slot
WOR
J
1
Slot
Fan
6
CD1
SIM LP IPMI
6
PCI-Exp x16
PCI-33MHz
2
J
C3
I
J
4
Exp x
PCI-
JWD
CI-X
P
JPL2
JPL1
-X
CI
P
CI-X
P
-Pin
4
5
WR
P
JPW2
D
I
MM
D
IMM 4
DIMM 3B (Bank
D
IMM 3A
DIMM
D
IMM 2A
D
IMM
D
I
MM
®
2
C4
I
4
Hz
133 M
Hz
M
133
2
2
I
J
C1
I
J
CR
Hz Z
100 M
2
4B
(B
A
(B
(B
2B
(Bank
(B
1B (Ban
1
A
(B
C2
(Green S
-Pin
4
A
ank
ank 4)
an
k
an
k 2
k
an
k 1
B
lot)
X PWR
T
4)
3)
3)
2)
1)
atter
)
)
G
North
y
JL
JPW1
reencree
Brid
1
SA
CPU
Fan 1
TA
PSF
7
Fan
J17
J3P
JAR
CPU1
k
e
g
JBT1
H
X
P
SATA4
SMB
0
1
SATA2
TA
SA
USB4/
SATA5
SA
2
U
CP
South
ge
rid
B
SAS
Controller
5
TA3
WOL
J
CPU
8-pin PWR
JPW3
Fan1
1
F
J
FP Control
2
Fan
SPK
PW LED
LE1
JOH1
SG
P
IO1
SG
P
IO2
Fan2
Fan3
Fan8
Flash
ct
DE1
JWF1
F1
C
J
OS
I
B
JP
I
Floppy
ompa
C
ACT4-
7
AC
T
0-3
S
1
7
-
4
SAS
SAS0-3
0
S1
J
Fan4
A. GLAN1/2
B
B. PWR LED/Speaker
2-19
X7DA3+ User's Manual
Power Fault (PWR Supply
Failure)
Connect a cable from your power
supply to the Power Fail header
(PSF) to provide warning of power
supply failure. This warning signal is
passed through the PWR_LED pin
to indicate of a power failure on the
chassis. See the table on the right for
pin defi nitions.
PWR Supply Fail LED
Pin Defi nitions
Pin# Defi nition
1PWR 1: Fail
2PWR 2: Fail
3PWR 3: Fail
4Signal: Alarm Reset
Note: This feature is only available when using
Supermicro redundant power supplies.
Overheat LED/Fan Fail
(JOH1)
The JOH1 header is used to connect
an LED to indicate chassis overheat-
ing. This LED blinks when there is a
fan failure. Refer to the table on right
for pin defi nitions.
K
M
USB
1/2/3
B/
ouse
COM1
0
Parrallel
LAN1/2
HD
Audio
G
C
/
Port
JLAN1
LAN
LR
T
5
Fan
6
Fan
UPER X7DA3+
S
CD1
Audio
CTRL
7
Slot
SIM LP IPMI
6
lot
S
PCI-Exp x16
5
Slot
PCI-33MHz
2
2
C4
I
J
3
C
I
J
4
Slot
Exp x4
PCI-
JWD
3
Slot
133 M
CI-X
P
JPL2
JPL1
2
Slot
133
-X
CI
P
WOR
J
1
Slot
100 M
CI-X
P
-Pin
4
2
WR
P
JPW2
D
IMM
4B (Ban
D
I
MM
4
A
(B
DIMM 3B
(Bank
D
IMM 3A
(
DIMM
2
B (Bank 2)
D
IMM 2A
(B
DIMM 1B (Ban
D
IMM 1A
(B
®
Hz
Hz
M
2
2
C2
I
J
C1
I
J
(Green
CR
Hz Z
-Pin
4
B
an
ank 3)
an
an
S
CPU
Fan 1
7
Fan
J17
J3P
JAR
X PWR
AT
JPW1
k
4)
k 4
)
3)
k
2)
k
1)
k
1)
k
reencree
G
e
g
Brid
North
y
atter
B
BT1
J
H
PX
)
lot
B
SM
JL
1
0
1
A
A
T
SAT
SA
SATA4
SATA2
Overheat LED
Pin Defi nitions
Pin# Defi nition
15vDC
2OH Active
OH/Fan Fail LED
State Message
SolidOverheat
BlinkingFan Fail
PSF
A
CPU1
2
U
CP
South
ge
rid
B
SAS
Controller
5
USB4/
SATA5
TA3
SA
WOL
J
CPU
8-pin PWR
JPW3
Fan1
F1
J
FP Control
2
Fan
SPK
PW LED
LE1
JOH1
SG
P
IO1
SG
P
IO2
Fan2
Fan3
Fan8
Flash
y
ct
DE1
I
1
JWF
1
F
C
J
Flopp
ompa
C
OS
I
B
ACT4-
7
AC
T
0-3
JP
S
1
7
-
4
SAS
3
-
0
SAS
0
S1
J
Fan4
A. Power Fault
B. Overheat LED
B
2-20
Chapter 2: Installation
SMB
A System Management Bus header is
located at J18. Connect the appropri-
ate cable here to utilize SMB on your
system.
Power SMB (I2 C) Connector
Power SMB (I2 C) Connector (J17)
monitors onboard power supply, fan
and system temperature. See the
table on the right for pin defi nitions.
SMB Header
Pin Defi nitions
Pin# Defi nition
1Data
2Ground
3Clock
4No Connection
PWR SMB
Pin Defi nitions
Pin# Defi nition
1Clock
2Data
3PWR Fail
4Ground
5+3.3V
K
M
B/
USB
1/2/3
COM1
ouse
Parrallel
LAN1/2
HD
Audio
G
C
0
Port
JLAN1
LAN
T
Fan
/
UPER X7DA3+
S
Audio
CTRL
7
Slot
lot
S
LR
5
Slot
Slot
3
Slot
2
Slot
WOR
J
1
Slot
Fan
6
CD1
SIM LP IPMI
6
PCI-Exp x16
PCI-33MHz
2
J
3
C
I
J
4
Exp x4
PCI-
JWD
CI-X
P
JPL2
JPL1
-X
CI
P
CI-X
P
-Pin
4
5
WR
P
D
IMM
D
I
MM
DIMM 3B
DIMM 3A
DIMM
D
IMM 2A
DIMM 1B (Ban
D
IMM 1A
®
2
C4
I
Hz
133 M
Hz
M
133
2
C1
I
J
Hz Z
100 M
JPW2
I
J
CR
2
C2
4B (Ban
4
2
(Green S
-Pin
4
2
AT
k
A
(B
an
k 4
(Bank
(
B
ank 3)
B (Bank 2)
(B
an
k
k
(B
an
k
B
lot
X PWR
4)
3)
2)
1)
1)
atter
)
)
G
North
y
JL
JPW1
reencree
Brid
1
SAT
CPU
Fan 1
B
PSF
7
Fan
J17
J3P
JAR
CPU1
k
e
g
BT1
J
H
PX
A
SATA4
B
SM
0
1
SATA2
A
A
T
SA
USB4/
SATA5
SA
2
U
CP
South
ge
rid
B
SAS
Controller
5
TA3
WOL
J
CPU
8-pin PWR
JPW3
Fan1
1
F
J
FP Control
2
Fan
SPK
PW LED
LE1
JOH1
SG
P
IO1
SG
P
IO2
Fan2
Fan3
Fan8
Flash
ct
DE1
I
1
JWF
1
F
C
J
Floppy
ompa
C
OS
I
B
ACT4-
7
AC
T
0-3
JP
S
1
7
-
4
SAS
3
-
0
SAS
0
S1
J
Fan4
A. SMB
B. PWR SMB
2-21
X7DA3+ User's Manual
Compact Flash Card PWR
Connector
A Compact Flash Card Power Connector is
located at JWF1. For the Compact Flash Card
to work properly, you will need to confi gure
the Jumper-JCF1 properly and connect a
Compact Flash Card power cable to JWF1
fi rst. Refer to the board layout below for
the location.
SGPIO Headers
There are two SGPIO (Serial General Purpose
Input/Output) headers (J29, J30) located on
the motherboard. These headers support
serial link interfaces for the onboard SATA
connectors. See the table on the right for pin
defi nitions. Refer to the board layout below
for the location.
Compact Flash Card PWR
Connector
Jumper Defi nition
OnCompact Flash
Power On
OffCompact Flash
Power Off
SGPIO
Pin Defi nitions
Pin# Defi nition Pin Defi nition
1NC2 NC
3Ground4DATA Out
5Load6Ground
7Clock8NC
Note: NC= No Connections
K
M
USB
1/2/3
B/
ouse
COM1
0
Parrallel
LAN1/2
HD
Audio
G
C
/
Port
JLAN1
LAN
LR
T
5
Fan
6
Fan
UPER X7DA3+
S
CD1
Audio
CTRL
7
Slot
SIM LP IPMI
6
lot
S
PCI-Exp x16
5
Slot
PCI-33MHz
2
2
C4
I
J
3
C
I
J
4
Slot
Exp x4
PCI-
JWD
3
Slot
133 M
CI-X
P
JPL2
JPL1
2
Slot
133
-X
CI
P
WOR
J
1
Slot
100 M
CI-X
P
-Pin
4
2
WR
P
JPW2
D
IMM
4B (Ban
D
I
MM
4
A
(B
DIMM 3B
(Bank
D
IMM 3A
(
DIMM
2
B (Bank 2)
D
IMM 2A
(B
DIMM 1B (Ban
D
IMM 1A
(B
®
Hz
Hz
M
2
2
C2
I
J
C1
I
J
(Green
CR
Hz Z
-Pin
4
B
AT
k
an
k 4
ank 3)
an
k
k
an
k
B
lot
S
X PWR
4)
3)
2)
1)
1)
atter
)
)
G
North
y
JL
JPW1
reencree
Brid
1
SAT
CPU
Fan 1
PSF
7
Fan
J17
J3P
JAR
CPU1
k
e
g
BT1
J
H
PX
SATA4
B
SM
0
1
SATA2
A
A
T
SA
USB4/
SATA5
SA
2
U
CP
South
ge
rid
B
SAS
Controller
5
TA3
WOL
J
CPU
8-pin PWR
JPW3
Fan1
F1
J
FP Control
2
Fan
SPK
PW LED
LE1
JOH1
SG
P
IO1
SG
P
IO2
Fan2
Fan3
Fan8
Flash
y
ct
DE1
I
1
JWF
1
F
C
J
A
Flopp
ompa
C
OS
I
B
ACT4-
7
AC
T
0-3
JP
S
1
7
-
4
SAS
3
-
0
SAS
0
S1
J
Fan4
A. Compact Flash PWR
B. SGPIO 1
C. SGPIO 2
B
C
2-22
High Defi nition Audio (HD Audio)
The X7DA3+ features a 7.1+2 Channel High
Defi nition Audio (HDA) (JC1) codecs that provide
10DAC channels, simultaneously supporting 7.1
sound playback with 2 channels of independent
stereo sound output (multiple streaming) through
the front panel stereo out (for front L&R, rear
L&R), center and subwoofer speakers. Use the
advanced software included in the CD-ROM that
came with your motherboard and enable the
Audio settings in the BIOS to use this feature.
Sound is then output through the Line In, Line
Out and MIC jacks (see the graphics at right).
Be sure to enable this function in the BIOS to
use this feature.
Orange:
CEN/LFE
Black: Back
Surround
Grey: Side
Surround
Chapter 2: Installation
Blue: Line-In
Green:Front
Pink: Mic-In
CD Connector
A CD connectors (CD1) is located below the
memory modules. See the tables on the right
for pin defi nitions.
KB/
ouse
M
USB
1/2/3
COM1
LAN1/2
0
Parrallel
HD
Audio
G
C
/
Port
JLAN1
AN
L
TLR
Audio
CTRL
Slot
Fan
S
A
7
Slot
Slot
Slot
3
Slot
2
Slot
WOR
J
1
Slot
-Pin
4
P
D
D
WR
I
MM
IMM 4
JPW2
4B
2
(B
A
(B
5
Fan
6
DIMM 3B (Bank
D
IMM 3A
(B
DIMM
2B
D
IMM 2A
(B
D
IMM
1B (Ban
D
I
MM
1
A
(B
®
UPER X7DA3+
B
CD1
SIM LP IPMI
6
PCI-Exp x16
5
PCI-33MHz
2
2
C4
I
J
C3
I
J
4
4
Exp x
PCI-
JWD
Hz
133 M
CI-X
P
JPL2
JPL1
Hz
M
133
-X
CI
P
CI-X
P
100 M
2
2
C2
I
J
C1
I
J
(Green S
CR
Hz Z
-Pin
4
ank
ank 4)
an
(Bank
an
an
CPU
X PWR
T
A
Fan 1
JPW1
4)
3)
k
3)
2)
k 2
)
k
1)
k 1
)
k
reencree
G
e
g
Brid
North
y
atter
B
lot)
SMB
JL
1
0
TA
SA
PSF
7
Fan
J17
J3P
JAR
CPU1
CP
JBT1
H
PX
1
TA
SA
SATA4
SATA2
USB4/
SAT
SA
South
ge
rid
B
5
5
A
TA3
WOL
J
U
2
SAS
Controller
CPU
CD1 Pin Defi nition
Pin# Defi nition
1Left
2Ground
3Ground
4Right
8-pin PWR
JPW3
Fan1
1
JF
FP Control
2
Fan
SPK
PW LED
LE1
JOH1
SG
P
IO1
SG
P
IO2
Fan2
F1
C
J
B
h
Fan3
Fan8
y
DE1
JWF1
OS
I
JP
I
Flopp
ompact Flas
C
ACT4-
7
AC
T
0-3
S
1
7
-
4
SAS
SAS0-3
0
S1
J
Fan4
A. HD Audio
B. CD1
2-23
X7DA3+ User's Manual
Connector
Pins
Jumper
Cap
Setting
2-7 Jumper Settings
Explanation of
Jumpers
To modify the operation of the
motherboard, jumpers can be used
to choose between optional settings.
Jumpers create shorts between two
pins to change the function of the
connector. Pin 1 is identifi ed with a
square solder pad on the printed circuit
board. See the motherboard layout
pages for jumper locations.
Note: On two pin jumpers, "Closed"
means the jumper is on and "Open"
3 2 1
3 2 1
Pin 1-2 short
means the jumper is off the pins.
GLAN Enable/Disable
JPL1/JPL2 enable or disable GLAN
Port1 and GLAN Port2 on the moth-
erboard. See the table on the right for
jumper settings. The default setting
is enabled.
K
M
U
1
B/
ouse
SB 0
/2/3
COM1
LAN1/2
HD
Audio
/
Parrallel
Port
JLAN1
LAN
G
LR
T
C
5
Fan
6
Fan
UPER X7DA3+
S
CD1
Audio
CTRL
7
Slot
SIM LP IPMI
6
lot
S
PCI-Exp x16
5
Slot
PCI-33MHz
2
2
C4
I
J
3
C
I
J
4
Slot
Exp x4
PCI-
JWD
3
Slot
A
133 M
-X
CI
P
B
JPL2
JPL1
2
Slot
133
-X
CI
P
WOR
J
1
Slot
100 M
CI-X
P
-Pin
-Pin
4
4
2
WR
P
JPW2
D
IMM
4B (Ban
D
IMM 4A
(B
an
DIMM 3B (Bank 3)
D
IMM 3A (B
ank 3)
DIMM 2
B
(B
IMM 2A
ank
(B
an
D
DIMM 1B (Ban
D
IMM 1A (Ban
®
Hz
Hz
M
2
2
C2
I
J
C1
I
J
Hz Z
CR
(Green
S
CPU
X PWR
AT
JPW1
k
4)
k 4
)
2
)
k
2)
k
1)
k
1)
reencree
G
North
y
atter
B
)
lot
JL
7
Fan
J17
Fan 1
J3P
JAR
k
e
g
Brid
BT1
J
H
X
P
SATA4
B
SM
1
0
1
SATA2
A
A
SAT
SAT
GLAN Enable
Pin# Defi nition
1-2Enabled (default)
2-3Disabled
PSF
CPU1
2
U
P
C
South
ge
rid
B
SAS
Controller
5
USB4/
TA5
SA
3
TA
SA
WOL
J
CPU
8-pin PWR
JPW3
Fan1
1
F
J
FP Control
2
Fan
SPK
PW LED
L
E1
JOH1
SG
P
IO1
SG
P
IO2
Fan2
Fan3
Fan8
Flash
ct
DE1
I
1
JWF
1
F
C
J
Floppy
ompa
C
OS
I
B
ACT4-
7
AC
T
0-3
JP
S
1
7
SAS4-
3
-
0
SAS
0
S1
J
Fan4
A. GLAN Port1 Enable
B. GLAN Port2 Enable
2-24
Chapter 2: Installation
CMOS Clear
JBT1 is used to clear CMOS. Instead of pins, this "jumper" consists of contact pads
to prevent the accidental clearing of CMOS. To clear CMOS, use a metal object such
as a small screwdriver to touch both pads at the same time to short the connection.
Always remove the AC power cord from the system before clearing CMOS.
Note: For an ATX power supply, you must completely shut down the system, remove
the AC power cord and then short JBT1 to clear CMOS.
Watch Dog Enable/Disable
Watch Dog is a system monitor that can reboot
the system when a software application hangs.
Close Pins 1-2 to reset the system if an applica-
tion hangs. Close Pins 2-3 to generate a non-
maskable interrupt signal for the application that
hangs. See the table on the right for jumper set-
tings. Watch Dog must also be enabled in the
BIOS.
K
M
U
1/2/3
B/
ouse
B
S
COM1
Parrallel
LAN1/2
HD
Audio
0
G
C
/
Port
JLAN1
LAN
R
TL
Audio
CTRL
Slot
Fan
S
7
Slot
Slot
Slot
3
Slot
2
Slot
WOR
J
1
Slot
-Pin
4
P
D
D
WR
I
MM
IMM 4
JPW2
4B
2
A
(B
5
Fan
6
DIMM 3B
D
IMM 3A
(
DIMM 2B
D
IMM 2A
D
IMM
1B (Ban
D
IMM 1A
®
UPER X7DA3+
CD1
SIM LP IPMI
6
PCI-Exp x16
5
PCI-33MHz
2
2
C4
I
J
C3
I
J
4
4
Exp x
PCI-
JWD
B
Hz
133 M
-X
CI
P
JPL2
JPL1
z
H
M
133
-X
CI
P
CI-X
P
100 M
2
2
C2
I
J
C1
I
J
(Green
CR
Hz Z
-Pin
4
(B
ank
an
(Bank
B
ank 3)
(Ban
(B
(B
CPU
X PWR
T
A
Fan 1
JPW1
4)
k 4
)
3)
k
2)
an
k 2
)
k
1)
an
k 1
)
k
reencree
G
e
g
Brid
North
y
atter
B
)
lot
S
SMB
JL
1
0
TA
SA
Fan
SA
J3P
JBT1
PSF
7
J17
JAR
CPU1
2
U
CP
A
South
ge
rid
B
H
X
P
USB4/
SA
SATA4
2
SA
A
1
SAT
TA
SAS
Controller
5
TA5
TA3
L
O
W
J
CPU
Watch Dog
Jumper Settings (JWD)
Jumper Setting Defi nition
Pins 1-2Reset
(default)
Pins 2-3NMI
OpenDisabled
8-pin PWR
JPW3
Fan1
1
JF
FP Control
Fan2
SPK
PW LED
LE1
SG
P
IO1
SG
P
IO2
Fan2
Fan3
Fan8
Flash
ct
JWF1
1
F
C
J
OS
I
B
JP
IDE1
Floppy
ompa
C
ACT4-
7
AC
T
0-3
S
1
7
-
4
SAS
-
SAS0
0
S1
J
Fan4
A. Clear CMOS
B. Watch Dog Enable
JOH1
3
2-25
X7DA3+ User's Manual
3rd PWR Supply PWR Fault
Detect (J3P)
The system can notify you in the event
of a power supply failure. This feature is
available when three power supply units
are installed in the chassis with one act-
ing as a backup. If you only have one
or two power supply units installed, you
should disable this (the default setting)
with J3P to prevent false alarms.
SAS Controller Enable/
Disable
JPS1 enables or disables the AIC
9140W Adaptec SAS Controller on the
motherboard. See the table on the right
for jumper settings. The default setting
is enabled.
3rd PWR Supply PWR Fault
Jumper Settings
Jumper Setting Defi nition
ClosedEnabled
Open Disabled (Default)
SAS Controller Enable
Jumper Settings
Jumper Setting Defi nition
Pins 1-2Enabled
(default)
Pins 2-3 Disabled
K
M
U
1
B/
ouse
COM1
0
B
S
/2/3
Parrallel
LAN1/2
HD
Audio
G
C
/
Port
JLAN1
LAN
LR
T
Audio
CTRL
Slot
Fan
S
7
lot6
S
5
Slot
Slot
3
Slot
2
Slot
WOR
J
1
Slot
-Pin
-Pin
4
4
WR
P
D
IMM
D
IMM 4A
DIMM
JPW2
2
4B (Ban
(B
3B
(Bank
5
Fan
6
DIMM 3A (B
DIMM
2
B
(B
D
IMM 2A
(B
DIMM 1B (Ban
D
IMM 1A
(B
®
UPER X7DA3+
CD1
SIM LP IPMI
PCI-Exp x16
PCI-33MHz
2
2
C4
I
J
3
C
I
J
4
Exp x4
PCI-
JWD
Hz
133 M
CI-X
P
JPL2
JPL1
Hz
M
133
-X
CI
P
CI-X
P
100 M
2
2
C2
I
J
C1
I
J
(Green S
CR
Hz Z
AT
k
an
k 4
ank 3)
ank 2)
an
k
k
an
k
B
lot
X PWR
4)
3)
2)
1)
1)
atter
)
)
G
North
y
JL
JPW1
reencree
Brid
1
SAT
CPU
Fan 1
A
PSF
7
Fan
J17
J3P
JAR
CPU1
k
e
g
BT1
J
H
X
P
SATA4
B
SM
0
1
SATA2
A
A
SAT
USB4/
SA
SA
2
U
P
C
South
ge
rid
B
SAS
Controller
5
TA5
3
TA
WOL
J
CPU
8-pin PWR
JPW3
Fan1
F1
J
FP Control
2
Fan
SPK
PW LED
LE1
JOH1
SG
P
IO1
SG
P
IO2
Fan2
Fan3
Fan8
Flash
y
ct
DE1
I
1
JWF
1
F
C
J
Flopp
ompa
C
OS
I
B
ACT4-
7
B
AC
T
0-3
JP
S
1
7
SAS4-
3
-
0
SAS
JS10
Fan4
A. 3rd PWR Fail
B. SAS Enable
2-26
Chapter 2: Installation
Compact Flash Master/Slave
Select
A Compact Flash Master/Slave Select
Jumper is located at JCF1. Close this
jumper to enable Compact Flash Card.
For the Compact Flash Card or the
Compact Flash Jumper (JCF1) to work
properly, you will need to connect the
Compact Flash Card power cable to JWF1
fi rst. Refer to the board layout below for
the location.
Alarm Reset
If three power supplies are installed
and Alarm Reset (JAR) is enabled, the
system will notify you when any of the
three power modules fails. Connect JAR
to a micro-switch to enable you to turn
off the alarm that is activated when a
power module fails. See the table on the
right for pin defi nitions.
Compact Flash Card Master/
Slave Select
Jumper Defi nition
OpenSlave
ClosedMaster
Alarm Reset
Pin Setting Defi nition
Pin 1Ground
Pin 2+5V
KB/
M
USB
1/2/3
COM1
ouse
Parrallel
LAN1/2
HD
Audio
G
C
0
Port
JLAN1
L
TLR
Fan
/
UPER X7DA3+
S
Audio
CTRL
7
Slot
AN
Slot
5
Slot
Slot
3
Slot
2
Slot
WOR
J
1
Slot
Fan
6
CD1
SIM LP IPMI
6
PCI-Exp x16
PCI-33MHz
2
J
C3
I
J
4
Exp x
PCI-
JWD
CI-X
P
JPL2
JPL1
-X
CI
P
CI-X
P
-Pin
4
5
WR
P
JPW2
D
I
MM
D
IMM 4
DIMM 3B (Bank
D
IMM 3A
DIMM
D
IMM 2A
D
IMM
D
I
MM
®
2
C4
I
4
Hz
133 M
Hz
M
133
2
2
I
J
C1
I
J
CR
Hz Z
100 M
2
4B
(B
A
(B
(B
2B
(Bank
(B
1B (Ban
1
A
(B
C2
(Green S
-Pin
4
A
ank
ank 4)
an
k
an
k 2
k
an
k 1
B
lot)
X PWR
T
4)
3)
3)
2)
1)
atter
)
)
G
North
y
JL
JPW1
reencree
Brid
1
SA
CPU
Fan 1
TA
PSF
7
Fan
J17
J3P
JAR
B
CPU1
k
e
g
JBT1
H
X
P
SATA4
SMB
0
1
SATA2
TA
SA
USB4/
SATA5
SA
2
U
CP
South
ge
rid
B
SAS
Controller
5
TA3
WOL
J
CPU
8-pin PWR
JPW3
Fan1
1
F
J
FP Control
2
Fan
SPK
PW LED
LE1
JOH1
SG
P
IO1
SG
P
IO2
Fan2
Fan3
Fan8
A
C
J
B
Flash
ct
DE1
JWF1
F1
OS
I
JP
I
Floppy
ompa
C
ACT4-
7
AC
T
0-3
S
1
7
-
4
SAS
SAS0-3
0
S1
J
Fan4
A. Compact Flash Master/
Slave Select
B. Alarm Reset
2-27
X7DA3+ User's Manual
SMB to PCI-X/PCI-E Slots
Jumpers JI2C1/JI2C2 allow you to con-
nect PCI-X Slots to the System Man-
agement Bus and Jumpers JI
allow you to connect PCI-Exp. Slots to
the System Management Bus. See the
table on the right for jumper settings.
2
C3/JI2C4
SMBus to PCI-X/PCI-Exp Slots
Jumper Settings
Jumper Setting Defi nition
Pins 1-2Enabled
Pins 2-3Disabled (Default)
K
M
U
1/2/3
B/
ouse
COM1
0
B
S
Parrallel
LAN1/2
HD
Audio
GLAN
C
/
Port
JLAN1
LR
T
Audio
CTRL
Slot
Fan
S
7
lot
S
5
Slot
Slot
3
Slot
2
Slot
WOR
J
1
Slot
-Pin
-Pin
4
4
WR
P
JPW2
D
IMM
D
IMM
DIMM
D
IMM 3A (B
DIMM
D
IMM 2A
2
4B (Ban
4
A
(B
3B
(Ban
2
B (Bank 2)
(B
5
Fan
6
DIMM 1B (Ban
D
IMM 1A
(B
®
UPER X7DA3+
CD1
SIM LP IPMI
6
PCI-Exp x16
PCI-33MHz
2
2
C4
I
J
3
C
I
J
4
JPL1
B
Exp x4
PCI-
JWD
Hz
133 M
-X
CI
P
JPL2
Hz
M
133
-X
CI
P
CI-X
P
100 M
2
2
A
C2
I
J
C1
I
J
(Green S
CR
Hz Z
AT
k
an
k 4
k
ank 3)
an
k
k
an
k
B
lot
X PWR
4)
3)
2)
1)
1)
atter
)
)
G
North
y
JL
JPW1
reencree
Brid
1
SA
CPU
Fan 1
T
PSF
7
Fan
J17
J3P
JAR
CPU1
k
e
g
BT1
J
H
X
P
SATA4
B
SM
1
0
SATA2
A
A
T
SA
USB4/
SA
SA
2
U
P
C
South
ge
rid
B
SAS
Controller
5
TA5
3
TA
WOL
J
CPU
8-pin PWR
JPW3
Fan1
F1
J
FP Control
2
Fan
SPK
PW LED
LE1
JOH1
SG
P
IO1
SG
P
IO2
Fan2
Fan3
Fan8
Flash
y
ct
DE1
I
1
JWF
1
F
C
J
Flopp
ompa
C
OS
I
B
AC
T
4-
7
AC
T
0-3
JP
S
1
7
SAS4-
3
-
0
SAS
JS10
Fan4
A. JI2C 1/2
B. JI2C 3/4
C. SAS Enable
2-28
2-8 Onboard Indicators
Chapter 2: Installation
GLAN LEDs
There are two GLAN ports on the moth-
erboard. Each Gigabit Ethernet LAN port
has two LEDs. The green LED indicates
activity, while the Link LED may be green,
amber or off to indicate the speed of the
connection. See the tables at right for
more information.
Onboard Power LED
There is an Onboard Power LED located
on the motherboard. When this LED is
lit, the onboard power is on. Be sure to
turn off the system and unplug the power
cord before removing or installing com-
ponents. See the layout below for the
LED location.
Activity
LED
Activity
LED
Link
LED
Link
LED
GLAN Activity Indicator
Color Status Defi nition
GreenFlashingActive
GLAN Link Indicator
LED Color Defi nition
OffNo Connection or 10 Mbps
Green (On)100 Mbps
Amber (On)1 Gbps
KB/
M
USB
1/2/3
ouse
COM1
LAN1/2
HD
Audio
/
0
Parrallel
Port
JLAN1
AN
L
G
TLR
C
5
Fan
6
Fan
UPER X7DA3+
S
A
CD1
Audio
CTRL
7
Slot
SIM LP IPMI
6
Slot
PCI-Exp x16
5
Slot
PCI-33MHz
2
2
C4
I
J
C3
I
J
4
Slot
Exp x
PCI-
JWD
3
Slot
133 M
CI-X
P
JPL2
JPL1
2
Slot
133
-X
CI
P
WOR
J
1
Slot
100 M
CI-X
P
-Pin
-Pin
4
4
2
WR
P
JPW2
D
I
MM
4B
(B
D
IMM 4
A
(B
DIMM 3B (Bank
D
IMM 3A
(B
DIMM
2B
(Bank
D
IMM 2A
(B
D
IMM
1B (Ban
D
I
MM
1
A
(B
®
4
Hz
Hz
M
2
2
C2
I
J
C1
I
J
(Green S
CR
Hz Z
T
A
ank
ank 4)
an
k
an
k 2
k
an
k 1
B
lot)
X PWR
4)
3)
3)
2)
atter
1)
)
)
G
North
y
JL
JPW1
reencree
Brid
1
SA
CPU
Fan 1
g
TA
PSF
7
Fan
J17
J3P
JAR
CPU1
k
e
JBT1
H
X
P
SATA4
SMB
0
1
SATA2
TA
SA
USB4/
SATA5
SA
2
U
CP
South
ge
rid
B
SAS
Controller
5
TA3
WOL
J
CPU
8-pin PWR
JPW3
B
LE1
SG
P
SG
P
Fan2
Fan3
Fan8
Flash
ct
JWF1
F1
C
J
Floppy
ompa
C
OS
I
B
ACT4-
7
AC
T
0-3
JP
S
1
4
SAS
SAS0-3
0
S1
J
Fan4
A. GLAN Port1 LEDs
Fan1
B. Standby PWR LED
1
F
J
FP Control
2
Fan
SPK
PW LED
JOH1
IO1
IO2
DE1
I
7
-
2-29
X7DA3+ User's Manual
Onboard SAS Activity LED
Indicators
There are eight Onboard SAS Activity
LED indicators on the X7DA3+. LED In-
dicators Act#0 to Act#7 indicate onboard
SAS connector activities. See the table on
the right for more information.
Onboard SAS_Activity_LED Indica-
tors (Note: Act=Active)
Act# Defi nition Act# Defi nition
Act#0SAS0:ActAct#4SAS4:Act
Act#1SAS1:ActAct#5SAS5:Act
Act#2SAS2:ActAct#6SAS6:Act
Act#3SAS3:ActAct#7SAS7:Act
KB/
M
USB
1/2/3
ouse
COM1
0
Parrallel
LAN1/2
HD
Audio
G
C
/
Port
JLAN1
AN
L
TLR
Audio
CTRL
Slot
Fan
S
7
Slot
5
Slot
Slot
3
Slot
2
Slot
WOR
J
1
Slot
-Pin
-Pin
4
4
WR
P
D
I
D
IMM 4
MM
JPW2
4B
2
(B
A
(B
5
Fan
6
DIMM 3B (Bank
D
IMM 3A
(B
DIMM
2B
(Bank
D
IMM 2A
(B
D
IMM
1B (Ban
D
I
MM
1
A
(B
®
UPER X7DA3+
CD1
SIM LP IPMI
6
PCI-Exp x16
PCI-33MHz
2
2
C4
I
J
C3
I
J
4
4
Exp x
PCI-
JWD
Hz
133 M
CI-X
P
JPL2
JPL1
Hz
M
133
-X
CI
P
CI-X
P
100 M
2
2
C2
I
J
C1
I
J
(Green
CR
Hz Z
A
ank
ank 4)
an
k
an
k 2
k
an
k 1
B
lot)
S
X PWR
T
3)
atter
4)
3)
2)
1)
)
)
G
North
y
JL
JPW1
reencree
Brid
1
SA
CPU
Fan 1
TA
PSF
7
Fan
J17
J3P
JAR
8-pin PWR
JPW3
A. SAS Act. #0-#3 LEDs
Fan1
B. SAS Act. #4-#7 LEDs
F1
J
Fan3
1
AC
y
Flopp
ACT4-
T
S1
J
0-3
SAS
0
LE1
SG
SG
Flash
ct
ompa
C
7
4
SAS0-3
Fan4
FP Control
2
Fan
SPK
PW LED
JOH1
P
IO1
P
IO2
DE1
I
7
-
Act. #4-#7 LEDs
B
Act. #0-#3 LEDs
A
CPU1
k
e
g
JBT1
H
X
P
SATA4
SMB
0
1
SATA2
TA
SA
USB4/
SATA5
SA
2
U
CP
CPU
Fan2
Fan8
JWF1
F1
C
South
rid
B
5
TA3
WOL
J
J
OS
I
SAS
Controller
B
JP
S
ge
2-30
Chapter 2: Installation
2-9 Parallel Port, Floppy Drive, Hard Disk Drive and
SIMLP IPMI Connections
Note the following when connecting the fl oppy and hard disk drive cables:
• The fl oppy disk drive cable has seven twisted wires.
• A red mark on a wire typically designates the location of pin 1.
• A single fl oppy disk drive ribbon cable has two connectors to provide for two
fl oppy disk drives. The connector with twisted wires always connects to drive
A, and the connector that does not have twisted wires always connects to drive
B.
Parallel (Printer) Port
Connector
The parallel (printer) port is located
at J21. See the table on the right for
pin defi nitions.
Pin# Defi nition Pin # Defi nition
1Strobe-2Auto Feed-
3Data Bit 04Error-
5Data Bit 16Init-
7Data Bit 28SLCT IN-
9Data Bit 310GND
11Data Bit 412GND
13Data Bit 514GND
15Data Bit 616GND
17Data Bit 718GND
19ACK20GND
21BUSY22Write Data
23PE24Write Gate
25SLCT26NC
Parallel (Printer) Port Connector
Pin Defi nitions
KB/
M
USB
1/2/3
ouse
COM1
Parrallel
LAN1/2
HD
Audio
0
GL
C
/
Port
JLAN1
AN
TLR
5
Fan
6
Fan
A
UPER X7DA3+
S
CD1
Audio
CTRL
7
Slot
SIM LP IPMI
6
Slot
PCI-Exp x16
5
Slot
PCI-33MHz
2
J
C3
I
J
4
Slot
Exp x
PCI-
JWD
3
Slot
CI-X
P
JPL2
JPL1
2
Slot
-X
CI
P
WOR
J
1
Slot
CI-X
P
-Pin
4
WR
P
JPW2
D
I
MM
D
IMM 4
DIMM 3B (Bank
D
IMM 3A
DIMM
D
IMM 2A
D
IMM
D
I
MM
®
2
C4
I
4
Hz
133 M
Hz
M
133
2
2
C2
I
J
C1
I
J
CR
Hz Z
100 M
4
2
4B
(B
A
(B
(B
2B
(Bank
(B
1B (Ban
1
A
(B
(Green
-Pin
ank
ank 4)
an
an
an
S
CPU
X PWR
T
A
Fan 1
JPW1
4)
3)
k
3)
2)
k 2
)
k
1)
k 1
)
k
reencree
G
e
g
Brid
North
y
atter
B
lot)
SMB
JL
1
0
TA
SA
Fan
SA
J3P
JBT1
PSF
7
J17
JAR
CPU1
2
U
CP
South
ge
rid
B
USB4/
SA
SAS
Controller
5
5
A
TA3
WOL
J
H
X
P
SAT
SATA4
1
SATA2
TA
CPU
8-pin PWR
JPW3
1
Fan
1
JF
FP Control
Fan2
SPK
PW LED
LE1
JOH1
SG
P
IO1
SG
P
IO2
Fan2
Fan3
Fan8
JWF1
F1
C
J
OS
I
B
JP
IDE1
Floppy
ompact Flash
C
ACT4-
7
AC
T
0-3
S
1
7
-
4
SAS
SAS0-3
0
S1
J
Fan4
A. Parallel Port
2-31
X7DA3+ User's Manual
Floppy Connector
The fl oppy connector is located at
J22. See the table below for pin
defi nitions.
SIMLP IPMI Slot
There is a SIM Low Profi le IPMI Slot
on the motherboard. Refer to the
layout below for the SIMLP IPMI Slot
location.
Floppy Drive Connector
Pin Defi nitions (Floppy)
Pin# Defi nition Pin # Defi nition
1Ground2FDHDIN
3Ground4Reserved
5Key6FDEDIN
7Ground8Index
9Ground10Motor Enable
11Ground12Drive Select B
13Ground14Drive Select B
15Ground16Motor Enable
17Ground18DIR
19Ground20STEP
21Ground22Write Data
23Ground24Write Gate
25Ground26Track 00
27Ground28Write Protect
29Ground30Read Data
31Ground32Side 1 Select
33Ground34Diskette
K
M
USB
1/2/3
B/
ouse
COM1
0
Parrallel
LAN1/2
HD
Audio
G
C
/
Port
JLAN1
LAN
LR
T
Audio
CTRL
Slot
Fan
S
7
lot
S
5
Slot
Slot
3
Slot
2
Slot
WOR
J
1
Slot
-Pin
-Pin
4
4
WR
P
JPW2
D
IMM
4B (Ban
D
I
MM
4
DIMM 3B
D
IMM 3A
DIMM
2
D
IMM 2A
2
A
(B
(Bank
(
B
B (Bank 2)
(B
5
Fan
6
DIMM 1B (Ban
D
IMM 1A
(B
®
UPER X7DA3+
CD1
B
SIM LP IPMI
6
PCI-Exp x16
PCI-33MHz
2
2
C4
I
J
3
C
I
J
4
Exp x4
PCI-
JWD
Hz
133 M
CI-X
P
JPL2
JPL1
Hz
M
133
-X
CI
P
CI-X
P
100 M
2
2
C2
I
J
C1
I
J
(Green
CR
Hz Z
AT
k
an
k 4
ank 3)
an
k
k
an
k
B
lot
S
X PWR
4)
3)
2)
1)
1)
atter
)
)
G
North
y
JL
JPW1
reencree
Brid
1
SAT
CPU
Fan 1
PSF
7
Fan
J17
J3P
JAR
CPU1
k
e
g
2
U
CP
8-pin PWR
JPW3
LE1
SG
SG
Fan1
F1
J
FP Control
2
Fan
SPK
PW LED
JOH1
P
IO1
P
IO2
A. Floppy
B. SIMLP IPMI
A
CPU
Fan2
Fan3
Fan8
Flash
y
ct
DE1
I
1
JWF
1
F
C
BT1
J
H
PX
B
SM
0
1
A
A
T
SA
SATA4
SATA2
USB4/
SATA5
SA
South
rid
B
5
TA3
WOL
J
J
Flopp
ompa
C
OS
I
SAS
Controller
B
ACT4-
7
AC
T
0-3
JP
S
1
7
-
4
SAS
3
-
0
SAS
0
S1
J
Fan4
ge
2-32
Chapter 2: Installation
IDE Connectors
There are two IDE Connectors
(JIDE1: Blue, JIDE2: White) on
the motherboard. The blue IDE
connector (JIDE1) is designated
the Primary IDE Drive. The white
IDE connector (JIDE2) is desig-
nated as the Secondary IDE Drive,
reserved for Compact Flash Card
use only. (See the note below.)
See the table on the right for pin
defi nitions.
Note: JIDE2 (the white slot) is
reserved for Compact Flash Card
use only. Do not use it for other
devices. If JIDE2 is populated
with a Compact Flash Card, JIDE1
(the blue slot) will be available for
one device only. For the Compact
Flash Card to work properly, you
will need to connect a power cable
to JWF1 fi rst.
IDE Drive Connectors
Pin Defi nitions
Pin# Defi nition Pin # Defi nition
1Reset IDE2Ground
3Host Data 74Host Data 8
5Host Data 66Host Data 9
7Host Data 58Host Data 10
9Host Data 410Host Data 11
11Host Data 312Host Data 12
13Host Data 214Host Data 13
15Host Data 116Host Data 14
17Host Data 018Host Data 15
19Ground20Key
21DRQ322Ground
23I/O Write24Ground
25I/O Read26Ground
27IOCHRDY28BALE
29DACK330Ground
31IRQ1432IOCS16
33Addr134Ground
35Addr036Addr2
37Chip Select 038Chip Select 1
39Activity40Ground
K
M
U
1/2/3
B/
ouse
B
S
COM1
Parrallel
LAN1/2
HD
Audio
0
G
C
/
Port
JLAN1
LAN
LR
T
Audio
CTRL
Slot
Fan
S
7
lot6
S
5
Slot
Slot
3
Slot
2
Slot
WOR
J
1
Slot
-Pin
-Pin
4
4
WR
P
JPW2
D
IMM
D
IMM
DIMM
D
IMM 3A (B
DIMM
D
IMM 2A
2
4B (Ban
4
A
(B
3B
(Bank
2
B
(B
(B
5
Fan
6
DIMM 1B (Ban
D
IMM 1A
(B
®
UPER X7DA3+
CD1
SIM LP IPMI
PCI-Exp x16
PCI-33MHz
2
2
C4
I
J
3
C
I
J
4
Exp x4
PCI-
JWD
Hz
133 M
CI-X
P
JPL2
JPL1
Hz
M
133
CI-X
P
CI-X
P
100 M
2
2
C2
I
J
C1
I
J
(Green
CR
Hz Z
AT
k
an
k 4
ank 3)
ank 2)
an
k
k
an
k
B
lot
S
X PWR
4)
3)
2)
1)
1)
atter
)
)
North
JPW1
reencree
G
y
JL
1
Brid
SA
CPU
Fan 1
T
PSF
7
Fan
J17
J3P
JAR
CPU1
k
e
g
BT1
J
H
X
P
SATA4
B
SM
0
1
SATA2
A
A
T
SA
USB4/
SA
SA
2
U
P
C
South
ge
rid
B
SAS
Controller
5
TA5
3
TA
WOL
J
CPU
8-pin PWR
JPW3
Fan1
1
F
J
FP Control
2
Fan
SPK
PW LED
LE1
JOH1
SG
SG
B
Fan2
Fan3
Fan8
Flash
ct
1
JWF
1
F
C
J
Floppy
ompa
C
OS
I
B
ACT
4-
7
AC
T
0-3
JP
S
1
SAS4-
SAS
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A. IDE#1
P
IO1
B. IDE#2 (Compact Flash)
P
IO2
A
DE1
I
7
3
-
0
Fan4
2-33
X7DA3+ User's Manual
SAS Connectors
There are eight Serial Attached
SCSI (SAS#0-#3, SAS#4-#7)
on the motherboard. See
the tables on the right for pin
defi nitions.
SAS Connector
Pin Defi nitions
Pin# Defi nition Pin # Defi nition
A1GroundB1Ground
A2RX 0+B2TX 0+
A3RX 0-B3TX 0-
A4GroundB4Ground
A5RX 1+B5TX 1+
A6RX 1-B6TX 1-
A7GroundB7Ground
A8SB7B8SB0
A9SB3B9SB1
A10SB4B10SB2
A11SB5B11SB6
A12GroundB12Ground
A13RX 2+B13TX 2+
A14RX 2-B14TX 2-
A15GroundB15Ground
A16RX 3+B16TX 3+
A17RX 3-B17TX 3-
A18GroundB18Ground
KB/
M
USB
1/2/3
ouse
COM1
0
Parrallel
LAN1/2
HD
Audio
G
C
/
Port
JLAN1
AN
L
TLR
Audio
CTRL
Slot
Fan
S
7
Slot
5
Slot
Slot
3
Slot
2
Slot
WOR
J
1
Slot
-Pin
-Pin
4
4
WR
P
D
I
D
IMM 4
MM
JPW2
4B
2
(B
A
(B
5
Fan
6
DIMM 3B (Bank
D
IMM 3A
(B
DIMM
2B
(Bank
D
IMM 2A
(B
D
IMM
1B (Ban
D
I
MM
1
A
(B
®
UPER X7DA3+
CD1
SIM LP IPMI
6
PCI-Exp x16
PCI-33MHz
2
2
C4
I
J
C3
I
J
4
4
Exp x
PCI-
JWD
Hz
133 M
CI-X
P
JPL2
JPL1
Hz
M
133
-X
CI
P
CI-X
P
100 M
2
2
C2
I
J
C1
I
J
(Green
CR
Hz Z
A
ank
ank 4)
an
k
an
k 2
k
an
k 1
B
lot)
S
X PWR
T
3)
atter
4)
3)
2)
1)
)
)
G
North
y
JL
JPW1
reencree
Brid
1
SA
CPU
Fan 1
TA
PSF
7
Fan
J17
J3P
JAR
CPU1
k
e
g
JBT1
H
X
P
SATA4
SMB
0
1
SATA2
TA
SA
USB4/
SATA5
SA
2
U
CP
South
ge
rid
B
SAS
Controller
5
TA3
WOL
J
CPU
8-pin PWR
JPW3
Fan1
F1
J
FP Control
2
Fan
SPK
PW LED
LE1
JOH1
SG
P
IO1
SG
P
IO2
Fan2
Fan3
Fan8
Flash
y
ct
DE1
JWF1
F1
C
J
OS
I
B
JP
I
Flopp
ompa
C
ACT4-
7
AC
T
0-3
S
1
7
-
4
SAS
SAS0-3
0
S1
J
Fan4
A. SAS #0-#3
B. SAS #4-#7
B
A
2-34
Chapter 3: Troubleshooting
Chapter 3
Troubleshooting
3-1 Troubleshooting Procedures
Use the following procedures to troubleshoot your system. If you have followed all
of the procedures below and still need assistance, refer to the ‘Technical Support
Procedures’ and/or ‘Returning Merchandise for Service’ section(s) in this chapter.
Note: Always disconnect the power cord before adding, changing or installing any
hardware components.
Before Power On
1. Make sure that there are no short circuits between the motherboard and chas-
sis.
2. Disconnect all ribbon/wire cables from the motherboard, including those for the
keyboard and mouse.
3. Remove all add-on cards.
4. Install one CPU (making sure it is fully seated) and connect the chassis speaker
and the power LED to the motherboard. (Check all jumper settings as well.)
No Power
1. Make sure that there are no short circuits between the motherboard and the
chassis.
2. Make sure that all jumpers are set to their default positions.
3. Check that the 115V/230V switch on the power supply is properly set.
4. Turn the power switch on and off to test the system.
5. The battery on your motherboard may be old. Check to make sure that it still
supplies ~3VDC. If it does not, replace it with a new one.
No Video
1. If the power is on, but you have no video, remove all the add-on cards and
cables.
2. Use the speaker to determine if any beep codes exist. Refer to the Appendix B
for details on beep codes.
3. Remove all memory modules and turn on the system. (If the alarm is on, check
the specs of the memory, reset the memory or try a different one.)
3-1
X7DA3+ User's Manual
Losing the System’s Setup Confi guration
1. Make sure that you are using a high quality power supply. A poor quality power
supply may cause the system to lose the CMOS setup information. Refer to
Section 1-6 for details on recommended power supplies.
2. The battery on your motherboard may be old. Check to make sure that it still
supplies ~3VDC. If it does not, replace it with a new one.
3. If the above steps do not fi x the Setup Confi guration problem, contact your
vendor for repairs.
NOTE
If you are a system integrator, VAR or OEM, a POST diagnostics
card is recommended. For I/O port 80h codes, refer to App. B.
Memory Errors
1. Make sure that the DIMM modules are properly and fully installed.
2. Check if different speeds of DIMMs have been installed and make sure that the
BIOS setup is confi gured for the fastest speed of RAM used. It is recommended
to use the same RAM speed for all DIMMs in the system.
3. Make sure you are using the correct type of DDR2 FBD (Fully Buffered) ECC
533/667 SDRAM (recommended by the manufacturer.)
4. Check for bad DIMM modules or slots by swapping a single module between
four slots and noting the results.
5. Make sure that all memory modules are fully seated in their slots. As an inter-
leaved memory scheme is used, you must install pair(s) of modules at a time,
beginning with Branch 1, then Branch 2, and so on (see Page 2-6).
6. Check the position of the 115V/230V switch on the power supply.
3-2 Technical Support Procedures
Before contacting Technical Support, please take the following steps. Also, note
that as a motherboard manufacturer, Super Micro does not sell directly to end-us-
ers, so it is best to fi rst check with your distributor or reseller for troubleshooting
services. They should know of any possible problem(s) with the specifi c system
confi guration that was sold to you.
1. Please go through the ‘Troubleshooting Procedures’ and 'Frequently Asked Ques-
tion' (FAQ) sections in this chapter or see the FAQs on our web site http://www.
supermicro.com/support/faqs/ before contacting Technical Support.
2. BIOS upgrades can be downloaded from our web site at http://www.supermicro.
com/support/bios/.
3-2
Chapter 3: Troubleshooting
Note: Not all BIOS can be fl ashed. It depends on the modifi cations to the boot
block code. 3. If
you still cannot resolve the problem, make sure to have the following information
ready when contacting Super Micro for technical support:
• Motherboard model and PCB revision number
• BIOS release date/version (this can be seen on the initial display when your
system fi rst boots up)
•System confi guration
An example of a Technical Support form is on our web site at http://www.
supermicro.com/support/contact.cfm/).
4. Distributors: For immediate assistance, please have your account number ready
when placing a call to our technical support department. We can be reached
by e-mail at support@supermicro.com or by fax at: (408) 503-8000, option
2.
3-3 Frequently Asked Questions
Question: What are the various types of memory that my motherboard can
support?
Answer: The X7DA3+ has eight 240-pin DIMM slots that support DDR2 FBD ECC
533/667 SDRAM modules. It is strongly recommended that you do not mix memory
modules of different speeds and sizes.
Question: How do I update my BIOS?
Answer: It is recommended that you do not upgrade your BIOS if you are experi-
encing no problems with your system. Updated BIOS fi les are located on our web
site at http://www.supermicro.com/support/bios/. Please check our BIOS warning
message and the information on how to update your BIOS on our web site. Also,
check the current BIOS revision and make sure that it is newer than your BIOS
before downloading. Select your motherboard model and download the BIOS fi le to
your computer. Unzip the BIOS fi les onto a bootable fl oppy and reboot your system.
Follow the Readme.txt to continue fl ashing the BIOS.
(
Warning: Do not shut down or reset the system while updating BIOS to
prevent possible system boot failure!)
Question: What's on the CD that came with my motherboard?
Answer: The supplied compact disc has quite a few drivers and programs that will
greatly enhance your system. We recommend that you review the CD and install the
applications you need. Applications on the CD include chipset drivers for Windows
and security and audio drivers.
3-3
X7DA3+ User's Manual
3-4 Returning Merchandise for Service
A receipt or copy of your invoice marked with the date of purchase is required be-
fore any warranty service will be rendered. You can obtain service by calling your
vendor for a Returned Merchandise Authorization (RMA) number. When returning
to the manufacturer, the RMA number should be prominently displayed on the
outside of the shipping carton, and mailed prepaid or hand-carried. Shipping and
handling charges will be applied for all orders that must be mailed when service
is complete.
This warranty only covers normal consumer use and does not cover damages in-
curred in shipping or from failure due to the alternation, misuse, abuse or improper
maintenance of products.
During the warranty period, contact your distributor fi rst for any product problems.
3-4
Chapter 4
Chapter 4: BIOS
BIOS
4-1 Introduction
This chapter describes the Phoenix BIOS™ Setup utility for the X7DA3+. The
Phoenix ROM BIOS is stored in a fl ash chip and can be easily upgraded using a
fl oppy disk-based program.
Note: Due to periodic changes to the BIOS, some settings may have been added or
deleted and might not yet be recorded in this manual. Please refer to the Manual
Download area of the Supermicro web site <http://www.supermicro.com> for any
changes to the BIOS that may not be refl ected in this manual.
System BIOS
The BIOS is the Basic Input Output System used in all IBM® PC, XT™, AT®, and
®
PS/2
compatible computers. The Phoenix BIOS stores the system parameters,
types of disk drives, video displays, etc. in the CMOS. The CMOS memory requires
very little electrical power. When the computer is turned off, a backup battery pro-
vides power to the CMOS logic, enabling it to retain system parameters. When a
computer is powered on, the computer is confi gured with the values stored in the
CMOS logic by the system BIOS, which gains control at boot up.
How To Change the Confi guration Data
The CMOS information that determines the system parameters may be changed by
entering the BIOS Setup utility. This Setup utility can be accessed by pressing the
<Delete> key at the appropriate time during system boot. (See below.)
Starting the Setup Utility
Normally, the only visible POST (Power On Self Test) routine is the memory test. As
the memory is being tested, press the <Delete> key to enter the main menu of the
BIOS Setup utility. From the main menu, you can access the other setup screens,
such as the Security and Power menus. Beginning with Section 4-3, detailed de-
scriptions are given for each parameter setting in the Setup utility.
Warning: Do not shut down or reset the system while updating BIOS to
prevent possible boot failure.
4-1
X7DA3+ User's Manual
4-2 Running Setup
Default settings are in bold text unless otherwise noted.
The BIOS setup options described in this section are selected by choosing the ap-
propriate text from the main BIOS Setup screen. All displayed text is described in
this section, although the screen display is often all you need to understand how
to set the options (see the next page).
When you fi rst power on the computer, the Phoenix BIOS™ is immediately acti-
vated.
While the BIOS is in control, the Setup program can be activated in one of two
ways:
1. By pressing <Delete> immediately after turning the system on, or
2. When the message shown below appears briefl y at the bottom of the screen
during the POST (Power On Self-Test), press the <Delete> key to activate the main
Setup menu:
Press the <Delete> key to enter Setup
4-3 Main BIOS Setup
All main Setup options are described in this section. The main BIOS Setup screen
is displayed below.
Use the Up/Down arrow keys to move between the different settings in each menu.
Use the Left/Right arrow keys to change the options for each setting.
Press the <Esc> key to exit the CMOS Setup Menu. The next section describes in
detail how to navigate through the menus.
Items that use submenus are indicated with the icon. With the item highlighted,
press the <Enter> key to access the submenu.
4-2
Main BIOS Setup Menu
Chapter 4: BIOS
Main Setup Features
System Time
To set the system date and time, key in the correct information in the appropriate
fi elds. Then press the <Enter> key to save the data.
System Date
Using the arrow keys, highlight the month, day and year fi elds, and enter the correct
data. Press the <Enter> key to save the data.
BIOS Date
The item displays the date that the BIOS was built.
Legacy Diskette A
This setting allows the user to set the type of fl oppy disk drive installed as diskette A.
The options are Disabled, 360Kb 5.25 in, 1.2MB 5.25 in, 720Kb 3.5 in, 1.44/1.25MB,
3.5 in and 2.88MB 3.5 in.
4-3
X7DA3+ User's Manual
IDE Channel 0 Master/Slave, Secondary Master/Slave, SATA Port2,
SATA Port3
These settings allow the user to set the parameters of IDE Channel 0 Master/Slave,
Secondary Master/Slave, SATA Port2, SATA Port3 slots. Hit <Enter> to activate
the following submenu screen for detailed options of these items. Set the correct
confi gurations accordingly. The items included in the submenu are:
Type
This option allows the user to select the type of IDE hard drive. The option
Auto will allow the BIOS to automatically confi gure the parameters of the
HDD installed at the connection. Enter a number between 1 to 39 to select a
predetermined HDD type. Select User to allow the user to enter the parameters
of the HDD installed. Select CDROM if a CDROM drive is installed. Select
ATAPI if a removable disk drive is installed.
Total Sectors: This item displays the number of total sectors available in the
LBA Format.
Maximum Capacity: This item displays the maximum capacity in the LBA
Format.
Multi-Sector Transfer
This item allows the user to specify the number of sectors per block to be used
in multi-sector transfer. The options are Disabled, 4 Sectors, 8 Sectors, and
16 Sectors.
4-4
Chapter 4: BIOS
LBA Mode Control
This item determines whether the Phoenix BIOS will access the IDE Channel 0
Master Device via the LBA mode. The options are Enabled and Disabled.
32 Bit I/O
This option allows the user to enable or disable the function of 32-bit data transfer.
The options are Enabled and Disabled.
Transfer Mode
This option allows the user to set the transfer mode. The options are Standard, Fast
PIO1, Fast PIO2, Fast PIO3, Fast PIO4, FPIO3/DMA1 and FPIO4/DMA2.
Ultra DMA Mode
This option allows the user to select Ultra DMA Mode. The options are Disabled,
This setting allows the user to enable or disable the function of Parallel ATA. The
options are Disabled and Enabled.
Serial ATA
This setting allows the user to enable or disable the function of Serial ATA. The
options are Disabled and Enabled.
Native Mode Operation
This feature allows you to select Serial ATA for SATA or Auto (Native Mode) for
ATA. The options are: Serial ATA and Auto.
SATA Controller Mode
Select Compatible to allow the SATA and PATA drives to be automatically-detected
and be placed in the Legacy Mode by the BIOS. Select Enhanced to allow the
SATA and PATA drives to be to be automatically-detected and be placed in the
Native IDE Mode. (Note: The Enhanced mode is supported by the Windows
2000 OS or a later version.)
Serial ATA (SATA) RAID Enable (Available when SATA Controller is
enabled.)
Select Enable to enable Serial ATA RAID Functions. (For the Windows OS
environment, use the RAID driver if this feature is set to Enabled. When this item
is set to Enabled, the item: "ICH RAID Code Base" will be available for you to
select either Intel or Adaptec Host RAID fi rmware to be activated. If this item is
set to Disabled, the item-SATA AHCI Enable will be available.) The options are
Enabled and Disabled.
4-5
X7DA3+ User's Manual
ICH RAID Code Base (Available when SATA RAID is enabled.)
Select Intel to enable Intel's SATA RAID fi rmware. Select Adaptec to use Adaptec's
HostRAID fi rmware. The options are Intel and Adaptec.
SATA AHCI (Available when SATA RAID is disabled.)
Select Enable to enable the function of Serial ATA Advanced Host Interface. (Take
caution when using this function. This feature is for advanced programmers only.
The options are Enabled and Disabled.)
System Memory
This display informs you how much system memory is recognized as being present
in the system.
Extended Memory
This display informs you how much extended memory is recognized as being
present in the system.
4-4 Advanced Setup
Choose Advanced from the Phoenix BIOS Setup Utility main menu with the arrow keys.
You should see the following display. The items with a triangle beside them have sub
menus that can be accessed by highlighting the item and pressing <Enter>.
4-6
Chapter 4: BIOS
Boot Features
Access the submenu to make changes to the following settings.
QuickBoot Mode
If enabled, this feature will speed up the POST (Power On Self Test) routine by
skipping certain tests after the computer is turned on. The settings are Enabled
and Disabled. If Disabled, the POST routine will run at normal speed.
Quiet Boot
This setting allows you to Enable or Disable the graphic logo screen during
boot-up.
POST Errors
Select Enabled to temporarily halt system boot and display POST (Power-On-
Self Testing) error messages when errors occur during bootup. Select Disable
to continue with system boot even when an error occurs. The options are
Enabled and Disabled.
ACPI Mode
Select Yes to use ACPI (Advanced Confi guration and Power Interface) power
management on your system. The options are Yes and No.
ACPI Sleep Mode
This option allows you to decide how you are going to use the ACPI (Advanced
Confi guration and Power Interface) power management on your system when
it is in the sleep mode. The options are S1, S1&S3, and S3.
Power Button Behavior
If set to Instant-Off, the system will power off immediately as soon as the user
hits the power button. If set to 4-sec., the system will power off when the user
presses the power button for 4 seconds or longer. The options are Instant-off
and 4-sec override.
Resume On Modem Ring
Select On to wake your system up when an incoming call is received by your
modem. The options are On and Off.
Keyboard On Now Function
This feature allows you to determine how a user can power on the system
by using the keyboard when it is in S3 or S5 state. Select Disable to disable
this feature. Select Space to allow the user to power on the system when the
user presses the <Space> bar. Select Password to allow the user to power
on the system by entering a pre-set password. (The preset password must be
5-character long.)
4-7
X7DA3+ User's Manual
Power Loss Control
This setting allows you to decide how the system will react when power returns
after an unexpected loss of power. The options are Stay Off, Power On, and
Last State.
Watch Dog
If enabled, this option will automatically reset the system if the system is not
active for more than 5 minutes. The options are Enabled and Disabled.
Summary Screen
This setting allows you to Enable or Disable the summary screen which displays
the system confi guration during bootup.
Memory Cache
Cache System BIOS Area
This setting allows you to designate a reserve area in the system memory to be used
as a System BIOS buffer to allow the BIOS to write (cache) data into this reserved
memory area. Select Write Protect to enable this function, and this area will be
reserved for BIOS ROM access only. Select Uncached to disable this function and
make this area available for other devices.
Cache Video BIOS Area
This setting allows you to designate a reserve area in the system memory to be
used as a Video BIOS buffer to allow the BIOS to write (cache) data into this
reserved memory area. Select Write Protect to enable the function and this area
will be reserved for Video BIOS ROM access only. Select Uncached to disable this
function and make this area available for other devices.
Cache Base 0-512K
512K to be cached (written) into a buffer, a storage area in Static DROM (SDROM)
or to be written into L1, L2 cache inside the CPU to speed up CPU operations.
Select Uncached to disable this function. Select Write Through to allow data to
be cached into the buffer and written into the system memory at the same time.
Select Write Protect to prevent data from being written into the base memory
area of Block 0-512K. Select Write Back to allow the CPU to write data back
directly from the buffer without writing data to the System Memory for fast CPU
data processing and operation. The options are Uncached, Write Through, Write
Protect, and Write Back.
Cache Base 512K-640K
If enabled, this feature will allow the data stored in the memory area: 512K-640K
to be cached (written) into a buffer, a storage area in the Static DROM (SDROM)
or written into L1, L2, L3 cache inside the CPU to speed up CPU operations.
4-8
Chapter 4: BIOS
Select Uncached to disable this function. Select Write Through to allow data to
be cached into the buffer and written into the system memory at the same time.
Select Write Protect to prevent data from being written into the base memory
area of Block 512-640K. Select Write Back to allow the CPU to write data back
directly from the buffer without writing data to the System Memory for fast CPU
data processing and operation. The options are Uncached, Write Through, Write
Protect, and Write Back.
Cache Extended Memory
If enabled, this feature will allow the data stored in the extended memory area
to be cached (written) into a buffer, a storage area in Static DROM (SDROM) or
written into L1, L2, L3 cache inside the CPU to speed up CPU operations. Select
Uncached to disable this function. Select Write Through to allow data to be cached
into the buffer and written into the system memory at the same time. Select Write
Protect to prevent data from being written into the system memory area above 1MB.
Select Write Back to allow the CPU to write data back directly from the buffer without
writing data to the System Memory for fast CPU data processing and operation. The
options are Uncached, Write Through, Write Protect, and Write Back.
Discrete MTRR Allocation
If enabled, MTRRs (-Memory Type Range Registers) are confi gured as distinct,
separate units and cannot be overlapped. If enabled, the user can achieve better
graphic effects when using a Linux graphic driver that requires the write-combining
confi guration with 4GB or more memory. The options are Enabled and Disabled.
PCI Confi guration
Access the submenu to make changes to the following settings for PCI devices.
Onboard GLAN1/Onboard GLAN2 (Gigabit- LAN) OPROM Confi gure
Enabling this option provides the capability to boot from GLAN. The options are
Disabled and Enabled.
Onboard Storage OPROM Confi gure (Available if an onboard MASS
Storage Controller is detected.)
Select Enable to allow the user to boot from a onboard mass storage device. The
options are Enabled and Disabled.
Default Primary Video Adapter
This feature allows the user to specify which video adapter to be used as the
default primary video adapter--the onboard video adapter or others. The options
are Other and Onboard Video.
4-9
X7DA3+ User's Manual
Emulated IRQ Solutions
When Enabled, the Emulated IRQ Scheme will allow PCI devices to run on legacy
operating systems that use the MSI mechanism to generate INTX compatible
interrupts. The options are Disabled and Enabled.
PCI-Exp. I/O Performance
Some add-on cards perform faster with the coalesce feature, which limits the
payload size to 128 Bytes; while others perform better with a payload size of 256
Bytes, which inhibits the coalesce feature. Please refer to your add-on card user
guide for the desired setting. The options are Payload (256 Bytes) and Coalesce
Enabled (128 Bytes).
PCI Parity Error Forwarding
The feature allows SERR and PERR errors detected in the PCI slots to be sent
(forwarded) to the BIOS DMI Event Log for the user to review. The options are
Enabled and Disabled.
ROM Scan Ordering
This feature allows the user to decide which Option ROM to be activated fi rst. The
options are Onboard fi rst and Add-On fi rst.
PCI Fast Delayed Transaction
Enable this function to improve DMA data transfer rate for a PCI 32-bit multimedia
card. The options are Enable and Disabled.
Reset Confi guration Data
If set to Yes, this setting clears the Extended System Confi guration Data- (ESCD)
area. The options are Yes and No.
Frequency for PCI-X#1/Mass (Mass Storage)
This option allows the user to change the bus frequency for the devices installed
in the slot indicated. The options are Auto, PCI 33 MHz, PCI 66 MHz, PCI-X 66
MHz, PCI-X 100 MHz, and PCI-X 133 MHz.
Frequency for PCI-X#2-#3
This option allows the user to change the bus frequency for the devices installed
in the slot indicated. The options are Auto, PCI 33 MHz, PCI 66 MHz, PCI-X 66
Select enable to enable Interleaved Memory for Memory Bus Branch 0 Rank or
Branch 1 Rank. The options for Memory Interleaving are 1:1, 2:1 and 4:1.
Enhanced x8 Detection
Select Enabled to enable Enhanced x8 DRAM UC Error Detection. The options
are Disabled and Enabled.
High Temperature DRAM Operation
When set to Enabled, the BIOS will refer to the SPD table to set the maximum
DRAM temperature. If disabled, the BIOS will set the maximum DRAM temperature
based on a predefi ned value. The options are Enabled and Disabled.
AMB Thermal Sensor
Select Enabled to enable the thermal sensor embedded in the Advanced Memory
Buffer on a fully buffered memory module for thermal monitoring. The options are
Disabled and Enabled.
Thermal Throttle
Select Enabled to enable closed-loop thermal throttling on a fully buffered (FBD)
memory module. In the closed-loop thermal environment, thermal throttling will be
activated when the temperature of the FBD DIMM module exceeds a predefi ned
threshold. The options are Enabled and Disabled.
Global Activation Throttle
Select Enabled to enable the function of open-loop global thermal throttling on the
fully buffered (FBD) memory modules and allow global thermal throttling to become
active when the number of activate control exceeds a predefi ned number. The
options are Enabled and Disabled.
4-12
Chapter 4: BIOS
Snoop Filter
Select Enabled to eliminate snoop traffi c to the graphics port to greatly improve
system performance when running graphics intensive applications. The options are
Enabled and Disabled.
Crystal Beach Features
Select Enabled to use the Intel I/O AT (Acceleration Technology) to accelerate
the performance of TOE devices. (Note: A TOE device is a specialized, dedicated
processor that is installed on an add-on card or a network card to handle some or all
packet processing of this add-on card. For this motherboard, the TOE device is built
inside the ESB 2 South Bridge chip.) The options are Enabled and Disabled.
HD (High Defi nition) Audio Controller
This option allows the user to enable or disable the onboard HD Audio Controller.
Select Auto to allow the HD Audio Controller to be automatically enabled when
detected by the BIOS. The options are Disabled and Auto.
Route Port 80h Cycles to
This feature allows the user to decide which bus to send debug information to. The
options are Disabled, PCI and LPC.
Clock Spectrum Feature
If Enabled, the BIOS will monitor the level of Electromagnetic Interference caused
by the components and will attempt to decrease the interference whenever needed.
The options are Enabled and Disabled.
High Precision Event Time
Select Yes to activate the High Precision Event Timer (HPET), which is capable of
producing periodic interrupts at a much higher frequency than a Real-time Clock
(RTC) can in synchronizing multimedia streams, providing smooth playback and
reducing the dependency on other timestamp calculation devices, such as an x86
RDTSC Instruction embedded in a CPU. The High Precision Event Timer is used
to replace the 8254 Programmable Interval Timer. The options for this feature are
Yes and No.
USB Function
Select Enabled to enable the function of USB devices specifi ed. The settings are
Enabled and Disabled.
Legacy USB Support
This setting allows you to enable support for Legacy USB devices. The settings
are Enabled and Disabled.
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Advanced Processor Options
Access the submenu to make changes to the following settings.
CPU Speed
This is a display that indicates the speed of the installed processor.
Frequency Ratio (Available when supported by the CPU.)
The feature allows the user to set the internal frequency multiplier for the CPU. The
options are: Default, x12, x13, x14, x15, x16, x17 and x18. (Note: The settings
can be different, depending on the CPU speed.)
Core-Multi-Processing (Available when supported by the CPU.)
Set to Enabled to use a processor's Second Core and beyond. (Please refer to
Intel's web site for more information.) The options are Disabled and Enabled.
Machine Checking (Available when supported by the CPU.)
Set to Enabled to activate the function of Machine Checking and allow the CPU to
detect and report hardware (machine) errors via a set of model-specifi c registers
(MSRs). The options are Disabled and Enabled.
Thermal Management 2 (Available when supported by the CPU.)
Set to Enabled to use Thermal Management 2 (TM2) which will lower CPU voltage
and frequency when the CPU temperature reaches a predefi ned overheat threshold.
Set to Disabled to use Thermal Manager 1 (TM1), allowing CPU clocking to be
regulated via CPU Internal Clock modulation when the CPU temperature reaches
the overheat threshold.
C1 Enhanced Mode (Available when supported by the CPU.)
Set to Enabled to enable Enhanced Halt State to lower CPU voltage/frequency to
prevent overheat. The options are Enabled and Disabled. Note: please refer to
Intel’s web site for detailed information.
Execute Disable Bit (Available when supported by the CPU and the
OS.)
Set to Enabled to enable Execute Disable Bit and allow the processor
to classify
it cannot, and thus preventing a worm or a virus from inserting or creating a fl ood
of codes to overwhelm the processor or damage the system during an attack.
(Note: this feature is available when your OS and your CPU support the function
of Execute Disable Bit.) The options are Disabled and Enabled. Note: For more
information regarding hardware/software support for this function, please refer to
Intel's and Microsoft's web sites.
areas in memory where an application code can execute and where
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Chapter 4: BIOS
Adjacent Cache Line Prefetch (Available when supported by the
CPU.)
The CPU fetches the cache line for 64 bytes if this option is set to Disabled. The
CPU fetches both cache lines for 128 bytes as comprised if Enabled. The options
are Disabled and Enabled.
Hardware Prefetch (Available when supported by the CPU.)
Set to this option to enabled to enable the hardware components that are used in
conjunction with software programs to prefetch data in order to shorten execution
cycles and maximize data processing effi ciency. The options are Disabled and
Enabled.
Direct Cache Access (Available when supported by the CPU.)
Set to Enable to route inbound network IO traffi c directly into processor caches
to reduce memory latency and improve network performance. The options are
Disabled and Enabled.
DCA Delay Clocks(Available when supported by the CPU.)
This feature allows the user to set the clock delay setting from snoop to prefetch
for Direct Cache Access. Select a setting from 8 (bus cycles) to 120 (bus cycles)
(in 8-cycle increment). The default setting is 32 (bus cycles).
Intel <R> Virtualization Technology (Available when supported by
the CPU.)
Select Enabled to use the feature of Virtualization Technology to allow one platform
to run multiple operating systems and applications in independent partitions, creating
multiple "virtual" systems in one physical computer. The options are Enabled and
Disabled. Note: If there is any change to this setting, you will need to power off
and restart the system for the change to take effect. Please refer to Intel’s web
site for detailed information.
Intel EIST Support (Available when supported by the CPU.)
Select Enabled to use the Enhanced Intel SpeedStep Technology and allows the
system to automatically adjust processor voltage and core frequency in an effort
to reduce power consumption and heat dissipation. The options are Enabled and
Disabled. Please refer to Intel’s web site for detailed information.
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X7DA3+ User's Manual
I/O Device Confi guration
Access the submenu to make changes to the following settings.
KBC Clock Input
This setting allows you to select clock frequency for KBC. The options are 6MHz,
8MHz, 12MHz, and 16MHz.
Serial Port A
This setting allows you to assign control of Serial Port A. The options are Enabled
(user defi ned), Disabled, and Auto (BIOS- or OS- controlled).
Base I/O Address
This setting allows you to select the base I/O address for Serial Port A. The
options are 3F8, 2F8, 3E8, and 2E8.
Interrupt
This setting allows you to select the IRQ (interrupt request) for Serial Port A.
The options are IRQ3 and IRQ4.
Serial Port B (Not for external use, used for IPMI only)
This setting allows you to assign control of Serial Port B. The options are Enabled
(user defi ned), Disabled, Auto (BIOS controlled) and OS Controlled.
Mode
This setting allows you to set the type of device that will be connected to Serial
Port B. The options are Normal and IR (for an infrared device).
Base I/O Address
This setting allows you to select the base I/O address for Serial Port B. The
options are 3F8, 2F8, 3E8 and 2E8.
Interrupt
This setting allows you to select the IRQ (interrupt request) for Serial Port B.
The options are IRQ3 and IRQ4.
Parallel Port
This setting allows you to assign control of the parallel port. The options are
Enabled (user defi ned), Disabled and Auto (BIOS-or OS- controlled).
Base I/O Address
Select the base I/O address for the parallel port. The options are 378, 278
and 3BC.
Interrupt
This setting allows you to select the IRQ (interrupt request) for the parallel port.
The options are IRQ5 and IRQ7.
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Chapter 4: BIOS
Mode
This feature allows you to specify the parallel port mode. The options are Output
only, Bi-Directional, EPP and ECP.
DMA Channel
This item allows you to specify the DMA channel for the parallel port. The
options are DMA1 and DMA3.
Floppy Disk Controller
This setting allows you to assign control of the fl oppy disk controller. The options
are Enabled (user defi ned), Disabled, and Auto (BIOS and OS controlled).
Base I/O Address
This setting allows you to select the base I/O address for the parallel port. The
options are Primary and Secondary.
DMI Event Logging
Access the submenu to make changes to the following settings.
Event Log Validity
This is a display to inform you of the event log validity. It is not a setting.
Event Log Capacity
This is a display to inform you of the event log capacity. It is not a setting.
View DMI Event Log
Highlight this item and press <Enter> to view the contents of the event log.
Event Logging
This setting allows you to Enable or Disable event logging.
ECC Event Logging
This setting allows you to Enable or Disable ECC event logging.
Mark DMI Events as Read
Highlight this item and press <Enter> to mark the DMI events as read.
Clear All DMI Event Logs
Select Yes and press <Enter> to clear all DMI event logs. The options are Yes
and No.
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Console Redirection
Access the submenu to make changes to the following settings.
COM Port Address
This item allows you to specify which COM port to direct the remote console to:
Onboard COM A or Onboard COM B. This setting can also be Disabled.
BAUD Rate
This item allows you to set the BAUD rate for Console Redirection. The options
are 300, 1200, 2400, 9600, 19.2K, 38.4K, 57.6K, and 115.2K.
Console Type
This item allows you to choose the console redirection type. The options are VT100,
VT100,8bit, PC-ANSI, 7bit, PC ANSI, VT100+, and VT-UTF8.
Flow Control
This item allows you to set the fl ow control for the console redirection. The options
are: None, XON/XOFF, and CTS/RTS.
Console Connection
This item allows you to decide how the console redirection is to be connected:
either Direct or Via Modem.
Continue CR after POST
This item allows you to decide whether you want to continue with console redirection
after POST routines. The options are On and Off.
.
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Chapter 4: BIOS
Hardware Monitor Logic
Note: The Phoenix BIOS will automatically detect the type of CPU(s) and hardware
monitoring chip used on the motherboard and will display the Hardware Monitoring
Screen accordingly. Your screen may look differently from the one shown below.
CPU Temperature Threshold
This option allows the user to set a CPU temperature threshold that will activate
the alarm system when the CPU temperature reaches this pre-set temperature
threshold. The options are 70
Highlight this and hit <Enter> to see the status for each of the following items:
CPU1 Temperature/CPU1 Second Core
CPU2 Temperature/CPU2 Second Core
PECI Agent 1 Temperature/PECI Agent 2 Temperature
PECI Agent 3 Temperature/PECI Agent 4 Temperature
System Temperature
Fan1-Fan8 Speeds: If the feature of Auto Fan Control is enabled, the BIOS will
automatically display the status of the fans indicated in this item.
o
C, 75oC, 80oC and 85oC.
Fan Speed Control Modes
This feature allows the user to decide how the system controls the speeds of the
onboard fans. The CPU temperature and the fan speed are correlative. When the
CPU on-die temperature increases, the fan speed will also increase, and vice versa.
If the option is set to 3-pin fan, the fan speed is controlled by voltage. If the option
is set to 4-pin, the fan speed will be controlled by Pulse Width Modulation (PWM).
Select 3-pin if your chassis came with 3-pin fan headers. Select 4-pin if your chas-
sis came with 4-pin fan headers. Select Workstation if your system is used as a
Workstation. Select Server if your system is used as a Server. Select Disable to
disable the fan speed control function and allow the onboard fans to constantly run
at full speed (12V). The Options are: 1. Full Speed@12V (Disable), 2. Optimized
Server w/3-pin, 3.Optimized Workstation w/3-pin, 4. Optimized Server w/4-pin, and
5. Optimized Server w/4-pin.
Voltage Monitoring
The following items will be monitored and displayed: