Supermicro X10DRG-O+-CPU, X10DRG-OT+-CPU, X10DRG-O-PCIE User Manual

X10DRG-O+-CPU

X10DRG-OT+-CPU

X10DRG-O-PCIE

USER’S MANUAL

Revision 1.1

The information in this user’s manual has been carefully reviewed and is believed to be accurate. The
vendor assumes no responsibility for any inaccuracies that may be contained in this document, and makes
no commitment to update or to keep current the information in this manual, or to notify any person or
organization of the updates. Please Note: For the most up-to-date version of this manual, please see our
website at

www.supermicro.com.

Super Micro Computer, Inc. ("Supermicro") reserves the right to make changes to the product described
in this manual at any time and without notice. This product, including software and documentation, is the
property of Supermicro and/or its licensors, and is supplied only under a license. Any use or reproduction
of this product is not allowed, except as expressly permitted by the terms of said license.

IN NO EVENT WILL SUPER MICRO COMPUTER, INC. BE LIABLE FOR DIRECT, INDIRECT, SPECIAL,
INCIDENTAL, SPECULATIVE OR CONSEQUENTIAL DAMAGES ARISING FROM THE USE OR
INABILITY TO USE THIS PRODUCT OR DOCUMENTATION, EVEN IF ADVISED OF THE POSSIBILITY
OF SUCH DAMAGES. IN PARTICULAR, SUPER MICRO COMPUTER, INC. SHALL NOT HAVE LIABILITY
FOR ANY HARDWARE, SOFTWARE, OR DATA STORED OR USED WITH THE PRODUCT, INCLUDING
THE COSTS OF REPAIRING, REPLACING, INTEGRATING, INSTALLING OR RECOVERING SUCH
HARDWARE, SOFTWARE, OR DATA.

Any disputes arising between manufacturer and customer shall be governed by the laws of Santa Clara
County in the State of California, USA. The State of California, County of Santa Clara shall be the exclusive
venue for the resolution of any such disputes. Supermicro's total liability for all claims will not exceed the
price paid for the hardware product.

FCC Statement: This equipment has been tested and found to comply with the limits for a Class A digital
device pursuant to Part 15 of the FCC Rules. These limits are designed to provide reasonable protection
against harmful interference when the equipment is operated in a commercial environment. This equipment
generates, uses, and can radiate radio frequency energy and, if not installed and used in accordance
with the manufacturer’s instruction manual, may cause harmful interference with radio communications.
Operation of this equipment in a residential area is likely to cause harmful interference, in which case you
will be required to correct the interference at your own expense.

California Best Management Practices Regulations for Perchlorate Materials: This Perchlorate warning
applies only to products containing CR (Manganese Dioxide) Lithium coin cells. “Perchlorate Material­special handling may apply. See

The products sold by Supermicro are not intended for and will not be used in life support systems, medical
equipment, nuclear facilities or systems, aircraft, aircraft devices, aircraft/emergency communication devices or
other critical systems whose failure to perform be reasonably expected to result in signifi cant injury or loss of life
or catastrophic property damage. Accordingly, Supermicro disclaims any and all liability, and should buyer use or
sell such products for use in such ultra-hazardous applications, it does so entirely at its own risk. Furthermore,
buyer agrees to fully indemnify, defend and hold Supermicro harmless for and against any and all claims, demands,
actions, litigation, and proceedings of any kind arising out of or related to such ultra-hazardous use or sale.

Manual Revision 1.1

Release Date: November 8, 2018

Unless you request and receive written permission from Super Micro Computer, Inc., you may not copy any part
of this document. Information in this document is subject to change without notice. Other products and companies
referred to herein are trademarks or registered trademarks of their respective companies or mark holders.

Copyright
All rights reserved
Printed in the United States of America

WARNING: This product can expose you to chemicals including
lead, known to the State of California to cause cancer and birth

!

defects or other reproductive harm. For more information, go
to www.P65Warnings.ca.gov

© 2018 by Super Micro Computer, Inc.

www.dtsc.ca.gov/hazardouswaste/perchlorate”.

.

Preface

This manual is written for system integrators, IT professionals, and

knowledgeable end users. It provides information for the installation and use of the

X10DRG-O+-CPU/X10DRG-OT+-CPU motherboard.

About This Motherboard

The Supermicro X10DRG-O+-CPU/X10DRG-OT+-CPU motherboard supports

dual Intel® E5-2600v3/v4 Series processors (Socket R3) that offer the new Intel®

Microarchitecture 22nm (E5-2600v3)/14nm (E5-2600v4) Processing Technology,

delivering the most balanced solution in performance, power effi ciency, and features

to address the diverse needs of next-generation data centers. With the PCH C612

built in, the X10DRG-O+-CPU/X10DRG-OT+-CPU supports Intel® Node Manager

3.0 and Management Engine (ME) technologies. This motherboard is optimized for

High-Performance Computing (HPC) or VDI platforms. Please refer to our website

(http://www.supermicro.com) for CPU and memory support updates.

Preface

Manual Organization

Chapter 1 describes the features, specifi cations, and performance of the mother-

board. It also provides detailed information about the Intel® PCH C612 chipset.

Chapter 2 provides hardware installation instructions. Read this chapter when in-

stalling the processor, memory modules, and other hardware components into the

system. If you encounter any problems, see Chapter 3, which describes trouble-

shooting procedures for video, memory, and system setup stored in the CMOS.

Chapter 4 includes an introduction to BIOS and provides detailed information on

running the CMOS setup utility.

Appendix A provides BIOS error beep codes.

Appendix B lists software installation instructions.

Appendix C contains UEFI BIOS recovery instructions.

iii

X10DRG-O(T)+-CPU/X10DRG-O-PCIE User’s Manual

Conventions Used in the Manual

Pay special attention to the following symbols for proper system installation:

Warning: Important information given to ensure proper system installation or to prevent

damage to the components or injury to yourself;

Note: Additional information given to differentiate between models or

instructions provided for proper system setup.

iv

Contacting Supermicro

Headquarters

Address: Super Micro Computer, Inc.

980 Rock Ave.

San Jose, CA 95131 U.S.A.

Tel: [phone]

Fax: [phone]

Email: [e-mail] (General Information)

[e-mail] (Technical Support)

Preface

Website:

Europe

Address: Super Micro Computer B.V.

Tel: [phone]

Fax: [phone]

Email: [e-mail] (General Information)

Website:

Asia-Pacifi c

Address: Super Micro Computer, Inc.

www.supermicro.com

Het Sterrenbeeld 28, 5215 ML

's-Hertogenbosch, The Netherlands

[e-mail] (Technical Support)

[e-mail] (Customer Support)

www.supermicro.nl

3F, No. 150, Jian 1st Rd.

Zhonghe Dist., New Taipei City 235

Tel: [phone]

Fax: [phone]

Email: [e-mail]

Website:

Taiwan (R.O.C)

www.supermicro.com.tw

v

X10DRG-O(T)+-CPU/X10DRG-O-PCIE User’s Manual

Table of Contents

Preface

Chapter 1 Overview

1-1 Overview ......................................................................................................... 1-1

1-2 Processor and Chipset Overview.................................................................. 1-14

1-3 Special Features ........................................................................................... 1-15

1-4 System Health Monitoring ............................................................................. 1-15

1-5 ACPI Features ............................................................................................... 1-16

1-6 Power Supply ................................................................................................ 1-16

1-7 Advanced Power Management ..................................................................... 1-17

Intel® Intelligent Power Node Manager (NM) (Available when the SPM Utility

is Installed) .................................................................................................... 1-17

Management Engine (ME) ............................................................................ 1-17

Chapter 2 Installation

2-1 Standardized Warning Statements ................................................................. 2-1

2-2 Static-Sensitive Devices .................................................................................. 2-4

2-3 System Board Installation ............................................................................... 2-5

2-4 Processor and Heatsink Installation................................................................ 2-7

Installing the LGA2011 Processor ................................................................. 2-7

Installing a Passive CPU Heatsink ................................................................2-11

Removing the Heatsink ................................................................................. 2-12

2-5 Installing and Removing the Memory Modules ............................................. 2-13

Installing Memory Modules ........................................................................... 2-13

Removing Memory Modules ......................................................................... 2-13

2-6 Control Panel Connectors and I/O Ports ...................................................... 2-16

Backpanel Connectors and I/O Ports ........................................................... 2-16

Backpanel I/O Port Locations and Defi nitions ............................................. 2-16

Video Connection ..................................................................................... 2-17

Ethernet Ports .......................................................................................... 2-17

Universal Serial Bus (USB) ...................................................................... 2-18

Unit Identifi er Switch/UID LED Indicator .................................................. 2-19

Serial Port ................................................................................................. 2-20

Front Control Panel ....................................................................................... 2-21

Front Control Panel Pin Defi nitions............................................................... 2-22

NMI Button ............................................................................................... 2-22

vi

Table of Contents

Power LED .............................................................................................. 2-22

HDD/UID LED .......................................................................................... 2-23

NIC1/NIC2 LED Indicators ....................................................................... 2-23

Overheat (OH)/Fan Fail/UID LED ............................................................ 2-24

Power Fail LED ........................................................................................ 2-24

Reset Button ........................................................................................... 2-25

Power Button ........................................................................................... 2-25

2-7 Connecting Cables ........................................................................................ 2-26

Power Connectors ................................................................................... 2-26

Fan Headers ............................................................................................. 2-27

Internal Speaker ....................................................................................... 2-28

TPM/Port 80 Header ................................................................................ 2-28

I-SGPIO1/2 & S-SGPIO Headers ............................................................. 2-29

Chassis Intrusion ..................................................................................... 2-29

SATA DOM Power Connectors ................................................................ 2-30

2-8 Jumper Settings ............................................................................................ 2-31

Explanation of Jumpers ................................................................................ 2-31

LAN Enable/Disable ................................................................................. 2-31

CMOS Clear ............................................................................................. 2-32

Watch Dog Enable/Disable ...................................................................... 2-32

VGA Enable .............................................................................................. 2-33

BMC Enable ............................................................................................ 2-33

Manufacturer Mode Select ....................................................................... 2-34

2-9 Onboard LED Indicators ............................................................................... 2-35

LAN LEDs ................................................................................................. 2-35

IPMI_LAN LEDs ....................................................................................... 2-35

Onboard Power LED ............................................................................... 2-36

BMC Heartbeat LED ................................................................................ 2-36

2-10 SATA Connections ......................................................................................... 2-37

Serial ATA Ports........................................................................................ 2-37

Chapter 3 Troubleshooting

3-1 Troubleshooting Procedures ........................................................................... 3-1

3-2 Technical Support Procedures ........................................................................ 3-5

3-3 Battery Removal and Installation .................................................................... 3-6

3-4 Frequently Asked Questions ........................................................................... 3-7

3-5 Returning Merchandise for Service................................................................. 3-8

vii

X10DRG-O(T)+-CPU/X10DRG-O-PCIE User’s Manual

Chapter 4 BIOS

4-1 Introduction ...................................................................................................... 4-1

4-2 Main Setup ...................................................................................................... 4-2

4-3 Advanced Setup Confi gurations...................................................................... 4-4

4-4 Event Logs .................................................................................................... 4-36

4-5 IPMI ...............................................................................................................4-38

4-6 Security Settings ........................................................................................... 4-41

4-7 Boot Settings ................................................................................................. 4-44

4-8 Save & Exit ................................................................................................... 4-47

Appendix A BIOS POST Error Beep Codes

BIOS Error Beep Codes .............................................................................................A-1

Appendix B Software Installation Instructions

B-1 Installing Software Programs ..........................................................................B-1

B-2 Confi guring SuperDoctor 5 .............................................................................B-2

Appendix C UEFI BIOS Recovery Instructions

C-1 An Overview to the UEFI BIOS ......................................................................C-1

C-2 How to Recover the UEFI BIOS Image (-the Main BIOS Block)....................C-1

C-3 To Recover the Main BIOS Block Using a USB-Attached Device..................C-1

viii

Chapter 1: Overview

Chapter 1

Overview

1-1 Overview

Checklist

Congratulations on purchasing your system board from an acknowledged leader in

the industry. Supermicro boards are designed with the utmost attention to detail to

provide you with the highest standards in quality and performance.

The X10DRG-O(T)+-CPU/X10DRG-O-PCIE board was designed to be used with

a Supermicro-proprietary chassis as an integrated server platform. It is not to be

used as a standalone product and will not be shipped independently in a retail box.

No shipping package will be provided in your shipment.

Note 1: For your system to work properly, please follow the links below

to download all necessary drivers/utilities and the user's manual for your

system board.

• Supermicro product manuals: http://www.supermicro.com/support/manuals/

• Product drivers and utilities: http://www.supermicro.com/wftp

Note 2: For safety considerations, please refer to the complete list of safety

warnings posted on the Supermicro website at http://www.supermicro.com/

about/policies/safety_information.cfm. If you have any questions, please

contact our support team at [e-mail]

1-1

X10DRG-O(T)+-CPU/X10DRG-O-PCIE User’s Manual

X10DRG-O+-CPU/X10DRG-OT+-CPU Image

Note: All graphics shown in this manual were based upon the latest PCB

revision available at the time of publishing of the manual. The motherboard

you've received may or may not look exactly the same as the graphics

shown in this manual.

1-2

X10DRG-O+-CPU/X10DRG-OT+-CPU Layout

SW1

LE1

JVRM1

JPG1

COM1

JVRM2

VGA

LEDM1

LAN2

BMC

LAN1

USB7/8(3.0)

LAN

CTRL

IPMI_LAN

USB5/6(3.0)

JPW10

Chapter 1: Overview

JPB1

JPME2

JBR1

JWD1

JSPK1

S-SGPIO

J1

JF1

FAN8

J33

J34

DESIGNED IN USA

JPW16

FAN7

P2 DIMMH3

CLOSE 1st

FAN3

USB4

JPW22

CPU2

PCH

JBT1

USB0/1

USB2/3

1

S-SATA2

S-SATA1

S-SATA0

S-SATA3

OPEN 1st

X10DRG-O+-CPU

REV:

BIOS LICENSE

P2 DIMMF1

P2 DIMMF2

P2 DIMMF3

1.00

BAR CODE

IPMI CODE

P2 DIMME2

P2 DIMME3

1G/10G MAC CODE

10G SAN MAC

P2 DIMME1

P1 DIMMC1

JPW21 JPW24JPW23

JPW3

JPW14

JPW13

JPW15

+

JTPM1

JL1

LE2

FAN4

1

P2 DIMMH2

P2 DIMMH1

P2 DIMMG2

P2 DIMMG1

P2 DIMMG3

JF1

X

PS

PWR

UID2NIC

HDDNIC

PWR

RST

NMI

FAIL LED

1 LED

LED

ON

P1 DIMMC2

P1 DIMMC3

J32

+

P1 DIMMD1

J31

BT1

P1 DIMMD2

P1 DIMMD3

I- SATA0

CLOSE 1st

JPP2

JPP1

JSD2

JSD1

JPW17JPW18

P1 DIMMA1

FAN5

FAN1

JPL1

LD1

LD2

JPW5

I-SGPIO2

I-SGPIO1

JPW6

JPW12

I- SATA1

I- SATA2

CPU1

JITP1

JPW4

I- SATA3

I- SATA5

I- SATA4

OPEN 1st

FAN2

FAN6

P1 DIMMB3

P1 DIMMB2

P1 DIMMB1

P1 DIMMA2

P1 DIMMA3

JPW7

Notes:

• For the latest CPU/memory updates, please refer to our website at http://www.

supermicro.com/products/motherboard/ for details.

• See Chapter 2 for detailed information on jumpers, I/O ports and JF1 front

panel connections.

• " " indicates the location of Pin 1.

• Jumpers/LED indicators not indicated are for internal testing only.

• Use only the correct type of onboard CMOS battery as specifi ed by the manufac-

turer. Do not install the onboard battery upside down to avoid possible explosion.

1-3

X10DRG-O(T)+-CPU/X10DRG-O-PCIE User’s Manual

X10DRG-O-PCIE Card Image

Note: All graphics shown in this manual were based upon the latest PCB

revision available at the time of publishing of the manual. The motherboard

you've received may or may not look exactly the same as the graphics

shown in this manual.

1-4

X10DRG-O-PCIE Card Layout

JCPLD

Chapter 1: Overview

FAN23FAN24FAN25

CPU1 SLOT1 PCI-E 3.0 X16

JPCIE1

JPCIE3

LED3
LED4
LED7

L5

CPU1 SLOT2 PCI-E 3.0 X16

CPU1 SLOT3 PCI-E 3.0 X16

JPCIE5

Root Port
SLOT 1
SLOT 2

SLOT 5
SLOT 4
SLOT 3

LED19
LED11
LED15

CPU1 SLOT4 PCI-E 3.0 X16

JPCIE4

JP2

JP4

CPU1 SLOT5 PCI-E 3.0 X16

JPCIE2

J33

J34

CPU1 SLOT7 PCI-E 3.0 X8 (IN X16)

CPU2

SLOT6 PCI-E 3.0 X16

JPCIE6

JPCIE12

JPCIE7

CUT OFF

CPU1 SLOT8 PCI-E 3.0 X16

CPU1 SLOT9 PCI-E 3.0 X16

JPCIE9

J32

J31

LED1
LED2
LED6

Root Port
SLOT 8
SLOT 9

LED18
LED14
LED10

SLOT 12
SLOT 11
SLOT 10

JP3

CPU1 SLOT10 PCI-E 3.0 X16

L3

JPCIE10

JPCIE11

JP1

X10DRG-O-PCIE

REV:1.00
DESIGNED IN USA

CPU1 SLOT11 PCI-E 3.0 X16

FAN21FAN22

CPU1 SLOT12 PCI-E 3.0 X16

JPCIE8

Note: Jumpers/LED Indicators not indicated are for testing only.

1-5

X10DRG-O(T)+-CPU/X10DRG-O-PCIE User’s Manual

X10DRG-O+-CPU/X10DRG-OT+-CPU Jumpers

Jumper

Description Default Setting

JBT1 Clear CMOS See Chapter 2

JPB1 BMC Enable Pins 1-2 (Enabled)

JPG1 VGA Enable Pins 1-2 (Enabled)

JPL1 GLAN1/GLAN2 Enable Pins 1-2 (Enabled)

JPME2 Manufacturer (ME) Mode Select Pins 1-2 (Normal)

JWD1 Watch-Dog Timer Enable Pins 1-2 (Reset)

X10DRG-O+-CPU/X10DRG-OT+-CPU Connectors

Connectors Description

Battery (JBT1) Onboard CMOS battery (See Chpt. 3 for used battery dis-

posal)

COM1 Backpanel COM Port 1 for front access

FAN1-FAN8 CPU/system cooling fan headers (Fans 1-8)

JF1 Front_Panel_Control header

J31/J32, J33/J34 PCI-E Slots (J31/J32: supported by CPU1), (J33/J34: sup-

ported by CPU2)

JL1 Chassis intrusion header

SP1 Onboard speaker header

JPW21/22/23/24 SMCI-proprietary main power connectors

JPW3-7, JPW12-18 12V 8-pin power connectors (JPW17/JPW18: white power

connectors used for BPD HDDs only.)

JSD1/JSD2 Power connector SATA DOM

JTPM1 TPM (Trusted Platform Module)/Port 80 header

LAN1/LAN2 G-bit Ethernet (GLAN) ports 1/2

IPMI_LAN IPMI_dedicated LAN support by the Aspeed controller

SP1 Internal buzzer/speaker

(I-)SATA 0-3 Intel® SATA 3.0 connectors (0-3) from Intel® PCH

(I-)SATA 4/5 Intel® SATA SuperDOM connectors (I-SATA4/5) from

Intel® PCH

(S)-SATA0-3 SATA connectors (0-3) from Intel® SCU

I-SGPIO1/2 Serial_Link General-Purpose I/O (SGPIO) headers for I-

SATA connections (I-SGPIO1 for I-SATA0-3, I-SGPIO2 for
I-SATA4/5)

S-SGPIO Serial_Link General-Purpose I/O (SGPIO) headers for S-

SW1 UID (Unit Identifi er switch)

(FP) USB 0/1 USB 2.0 connections 0/1 for front access

SATA connections (S-SATA0-3) supported by Intel® SCU

1-6

Chapter 1: Overview

(FP) USB 2/3 USB 2.0 connections 2/3 for front access

(FP) USB 4 Type A USB (2.0) connector 4 for front access

(BP) USB 5/6 (3.0) USB 3.0 connections 5/6 for rear access

(BP) USB 7/8 (3.0) USB 3.0 connections 7/8 header for rear access

VGA Backpanel VGA port

X10DRG-O+-CPU/X10DRG-OT+-CPU LED Indicators

LED Description State Status

LE1 Rear UID LED Blue: On Unit Identifi ed

LE2 Onboard PWR LED On System Power On

LEDM1 BMC Heartbeat LED Green: Blinking BMC Normal

1-7

X10DRG-O(T)+-CPU/X10DRG-O-PCIE User’s Manual

X10DRG-O-PCIE Connectors

Connector Description

JPCIE1 CPU1 Slot1 3.0 x16

JPCIE2 CPU1 Slot5 3.0 x16

JPCIE3 CPU1 Slot2 3.0 x16

JPCIE4 CPU1 Slot4 3.0 x16

JPCIE5 CPU1 Slot3 3.0 x16

JPCIE6 CPU1 Slot7 3.0 x8 (in x16)

JPCIE7 CPU1 Slot8 3.0 x16

JPCIE8 CPU1 Slot12 3.0 x16

JPCIE9 CPU1 Slot9 3.0 x16

JPCIE10 CPU1 Slot10 3.0 x16

JPCIE11 CPU1 Slot11 3.0 x16

JPCIE12 CPU2 Slot6 3.0 x16

1-8

CPU Board Features

Chapter 1: Overview

CPU

Memory

Chipset

Expansion

• Dual Intel® E5-2600v3/v4 Series processors (Socket

R3) (LGA 2011); each processor supports dual full-

width Intel® QuickPath Interconnect (QPI) links (of

up to 9.6 GT/s one direction per QPI)

Note: E5-2600v4 requires Revision 2.0 BIOS

(or higher).

• Integrated memory controller supports:

Up to 3072 GB of 288-pin Load Reduced (LRDIMM)

or 768 GB of Registered (RDIMM) DDR4 ECC

2400/2133/1866/1600 MHz in 24 slots.

Note: For the latest CPU/memory updates,

please refer to our website at http://www.super-

micro.com/products/motherboard.

DIMM sizes

• DIMM Up to 128GB at 1.2V

• Intel® PCH C612

• Four (4) PCI-E 3.0 x24 slots (J31/J32, J33/J34)

Slots

Graphics

Network

I/O Devices

• Graphics controller via the Aspeed AST2400 BMC

• Intel® i350 Gigabit (10/100/1000 Mb/s) Ethernet

controller for LAN 1/LAN 2 ports (X10DRG-O+-CPU)

• Intel® X540 10GbE (TLAN) Ethernet controller for

LAN 1/LAN 2 ports (X10DRG-OT+-CPU)

• Aspeed 2400 Baseboard Controller (BMC) supports

IPMI_LAN 2.0

SATA Connections

• SATA Ports Ten (10) SATA 3.0 ports

• I-SATA 0-3

• I-SATA 4/5 (SuperDOM sup-

port)

• S-SATA 0-3

• RAID RAID 0, 1, 5, 10

IPMI 2.0

• IPMI 2.0 supported by Aspeed AST2400

1-9

X10DRG-O(T)+-CPU/X10DRG-O-PCIE User’s Manual

Serial (COM) Port

• One (1) Fast UART 16550 connections (COM1: for

backpanel support)

Peripheral
Devices

BIOS

Power

Management

USB Devices

• Four (4) USB 3.0 ports on the rear I/O panel (USB

5/6, USB 7/8)

• Two (2) USB 2.0 header for four USB 2.0 front-

accessible connections (USB 0/1, 2/3)

• One (1) USB 2.0 Type A header front-access (USB 4)

• 16 MB SPI AMI BIOS

®

SM Flash UEFI BIOS

• ACPI 3.0/4.0, PCI F/W 3.0, BIOS rescue hot-key,

riser card detection, Plug & Play (PnP) and SMBIOS

2.7 or later

• ACPI power management

• Main switch override mechanism

• Power-on mode for AC power recovery

• Intel® Intelligent Power Node Manager 3.0 (Available

when the SPM utility is installed and special power

supply is used.)

• Management Engine (ME)

System
Health

Monitoring

System Health/CPU Monitoring

• Onboard voltage monitoring for +3.3V, 3.3V standby,

+5V, +5V standby, +12V, chipset, BMC, memory, bat-

tery, and CPU core voltages

• Temperature monitoring for system/memory/PCH/

CPU temperatures

• CPU 5-phase switching voltage regulator

• CPU/system overheat LED and control

• CPU thermal trip support

• Status monitor for speed control

• Status monitor for On/Off control

• CPU Thermal Design Power (TDP) support of up to

160W (See Note 1 on the next page.)

Fan Control

• Fan status monitoring via IPMI connections

• Dual cooling zone

• Multi-fan speed control via BMC

• Pulse Width Modulation (PWM) fan control

1-10

Chapter 1: Overview

System
Management

• PECI (Platform Environment Confi guration Interface)

2.0 support

• UID (Unit Identifi cation)/Remote UID

• System resource alert via SuperDoctor® 5

• SuperDoctor® 5, Watch Dog, NMI

• Chassis Intrusion header and detection

Dimensions

Note 1: The CPU maximum thermal design power (TDP) is subject to

chassis and heatsink cooling restrictions. For proper thermal management,

please check the chassis and heatsink specifi cations for proper CPU TDP

sizing.

Note 2: For IPMI confi guration instructions, please refer to the Embedded

IPMI Confi guration User's Guide available @ http://www.supermicro.com/

support/manuals/.

Note 3: It is strongly recommended that you change BMC login information

upon initial system power-on. The manufacture default username is ADMIN

and the password is ADMIN. For proper BMC confi guration, please refer to

http://www.supermicro.com/products/info/fi les/IPMI/Best_Practices_BMC_

Security.pdf.

• 19.00" (L) x 17.00" (W) (482.60 mm x 431.80 mm)

1-11

X10DRG-O(T)+-CPU/X10DRG-O-PCIE User’s Manual

PC

G

10G

G

S

4

S

3

S

8

X16

X16

16

p

1

p
DMI2

1

.00

p

p

p

1

X8XX16XX16

X

CPU

G

#D-3

#D-2

#D-1

#C-3

#C-2

#C-1

#B-3

#B-2

#A-1

#A-2

#B-1

#A-3

2133

DDRIV

CPU1

E5

DDR-IV

#2 #3 #1 #2 #3#1DMI2

P0

QPI

9.6G

P1 P0

QPI

9.6G

CPU2

P1

E5

DDR-IV

DMI2

#E-1

#E-2

#F-3

#F-2

#F-1

#E-3

2133

DDRIV

#G-1

#G-2

#G-3

#H-1

#H-2

#H-3

P50

Dedicated LAN

P48

VGA port

PCI-E X16 Gen3

PCI-E X16 Gen3

PCI-E X8 Gen3

PCI-E X24

PCI-E X4 Gen2

BMC
ASD2400

VGA

Internal
COM Port

P30

Header

USB

P30

4 in Rear IO: USB3.0
1 internal Type A: USB2.0
2 internal headers: USB2.0

PCIe X1 Gen2

USB 3.0/2.0

”

9

PCI-E X16 Gen3

PCI-E X16 Gen3

DMI2
5GB/s

DMI2

P28

PCH
C612

PCIE

PCIE

SAS

PORTs#0~3

SAS

PORTs#2~5

SAS

PORTs#0~1

SATA3

6.0 Gb/S

For PORT 6~9

SATA3

6.0 Gb/S

For PORT 2~5

SATA3

6.0 Gb/S

For PORT 0~1

PCI-E X16 Gen3

LAN

X540 (-OT+)
I350 (-O+)

#8

#7

#6

#4

#3

#2

#1

#0

PCI-E X24

PCI-E X4 Gen2

#9

S_SATA

#5

i_SATAi_SATA

SPI

LAN

EN2, X1

EN2

X4

XB

XB

XB2SXB1

EN2

X4

H

X

Note: This is a general block diagram and may not represent the features

on your motherboard. See the "Motherboard Features" pages for the actual

specifi cations of each board.

ort

ort3

ort2

ort3

ort2port

1CPU2

7.00”

System Block Diagram

1-12

Chapter 1: Overview

X10 DRG-O-PCIE System Block Diagram

Note: This is a general block diagram and may not represent the features

on your motherboard. See the "Motherboard Features" pages for the actual

specifi cations of each board.

1-13

X10DRG-O(T)+-CPU/X10DRG-O-PCIE User’s Manual

1-2 Processor and Chipset Overview

Built upon the functionality and capability of the Intel® E5-2600v3/v4 Series

processors (Socket R3) and the Intel® PCH C612, the X10DRG-O(T)+-CPU/

X10DRG-O-PCIE platform provides the best balanced solution of performance,

power effi ciency, and features to address the diverse needs of next-generation

computer users.

With support of new Intel® Microarchitecture 22nm (E5-2600v3)/14nm (E5-

2600v4) Processing Technology, the X10DRG-O(T)+-CPU/X10DRG-O-PCIE dra-

matically increases performance for a multitude of server applications.

The PCH C612 chip provides Enterprise SMbus and MCTP support with the fol-

lowing features included:

• DDR4 288-pin memory support

• Support for MCTP protocol and ME

• GSX capable of GPIO expansion

• Improved I/O capabilities to high-storage-capacity confi gurations

• SPI enhancements

• Intel® Node Manager 3.0

• BMC supports remote management, virtualization, and the security package

for enterprise platforms

Notes:

1. E5-2600v4 requires Revision 2.0 BIOS (or higher).

2. Intel® Node Manager 3.0 support depends on the power supply used

in the system.

1-14

Chapter 1: Overview

1-3 Special Features

Recovery from AC Power Loss

The Basic I/O System (BIOS) provides a setting that determines how the system will

respond when AC power is lost and then restored to the system. You can choose for

the system to remain powered off (in which case you must press the power switch

to turn it back on), or for it to automatically return to the power-on state. See the

Advanced BIOS Setup section for this setting. The default setting is Last State.

1-4 System Health Monitoring

This section describes the features of system health monitoring of the mother-

board. This motherboard has an onboard BMC chip that monitors system health.

An onboard voltage monitor will scan the following onboard voltages continuously:

+3.3V, 3.3V standby, +5V, +5V standby, +12V, CPU core, memory, BMC, chipset,

and battery voltages. Once a voltage becomes unstable, a warning is given, or an

error message is sent to the screen. The user can adjust the voltage thresholds to

defi ne the sensitivity of the voltage monitor.

Fan Status Monitor with Firmware Control

The system health monitoring support provided by the BMC controller can check

the RPM status of a cooling fan. The onboard CPU and chassis fan speeds are

controlled by IPMI interface.

Environmental Temperature Control

A thermal control sensor embedded in IPMI 2.0 monitors the CPU temperatures in

real time and will turn on the onboard cooling fans whenever the CPU temperature

exceeds a user-defi ned threshold to prevent the CPU from overheating, and it will

also send warning messages to alert the user when the chassis temperature is

too high.

Note: To avoid possible system overheating, please be sure to provide

adequate airfl ow to your system.

System Resource Alert

This feature is available when used with SuperDoctor® 5, which is used to notify

the user of certain system events. For example, you can confi gure SuperDoctor®

5 to provide you with warnings when the system temperature, CPU temperatures,

voltages, or fan speeds go beyond a predefi ned range.

1-15

X10DRG-O(T)+-CPU/X10DRG-O-PCIE User’s Manual

1-5 ACPI Features

ACPI stands for Advanced Confi guration and Power Interface. The ACPI specifi ca-

tion defi nes a fl exible and abstract hardware interface that provides a standard

way to integrate power management features throughout a PC system, including

its hardware, operating system, and application software. This enables the system

to automatically turn on and off peripherals such as CD-ROMs, network cards, hard

disk drives, and printers.

In addition to operating system-directed power management, ACPI also provides a

generic system-event mechanism for Plug and Play, and an operating system-inde-

pendent interface for confi guration control. ACPI leverages the Plug and Play BIOS

data structures, while providing a processor architecture-independent implementa-

tion that is compatible with Windows 2012/R2 and Windows 16 operating systems.

1-6 Power Supply

As with all computer products, a stable power source is necessary for proper and

reliable operation. It is even more important for processors that have high CPU

clock rates.

The X10DRG-O(T)+-CPU/X10DRG-O-PCIE motherboard accommodates four

SMCI-proprietary power connectors and ten 12V 8-pin power connectors. Although

most power supplies generally meet the specifi cations required by the CPU, some

are inadequate. To ensure adequate power supply to the system, two additional

8-pin power connections (JPW17/18) are also required for BPD HDD use. Your

power supply must also supply at least 1.5A of 12V standby power for the Ethernet

ports.

Warning: To avoid damaging the power supply or the motherboard, please use a power

supply that contains four SMCI-proprietary power connectors (JPW21-24) and twelve

8-pin power connectors (JPW3-7, JPW12-16, and JPW17/18). Be sure to connect these

power connectors to your power supply. Failure in doing so may void the manufacturer

warranty on your power supply and motherboard.

It is strongly recommended that you use a high quality power supply that meets ATX

Power Supply Specifi cation 2.02 or above. It must also be SSI-compliant. (For more

information, please refer to the website at http://www.ssiforum.org/.) Additionally, in

areas where noisy power transmission is present, you may choose to install a line

fi lter to shield the computer from noise. It is recommended that you also install a

power surge protector to help avoid problems caused by power surges.

1-16

Chapter 1: Overview

1-7 Advanced Power Management

The following new advanced power management features are supported by this

board:

Intel® Intelligent Power Node Manager (NM) (Available
when the SPM Utility is Installed)

The Intel® Intelligent Power Node Manager 3.0 (IPNM) provides your system with

real-time thermal control and power management for maximum energy effi ciency.

Although IPNM Specifi cation Version 2.0/3.0 is supported by the BMC (Baseboard

Management Controller), your system must also have IPNM-compatible Manage-

ment Engine (ME) fi rmware installed to use this feature.

Note: IPNM support depends on the power supply used in the system.

Management Engine (ME)

Management Engine, an ARC controller embedded in the PCH, provides Server

Platform Services (SPS) support to your system. The services provided by SPS are

different from those provided by the ME on client platforms.

1-17

Chapter 2: Installation

Chapter 2

Installation

2-1 Standardized Warning Statements

The following statements are industry-standard warnings provided to warn the user

of situations that possible bodily injury might occur. Should you have questions or

experience diffi culty, contact Technical Support at Supermicro for assistance. Only

certifi ed technicians should attempt to install or remove components and confi gure

system settings.

Read this section in its entirety before installing/removing components or confi guring

settings in the Supermicro system.

Battery Handling

Warning!

There is a danger of explosion if the battery is replaced incorrectly. Replace the

battery only with the same or equivalent type recommended by the manufacturer.

Dispose of used batteries according to the manufacturer's instructions.

電池の取り扱い

電池交換が正しく行われなかった場合、破裂の危険性があります。交換する電池はメー
カーが推奨する型、または同 等のものを使 用下さい。使用済電池は製造元の指示に従

って処 分して 下さい。

警告
电池更换不当会有爆炸危险。请只使用同类电池或制造商推荐的功能相当的电池更
换原有电池。请按制造商的说明处理废旧电池。

警告
電池更換不當會有爆炸危險。請使用製造商建議之相同或功能相當的電池更換原有
電池。請按照製造商的說明指示處理廢棄舊電池。

Warnung

Bei Einsetzen einer falschen Batterie besteht Explosionsgefahr. Ersetzen Sie die

Batterie nur durch den gleichen oder vom Hersteller empfohlenen Batterietyp.

Entsorgen Sie die benutzten Batterien nach den Anweisungen des Herstellers.

2-1

X10DRG-O(T)+-CPU/X10DRG-O-PCIE User’s Manual

!הרהזא

Attention

Danger d'explosion si la pile n'est pas remplacée correctement. Ne la remplacer

que par une pile de type semblable ou équivalent, recommandée par le fabricant.

Jeter les piles usagées conformément aux instructions du fabricant.

¡Advertencia!

Existe peligro de explosión si la batería se reemplaza de manera incorrecta. Re-

emplazar la batería exclusivamente con el mismo tipo o el equivalente recomen-

dado por el fabricante. Desechar las baterías gastadas según las instrucciones

del fabricante.

תנכס תמייקץוציפ .הניקת אל ךרדב הפלחוהו הדימב הללוסה לש ףילחהל שי

גוסב הללוסה תא מ םאותה תרבחלמומ ןרציתצ.

תוללוסה קוליס תושמושמה עצבל שי .ןרציה תוארוה יפל

ﺮﻄﺧ كﺎﻨھ ﻦﻣ لاﺪﺒﺘﺳا ﺔﻟﺎﺣ ﻲﻓ رﺎﺠﻔﻧا ﺔﯾرﺎﻄﺒﻟا ﺔﺤﯿﺤﺻ ﺮﯿﻏ ﺔﻘﯾﺮﻄﺑ ﻚﯿﻠﻌﻓ

ﺔﯾرﺎﻄﺒﻟا لاﺪﺒﺘﺳا

ﻂﻘﻓ عﻮﻨﻟا ﺲﻔﻨﺑ ﺎﮭﻟدﺎﻌﯾ ﺎﻣ وأ ﺎﻤﻛﺖﺻوأ ﺔﻌﻨﺼﻤﻟا ﺔﻛﺮﺸﻟا ﮫﺑ

تﺎﯾرﺎﻄﺒﻟا ﻦﻣ ﺺﻠﺨﺗ ﻟ ﺎﻘﻓو ﺔﻠﻤﻌﺘﺴﻤﻟاﺔﻌﻧﺎﺼﻟا ﺔﻛﺮﺸﻟا تﺎﻤﯿﻠﻌﺘ

경고!

배터리가 올바르게 교체되지 않으면 폭발의 위험이 있습니다. 기존 배터리와 동일
하거나 제조사에서 권장하는 동등한 종류의 배터리로만 교체해야 합니다. 제조사
의 안내에 따라 사용된 배터리를 처리하여 주십시오.

Waarschuwing

Er is ontploffi ngsgevaar indien de batterij verkeerd vervangen wordt. Vervang de

batterij slechts met hetzelfde of een equivalent type die door de fabrikant aan-

bevolen wordt. Gebruikte batterijen dienen overeenkomstig fabrieksvoorschriften

afgevoerd te worden.

2-2

Chapter 2: Installation

רצומה קוליס

Product Disposal

Warning!

Ultimate disposal of this product should be handled according to all national laws

and regulations.

製品の廃棄

この製品を廃棄処分する場合、国の関係する全ての法律・条例に従い処理する必要が

あります。

警告
本产品的废弃处理应根据所有国家的法律和规章进行。

警告
本產品的廢棄處理應根據所有國家的法律和規章進行。

Warnung

Die Entsorgung dieses Produkts sollte gemäß allen Bestimmungen und Gesetzen

des Landes erfolgen.

¡Advertencia!

Al deshacerse por completo de este producto debe seguir todas las leyes y regla-

mentos nacionales.

Attention

La mise au rebut ou le recyclage de ce produit sont généralement soumis à des

lois et/ou directives de respect de l'environnement. Renseignez-vous auprès de

l'organisme compétent.

!הרהזא

ו תויחנהל םאתהב תויהל בייח הז רצומ לש יפוס קוליס.הנידמה יקוח

2-3

X10DRG-O(T)+-CPU/X10DRG-O-PCIE User’s Manual

ﻲﺋﺎﮭﻨﻟا ﺺﻠﺨﺘﻟا ﻦﻣ ﺞﺘﻨﻤﻟا اﺬھ ﮫﻌﻣ ﻞﻣﺎﻌﺘﻟا ﻲﻐﺒﻨﯾ ﻟ ﺎﻘﻓو ﻊﯿﻤﺠﺔﯿﻨطﻮﻟا ﺢﺋاﻮﻠﻟاو ﻦﯿﻧاﻮﻘﻟا ﺪﻨﻋ

경고!

이 제품은 해당 국가의 관련 법규 및 규정에 따라 폐기되어야 합니다.

Waarschuwing

De uiteindelijke verwijdering van dit product dient te geschieden in overeenstemming

met alle nationale wetten en reglementen.

2-2 Static-Sensitive Devices

Electrostatic discharge (ESD) can damage electronic com ponents. To avoid dam-

aging your system board, it is important to handle it very carefully. The following

measures are generally suffi cient to protect your equipment from ESD.

Precautions

• Use a grounded wrist strap designed to prevent static discharge.

• Touch a grounded metal object before removing the motherboard from the

antistatic bag.

• Handle the motherboard by its edges only; do not touch its components, periph-

eral chips, memory modules or gold contacts.

• When handling chips or modules, avoid touching their pins.

• Put the motherboard and peripherals back into their antistatic bags when not

in use.

• For grounding purposes, make sure that your system chassis provides excellent

conductivity between the power supply, the case, the mounting fasteners, and

the motherboard.

Unpacking

The motherboard is shipped in antistatic packaging to avoid static damage.

When unpacking the motherboard, make sure that the person handling it is static

protected.

2-4

Chapter 2: Installation

2-3 System Board Installation

All boards have standard mounting holes to fi t different types of chassis. Make

sure that the locations of all the mounting holes for both motherboard and chassis

match. Although a chassis may have both plastic and metal mounting fasteners,

metal ones are highly recommended because they ground the motherboard to the

chassis. Make sure that the metal standoffs click in or are screwed in tightly. Then

use a screwdriver to secure the motherboard onto the motherboard tray.

Tools Needed

• Phillips Screwdriver

• Pan-head screws (14 pieces)

• Standoffs (14 pieces, if needed)

Location of Mounting Holes

There are fourteen (14) mounting holes on this motherboard as shown below.

SW1

LE1

COM1

VGA

LEDM1

JVRM1

JVRM2

BMC

JPG1

J33

J34

DESIGNED IN USA

P2 DIMMH1

JPW15

P2 DIMMH2

P2 DIMMH3

JPW16

FAN7

JPW22

USB4

S-SATA2

S-SATA1

S-SATA3

CLOSE 1st

CPU2

OPEN 1st

FAN3

JBT1

USB0/1

USB2/3

1

X10DRG-O+-CPU

S-SATA0

BIOS LICENSE

P2 DIMMF3

P2 DIMMF2

REV:

P2 DIMMF1

BAR CODE

IPMI CODE

P2 DIMME3

1.00

JPW21 JPW24JPW23

JPW3

JPW14

JPW13

S-SGPIO

+

JTPM1

JPB1

JL1

J1

JPME2

JBR1

JWD1

LE2

JSPK1

FAN4

JF1

1

FAN8

P2 DIMMG2

P2 DIMMG1

P2 DIMMG3

JF1

X

PS

UID2NIC

HDDNIC

PWR

PWR

RST

NMI

1LED

LED

FAIL LED

ON

LAN2

P2 DIMME2

PCH

1G/10G MAC CODE

10G SAN MAC

P2 DIMME1

P1 DIMMC1

LAN1

P1 DIMMC2

USB7/8(3.0)

LAN

CTRL

J32

+

P1 DIMMC3

IPMI_LAN

USB5/6(3.0)

P1 DIMMD1

P1 DIMMD2

BT1

J31

JPW10

P1 DIMMD3

I-S ATA1

I-S ATA0

I-S ATA3

I-S ATA2

I-S ATA5

I-S ATA4

CLOSE 1st

CPU1

OPEN 1st

FAN2

FAN6

JPP2

JPP1

P1 DIMMB3

JITP1

P1 DIMMB2

P1 DIMMB1

P1 DIMMA3

P1 DIMMA2

JSD1

P1 DIMMA1

FAN5

JSD2

JPW17JPW18

FAN1

I-SGPIO2

I-SGPIO1

JPL1

LD1

LD2

JPW5

JPW6

JPW12

JPW7

JPW4

Caution: 1) To avoid damaging the motherboard and its components, please do

not use a force greater than 8 lb/inch on each mounting screw when installation the

motherboard. 2) Some components are very close to the mounting holes. Please take

precautionary measures to prevent damage to these components when installing the

motherboard to the chassis.

2-5

X10DRG-O(T)+-CPU/X10DRG-O-PCIE User’s Manual

Installing the System Board

1. Install the I/O shield into the chassis.

2. Locate the mounting holes on the motherboard as shown below.

JPW21 JPW24JPW23

JPW3

JPW16

JPW14

JPW13

S-SGPIO

JPW15

+

JTPM1

JPB1

JL1

J1

JPME2

JBR1

JWD1

LE2

JSPK1

FAN4

JF1

1

FAN8

FAN7

P2 DIMMH3

P2 DIMMG3

P2 DIMMH2

P2 DIMMH1

P2 DIMMG2

P2 DIMMG1

JF1

X

PS

UID2NIC

HDDNIC

PWR

PWR

RST

NMI

1LED

LED

FAILLED

ON

SW1

LE1

COM1

JVRM1

JVRM2

BMC

JPG1

J33

DESIGNED IN USA

JPW22

USB0/1

USB2/3

1

USB4

S-SATA2

S-SATA1

S-SATA0

S-SATA3

BIOS LICENSE

CLOSE 1st

CPU2

OPEN 1st

FAN3

P2 DIMMF3

P2 DIMMF2

VGA

LEDM1

LAN2

J34

JBT1

X10DRG-O+-CPU

1.00

REV:

BAR CODE

IPMI CODE

P2 DIMME2

P2 DIMMF1

P2 DIMME3

P2 DIMME1

PCH

1G/10G MAC CODE

10G SAN MAC

P1 DIMMC1

IPMI_LAN

USB5/6(3.0)

USB7/8(3.0)

LAN1

JPW10

LAN
CTRL

J31

J32

BT1

P1 DIMMC2

P1 DIMMC3

+

P1 DIMMD1

P1 DIMMD2

P1 DIMMD3

JPW4

I-SATA1

I-SATA0

I-SATA3

I-SATA2

I-SATA5

I-SATA4

CLOSE 1st

CPU1

OPEN 1st

FAN2

FAN6

P1 DIMMB3

JPP2

JITP1

JPP1

JPW5

JPW6

JPW12

JPW7

JSD2

JSD1

I-SGPIO2

I-SGPIO1

JPL1

LD1

LD2

JPW17JPW18

P1 DIMMB2

P1 DIMMA3

P1 DIMMB1

P1 DIMMA2

P1 DIMMA1

FAN5

FAN1

3. Locate the matching mounting holes on the chassis. Align the mounting holes

on the motherboard against the mounting holes on the chassis.

4. Install standoffs in the chassis as needed.

5. Install the motherboard into the chassis carefully to avoid damaging board

components.

6. Using the Phillips screwdriver, insert a pan-head #6 screw into a mounting

hole on the motherboard and its matching mounting hole on the chassis.

7. Repeat Step 5 to insert #6 screws into all mounting holes.

8. Make sure that the motherboard is securely placed in the chassis.

Note: Images displayed are for illustration only. Your chassis or compo-

nents might look different from those shown in this manual.

2-6

Chapter 2: Installation

OPEN 1st

OPEN 1st

2-4 Processor and Heatsink Installation

Warning: When handling the processor package, avoid placing direct pressure on

the label area.

Notes:

• Always connect the power cord last, and always remove it before adding, remov-

ing, or changing any components. Make sure that you install the processor into

the CPU socket before you install the CPU heatsink.

• If you buy a CPU separately, make sure that you use an Intel-certifi ed multi-

directional heatsink only.

• Make sure to install the motherboard into the chassis before you install the

CPU heatsink.

• When receiving a motherboard without a processor pre-installed, make sure

that the plastic CPU socket cap is in place and that none of the socket pins are

bent; otherwise, contact your retailer immediately.

• Refer to the Supermicro website for updates on CPU support.

Installing the LGA2011 Processor

1. There are two load levers on the LGA2011 socket. To open the socket cover,

fi rst press and release the load lever labeled 'Open 1st'.

1

OPEN 1st

Press down

Load Lever

on

labeled 'Open 1st'.

2

OPEN 1st

Note: All graphics, drawings, and pictures shown in this manual are for

illustration only. The components that came with your system may or may

not look exactly the same as those shown in this manual.

2-7

X10DRG-O(T)+-CPU/X10DRG-O-PCIE User’s Manual

OPEN 1st

OPEN 1st

OPEN 1st

2. Press the second load lever labeled 'Close 1st' to release the load plate that

covers the CPU socket from its locking position.

Pull lever away from

2

the socket

OPEN 1st

1

Press down on

Lever 'Close 1st'

OPEN 1st

Load

3. With the lever labeled 'Close 1st' fully retracted, gently push down on the

lever labeled 'Open 1st' to open the load plate. Lift the load plate to open it

completely.

Gently push
down to pop the

1

load plate open.

2

OPEN 1st

Note: All graphics, drawings, and pictures shown in this manual are for

illustration only. The components that came with your system may or may

not look exactly the same as those shown in this manual.

2-8

Chapter 2: Installation

1. Use your thumb and the index fi nger to loosen the lever and open the load

plate.

2. Using your thumb and index fi nger, hold the CPU on its edges. Align the CPU

keys, which are semi-circle cutouts, against the socket keys.

Socket Keys

CPU Keys

3. Once they are aligned, carefully lower the CPU straight down into the socket.

(Do not drop the CPU on the socket. Do not move the CPU horizontally or

vertically. Do not rub the CPU against the surface or against any pins of the

socket to avoid damaging the CPU or the socket.)

Warning: You can only install the CPU

inside the socket in one direction. Make

sure that it is properly inserted into the

CPU socket before closing the load

plate. If it doesn't close properly, do not

force it as it may damage your CPU.

Instead, open the load plate again to

make sure that the CPU is aligned

properly.

2-9

X10DRG-O(T)+-CPU/X10DRG-O-PCIE User’s Manual

OPEN 1st

OPEN

1s

t

OPEN 1st

4. With the CPU inside the socket, inspect the four corners of the CPU to make

sure that the CPU is properly installed.

5. Close the load plate with the CPU inside the socket. Lock the lever labeled

'Close 1st' fi rst, then lock the lever labeled 'Open 1st' second. Using your

thumb gently push the load levers down to the lever locks.

Gently close

12

the load plate.

3

Push down and lock the

lever labeled 'Close 1st'.

OPEN 1st

4

Lever Lock

OPEN 1st

Push down and

lock the lever

labeled 'Open 1st'.

2-10

OPEN 1st

Lever Lock

Chapter 2: Installation

OP

EN 1st

Installing a Passive CPU Heatsink

1. Do not apply any thermal grease to the heatsink or the CPU die -- the re-

quired amount has already been applied.

2. Place the heatsink on top of the CPU so that the four mounting holes are

aligned with those on the motherboard and the heatsink bracket underneath.

3. Screw in two diagonal screws (e.g., the #1 and the #2 screws) until just snug

(Do not over-tighten the screws to avoid damaging the CPU.)

4. Finish the installation by fully tightening all four screws.

Direction of Airfl ow

Screw#1

OPEN 1st

Screw#2

Mounting Holes

Note: For optimized airfl ow, please follow the airfl ow direction of your

heatsink for proper installation. Graphics included in this manual are for

reference only. They may look different from the components installed in

your system.

2-11

X10DRG-O(T)+-CPU/X10DRG-O-PCIE User’s Manual

Removing the Heatsink

Warning: We do not recommend that the CPU or the heatsink be removed. However,

if you do need to uninstall the heatsink, please follow the instructions below to remove

the heatsink to prevent damage done to the CPU or the CPU socket.

1. Unscrew the heatsink screws from the motherboard in the sequence as

shown in the illustration below.

2. Gently wriggle the heatsink to loosen it from the CPU. (Do not use excessive

force when wriggling the heatsink!)

3. Once the CPU is loosened from the socket, remove the CPU from the CPU

socket.

4. Remove the used thermal grease and clean the surface of the CPU and the

heatsink, Reapply the proper amount of thermal grease on the surface before

reinstalling the CPU and the heatsink.

Loosen screws
in sequence as
shown.

Screw#1

Screw#4

Screw#2

Screw#3

Note: All graphics, drawings and pictures shown in this manual are for

illustration only. The components that came with your system may or may

not look exactly the same as those shown in this manual.

2-12

Chapter 2: Installation

2-5 Installing and Removing the Memory Modules

Note: Check Supermicro's website for recommended memory modules.

CAUTION

Exercise extreme care when installing or removing DIMM

modules to prevent any possible damage.

Installing Memory Modules

1. Insert the desired number of DIMMs into the memory slots, starting with

P1-DIMMA1. (For best performance, please use the memory modules of the

same type and speed in the same bank.)

2. Push the release tabs outwards on both ends of the DIMM slot to unlock it.

JPW21 JPW24JPW23

JPW3

JPW14

JPW13

S-SGPIO

JPW15

+

JTPM1

JPB1

JL1

J1

JPME2

JBR1

JWD1

LE2

JSPK1

FAN4

JF1

1

FAN8

P2 DIMMH3

P2 DIMMG3

P2 DIMMH2

P2 DIMMH1

P2 DIMMG2

P2 DIMMG1

JF1

X

PS

PWR

UID2NIC

HDDNIC

PWR

RST

NMI

FAILLED

1LED

LED

ON

SW1

LE1

JVRM1

JPG1

DESIGNED IN USA

JPW22

USB2/3

USB4

JPW16

S-SATA2

S-SATA1

S-SATA0

S-SATA3

CLOSE 1st

CPU2

OPEN 1st

FAN3

FAN7

COM1

VGA

JVRM2

J33

USB0/1

1

BIOS LICENSE

P2 DIMMF3

P2 DIMMF2

LEDM1

LAN2

BMC

J34

JBT1

X10DRG-O+-CPU

1.00

REV:

BAR CODE

IPMI CODE

P2 DIMME2

P2 DIMMF1

P2 DIMME3

IPMI_LAN
USB5/6(3.0)

USB7/8(3.0)

LAN1

JPW10

LAN

CTRL

J31

J32

PCH

BT1

+

I-SATA1

I-SATA0

I-SATA3

I-SATA2

I-SATA5

1G/10G MAC CODE

10G SAN MAC

P2 DIMME1

P1 DIMMC1

P1 DIMMC2

I-SATA4

CLOSE 1st

CPU1

OPEN 1st

P1 DIMMC3

P1 DIMMD1

FAN6

P1 DIMMD2

P1 DIMMD3

JPP2

JITP1

JPP1

JPW5

JPW6

JPW12

JPW7

JPW4

JSD2

JSD1

I-SGPIO2

I-SGPIO1

JPL1

LD1

LD2

JPW17JPW18

FAN2

P1 DIMMB3

P1 DIMMB2

P1 DIMMA3

P1 DIMMB1

P1 DIMMA2

P1 DIMMA1

FAN5

FAN1

Release Tabs

Notches

3. Align the key of the DIMM module with the receptive point on the memory

slot.

4. Align the notches on both ends of the module against the receptive points on

the ends of the slot.

5. Use two thumbs together to press the notches on both ends of the module

straight down into the slot until the module snaps into place.

6. Press the release tabs to the locking positions to secure the DIMM module

into the slot.

Press both notches straight

down into the memory slot at

the same time.

Removing Memory Modules

Press both notches on the ends of the DIMM module to unlock it. Once the DIMM

module is loosened, remove it from the memory slot.

2-13

X10DRG-O(T)+-CPU/X10DRG-O-PCIE User’s Manual

Memory Support for the X10DRG-O+-CPU/X10DRG-OT+-CPU
Board

The X10DRG-O(T)+-CPU/X10DRG-O-PCIE motherboard supports up to 3072 GB

of 288-pin Load Reduced (LRDIMM) or 768 GB or Registered (RDIMM) DDR4 ECC

2400/2133/1866/1600 MHz in 24 slots. For the latest memory updates, please refer

to our website at http://www.supermicro.com/products/motherboard.

Processor & Memory Module Population Confi guration

For memory to work properly, follow the tables below for memory installation.

Processors and their Corresponding Memory Modules

CPU# Corresponding DIMM Modules

CPU 1

P1-DIMM-

CPU2

P2-DIMM-

A1 B1 C1 D1 A2 B2 C2 D2 A3 B3 C3 D3

E1 F1 G1 H1 E2 F2 G2 H2 E3 F3 G3 H3

Populating RDIMM/LRDIMM DDR4 Memory Modules for the E5­2600v3-based Motherboard

3 Slots Per Channel

1.2V

1.2V

Ranks Per
DIMM and

Type

RDIMM SRx4 8GB 16GB

RDIMM SRx8 4GB 8GB

RDIMM DRx8 8GB 16GB

RDIMM DRx4 16GB 32GB

LRDIMM QRx4 32GB 64GB

LRDIMM

3DS

Data

Width

8Rx4 64GB 128GB

†

DIMM Capacity

4Gb 8Gb

(GB)

Slot Per Channel (SPC) and DIMM Per Channel (DPC)

1 Slot Per

Channel

1DPC 1DPC 2DPC 1DPC 2DPC 3DPC

1.2V

2133 2133 1866 2133 1866 1600

2133 2133 1866 2133 1866 1600

2133 2133 1866 2133 1866 1600

2133 2133 1866 2133 1866 1600

2133 2133 2133 2133 2133 1600

2133 2133 2133 2133 2133 1600

Speed (MT/s); Voltage (V);

2 Slots Per Channel

1.2V

1.2V

1.2V

2-14

Chapter 2: Installation

Populating RDIMM/LRDIMM DDR4 Memory Modules for the E5­2600v4-based Motherboard

Ranks Per
DIMM and

Type

RDIMM SRx4 8GB 16GB

RDIMM SRx8 4GB 8GB

RDIMM DRx8 8GB 16GB

RDIMM DRx4 16GB 32GB

LRDIMM QRx4 32GB 64GB

LRDIMM

3DS

Data

Width

8Rx4 64GB 128GB

DIMM Capacity

(GB)

4Gb 8Gb

Slot Per Channel (SPC) and DIMM Per Channel (DPC)

Speed (MT/s); Voltage (V);

3 Slots Per Channel

1DPC 2DPC 3DPC

1.2V 1.2V 1.2V

2400 2133 1600

2400 2133 1600

2400 2133 1600

2400 2133 1600

2400 2400 1866

2400 2400 1866

An Important Note:

• For the memory modules to work properly, please install DIMM modules of the

same type and speed on the motherboard. Mixing of DIMMs of different types

or different speeds is not allowed.

2-15

X10DRG-O(T)+-CPU/X10DRG-O-PCIE User’s Manual

1

2345678

9

2-6 Control Panel Connectors and I/O Ports

The I/O ports are color-coded in conformance with the industry standards. See

the picture below for the colors and locations of the various I/O ports.

Backpanel Connectors and I/O Ports

SW1

JVRM1

LE1

COM1

VGA

LEDM1

JVRM2

BMC

JPG1

IPMI_LAN

USB5/6(3.0)

USB7/8(3.0)

LAN2

LAN1

JPW10

LAN

CTRL

J33

J34

DESIGNED IN USA

JPW14

P2 DIMMH1

JPW15

P2 DIMMH2

P2 DIMMH3

JPW16

FAN7

JPW22

USB2/3

USB4

S-SATA2

S-SATA1

S-SATA0

S-SATA3

CLOSE 1st

CPU2

OPEN 1st

FAN3

1

BIOS LICENSE

P2 DIMMF3

USB0/1

P2 DIMMF2

P2 DIMMF1

PCH

JBT1

X10DRG-O+-CPU

1.00

REV:

1G/10G MAC CODE

BAR CODE

10G SAN MAC

IPMI CODE

P2 DIMME2

P2 DIMME3

P2 DIMME1

P1 DIMMC1

JPW21 JPW24JPW23

JPW3

JPW13

S-SGPIO

+

JTPM1

JPB1

JL1

J1

JPME2

JBR1

JWD1

LE2

JSPK1

FAN4

JF1

1

FAN8

P2 DIMMG2

P2 DIMMG1

P2 DIMMG3

JF1

X

PS

PWR

UID2NIC

HDDNIC

PWR

RST

NMI

FAIL LED

1 LED

LED

ON

P1 DIMMC2

J32

+

P1 DIMMC3

P1 DIMMD1

J31

BT1

P1 DIMMD2

P1 DIMMD3

I-SATA 1

I-SATA 0

I-SATA 3

I-SATA 2

I-SATA5

I-SATA 4

CLOSE 1st

CPU1

OPEN 1st

FAN2

FAN6

JPP2

JPP1

P1 DIMMB3

JITP1

P1 DIMMB2

P1 DIMMB1

P1 DIMMA3

P1 DIMMA2

JSD1

P1 DIMMA1

FAN5

JSD2

JPW17JPW18

FAN1

I-SGPIO2

I-SGPIO1

JPL1

LD1

LD2

JPW5

JPW6

JPW12

JPW7

JPW4

Backpanel I/O Port Locations and Defi nitions

1. Backpanel USB 3.0 Port 5

2. Backpanel USB 3.0 Port 6

3. IPMI_dedicated LAN

4. Backpanel USB 3.0 Port 7

5. Backpanel USB 3.0 Port 8

6. GLAN 1 (X10DRG-O+), 10G_LAN 1 (X10DRG-OT+)

7. GLAN 2 (X10DRG-O+), 10G_LAN 2 (X10DRG-OT+)

8. Backpanel VGA (Blue)

9. UID Switch/LED (on the motherboard)

2-16

Chapter 2: Installation

4

123

Video Connection

A Video (VGA) port is located next to LAN port 2 on the I/O backplane. Refer to

the system board layout below for the location.

Ethernet Ports

Two Ethernet ports (LAN1, LAN2) are

located on the I/O backplane. These

Ethernet ports support 10G LAN

connections on the X10DRG-OT+,

and Gigabit LAN connections on the

X10DRG-O+. In addition, an IPMI_

dedicated LAN that supports Gigabit

LAN is located above USB 5/6 ports

on the backplane. All Ethernet ports

accept RJ45-type cables. Please refer

to the LED indicator section for LAN

LED information.

SW1

JVRM1

LE1

JPG1

COM1

JVRM2

VGA

LEDM1

BMC

LAN2

LAN1

LAN

CTRL

IPMI_LAN

USB5/6(3.0)

USB7/8(3.0)

JPW10

LAN Ports

Pin Defi nition

Pin# Defi nition

1 P2V5SB 10 SGND

2 TD0+ 11 Act LED

3 TD0- 12 P3V3SB

4 TD1+ 13 Link 100 LED

(Yellow, +3V3SB)

5 TD1- 14 Link 1000 LED

(Yellow, +3V3SB)

6 TD2+ 15 Ground

7 TD2- 16 Ground

8 TD3+ 17 Ground

9 TD3- 18 Ground

(NC: No Connection)

DESIGNED IN USA

JPW15

P2 DIMMH2

P2 DIMMH3

JPW16

FAN7

JPW22

CPU2

USB2/3

S-SATA2

S-SATA1

S-SATA0

S-SATA3

OPEN 1st

USB4

CLOSE 1st

FAN3

JPW21 JPW24JPW23

JPW3

JPW14

JPW13

S-SGPIO

+

JTPM1

JPB1

JL1

J1

JPME2

JBR1

JWD1

LE2

JSPK1

FAN4

JF1

1

FAN8

P2 DIMMH1

P2 DIMMG2

P2 DIMMG1

P2 DIMMG3

JF1

X

PS

PWR

UID2NIC

HDDNIC

PWR

RST

NMI

FAIL LED

1LED

LED

ON

J33

USB0/1

1

X10DRG-O+-CPU

REV:

BIOS LICENSE

P2 DIMMF1

P2 DIMMF2

P2 DIMMF3

J34

JBT1

1.00

BAR CODE

IPMI CODE

P2 DIMME3

P2 DIMME2

P2 DIMME1

PCH

1G/10G MAC CODE

10G SAN MAC

P1 DIMMC1

P1 DIMMC2

J32

+

P1 DIMMC3

P1 DIMMD1

J31

BT1

P1 DIMMD2

P1 DIMMD3

1. VGA

P1 DIMMA3

JPW7

P1 DIMMA2

P1 DIMMA1

JPW5

JSD2

JSD1

I-SGPIO2

I-SGPIO1

JPL1

LD1

LD2

JPW17JPW18

FAN5

FAN1

JPW6

JPW12

JPW4

I-S ATA1

I-SATA0

I-S ATA3

I-S ATA2

I-SATA5

I-S ATA4

CLOSE 1st

CPU1

OPEN 1st

FAN2

FAN6

P1 DIMMB2

P1 DIMMB3

JPP2

JITP1

JPP1

P1 DIMMB1

2. LAN1

3. LAN2

4. IPMI_LAN

2-17

X10DRG-O(T)+-CPU/X10DRG-O-PCIE User’s Manual

5

123

4

6

7

Universal Serial Bus (USB)

Four USB 3.0 ports (USB 5/6, 7/8) are located on the I/O backpanel. In addition,

two internal USB headers provide four USB 2.0 connections (USB 0/1, 2/3) for

front panel support. A Type A USB 2.0 connector (USB 4) is also located on the

motherboard for front access. (Cables are not included.) See the tables below for

pin defi nitions.

BP USB (3.0) 5/6, 7/8

Pin Defi nitions

Pin# Description

1 VBUS

2 SSRX-

3 SSRX+

4 Ground

5 SSTX-

6 SSTX+

7 GND_DRAIN

8D-

9D+

SW1

LE1

COM1

VGA

LEDM1

LAN2

JVRM1

JVRM2

BMC

JPG1

J33

J34

DESIGNED IN USA

Front Panel (USB 2.0) 0/1, 2/3, 4

Pin Defi nitions

Pin# Defi nition Pin# Defi nition

1 +5V 5 +5V

2 USB_PN1 6 USB_PN0

3 USB_PP1 7 USB_PP0

4 Ground 8 Ground

IPMI_LAN

USB5/6(3.0)

USB7/8(3.0)

LAN1

JPW10

LAN

CTRL

1. Backpanel USB 5 (USB3.0)

2. Backpanel USB 6 (USB3.0)

3. Backpanel USB 7 (USB3.0)

4. Backpanel USB 8 (USB3.0)

5. FP USB 0/1 (USB 2.0)

J31

J32

6. FP USB 2/3 (USB 2.0)

7. Type A USB 4 (USB 2.0)

JPW14

P2 DIMMH1

JPW15

P2 DIMMH2

P2 DIMMH3

JPW16

FAN7

JPW22

USB4

S-SATA3

CLOSE 1st

CPU2

FAN3

USB0/1

USB2/3

1

S-SATA2

X10DRG-O+-CPU

S-SATA1

S-SATA0

REV:

BIOS LICENSE

OPEN 1st

P2 DIMMF1

P2 DIMMF2

P2 DIMMF3

JPW21 JPW24JPW23

JPW3

JPW13

S-SGPIO

+

JTPM1

JPB1

JL1

J1

JPME2

JBR1

JWD1

LE2

JSPK1

FAN4

JF1

1

FAN8

P2 DIMMG2

P2 DIMMG1

P2 DIMMG3

JF1

X

PS

PWR

UID2NIC

HDDNIC

PWR

RST

NMI

FAIL LED

1 LED

LED

ON

JBT1

1.00

BAR CODE

IPMI CODE

P2 DIMME3

P2 DIMME2

P2 DIMME1

PCH

1G/10G MAC CODE

10G SAN MAC

P1 DIMMC1

P1 DIMMC2

+

P1 DIMMC3

P1 DIMMD1

BT1

P1 DIMMD2

P1 DIMMD3

JPW4

I-SATA 1

I-SATA0

I-SATA 3

I-SATA 2

I-SATA 5

I-SATA 4

CLOSE 1st

CPU1

OPEN 1st

FAN2

FAN6

JPP2

JITP1

JPP1

P1 DIMMB3

P1 DIMMB2

P1 DIMMB1

P1 DIMMA3

P1 DIMMA2

JSD1

P1 DIMMA1

FAN5

JSD2

JPW17JPW18

FAN1

I-SGPIO2

I-SGPIO1

JPL1

LD1

LD2

JPW5

JPW6

JPW12

JPW7

2-18

Chapter 2: Installation

1

2

3

Unit Identifi er Switch/UID LED Indicator

A Unit Identifi er (UID) switch (SW1) and

two UID LED indicators are located on the

motherboard. The rear UID LED (LE1) is

located next to the UID switch. The front UID

LED is located on pins 7 on the front control

panel (JF1). When you press the UID switch,

both rear and front UID LED indicators will

be turned on. Press the UID switch again to

turn off the LED indicators. The UID indica-

tors provide easy identifi cation of a system

unit that may be in need of service.

Note: UID can also be triggered

via IPMI on the motherboard. For

more information on IPMI, please

refer to the IPMI User's Guide

posted on our website @ http://

www.supermicro.com.

UID LED

Status

Color/State Status

Blue: On Unit Identifi ed

SW1

LE1

COM1

VGA

LEDM1

LAN2

JVRM1

JVRM2

BMC

JPG1

J33

J34

DESIGNED IN USA

JPW14

P2 DIMMH1

JPW15

P2 DIMMH2

JPW16

P2 DIMMH3

JPW22

USB2/3

USB4

S-SATA2

S-SATA1

S-SATA0

S-SATA3

CLOSE 1st

CPU2

OPEN 1st

FAN3

FAN7

1

BIOS LICENSE

P2 DIMMF3

USB0/1

P2 DIMMF1

P2 DIMMF2

PCH

JBT1

X10DRG-O+-CPU

1.00

REV:

1G/10G MAC CODE

BAR CODE

10G SAN MAC

IPMI CODE

P2 DIMME2

P2 DIMME1

P2 DIMME3

P1 DIMMC1

JPW21 JPW24JPW23

JPW3

JPW13

S-SGPIO

+

JTPM1

JPB1

JL1

J1

JPME2

JBR1

JWD1

LE2

JSPK1

FAN4

JF1

1

FAN8

P2 DIMMG2

P2 DIMMG1

P2 DIMMG3

JF1

X

PS

PWR

UID2NIC

HDDNIC

PWR

RST

NMI

FAIL LED

1LED

LED

ON

LAN1

P1 DIMMC2

LAN

CTRL

J32

+

P1 DIMMC3

IPMI_LAN

USB5/6(3.0)

USB7/8(3.0)

BT1

P1 DIMMD1

P1 DIMMD2

J31

P1 DIMMD3

JPW10

1. Rear UID Switch

2. Rear UID LED

3. Front UID LED

1

2

Power Button

PWR

Reset Button

Reset

Power Fail LED

UID LED

NIC2 Link LED

NIC1 Link LED

JPW5

I-SGPIO2

I-SGPIO1

HDD LED

PWR LED

X

19 20

JPW6

JPW12

JPW7

JPW4

I-S ATA1

I-S ATA0

I-S ATA3

I-S ATA2

I-S ATA5

I-S ATA4

CLOSE 1st

CPU1

OPEN 1st

FAN2

FAN6

JPP2

JPP1

P1 DIMMB3

JITP1

P1 DIMMB2

P1 DIMMB1

P1 DIMMA3

P1 DIMMA2

P1 DIMMA1

JSD2

JSD1

JPL1

LD1

LD2

JPW17JPW18

FAN5

FAN1

Ground

Ground

3.3V

OH/Fan Fail LED

NIC2 Activity LED

NIC1 Activity LED

ID_UID_SW/3/3V Stby

3.3V

X

GroundNMI

2-19

X10DRG-O(T)+-CPU/X10DRG-O-PCIE User’s Manual

1

Serial Port

One COM connection (COM1) is lo-

cated on the motherboard to provide

front access support. See the table on

the right for pin defi nitions.

Serial (COM) Port

Pin Defi nitions

Pin # Defi nition Pin # Defi nition

1 DCD 6 DSR

2 RXD 7 RTS

3 TXD 8 CTS

4 DTR 9 RI

5 Ground 10 N/A

JPB1

JPME2

JBR1

JWD1

JSPK1

SW1

LE1

COM1

VGA

LEDM1

LAN2

JVRM1

JVRM2

BMC

JPG1

J33

DESIGNED IN USA

JPW15

P2 DIMMH2

P2 DIMMH3

JPW16

FAN7

CLOSE 1st

FAN3

USB4

JPW22

CPU2

USB0/1

USB2/3

1

S-SATA2

S-SATA1

S-SATA0

S-SATA3

BIOS LICENSE

OPEN 1st

P2 DIMMF2

P2 DIMMF3

JPW21 JPW24JPW23

JPW3

JPW14

JPW13

S-SGPIO

+

JTPM1

JL1

J1

LE2

FAN4

JF1

1

FAN8

JF1

PWR

RST

ON

P2 DIMMH1

P2 DIMMG2

P2 DIMMG1

P2 DIMMG3

X

PS

UID2NIC

HDDNIC

PWR

NMI

FAIL LED

1LED

LED

LAN1

J34

PCH

JBT1

X10DRG-O+-CPU

1.00

REV:

1G/10G MAC CODE

BAR CODE

10G SAN MAC

IPMI CODE

P2 DIMME2

P2 DIMMF1

P2 DIMME1

P2 DIMME3

P1 DIMMC1

LAN

CTRL

P1 DIMMC2

P1 DIMMC3

J32

+

IPMI_LAN

USB5/6(3.0)

USB7/8(3.0)

J31

BT1

P1 DIMMD1

P1 DIMMD2

JPW10

P1 DIMMD3

I-SATA0

CLOSE 1st

JPP2

JPP1

1. COM Port 1

JPW7

P1 DIMMA2

P1 DIMMA1

JSD1

FAN5

JSD2

JPW17JPW18

FAN1

JPW5

I-SGPIO2

I-SGPIO1

JPL1

LD1

LD2

I-S ATA2

CPU1

I-S ATA3

JITP1

JPW4

I-S ATA5

I-S ATA4

OPEN 1st

FAN2

FAN6

P1 DIMMB2

P1 DIMMB3

P1 DIMMB1

P1 DIMMA3

I-S ATA1

JPW6

JPW12

2-20

Chapter 2: Installation

Front Control Panel

JF1 contains header pins for various buttons and indicators that are normally located

on a control panel at the front of the chassis. These connectors are designed spe-

cifi cally for use with Supermicro's chassis. See the fi gure below for the descriptions

of the control panel buttons and LED indicators. Refer to the following section for

descriptions and pin defi nitions.

SW1

JVRM1

LE1

JPG1

COM1

JVRM2

VGA

LEDM1

LAN2

BMC

LAN1

LAN

CTRL

IPMI_LAN

USB5/6(3.0)

USB7/8(3.0)

JPW10

J33

J34

DESIGNED IN USA

JPW15

P2 DIMMH2

JPW16

P2 DIMMH3

JPW22

CPU2

USB2/3

S-SATA2

S-SATA1

S-SATA0

S-SATA3

OPEN 1st

P2 DIMMF3

USB4

CLOSE 1st

FAN3

FAN7

JBT1

USB0/1

1

X10DRG-O+-CPU

REV:

BAR CODE

BIOS LICENSE

IPMI CODE

P2 DIMMF1

P2 DIMMF2

P2 DIMME3

1.00

P2 DIMME2

PCH

1G/10G MAC CODE

10G SAN MAC

P2 DIMME1

P1 DIMMC1

JPW21 JPW24JPW23

JPW3

JPW14

JPW13

S-SGPIO

+

JTPM1

JPB1

JL1

J1

JPME2

JBR1

JWD1

LE2

JSPK1

FAN4

JF1

1

FAN8

P2 DIMMH1

P2 DIMMG2

P2 DIMMG1

P2 DIMMG3

JF1

X

PS

PWR

UID2NIC

HDDNIC

PWR

RST

NMI

FAIL LED

1 LED

LED

ON

JF1 Header Pins

1

2

PWR

Reset

Power Button

Reset Button

P1 DIMMC2

J32

+

P1 DIMMC3

P1 DIMMD1

J31

BT1

P1 DIMMD2

P1 DIMMD3

Ground

Ground

I-S ATA0

CLOSE 1st

JPP1

JPP2

JPW7

P1 DIMMA2

P1 DIMMA1

JSD1

JPW5

JSD2

I-SGPIO2

I-SGPIO1

JPL1

LD1

LD2

JPW17JPW18

FAN5

FAN1

JPW6

JPW12

CPU1

JPW4

I-S ATA3

I-S ATA2

I-S ATA5

I-S ATA4

OPEN 1st

FAN2

FAN6

P1 DIMMB2

P1 DIMMB3

P1 DIMMB1

JITP1

P1 DIMMA3

I-S ATA1

Power Fail LED

UID LED

NIC2 Link LED

NIC1 Link LED

HDD LED

PWR LED

X

3.3V

OH/Fan Fail LED

NIC2 Activity LED

NIC1 Activity LED

ID_UID_SW/3/3V Stby

3.3V

X

GroundNMI

19 20

2-21

X10DRG-O(T)+-CPU/X10DRG-O-PCIE User’s Manual

1

2

Front Control Panel Pin Defi nitions

NMI Button

The non-maskable interrupt button

header is located on pins 19 and 20

of JF1. Refer to the table on the right

for pin defi nitions.

Power LED

The Power LED connection is located

on pins 15 and 16 of JF1. Refer to the

table on the right for pin defi nitions.

NMI Button

Pin Defi nitions (JF1)

Pin# Defi nition

19 Control

20 Ground

Power LED

Pin Defi nitions (JF1)

Pin# Defi nition

15 3.3V

16 PWR LED

SW1

LE1

COM1

VGA

LEDM1

JVRM2

BMC

JPG1

J33

J34

DESIGNED IN USA

JBT1

USB0/1

1

X10DRG-O+-CPU

REV:

BAR CODE

BIOS LICENSE

IPMI CODE

P2 DIMMF3

P2 DIMMF1

P2 DIMMF2

P2 DIMME3

1.00

P2 DIMME2

LAN2

P2 DIMME1

PCH

1G/10G MAC CODE

P1 DIMMC1

10G SAN MAC

JVRM1

JPW15

P2 DIMMH2

JPW16

P2 DIMMH3

JPW22

CPU2

USB2/3

S-SATA2

S-SATA1

S-SATA0

S-SATA3

OPEN 1st

USB4

CLOSE 1st

FAN3

FAN7

JPW21 JPW24JPW23

JPW3

JPW14

JPW13

S-SGPIO

+

JTPM1

JPB1

JL1

J1

JPME2

JBR1

JWD1

LE2

JSPK1

FAN4

JF1

1

FAN8

P2 DIMMH1

P2 DIMMG2

P2 DIMMG1

P2 DIMMG3

JF1

X

PS

PWR

UID2NIC

HDDNIC

PWR

RST

NMI

FAIL LED

1 LED

LED

ON

LAN1

P1 DIMMC2

LAN

CTRL

J32

+

P1 DIMMC3

IPMI_LAN

USB5/6(3.0)

USB7/8(3.0)

J31

BT1

P1 DIMMD1

P1 DIMMD2

JPW10

P1 DIMMD3

I-S ATA0

CLOSE 1st

JPP1

JPP2

1

2

PWR

Reset

Power Button

Reset Button

Power Fail LED

UID LED

NIC2 Link LED

NIC1 Link LED

HDD LED

PWR LED

X

Ground

Ground

3.3V

OH/Fan Fail LED

NIC2 Activity LED

NIC1 Activity LED

ID_UID_SW/3/3V Stby

3.3V

X

GroundNMI

19 20

JPW7

JSD1

JSD2

JPW5

I-SGPIO2

I-SGPIO1

JPL1

1. NMI

JPW6

JPW12

I-SATA1

JPW4

I-S ATA3

I-S ATA2

I-S ATA5

I-SATA4

2. PWR LED

CPU1

JITP1

OPEN 1st

FAN2

FAN6

P1 DIMMB2

P1 DIMMB3

P1 DIMMB1

P1 DIMMA3

P1 DIMMA2

P1 DIMMA1

LD1

LD2

JPW17JPW18

FAN5

FAN1

2-22

Chapter 2: Installation

1

2

3

HDD/UID LED

The HDD LED connection is located

on pins 13 and 14 of JF1. Attach a

cable here to indicate HDD activity

and UID status. See the table on the

right for pin defi nitions.

NIC1/NIC2 LED Indicators

The NIC (Network Interface Control-

ler) LED connection for LAN Port 1

is located on pins 11 and 12 of JF1,

and for LAN Port 2 is on pins 9 and

10. Attach the NIC LED cables here to

display network activity. Refer to the

table on the right for pin defi nitions.

HDD LED

Pin Defi nitions (JF1)

Pin# Defi nition

13 UID LED

14 HD Active

GLAN1/2 LED

Pin Defi nitions (JF1)

Pin# Defi nition

9 NIC 2 Activity LED

10 NIC 2 Link LED

11 NIC 1 Activity LED

12 NIC 1 Link LED

SW1

LE1

COM1

VGA

LEDM1

LAN2

BMC

J33

J34

JBT1

USB0/1

X10DRG-O+-CPU

1.00

REV:

BAR CODE

IPMI CODE

P2 DIMME2

P2 DIMMF1

P2 DIMMF2

P2 DIMME3

PCH

P2 DIMME1

LAN1

1G/10G MAC CODE

10G SAN MAC

P1 DIMMC1

JVRM1

JVRM2

JPG1

DESIGNED IN USA

JPW15

P2 DIMMH2

JPW16

P2 DIMMH3

JPW22

USB2/3

USB4

S-SATA3

CLOSE 1st

CPU2

FAN3

FAN7

1

S-SATA2

S-SATA1

S-SATA0

BIOS LICENSE

OPEN 1st

P2 DIMMF3

JPW21 JPW24JPW23

JPW3

JPW14

JPW13

S-SGPIO

+

JTPM1

JPB1

JL1

J1

JPME2

JBR1

JWD1

LE2

JSPK1

FAN4

JF1

1

FAN8

P2 DIMMH1

P2 DIMMG2

P2 DIMMG1

P2 DIMMG3

JF1

X

PS

UID2NIC

HDDNIC

PWR

PWR

RST

NMI

1 LED

LED

FAIL LED

ON

CTRL

P1 DIMMC2

P1 DIMMC3

USB7/8(3.0)

LAN

J32

+

P1 DIMMD1

IPMI_LAN

USB5/6(3.0)

J31

BT1

P1 DIMMD3

P1 DIMMD2

JPW10

I-S ATA0

CLOSE 1st

JPP1

JPP2

1

2

PWR

Reset

Power Button

Reset Button

Power Fail LED

UID LED

NIC2 Link LED

NIC1 Link LED

HDD LED

PWR LED

X

Ground

Ground

3.3V

OH/Fan Fail LED

NIC2 Activity LED

NIC1 Activity LED

ID_UID_SW/3/3V Stby

3.3V

X

GroundNMI

19 20

JPW7

JSD1

JSD2

JPW5

I-SGPIO2

I-SGPIO1

JPL1

1. HDD/UID LED

JPW6

JPW12

I-S ATA1

JPW4

I-S ATA3

I-S ATA2

I-S ATA5

I-SATA4

2. NIC1 LED

CPU1

JITP1

LD1

OPEN 1st

FAN2

FAN6

P1 DIMMB3

P1 DIMMB2

P1 DIMMB1

P1 DIMMA3

P1 DIMMA2

P1 DIMMA1

FAN5

LD2

JPW17JPW18

FAN1

3. NIC2 LED

2-23

X10DRG-O(T)+-CPU/X10DRG-O-PCIE User’s Manual

1

2

3

Overheat (OH)/Fan Fail/UID LED

Connect an LED cable to pins 7 and 8

of JF1 to use the UID LED and Over-

heat/Fan Fail LED connections. The

red LED on pin 8 provides warnings

of overheating, fan failure, or power

failure. The blue LED on pin 7 works

as the front panel UID LED indicator.

Refer to the tables on the right for pin

defi nitions.

Power Fail LED

The Power Fail LED connection is

located on pins 5 and 6 of JF1. Re-

fer to the table on the right for pin

defi nitions.

OH/Fan Fail/ PWR Fail/Blue_UID

LED Pin Defi nitions (JF1)

Pin# Defi nition

7 Blue_UID LED

8 OH/Fan Fail/Power Fail

OH/Fan Fail/PWR Fail

LED Status (Red LED)

State Defi nition

Off Normal

On Overheat

Flashing Fan Fail

PWR Fail LED

Pin Defi nitions (JF1)

Pin# Defi nition

5 3.3V

6 PWR Supply Fail

SW1

LE1

COM1

VGA

LEDM1

JVRM2

BMC

JPG1

J33

DESIGNED IN USA

JBT1

USB0/1

1

X10DRG-O+-CPU

REV:

BAR CODE

BIOS LICENSE

IPMI CODE

P2 DIMMF1

P2 DIMMF2

P2 DIMMF3

P2 DIMME3

J34

1.00

P2 DIMME2

LAN2

PCH

1G/10G MAC CODE

10G SAN MAC

P2 DIMME1

P1 DIMMC1

JVRM1

JPW15

P2 DIMMH2

P2 DIMMH3

JPW16

FAN7

JPW22

CPU2

USB2/3

S-SATA2

S-SATA1

S-SATA0

S-SATA3

OPEN 1st

USB4

CLOSE 1st

FAN3

JPW21 JPW24JPW23

JPW3

JPW14

JPW13

S-SGPIO

+

JTPM1

JPB1

JL1

J1

JPME2

JBR1

JWD1

LE2

JSPK1

FAN4

JF1

1

FAN8

P2 DIMMH1

P2 DIMMG2

P2 DIMMG1

P2 DIMMG3

JF1

X

PS

PWR

UID2NIC

HDDNIC

PWR

RST

NMI

FAIL LED

1 LED

LED

ON

LAN1

P1 DIMMC2

LAN

CTRL

J32

+

P1 DIMMC3

IPMI_LAN

USB5/6(3.0)

USB7/8(3.0)

J31

BT1

P1 DIMMD1

P1 DIMMD2

JPW10

P1 DIMMD3

I-SATA0

CLOSE 1st

JPP1

JPP2

1

2

PWR

Reset

Power Button

Reset Button

Power Fail LED

UID LED

NIC2 Link LED

NIC1 Link LED

HDD LED

PWR LED

X

Ground

Ground

3.3V

OH/Fan Fail LED

NIC2 Activity LED

NIC1 Activity LED

ID_UID_SW/3/3V Stby

3.3V

X

GroundNMI

19 20

JPW5

JPW6

JPW12

I-S ATA1

JPW4

I-S ATA3

I-S ATA2

I-S ATA5

I-S ATA4

JPW7

JSD1

JSD2

1. UID LED

I-SGPIO2

I-SGPIO1

2. OH/Fail/PWR Fail LED

JPL1

3. PWR Supply Fail

CPU1

JITP1

OPEN 1st

FAN2

FAN6

P1 DIMMB2

P1 DIMMB3

P1 DIMMB1

P1 DIMMA3

P1 DIMMA2

P1 DIMMA1

LD1

LD2

JPW17JPW18

FAN1

FAN5

2-24

Chapter 2: Installation

1

2

Reset Button

The Reset Button connection is located on pins

3 and 4 of JF1. Attach it to a hardware reset

switch on the computer case. Refer to the table

on the right for pin defi nitions.

Power Button

The Power Button connection is located on pins

1 and 2 of JF1. Momentarily contacting both pins

will power on/off the system. This button can also

be confi gured to function as a suspend button

(with a setting in the BIOS - See Chapter 4). To

turn off the power when the system is in suspend

mode, press the button for 4 seconds or longer.

Refer to the table on the right for pin defi nitions.

Reset Button

Pin Defi nitions (JF1)

Pin# Defi nition

3 Reset

4 Ground

Power Button

Pin Defi nitions (JF1)

Pin# Defi nition

1 Signal

2 Ground

SW1

LE1

COM1

VGA

LEDM1

JVRM2

BMC

JPG1

J33

J34

DESIGNED IN USA

JBT1

USB0/1

1

X10DRG-O+-CPU

REV:

BAR CODE

BIOS LICENSE

IPMI CODE

P2 DIMMF1

P2 DIMMF2

P2 DIMMF3

P2 DIMME3

LAN2

1.00

P2 DIMME2

PCH

1G/10G MAC CODE

10G SAN MAC

P2 DIMME1

P1 DIMMC1

JVRM1

JPW15

P2 DIMMH2

P2 DIMMH3

JPW16

FAN7

JPW22

CPU2

USB2/3

S-SATA2

S-SATA1

S-SATA0

S-SATA3

OPEN 1st

USB4

CLOSE 1st

FAN3

JPW21 JPW24JPW23

JPW3

JPW14

JPW13

S-SGPIO

+

JTPM1

JPB1

JL1

J1

JPME2

JBR1

JWD1

LE2

JSPK1

FAN4

JF1

1

FAN8

P2 DIMMH1

P2 DIMMG2

P2 DIMMG1

P2 DIMMG3

JF1

X

PS

PWR

UID2NIC

HDDNIC

PWR

RST

NMI

FAIL LED

1 LED

LED

ON

LAN1

P1 DIMMC2

USB7/8(3.0)

LAN

CTRL

J32

+

P1 DIMMC3

IPMI_LAN

USB5/6(3.0)

BT1

P1 DIMMD1

P1 DIMMD2

J31

P1 DIMMD3

JPW10

I-SATA0

CLOSE 1st

JPP2

JPP1

1

2

PWR

Reset

Power Button

Reset Button

Power Fail LED

UID LED

NIC2 Link LED

NIC1 Link LED

HDD LED

PWR LED

X

Ground

Ground

3.3V

OH/Fan Fail LED

NIC2 Activity LED

NIC1 Activity LED

ID_UID_SW/3/3V Stby

3.3V

X

GroundNMI

19 20

1. Reset Button

2. PWR Button

P1 DIMMA3

JPW7

P1 DIMMA2

P1 DIMMA1

JSD1

JPW5

JSD2

I-SGPIO2

I-SGPIO1

JPL1

LD1

LD2

JPW17JPW18

FAN1

FAN5

I-S ATA2

CPU1

JITP1

JPW4

I-S ATA3

I-S ATA5

I-S ATA4

OPEN 1st

FAN2

FAN6

P1 DIMMB2

P1 DIMMB3

P1 DIMMB1

I-S ATA1

JPW6

JPW12

2-25

X10DRG-O(T)+-CPU/X10DRG-O-PCIE User’s Manual

9

5

1

2

3

4

6

7

8

2-7 Connecting Cables

Power Connectors

Four SMCI-proprietary power connectors (JPW21-

JPW24), ten 8-pin connectors (JPW3-7, JPW12-

16), and two white 8-pin power connectors

(JPW17/18) are located on the motherboard. These

power connectors meet the SSI EPS 12V specifi ca-

tion and must be connected to your power supply

to provide adequate power to the system. See the

tables on the right for pin defi nitions.

Note: JPW17/18 are reserved for BPD

HDD use only.

SW1

LE1

COM1

VGA

LEDM1

JVRM2

BMC

JPG1

J33

J34

DESIGNED IN USA

JBT1

USB0/1

1

X10DRG-O+-CPU

REV:

BAR CODE

BIOS LICENSE

IPMI CODE

P2 DIMMF1

P2 DIMMF2

P2 DIMMF3

P2 DIMME3

LAN2

1.00

P2 DIMME2

JVRM1

13

JPW15

P2 DIMMH2

14

JPW16

P2 DIMMH3

JPW22

CPU2

USB2/3

S-SATA2

S-SATA1

S-SATA0

S-SATA3

OPEN 1st

USB4

CLOSE 1st

FAN3

FAN7

JPW21 JPW24JPW23

12

11

JPW3

JPW14

JPW13

S-SGPIO

+

JTPM1

JPB1

JL1

J1

JPME2

JBR1

JWD1

LE2

JSPK1

FAN4

JF1

1

FAN8

P2 DIMMH1

P2 DIMMG2

P2 DIMMG1

P2 DIMMG3

JF1

X

PS

PWR

UID2NIC

HDDNIC

PWR

RST

NMI

FAIL LED

1LED

LED

ON

PCH

1G/10G MAC CODE

10G SAN MAC

P2 DIMME1

P1 DIMMC1

LAN1

P1 DIMMC2

USB7/8(3.0)

LAN

CTRL

J32

+

P1 DIMMC3

P1 DIMMD1

IPMI_LAN

USB5/6(3.0)

J31

BT1

P1 DIMMD2

P1 DIMMD3

JPW10

I-S ATA0

CLOSE 1st

JPP1

JPP2

I-SATA2

CPU1

JITP1

JPW4

I-SATA3

I-S ATA5

I-S ATA4

OPEN 1st

FAN2

FAN6

I-S ATA1

10

JPW12

P1 DIMMB2

P1 DIMMB3

JPW6

P1 DIMMB1

P1 DIMMA2

P1 DIMMA3

12V 8-pin Power Connector

Pin Defi nitions

Pins Defi nition

1 through 3 +12V

4 through 8 Ground

(Required)

1. JPW21: SMCI-proprietary

PWR(Req'd)

2. JPW22: SMCI-proprietary

PWR(Req'd)

3. JPW23: SMCI-proprietary

PWR(Req'd)

4. JPW24: SMCI-proprietary

PWR(Req'd)

5. JPW3: 8-pin PWR (Req'd)

6. JPW4: 8-pin PWR (Req'd)

7. JPW5: 8-pin PWR (Req'd)

8. JPW6: 8-pin PWR (Req'd)

9. JPW7: 8-pin PWR (Req'd)

10. JPW12: 8-pin PWR (Req'd)

11. JPW13: 8-pin PWR (Req'd)

12. JPW14: 8-pin PWR (Req'd)

13. JPW15: 8-pin PWR (Req'd)

14. JPW16: 8-pin PWR (Req'd)

15. JPW17: 8-pin PWR (for BPD

HDD use) (Req'd)

16. JPW18: 8-pin PWR (for BPD

HDD use) (Req'd)

JPW5

JPW7

JSD2

JSD1

I-SGPIO2

I-SGPIO1

JPL1

LD1

LD2

16

JPW17JPW18

P1 DIMMA1

15

FAN5

FAN1

2-26

Chapter 2: Installation

5

1

2

3

4

6

7

8

Fan Headers

This motherboard has eight system/CPU fan

headers (Fan 1 - Fan 8) on the motherboard. All

these 4-pin fans headers are backward compat-

ible with the traditional 3-pin fans. However, fan

speed control is available for 4-pin fans only. The

fan speeds are controlled by thermal management

via IPMI 2.0 interface. See the table on the right

for pin defi nitions.

Fan Header

Pin Defi nitions

Pin# Defi nition

1 Ground

2 +12V

3 Tachometer

4 PWR Modulation

SW1

LE1

COM1

VGA

LEDM1

LAN2

JVRM1

JVRM2

BMC

JPG1

J33

J34

DESIGNED IN USA

JPW14

P2 DIMMH1

JPW15

P2 DIMMH2

P2 DIMMH3

JPW16

FAN7

JPW22

USB2/3

USB4

S-SATA2

S-SATA1

S-SATA0

S-SATA3

CLOSE 1st

CPU2

OPEN 1st

FAN3

USB0/1

1

X10DRG-O+-CPU

REV:

BIOS LICENSE

P2 DIMMF1

P2 DIMMF2

P2 DIMMF3

JBT1

1.00

BAR CODE

IPMI CODE

P2 DIMME3

P2 DIMME2

PCH

P2 DIMME1

1G/10G MAC CODE

10G SAN MAC

P1 DIMMC1

JPW21 JPW24JPW23

JPW3

JPW13

S-SGPIO

+

JTPM1

JPB1

JL1

J1

JPME2

JBR1

JWD1

LE2

JSPK1

FAN4

JF1

1

FAN8

P2 DIMMG2

P2 DIMMG1

P2 DIMMG3

JF1

X

PS

PWR

UID2NIC

HDDNIC

PWR

RST

NMI

FAIL LED

1 LED

LED

ON

LAN1

P1 DIMMC2

LAN

CTRL

J32

+

P1 DIMMC3

IPMI_LAN

USB5/6(3.0)

USB7/8(3.0)

J31

BT1

P1 DIMMD1

P1 DIMMD2

P1 DIMMD3

JPW10

1. Fan 1

2. Fan 2

3. Fan 3

4. Fan 4

5. Fan 5

6. Fan 6

7. Fan 7

8 Fan 8

JPW5

JPW6

JPW12

JPW7

JPW4

I-S ATA1

I-SATA0

I-SATA3

I-SATA2

I-S ATA5

I-S ATA4

CLOSE 1st

CPU1

OPEN 1st

FAN2

FAN6

JPP2

JPP1

P1 DIMMB3

JITP1

P1 DIMMB2

P1 DIMMB1

P1 DIMMA3

P1 DIMMA2

JSD1

P1 DIMMA1

FAN5

JSD2

JPW17JPW18

FAN1

I-SGPIO2

I-SGPIO1

JPL1

LD1

LD2

2-27

X10DRG-O(T)+-CPU/X10DRG-O-PCIE User’s Manual

1

2

Internal Speaker

The internal speaker (SP1) provides

audible indications for various beep

codes. See the table on the right for

pin defi nitions. Refer to the layout

below for the location of the internal

buzzer.

TPM/Port 80 Header

A Trusted Platform Module/Port 80

header, located at JTPM1, provides

TPM support and Port 80 connection.

Use this header to enhance system

performance and data security. See

the table on the right for pin defi nitions.

Internal Buzzer

Pin Defi nition

Pin# Defi nitions

Pin 1 Pos. (+) Beep In

Pin 2 Neg. (-) Alarm Speaker

TPM/Port 80 Header

Pin Defi nitions

Pin# Defi nition Pin# Defi nition

1 LCLK 2 GND

3 LFRAME# 4 <(KEY)>

5 LRESET# 6 +5V (X)

7 LAD 3 8 LAD 2

9 +3.3V 10 LAD1

11 LAD0 12 GND

13 SMB_CLK4 14 SMB_DAT4

15 +3V_DUAL 16 SERIRQ

17 GND 18 CLKRUN# (X)

19 LPCPD# 20 LDRQ# (X)

SW1

LE1

COM1

VGA

LEDM1

JVRM2

BMC

JPG1

J33

J34

DESIGNED IN USA

JBT1

USB0/1

1

X10DRG-O+-CPU

REV:

BAR CODE

BIOS LICENSE

IPMI CODE

P2 DIMMF3

P2 DIMMF1

P2 DIMMF2

P2 DIMME3

LAN2

1.00

P2 DIMME2

PCH

1G/10G MAC CODE

10G SAN MAC

P2 DIMME1

P1 DIMMC1

JVRM1

JPW15

P2 DIMMH2

JPW16

FAN7

P2 DIMMH3

CLOSE 1st

FAN3

USB4

JPW22

CPU2

USB2/3

S-SATA2

S-SATA1

S-SATA0

S-SATA3

OPEN 1st

JPW21 JPW24JPW23

JPW3

JPW14

JPW13

S-SGPIO

+

JTPM1

JPB1

JL1

J1

JPME2

JBR1

JWD1

LE2

JSPK1

FAN4

JF1

1

FAN8

P2 DIMMG3

P2 DIMMH1

P2 DIMMG2

P2 DIMMG1

JF1

X

PS

PWR

UID2NIC

HDDNIC

PWR

RST

NMI

FAIL LED

1 LED

LED

ON

LAN1

P1 DIMMC2

USB7/8(3.0)

LAN

CTRL

J32

+

P1 DIMMC3

P1 DIMMD1

IPMI_LAN

USB5/6(3.0)

J31

BT1

P1 DIMMD2

P1 DIMMD3

JPW10

I-S ATA0

CLOSE 1st

JPP2

JPP1

1. Internal Speaker

(Buzzer)

2. TPM/80 Port

JPW7

P1 DIMMA2

P1 DIMMA1

JSD1

JPW5

JSD2

I-SGPIO2

I-SGPIO1

JPL1

LD1

LD2

JPW17JPW18

FAN5

FAN1

I-S ATA2

CPU1

JITP1

JPW4

I-S ATA3

I-S ATA5

I-S ATA4

OPEN 1st

FAN2

FAN6

P1 DIMMB2

P1 DIMMB3

P1 DIMMB1

P1 DIMMA3

I-S ATA1

JPW6

JPW12

2-28

Chapter 2: Installation

123

4

I-SGPIO1/2 & S-SGPIO Headers

Three SGPIO (Serial Link General Purpose

Input/Output) headers are located on the sys-

tem board. I-SGPIO1 supports I-SATA 0-3,

I-SGPIO2 supports I-SATA 4/5. S-SGPIO is

used for S-SATA 0-3. See the table on the

right for pin defi nitions.

Chassis Intrusion

A Chassis Intrusion header is located at JL1

on the motherboard. Attach an appropri-

ate cable from the chassis to inform you

of a chassis intrusion when the chassis is

opened.

I-SGPIO1/2 & S-SGPIO Headers

Pin Defi nitions

Pin# Defi nition Pin# Defi nition

1NC 2NC

3 Ground 4 Data

5 Load 6 Ground

7 Clock 8 NC

Note: NC= No Connection

Chassis Intrusion

Pin Defi nitions

Pin# Defi nition

1 Intrusion Input

2 Ground

SW1

LE1

COM1

VGA

LEDM1

JVRM2

BMC

JPG1

J33

DESIGNED IN USA

USB0/1

1

X10DRG-O+-CPU

REV:

BAR CODE

BIOS LICENSE

IPMI CODE

P2 DIMMF1

P2 DIMMF2

P2 DIMMF3

P2 DIMME3

J34

JBT1

1.00

P2 DIMME2

LAN2

PCH

P2 DIMME1

1G/10G MAC CODE

10G SAN MAC

P1 DIMMC1

JVRM1

JPW15

P2 DIMMH2

JPW16

P2 DIMMH3

JPW22

CPU2

USB2/3

S-SATA2

S-SATA1

S-SATA0

S-SATA3

OPEN 1st

USB4

CLOSE 1st

FAN3

FAN7

JPW21 JPW24JPW23

JPW3

JPW14

JPW13

S-SGPIO

+

JTPM1

JPB1

JL1

J1

JPME2

JBR1

JWD1

LE2

JSPK1

FAN4

JF1

1

FAN8

P2 DIMMH1

P2 DIMMG2

P2 DIMMG1

P2 DIMMG3

JF1

X

PS

PWR

UID2NIC

HDDNIC

PWR

RST

NMI

FAIL LED

1 LED

LED

ON

LAN1

P1 DIMMC2

LAN

CTRL

J32

+

P1 DIMMC3

IPMI_LAN

USB5/6(3.0)

USB7/8(3.0)

J31

BT1

P1 DIMMD1

P1 DIMMD2

JPW10

P1 DIMMD3

1. I-SGPIO1 (for I-SATA0-3)

2. I-SGPIO2 (for I-SATA4/5)

3. S-SGPIO (for S-SATA0-3)

4. Chassis Intrusion

JPW7

P1 DIMMA2

P1 DIMMA1

JSD1

JPW5

JSD2

I-SGPIO2

I-SGPIO1

JPL1

LD1

LD2

JPW17JPW18

FAN5

FAN1

I-SATA2

CPU1

JITP1

JPW4

I-SATA3

I-SATA5

I-S ATA4

OPEN 1st

FAN2

FAN6

P1 DIMMB2

P1 DIMMB3

P1 DIMMA3

P1 DIMMB1

I-S ATA1

I-S ATA0

CLOSE 1st

JPP2

JPP1

JPW6

JPW12

2-29

X10DRG-O(T)+-CPU/X10DRG-O-PCIE User’s Manual

1

2

SATA DOM Power Connectors

Two power connectors for SATA DOM

(Disk_On_Module) devices are located

at JSD1/JSD2. Connect appropriate

cables here to provide power support

for your SATA DOM devices.

SATA DOM PWR

Pin Defi nitions

Pin# Defi nition

1 +5V

2 Ground

3 Ground

JPB1

JPME2

JBR1

JWD1

JSPK1

SW1

LE1

COM1

VGA

LEDM1

LAN2

BMC

J34

JBT1

X10DRG-O+-CPU

1.00

REV:

BAR CODE

IPMI CODE

P2 DIMME2

P2 DIMMF1

P2 DIMME3

P2 DIMME1

PCH

1G/10G MAC CODE

10G SAN MAC

P1 DIMMC1

LAN1

P1 DIMMC2

LAN

CTRL

J32

+

P1 DIMMC3

JVRM1

JVRM2

JPG1

J33

DESIGNED IN USA

JPW15

P2 DIMMH2

P2 DIMMH3

JPW16

FAN7

CLOSE 1st

FAN3

USB4

JPW22

CPU2

USB0/1

USB2/3

1

S-SATA2

S-SATA1

S-SATA0

S-SATA3

BIOS LICENSE

OPEN 1st

P2 DIMMF3

P2 DIMMF2

JPW21 JPW24JPW23

JPW3

JPW14

JPW13

S-SGPIO

+

JTPM1

JL1

J1

LE2

FAN4

JF1

1

FAN8

JF1

PWR
ON

P2 DIMMH1

P2 DIMMG2

P2 DIMMG1

P2 DIMMG3

X

PS

UID2NIC

HDDNIC

PWR

RST

NMI

1 LED

LED

FAIL LED

IPMI_LAN

USB5/6(3.0)

USB7/8(3.0)

J31

BT1

P1 DIMMD1

P1 DIMMD2

P1 DIMMD3

JPW10

I-S ATA0

CLOSE 1st

JPP1

JPP2

1. JSD1

2. JSD2

JPW7

P1 DIMMA2

JSD2

JSD1

P1 DIMMA1

FAN5

LD1

LD2

JPW17JPW18

FAN1

JPL1

JPW5

I-SGPIO2

I-SGPIO1

I-SATA2

CPU1

I-SATA3

JITP1

JPW4

I-S ATA5

I-SATA4

OPEN 1st

FAN2

FAN6

P1 DIMMB2

P1 DIMMB3

P1 DIMMB1

P1 DIMMA3

I-S ATA1

JPW6

JPW12

2-30

2-8 Jumper Settings

Connector

Pins

Jumper

Cap

Setting

1

Chapter 2: Installation

Explanation of Jumpers

To modify the operation of the motherboard,

jumpers can be used to choose between

optional settings. Jumpers create shorts be-

tween two pins to change the function of the

connector. Pin 1 is identifi ed with a square

solder pad on the printed circuit board. See

the board layout pages for jumper locations.

Note: On two-pin jumpers,

"Closed" means the jumper is on

and "Open" means the jumper is

off the pins.

LAN Enable/Disable

JPL1 enables or disables Gigabit_LAN

ports 1/2 on the X10DRG-O+ and 10G_

LAN on the X10DRG-OT+. See the table

on the right for jumper settings. The default

setting is Enabled.

3 2 1

3 2 1

Pin 1-2 short

LAN Enable

Jumper Settings

Pin# Defi nition

1-2 Enabled (default)

2-3 Disabled

SW1

LE1

COM1

VGA

LEDM1

JVRM2

BMC

JPG1

J33

J34

DESIGNED IN USA

JBT1

USB0/1

1

X10DRG-O+-CPU

REV:

BAR CODE

BIOS LICENSE

IPMI CODE

P2 DIMMF1

P2 DIMMF2

P2 DIMMF3

P2 DIMME3

LAN2

1.00

P2 DIMME2

PCH

P2 DIMME1

1G/10G MAC CODE

10G SAN MAC

P1 DIMMC1

JVRM1

JPW15

P2 DIMMH2

JPW16

P2 DIMMH3

JPW22

CPU2

USB2/3

S-SATA2

S-SATA1

S-SATA0

S-SATA3

OPEN 1st

USB4

CLOSE 1st

FAN3

FAN7

JPW21 JPW24JPW23

JPW3

JPW14

JPW13

S-SGPIO

+

JTPM1

JPB1

JL1

J1

JPME2

JBR1

JWD1

LE2

JSPK1

FAN4

JF1

1

FAN8

P2 DIMMH1

P2 DIMMG2

P2 DIMMG1

P2 DIMMG3

JF1

X

PS

UID2NIC

HDDNIC

PWR

PWR

RST

NMI

1 LED

LED

FAIL LED

ON

LAN1

P1 DIMMC2

LAN

CTRL

J32

+

P1 DIMMC3

IPMI_LAN

USB5/6(3.0)

USB7/8(3.0)

J31

BT1

P1 DIMMD1

P1 DIMMD2

JPW10

P1 DIMMD3

1. GLAN1/2 Enable

(X10DRG-O+)

1. GLAN1/2 Enable

(X10DRG-OT+)

JPW7

P1 DIMMA2

P1 DIMMA1

JSD1

JPW5

JSD2

I-SGPIO2

I-SGPIO1

JPL1

LD1

LD2

JPW17JPW18

FAN5

FAN1

I-SATA2

CPU1

JITP1

JPW4

I-SATA3

I-SATA5

I-S ATA4

OPEN 1st

FAN2

FAN6

P1 DIMMB2

P1 DIMMB3

P1 DIMMB1

P1 DIMMA3

I-S ATA1

I-S ATA0

CLOSE 1st

JPP2

JPP1

JPW6

JPW12

2-31

X10DRG-O(T)+-CPU/X10DRG-O-PCIE User’s Manual

1

2

CMOS Clear

JBT1 is used to clear the CMOS. Instead of pins, this "jumper" consists of contact

pads to prevent accidental clearing of the CMOS. To clear the CMOS, use a metal

object such as a small screwdriver to touch both pads at the same time to short

the connection.

Note 1: For an ATX power supply, you must completely shut down the

system, and then short JBT1 to clear the CMOS.

Note 2: Clearing the CMOS will also clear all passwords.

Watch Dog Enable/Disable

Watch Dog (JWD1) is a system monitor that will

reboot the system when a software application

hangs. Close pins 1-2 to reset the system if an

application hangs. Close pins 2-3 to generate a

non-maskable interrupt signal for the application

that hangs. See the table on the right for jumper

settings. Watch Dog must also be enabled in the

BIOS.

SW1

LE1

COM1

VGA

JVRM1

JVRM2

BMC

JPG1

J33

DESIGNED IN USA

LEDM1

J34

LAN2

LAN1

LAN

CTRL

J32

IPMI_LAN

USB5/6(3.0)

USB7/8(3.0)

J31

JPW10

Watch Dog

Jumper Settings

Pin# Defi nition

1-2 Reset (default)

2-3 NMI

Open Disabled

1. Clear CMOS

2. Watch Dog Enable

JPW15

P2 DIMMH2

JPW16

FAN7

P2 DIMMH3

JPW22

CPU2

USB2/3

S-SATA2

S-SATA1

S-SATA0

S-SATA3

OPEN 1st

P2 DIMMF3

USB4

CLOSE 1st

FAN3

JPW21 JPW24JPW23

JPW3

JPW14

JPW13

S-SGPIO

+

JTPM1

JPB1

JL1

J1

JPME2

JBR1

JWD1

LE2

JSPK1

FAN4

JF1

1

FAN8

P2 DIMMG3

P2 DIMMH1

P2 DIMMG2

P2 DIMMG1

JF1

X

PS

PWR

UID2NIC

HDDNIC

PWR

RST

NMI

FAIL LED

1 LED

LED

ON

JBT1

USB0/1

1

X10DRG-O+-CPU

REV:

BAR CODE

BIOS LICENSE

IPMI CODE

P2 DIMMF1

P2 DIMMF2

P2 DIMME3

1.00

P2 DIMME2

PCH

1G/10G MAC CODE

10G SAN MAC

P2 DIMME1

P1 DIMMC1

P1 DIMMC2

P1 DIMMC3

+

P1 DIMMD1

P1 DIMMD2

BT1

P1 DIMMD3

I-S ATA0

CLOSE 1st

JPP2

JPP1

I-S ATA1

I-SATA3

I-SATA2

CPU1

JITP1

2-32

P1 DIMMA3

P1 DIMMA2

JPW7

P1 DIMMA1

JSD1

JPW5

JSD2

I-SGPIO2

I-SGPIO1

JPL1

LD1

LD2

JPW17JPW18

FAN5

FAN1

JPW6

JPW12

JPW4

I-SATA5

I-S ATA4

OPEN 1st

FAN2

FAN6

P1 DIMMB3

P1 DIMMB2

P1 DIMMB1

Chapter 2: Installation

1

2

VGA Enable

VGA Enable

Jumper Settings

Jumper JPG1 allows the user to enable

the onboard VGA connector. The default

Pin# Defi nition

1-2 Enabled (Default)

setting is on pins 1-2 to enable the con-

nection. See the table on the right for

2-3 Disabled

jumper settings.

BMC Enable

Jumper JPB1 is used to enable or

disable the embedded AST2400 BMC

Jumper Setting Defi nition

Pins 1-2 BMC Enable (Manufacture Default)

BMC Enable

Jumper Settings

(Baseboard Management Controller)

that provides IPMI 2.0/KVM support on

Pins 2-3 Disable (Do not use this setting!)

the board. See the table on the right for

jumper settings.

Warning! Jumper JPB1 (BMC Enable) is for engineering debugging only. The manu-

facturer default setting is on pins 1-2 to enable BMC. Do not change the default set-

ting. Disabling BMC will disable onboard graphic controller, hardware monitoring and

system health management.

SW1

LE1

COM1

VGA

LEDM1

JVRM2

BMC

JPG1

J33

J34

DESIGNED IN USA

JBT1

USB0/1

1

X10DRG-O+-CPU

REV:

BAR CODE

BIOS LICENSE

IPMI CODE

P2 DIMMF3

P2 DIMMF1

P2 DIMMF2

P2 DIMME3

LAN2

1.00

P2 DIMME2

PCH

1G/10G MAC CODE

10G SAN MAC

P2 DIMME1

P1 DIMMC1

JVRM1

JPW15

P2 DIMMH2

JPW16

FAN7

P2 DIMMH3

JPW22

CPU2

USB2/3

S-SATA2

S-SATA1

S-SATA0

S-SATA3

OPEN 1st

USB4

CLOSE 1st

FAN3

JPW21 JPW24JPW23

JPW3

JPW14

JPW13

S-SGPIO

+

JTPM1

JPB1

JL1

J1

JPME2

JBR1

JWD1

LE2

JSPK1

FAN4

JF1

1

FAN8

P2 DIMMG3

P2 DIMMH1

P2 DIMMG2

P2 DIMMG1

JF1

X

PS

PWR

UID2NIC

HDDNIC

PWR

RST

NMI

FAIL LED

1 LED

LED

ON

LAN1

P1 DIMMC2

USB7/8(3.0)

LAN

CTRL

J32

+

P1 DIMMC3

P1 DIMMD1

IPMI_LAN

USB5/6(3.0)

J31

BT1

P1 DIMMD2

P1 DIMMD3

JPW10

1. VGA Enabled

2. BMC Enabled

JPW7

P1 DIMMA2

P1 DIMMA1

JSD1

JPW5

JSD2

I-SGPIO2

I-SGPIO1

JPL1

LD1

LD2

JPW17JPW18

FAN5

FAN1

JPW6

JPW12

CPU1

JPW4

I-SATA3

I-SATA2

I-SATA5

I-S ATA4

OPEN 1st

FAN2

FAN6

P1 DIMMB3

P1 DIMMB2

P1 DIMMB1

JITP1

P1 DIMMA3

I-S ATA1

I-S ATA0

CLOSE 1st

JPP2

JPP1

2-33

X10DRG-O(T)+-CPU/X10DRG-O-PCIE User’s Manual

1

Manufacturer Mode Select

Close pins 2 and 3 of Jumper JPME2 to bypass

SPI fl ash security and force the system to oper-

ate in the Manufacturer mode, which will allow

the user to fl ash the system fi rmware from a

host server for system setting modifi cations.

See the table on the right for jumper settings.

ME Mode Select

Jumper Settings

Pin# Defi nition

1-2 Normal (Default)

2-3 Manufacture Mode

SW1

LE1

COM1

VGA

LEDM1

JVRM2

BMC

JPG1

J33

DESIGNED IN USA

JBT1

USB0/1

1

X10DRG-O+-CPU

REV:

BAR CODE

BIOS LICENSE

IPMI CODE

P2 DIMMF1

P2 DIMMF2

P2 DIMMF3

P2 DIMME3

J34

1.00

P2 DIMME2

LAN2

PCH

1G/10G MAC CODE

10G SAN MAC

P2 DIMME1

P1 DIMMC1

JVRM1

JPW15

P2 DIMMH2

P2 DIMMH3

JPW16

FAN7

JPW22

CPU2

USB2/3

S-SATA2

S-SATA1

S-SATA0

S-SATA3

OPEN 1st

USB4

CLOSE 1st

FAN3

JPW21 JPW24JPW23

JPW3

JPW14

JPW13

S-SGPIO

+

JTPM1

JPB1

JL1

J1

JPME2

JBR1

JWD1

LE2

JSPK1

FAN4

JF1

1

FAN8

P2 DIMMH1

P2 DIMMG2

P2 DIMMG1

P2 DIMMG3

JF1

X

PS

PWR

UID2NIC

HDDNIC

PWR

RST

NMI

FAIL LED

1 LED

LED

ON

LAN1

P1 DIMMC2

USB7/8(3.0)

LAN

CTRL

J32

+

P1 DIMMC3

IPMI_LAN

USB5/6(3.0)

BT1

P1 DIMMD1

P1 DIMMD2

J31

P1 DIMMD3

JPW10

1. JPME2

P1 DIMMA2

P1 DIMMA3

JPW7

P1 DIMMA1

JSD1

JPW5

JSD2

I-SGPIO2

I-SGPIO1

JPL1

LD1

LD2

JPW17JPW18

FAN5

FAN1

I-SATA2

CPU1

JITP1

JPW4

I-SATA3

I-SATA5

I-S ATA4

OPEN 1st

FAN2

FAN6

P1 DIMMB2

P1 DIMMB3

P1 DIMMB1

I-S ATA1

I-S ATA0

CLOSE 1st

JPP2

JPP1

JPW6

JPW12

2-34

2-9 Onboard LED Indicators

1

2

LAN LEDs

Link LED

Chapter 2: Installation

Activity LED

The LAN ports are located on the IO back

panel on the motherboard. Each Ethernet

LAN port has two LEDs. The yellow LED

indicates activity. The Link LED on the

left side of the LAN port may be green,

amber, or off to indicate the speed of the

connection. See the tables at right for

more information.

IPMI_LAN LEDs

In addition to LAN1/LAN2, an IPMI_LAN

is also located above USB 5/6 on the I/O

back panel. The amber LED on the right

indicates activity, while the green LED on

the left indicates the speed of the con-

nection. See the tables at right for more

information.

SW1

JVRM1

LE1

COM1

VGA

LEDM1

JVRM2

BMC

JPG1

IPMI_LAN

USB5/6(3.0)

USB7/8(3.0)

LAN2

LAN1

JPW10

LAN

CTRL

Rear View (when facing the
rear side of the chassis)

GLAN Activity Indicator (Left)

Color Status Defi nition

Yellow Flashing Active

LAN Link LED

Settings

(For X10DRG-O+)

Color Defi nition

Off No Con-

Green 100 Mbps

Amber 1 Gbps

Link LED Activity LED

IPMI LAN Link LED (Left) &

Color/State Defi nition

Link (Left) Green: Solid

Activity (Right) Amber: Blinking Active

LED Settings

(For X10DRG-OT+)

Color Defi nition

Off No Connec­nection,
10 Mbps

Green 10 Gbps

Amber 1 Gbps

IPMI LAN

Activity LED (Right)

Amber: Solid

LAN Link LED Set-

tings

tion,
10 or 100
Mbps

100 Mbps
1 Gbps

1. LAN1/2 LEDs

2. IPMI LAN LEDs

DESIGNED IN USA

JPW15

P2 DIMMH2

JPW16

P2 DIMMH3

JPW22

CPU2

USB2/3

S-SATA2

S-SATA1

S-SATA0

S-SATA3

OPEN 1st

USB4

CLOSE 1st

FAN3

FAN7

JPW21 JPW24JPW23

JPW3

JPW14

JPW13

S-SGPIO

+

JTPM1

JPB1

JL1

J1

JPME2

JBR1

JWD1

LE2

JSPK1

FAN4

JF1

1

FAN8

P2 DIMMH1

P2 DIMMG2

P2 DIMMG1

P2 DIMMG3

JF1

X

PS

PWR

UID2NIC

HDDNIC

PWR

RST

NMI

FAIL LED

1LED

LED

ON

J33

USB0/1

1

X10DRG-O+-CPU

BIOS LICENSE

P2 DIMMF1

P2 DIMMF2

P2 DIMMF3

JBT1

REV:

BAR CODE

IPMI CODE

P2 DIMME3

J34

1.00

P2 DIMME2

PCH

P2 DIMME1

1G/10G MAC CODE

10G SAN MAC

P1 DIMMC1

P1 DIMMC2

P1 DIMMC3

J32

+

P1 DIMMD1

P1 DIMMD2

BT1

J31

P1 DIMMD3

I-SATA1

I-SATA0

I-SATA3

I-SATA2

I-SATA5

I-SATA4

CLOSE 1st

CPU1

OPEN 1st

FAN2

FAN6

JPP2

JPP1

P1 DIMMB3

JITP1

P1 DIMMB2

P1 DIMMB1

P1 DIMMA3

P1 DIMMA2

JSD1

P1 DIMMA1

FAN5

JSD2

JPW17JPW18

I-SGPIO2

I-SGPIO1

JPL1

LD1

LD2

FAN1

JPW5

JPW6

JPW12

JPW7

JPW4

2-35

X10DRG-O(T)+-CPU/X10DRG-O-PCIE User’s Manual

1

2

Onboard Power LED

An Onboard Power LED is located at LE2 on

the board. When this LED is on, the system is

on. Be sure to turn off the system and unplug

the power cord before removing or installing

components. See the table on the right for

more information.

BMC Heartbeat LED

A BMC Heartbeat LED is located at LEDM1

on the motherboard. When LEDM1 is blink-

ing, BMC functions normally. See the table

on the right for more information.

Onboard PWR LED Indicator

LED States

LED Color Defi nition

Off System Off (PWR cable

not connected)

Green System On

Green:

ACPI State
Flashing
Quickly

BMC Heartbeat LED

States

Color/State Defi nition

Green:

BMC: Normal

Blinking

Note: Refer to Page 2-19 for information on the rear UID LED (LE1.)

SW1

LE1

COM1

VGA

LEDM1

JVRM2

BMC

JPG1

J33

J34

DESIGNED IN USA

JBT1

USB0/1

1

X10DRG-O+-CPU

REV:

BAR CODE

BIOS LICENSE

IPMI CODE

P2 DIMMF1

P2 DIMMF2

P2 DIMMF3

P2 DIMME3

LAN2

1.00

P2 DIMME2

PCH

1G/10G MAC CODE

10G SAN MAC

P2 DIMME1

P1 DIMMC1

JVRM1

JPW15

P2 DIMMH2

P2 DIMMH3

JPW16

FAN7

JPW22

CPU2

USB2/3

S-SATA2

S-SATA1

S-SATA0

S-SATA3

OPEN 1st

USB4

CLOSE 1st

FAN3

JPW21 JPW24JPW23

JPW3

JPW14

JPW13

S-SGPIO

+

JTPM1

JPB1

JL1

J1

JPME2

JBR1

JWD1

LE2

JSPK1

FAN4

JF1

1

FAN8

P2 DIMMH1

P2 DIMMG2

P2 DIMMG1

P2 DIMMG3

JF1

X

PS

PWR

UID2NIC

HDDNIC

PWR

RST

NMI

FAIL LED

1 LED

LED

ON

LAN1

P1 DIMMC2

USB7/8(3.0)

LAN

CTRL

J32

+

P1 DIMMC3

P1 DIMMD1

IPMI_LAN

USB5/6(3.0)

J31

BT1

P1 DIMMD2

P1 DIMMD3

JPW10

1. PWR LED (LE2)

2. BMC LED (LEDM1)

P1 DIMMA3

JPW7

P1 DIMMA2

P1 DIMMA1

JSD1

FAN5

JSD2

JPW17JPW18

JPW5

I-SGPIO2

I-SGPIO1

JPL1

LD1

LD2

FAN1

I-SATA2

CPU1

JITP1

JPW4

I-SATA3

I-SATA5

I-S ATA4

OPEN 1st

FAN2

FAN6

P1 DIMMB2

P1 DIMMB3

P1 DIMMB1

I-S ATA1

I-S ATA0

CLOSE 1st

JPP2

JPP1

JPW6

JPW12

2-36

2-10 SATA Connections

9

5

123

4

678

Chapter 2: Installation

Serial ATA Ports

Six Serial ATA 3.0 ports (I-SATA0-I-SATA5), supported by the

Intel PCH, are located on the motherboard. In addition, four S-

SATA connectors (S-SATA0-3), supported by the Intel SCU, are

also located on the motherboard. I-SATA4/5, colored in yellow,

are used with Supermicro SuperDOM (Disk-on-Module) con-

nectors with power pins built in, and are backward-compatible

with regular SATA HDDs and SATA DOMs that requires external

power cables. All SATA ports provide serial-link signal connec-

tions, which are faster than the connections of Parallel ATA. See

the table on the right for pin defi nitions.

Note: Please refer to the Intel SATA HostRAID User's Guide posted on our

website @ http://www.supermicro.com for more info on SATA.

SATA 3.0

Pin Defi nitions

Pin# Defi nition

1 Ground

2 TX_P

3 TX_N

4 Ground

5 RX_N

6 RX_P

7 Ground

SW1

LE1

COM1

VGA

LEDM1

JVRM2

BMC

JPG1

J33

J34

DESIGNED IN USA

JBT1

USB0/1

1

X10DRG-O+-CPU

REV:

BAR CODE

BIOS LICENSE

IPMI CODE

P2 DIMMF1

P2 DIMMF2

P2 DIMMF3

P2 DIMME3

LAN2

1.00

P2 DIMME2

PCH

1G/10G MAC CODE

10G SAN MAC

P2 DIMME1

P1 DIMMC1

JVRM1

JPW15

P2 DIMMH2

JPW16

P2 DIMMH3

JPW22

CPU2

USB2/3

S-SATA2

S-SATA1

S-SATA0

S-SATA3

10

OPEN 1st

USB4

CLOSE 1st

FAN3

FAN7

JPW21 JPW24JPW23

JPW3

JPW14

JPW13

S-SGPIO

+

JTPM1

JPB1

JL1

J1

JPME2

JBR1

JWD1

LE2

JSPK1

FAN4

JF1

1

FAN8

P2 DIMMH1

P2 DIMMG2

P2 DIMMG1

P2 DIMMG3

JF1

X

PS

PWR

UID2NIC

HDDNIC

PWR

RST

NMI

FAIL LED

1 LED

LED

ON

LAN1

P1 DIMMC2

LAN

CTRL

J32

+

P1 DIMMC3

IPMI_LAN

USB5/6(3.0)

USB7/8(3.0)

J31

BT1

P1 DIMMD1

P1 DIMMD2

JPW10

P1 DIMMD3

1. I-SATA0

2. I-SATA1

3. I-SATA2

4. I-SATA3

5. I-SATA4

6. I-SATA5

7. S-SATA0

8. S-SATA1

9. S-SATA2

10. S-SATA3

P1 DIMMA2

P1 DIMMA3

JPW7

P1 DIMMA1

JSD1

JPW5

JSD2

I-SGPIO2

I-SGPIO1

JPL1

LD1

LD2

JPW17JPW18

FAN5

FAN1

JPW6

JPW12

CPU1

JPW4

I-SATA3

I-SATA2

I-SATA5

I-S ATA4

OPEN 1st

FAN2

FAN6

P1 DIMMB2

P1 DIMMB3

JITP1

P1 DIMMB1

I-S ATA1

I-S ATA0

CLOSE 1st

JPP2

JPP1

2-37

Chapter 3: Troubleshooting

Chapter 3

Troubleshooting

3-1 Troubleshooting Procedures

Use the following procedures to troubleshoot your system. If you have followed all

of the procedures below and still need assistance, refer to the "Technical Support

Procedures" and/or "Returning Merchandise for Service" section(s) in this chapter.

Note: Always disconnect the power cord before adding, changing, or

installing any hardware components.

Before Power On

1. Make sure that there are no short circuits between the motherboard and

chassis.

2. Disconnect all ribbon/wire cables from the motherboard, including those for

the keyboard and mouse.

3. Remove all add-on cards.

4. Install CPU 1 fi rst (making sure it is fully seated) and connect the front panel

connectors to the motherboard.

No Power

1. Make sure that there are no short circuits between the motherboard and the

chassis.

2. Make sure that the ATX power connectors are properly connected.

3. Check that the 115V/230V switch on the power supply is properly set, if avail-

able.

4. Turn the power switch on and off to test the system, if applicable.

5. The battery on your motherboard may be old. Check to verify that it still sup-

plies ~3VDC. If it does not, replace it with a new one.

3-1

X10DRG-O(T)+-CPU/X10DRG-O-PCIE User’s Manual

No Video

1. If the power is on but you have no video, remove all the add-on cards and

cables.

2. Use the speaker to determine if any beep codes exist. Refer to Appendix A

for details on beep codes.

System Boot Failure

If the system does not display POST or does not respond after the power is turned

on, check the following:

1. Check for any error beep from the motherboard speaker.

• If there is no error beep, try to turn on the system without DIMM modules in-

stalled. If there is still no error beep, try to turn on the system again with only

one processor installed in CPU Socket#1. If there is still no error beep, replace

the motherboard.

• If there are error beeps, clear the CMOS settings by unplugging the power

cord and contacting both pads on the CMOS Clear Jumper (JBT1). (Refer to

Section 2-8 in Chapter 2.)

2. Remove all components from the motherboard, especially the DIMM mod-

ules. Make sure that system power is on, and that memory error beeps are

activated.

3. Turn on the system with only one DIMM module installed. If the system

boots, check for bad DIMM modules or slots by following the Memory Errors

Troubleshooting procedure in this Chapter.

Losing the System’s Setup Confi guration

1. Make sure that you are using a high-quality power supply. A poor-quality

power supply may cause the system to lose the CMOS setup information.

Refer to Section 1-6 for details on recommended power supplies.

2. The battery on your motherboard may be old. Check to verify that it still sup-

plies ~3VDC. If it does not, replace it with a new one.

3. If the above steps do not fi x the setup confi guration problem, contact your

vendor for repairs.

3-2

Chapter 3: Troubleshooting

Memory Errors

If a "no memory" beep code is issued by the system, check the following:

1. Make sure that the memory modules are compatible with the system and that

the DIMM modules are properly and fully installed. (For memory compatibility,

refer to the Memory Compatibility Chart posted on our website @ http://www.

supermicro.com.)

2. Check if different speeds of DIMMs have been installed. It is strongly recom-

mended that you use the same RAM type and speed for all DIMMs in the

system.

3. Make sure that you are using the correct type of Registered (RDIMM)/Load

Reduction (LRDIMM) DDR4 ECC modules recommended by the manufac-

turer.

4. Check for bad DIMM modules or slots by swapping a single module among

all memory slots and check the results.

5. Make sure that all memory modules are fully seated in their slots. Follow the

instructions given in Section 2-5 in Chapter 2.

6. Please follow the instructions given in the DIMM population tables listed in

Section 2-5 to install your memory modules.

When the System Becomes Unstable

A. If the system becomes unstable during or after OS installation, check the

following:

1. CPU/BIOS support: Make sure that your CPU is supported and you have the

latest BIOS installed in your system.

2. Memory support: Make sure that the memory modules are supported by test-

ing the modules using memtest86 or a similar utility.

Note: Refer to the product page on our website http:\\www.supermicro.

com for memory and CPU support and updates.

3. HDD support: Make sure that all hard disk drives (HDDs) work properly. Re-

place the bad HDDs with good ones.

4. System cooling: Check system cooling to make sure that all heatsink fans,

and CPU/system fans, etc., work properly. Check hardware monitoring set-

3-3

X10DRG-O(T)+-CPU/X10DRG-O-PCIE User’s Manual

tings in the IPMI to make sure that the CPU and system temperatures are

within the normal range. Also check the front-panel Overheat LED is not on.

5. Adequate power supply: Make sure that the power supply provides adequate

power to the system. Make sure that all power connectors are connected.

Please refer to our website for more information on minimum power require-

ments.

6. Proper software support: Make sure that the correct drivers are used.

B. When the system becomes unstable before or during OS installation, check

the following:

1. Source of installation: Make sure that the devices used for installation are

working properly, including boot devices such as CD/DVD disc.

2. Cable connection: Check to make sure that all cables are connected and

working properly.

3. Using minimum confi guration for troubleshooting: Remove all unnecessary

components (starting with add-on cards fi rst), and use minimum confi guration

(with a CPU and a memory module installed) to identify the trouble areas.

Refer to the steps listed in Section A above for proper troubleshooting proce-

dures.

4. Identifying bad components by isolating them: If necessary, remove a compo-

nent in question from the chassis, and test it in isolation to make sure that it

works properly. Replace a bad component with a good one.

5. Check and change one component at a time instead of changing several

items at the same time. This will help isolate and identify the problem.

6. To fi nd out if a component is good, swap this component with a new one to

see if the system will work properly. If so, then the old component is bad.

You can also install the component in question in another system. If the new

system works, the component is good and the old system has problems.

3-4

Chapter 3: Troubleshooting

3-2 Technical Support Procedures

Before contacting Technical Support, please take the following steps. Also, please

note that as a motherboard manufacturer, Supermicro also sells motherboards

through its channels, so it is best to fi rst check with your distributor or reseller for

troubleshooting services. They should know of any possible problem(s) with the

specifi c system confi guration that was sold to you.

1. Please go through the "Troubleshooting Procedures" and "Frequently Asked

Question" (FAQ) sections in this chapter or see the FAQs on our website

http://www.supermicro.com/) before contacting Technical Support.

(

2. BIOS upgrades can be downloaded from our website

).

com

3. If you still cannot resolve the problem, include the following information when

contacting Supermicro for technical support:

(http://www.supermicro.

• Motherboard model and PCB revision number

• BIOS release date/version (This can be seen on the initial display when your

system fi rst boots up.)

• System confi guration

4. An example of a Technical Support form is on our website at

supermicro.com).

(http://www.

• Distributors: For immediate assistance, please have your account number ready

when placing a call to our technical support department. We can be reached by

e-mail at [e-mail].

3-5

X10DRG-O(T)+-CPU/X10DRG-O-PCIE User’s Manual

3-3 Battery Removal and Installation

Battery Removal

To remove the onboard battery, follow the steps below:

1. Power off your system and unplug your power cable.

2. Locate the onboard battery as shown below.

3. Using a tool such as a pen or a small screwdriver, push the battery lock out-

wards to unlock it. Once unlocked, the battery will pop out from the holder.

4. Remove the battery.

Proper Battery Disposal

Warning: Please handle used batteries carefully. Do not damage the battery in any

way; a damaged battery may release hazardous materials into the environment. Do

not discard a used battery in the garbage or a public landfi ll. Please comply with the

regulations set up by your local hazardous waste management agency to dispose of

your used battery properly.

OR

3-6

Chapter 3: Troubleshooting

3-4 Frequently Asked Questions

Question: What are the various types of memory that my board can support?

Answer: The board supports Registered (RDIMM)/Load Reduction (LRDIMM) ECC

DDR4 DIMM modules. To enhance memory performance, do not mix memory mod-

ules of different speeds and sizes. Please follow all memory installation instructions

given on Section 2-5 in Chapter 2.

Question: How do I update my BIOS?

It is recommended that you do not upgrade your BIOS if you are not experiencing

any problems with your system. Updated BIOS fi les are located on our website

http://www.supermicro.com. Please check our BIOS warning message and the

at

information on how to update your BIOS on our website. Select your motherboard

model and download the BIOS fi le to your computer. Also, check the current BIOS

revision to make sure that it is newer than your BIOS before downloading. You can

choose from the zip fi le and the .exe fi le. If you choose the zip BIOS fi le, please

unzip the BIOS fi le onto a bootable USB device. Run the batch fi le using the format

FLASH.bat fi lename.rom from your bootable USB device to fl ash the BIOS. Then

your system will automatically reboot.

Warning: Do not shut down or reset the system while updating the BIOS to prevent

possible system boot failure!

Note: The SPI BIOS chip used on this motherboard cannot be removed.

Send your motherboard back to our RMA Department at Supermicro for

repair. For BIOS recovery instructions, please refer to the AMI BIOS Re-

covery Instructions posted at http://

Question: How do I handle the used battery?

Answer: Please handle used batteries carefully. Do not damage the battery in any

way; a damaged battery may release hazardous materials into the environment.

Do not discard a used battery in the garbage or a public landfi ll. Please comply

with the regulations set up by your local hazardous waste management agency to

dispose of your used battery properly.

www.supermicro.com.

3-7

X10DRG-O(T)+-CPU/X10DRG-O-PCIE User’s Manual

3-5 Returning Merchandise for Service

A receipt or copy of your invoice marked with the date of purchase is required before

any warranty service will be rendered. You can obtain service by calling your ven-

dor for a Returned Merchandise Authorization (RMA) number. When returning the

motherboard to the manufacturer, the RMA number should be prominently displayed

on the outside of the shipping carton, and the shipping package is mailed prepaid

or hand-carried. Shipping and handling charges will be applied for all orders that

must be mailed when service is complete. For faster service, you can also request

an RMA authorization online (http://www.supermicro.com/RmaForm/).

This warranty only covers normal consumer use and does not cover damages in-

curred in shipping or from failure due to the alternation, misuse, abuse, or improper

maintenance of products.

During the warranty period, contact your distributor fi rst for any product problems.

3-8

Chapter 4: AMI BIOS

Chapter 4

BIOS

4-1 Introduction

This chapter describes the AMI BIOS setup utility for the X10DRG-O(T)+-CPU. The

ROM BIOS is stored in a Flash EEPROM and can be easily updated. This chapter

describes the basic navigation of the AMI BIOS setup utility screens.

Note: For AMI BIOS recovery, please refer to the UEFI BIOS Recovery

Instructions in Appendix C.

Starting BIOS Setup Utility

To enter the AMI BIOS setup utility screens, press the <Delete> key while the

system is booting up.

Note: In most cases, the <Delete> key is used to invoke the AMI BIOS

setup screen.

Each main BIOS menu option is described in this manual. The AMI BIOS setup

menu screen has two main frames. The left frame displays all the options that can

be confi gured. Grayed-out options cannot be confi gured. Options in blue can be

confi gured by the user. The right frame displays the key legend. Above the key

legend is an area reserved for a text message. When an option is selected in the

left frame, it is highlighted in white. Often a text message will accompany it.

Note: The AMI BIOS has default text messages built in. Supermicro retains

the option to include, omit, or change any of these text messages.

The AMI BIOS setup utility uses a key-based navigation system called "hot keys."

Most of the AMI BIOS setup utility "hot keys" can be used at any time during the

setup navigation process. These keys include <F1>, <F4>, <Enter>, <Esc>, arrow

keys, etc.

Note: Options printed in Bold are default settings.

How To Change the Confi guration Data

The confi guration data that determines the system parameters may be changed by

entering the AMI BIOS setup utility. This setup utility can be accessed by pressing

<Del> at the appropriate time during system boot.

4-1

X10DRG-O(T)+-CPU User’s Manual

How to Start the Setup Utility

Normally, the only visible Power-On Self-Test (POST) routine is the memory test.

As the memory is being tested, press the <Delete> key to enter the main menu of

the AMI BIOS setup utility. From the main menu, you can access the other setup

screens. An AMI BIOS identifi cation string is displayed at the left bottom corner of

the screen, below the copyright message.

Warning: Do not upgrade the BIOS unless your system has a BIOS-related issue.

Flashing the wrong BIOS can cause irreparable damage to the system. In no event shall

Supermicro be liable for direct, indirect, special, incidental, or consequential damages

arising from a BIOS update. If you have to update the BIOS, do not shut down or reset

the system while the BIOS is updating to avoid possible boot failure.

4-2 Main Setup

When you fi rst enter the AMI BIOS setup utility, you will enter the Main setup screen.

You can always return to the Main setup screen by selecting the Main tab on the

top of the screen. The Main BIOS setup screen is shown below.

4-2

Chapter 4: AMI BIOS

The following Main menu items will be displayed:

System Date/System Time

Use this option to change the system date and time. Highlight System Date or

System Time using the arrow keys. Enter new values using the keyboard. Press the

<Tab> key or the arrow keys to move between fi elds. The date must be entered in

Day MM/DD/YYYY format. The time is entered in HH:MM:SS format.

Note: The time is in the 24-hour format. For example, 5:30 P.M. appears

as 17:30:00.

Supermicro X10DRG-O(T)+

BIOS Version: This item displays the version of the BIOS ROM used in the system.

Build Date: This item displays the date when the version of the BIOS ROM used

in the system was built.

Memory Information

Total Memory: This item displays the total size of memory available in the system.

Memory Speed: This item displays the default speed of the memory modules

installed in the system.

4-3

X10DRG-O(T)+-CPU User’s Manual

4-3 Advanced Setup Confi gurations

Use the arrow keys to select Advanced setup and press <Enter> to access the

submenu items:

Warning: Take caution when changing the Advanced settings. An incorrect value, a

very high DRAM frequency, or an incorrect BIOS timing setting may cause the system to

malfunction. When this occurs, restore the setting to the manufacturer's default setting.



Boot Feature

Quiet Boot

Use this feature to select the screen display between POST messages or the OEM

logo at bootup. Select Disabled to display the POST messages. Select Enabled

to display the OEM logo instead of the normal POST messages. The options are

Disabled and Enabled.

AddOn ROM Display Mode

Use this item to set the display mode for the Option ROM. Select Keep Current to

use the current AddOn ROM display setting. Select Force BIOS to use the Option

ROM display mode set by the system BIOS. The options are Force BIOS and

Keep Current.

4-4

Chapter 4: AMI BIOS

Bootup Num-Lock State

Use this feature to set the Power-on state for the Numlock key. The options are

On and Off.

Wait For "F1" If Error

Select Enabled to force the system to wait until the <F1> key is pressed if an error

occurs. The options are Disabled and Enabled.

INT19 (Interrupt 19) Trap Response

Interrupt 19 is the software interrupt that handles the boot disk function. When this

item is set to Immediate, the ROM BIOS of the host adaptors will "capture" Inter-

rupt 19 at bootup immediately and allow the drives that are attached to these host

adaptors to function as bootable disks. If this item is set to Postponed, the ROM

BIOS of the host adaptors will not capture Interrupt 19 immediately and allow the

drives attached to these adaptors to function as bootable devices at bootup. The

options are Immediate and Postponed.

Re-try Boot

When EFI Boot is selected, the system BIOS will automatically reboot the system

from an EFI boot device after its initial boot failure. Select Legacy Boot to allow

the BIOS to automatically reboot the system from a Legacy boot device after its

initial boot failure. The options are Disabled, Legacy Boot, and EFI Boot.

Power Confi guration

Watch Dog Function

Select Enabled to allow the Watch Dog timer to reboot the system when it is inac-

tive for more than 5 minutes. The options are Disabled and Enabled.

Power Button Function

This feature controls how the system shuts down when the power button is pressed.

Select 4 Seconds Override for the user to power off the system after pressing and

holding the power button for 4 seconds or longer. Select Instant Off to instantly

power off the system as soon as the user presses the power button. The options

are Instant Off and 4 Seconds Override.

Restore on AC Power Loss

Use this feature to set the power state after a power outage. Select Power-Off for

the system power to remain off after a power loss. Select Power-On for the system

power to be turned on after a power loss. Select Last State to allow the system

to resume its last power state before a power loss. The options are Power On,

Stay Off, and Last State.

4-5

X10DRG-O(T)+-CPU User’s Manual

CPU Confi guration

This submenu displays the following CPU information as detected by the BIOS. It

also allows the user to confi gure CPU settings.

• Processor Socket

• Processor ID

• Processor Frequency

• Processor Max Ratio

• Processor Min Ratio

• Microcode Revision

• L1 Cache RAM

• L2 Cache RAM

• L3 Cache RAM

• CPU1 Version

• CPU2 Version

Clock Spread Spectrum

Select Enable to allow the BIOS to monitor and attempt to reduce the level of

Electromagnetic Interference caused by the components whenever needed. The

options are Disable and Enable.

Hyper-Threading (All)

Select Enable to support Intel's Hyper-threading Technology to enhance CPU per-

formance. The options are Disable and Enable.

Cores Enabled

This feature allows the user to set the number of CPU cores to enable. Enter "0"

to enable all cores. The default setting is 0.

Execute-Disable Bit (Available if supported by the OS & the CPU)

Select Enable for Execute Disable Bit Technology support, which will allow the

processor to designate areas in the system memory where an application code can

execute and where it cannot, thus preventing a worm or a virus from fl ooding illegal

4-6

Chapter 4: AMI BIOS

codes to overwhelm the processor to damage the system during an attack. This

feature is used in conjunction with the items: "Clear MCA," "VMX," "Enable SMX,"

and "Lock Chipset" for Virtualization media support. The options are Disable and

Enable. (Refer to Intel and Microsoft websites for more information.)

PPIN Control

Select Unlock/Enable to use the Protected-Processor Inventory Number (PPIN) in

the system. The options are Unlock/Disable and Unlock/Enable.

Hardware Prefetcher (Available when supported by the CPU)

If set to Enable, the hardware prefetcher will prefetch streams of data and instruc-

tions from the main memory to the L2 cache to improve CPU performance. The

options are Enable and Disable.

Adjacent Cache Prefetch (Available when supported by the CPU)

Select Enable for the CPU to prefetch both cache lines for 128 bytes as comprised.

Select Disable for the CPU to prefetch both cache lines for 64 bytes. The options

are Enable and Disable.

Note: Please reboot the system for changes on this setting to take effect.

Please refer to Intel’s website for detailed information.

DCU (Data Cache Unit) Streamer Prefetcher (Available when supported by
the CPU)

If set to Enable, the DCU Streamer Prefetcher will prefetch data streams from the

cache memory to the DCU (Data Cache Unit) to speed up data accessing and

processing to enhance CPU performance. The options are Enable and Disable.

DCU IP Prefetcher

If set to Enable, the IP prefetcher in the DCU (Data Cache Unit) will prefetch IP

addresses to improve network connectivity and system performance. The options

are Enable and Disable.

Direct Cache Access (DCA)

Select Enable to use Intel DCA (Direct Cache Access) Technology to improve the

effi ciency of data transferring and accessing. The options are Disable, Enable,

and Auto.

X2APIC (Advanced Programmable Interrupt Controller)

Based on Intel's Hyper-Threading architecture, each logical processor (thread) is

assigned 256 APIC IDs (APIDs) in 8-bit bandwidth. When this feature is set to En-

able, the APIC ID will be expanded from 8 bits (X2) to 16 bits to provide 512 APIDs

to each thread to enhance CPU performance. The options are Disable and Enable.

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X10DRG-O(T)+-CPU User’s Manual

AES-NI

Select Enable to use the Intel Advanced Encryption Standard (AES) New Instruc-

tions (NI) to ensure data security. The options are Disable and Enable.

Intel Virtualization Technology

Select Enable to use Intel Virtualization Technology support for Direct I/O VT-d sup-

port

by reporting the I/O device assignments to the VMM (Virtual Machine Monitor)

through the DMAR ACPI tables. This feature offers fully-protected I/O resource

sharing across Intel platforms, providing greater reliability, security and availability

in networking and data-sharing. The options are Disable and Enable.

Chipset Confi guration

Warning! Please set the correct settings for the items below. A wrong confi guration

setting may cause the system to malfunction.

North Bridge

This feature allows the user to confi gure the settings for the Intel North Bridge.

IIO Confi guration

EV DFX (Device Function On-Hide) Feature

When this feature is set to Enable, the EV_DFX Lock Bits that are located on a

processor will always remain clear during electric tuning. The options are Dis-

able and Enable.

IIO0 Confi guration

IOU2 (IOU PCIe Port1)

This item confi gures the PCI-E port Bifuraction setting for a PCI-E port specifi ed

by the user. The options are x4x4, x8, and Auto.

IOU0 (IOU PCIe Port2)

This item confi gures the PCI-E port Bifuraction setting for a PCI-E port specifi ed

by the user. The options are x4x4x4x4, x4x4x8, x8x4x4, x8x8, x16, and Auto.

IOU1 (IOU PCIe Port3)

This item confi gures the PCI-E port Bifuraction setting for a PCI-E port specifi ed

by the user. The options are x4x4x4x4, x4x4x8, x8x4x4, x8x8, x16, and Auto.

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Chapter 4: AMI BIOS

No PCIe Port Active ECO

This item provides a workaround solution when there is no PCIe port active.

The options are PCU Squelch exit ignore option and Reset the SQ FLOP by

CSR option.

Socket 0 PCIED00F0 - Port 0/DMI

This submenu allows the user to confi gure the settings for the following PCI-E
ports: 0, 1A, 1B, 2A, 2B, 2C, 2D, 3A, 3B, 3C, and 3D.

Link Speed

Use this item to confi gure the link speed of a PCI-E device installed on the

PCI-E slot specifi ed by the user. The options are Auto, Gen 1 (2.5 GT/s), and

Gen 2 (5 GT/s).

PCI-E Port DeEmphasis

DeEmphasis is used to decrease the magnitude of very high frequencies in

relation to the magnitude of very low frequencies to improve the overall signal-

to-noise ratio by reducing the level of all (signals) data bits transmitted except the

fi rst one, acting as a form of transmitter equalization to enhance signal transmis-

sion and audio performance. The options are -6.0 dB and -3.5 dB.

The following items will display:

PCI-E Port Link Status

PCI-E Port Link Max

PCI-E Port Link Speed

PCI-E Port L0s Exit Latency

Use this item to confi gure the exit latency of the PCI-E port L0s link state, mea-

suring the length of time needed to transition from the L0s link state to L0. The

available latency option is 4uS - 8uS. (Note: "uS" stands for "microseconds.")

PCI-E Port L1 Exit Latency

Use this item to confi gure the exit latency of the PCI-E port L1 link state, measur-

ing the length of time needed to transition from the L1 link state to L0. The latency

options are <1uS, 1uS - 2uS, 2uS - 4uS, 4uS - 8uS, 8uS - 16uS, 16uS - 32uS,

32uS - 64uS, and >64uS. (Note: "uS" stands for "microseconds.")

Fatal Err Over (Fatal Error Overwrite)

This item confi gures the option to overwrite fatal errors. The options are Dis-

able and Enable.

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X10DRG-O(T)+-CPU User’s Manual

Non-Fatal Err Over (Non-Fatal Error Overwrite)

This item confi gures the option to overwrite non-fatal errors. The options are

Disable and Enable.

Corr Err Over (Correctable Error Overwrite)

This item confi gures the option to overwrite correctable errors for ECC memory.

The options are Disable and Enable.

L0s Support

This item confi gures the option to enable support for the L0s PCI-E link state

(non supported in this motherboard). The only available option is Disable.

Socket 0 PcieD00F0 - Port 1A/Port 2A/Port 3A

PCI-E Port

Select Enable to enable a PCI-E port specifi ed by the user. Select Disable to

de-activate a PCI-E port specifi ed by the user. Select Auto for the BIOS ROM

to automatically discard a PCI-E port specifi ed by the user when there is no

HP-compatible device connected to this port or when there is no error detected

in this port. The options are Auto, Enable, and Disable.

Hot Plug Capable

Use this feature to enable or disable hot-plug support for a port specifi ed by the

user. The options are Disable and Enable.

PCI-E Port Link

Use this feature to disable the physical link connected to a PCI-E port specifi ed

by a user so that no training will take place on the component-level while the

PCI-E confi guration commands are still in full force. The options are Enable

and Disable.

Link Speed

Use this item to confi gure the link speed of a PCI-E port specifi ed by the user.

The options are Auto, Gen 1 (Generation 1) (2.5 GT/s), Gen 2 (Generation 2)

(5 GT/s), and Gen 3 (Generation 3) (8 GT/s).

PCI-E Port DeEmphasis

This item confi gures the De-Emphasis Control (LANKCON2 [6]) setting for this

computer. The options are -6.0 dB and -3.5 dB.

The following items will display:

PCI-E Port Link Status

PCI-E Port Link Max

PCI-E Port Link Speed

4-10

Chapter 4: AMI BIOS

PCI-E Port L0s Exit Latency

Use this feature to set the length of time required for the port specifi ed by the

user to complete the transition from L0s to L0. The default setting is 4uS - 8uS.

PCI-E Port L1 Exit Latency

Use this feature to set the length of time required for the port specifi ed by the

user to complete the transition from L1 to L0. The default setting is <1uS, 1uS -

2uS, 2uS - 4uS, 4uS - 8uS, 8uS - 16uS, 16uS - 32uS, 32uS - 64uS, and >64uS.

Fatal Err (Error) Over

Select Enable to force fatal error propagation to the II0 core error logic for the

port specifi ed by the user. The options are Disable and Enable.

Non-Fatal Err (Error) Over

Select Enable to force non-fatal error propagation to the II0 core error logic for

the port specifi ed by the user. The options are Disable and Enable.

Corr Err (Correctable Error) Over

Select Enable to force correctable error propagation to the II0 core error logic for

the port specifi ed by the user. The options are Disable and Enable.

L0s Support

When this item is set to Disable, II0 will not put its transmitter in the L0s state.

The default setting is Disable.

PM ACPI Mode

Select Enable to generate an _HPGPE message on a PM ACPI event. Select

Disable to generate an MSI message. The options are Disable and Enable.

Gen3 (Generation 3) Eq (Equalization) Mode

Use this item to set PCI-E Gen3 Adaptive Equalization mode. The options are

Auto; Enable Phase 0,1,2,3; Disable Phase 0,1,2,3; Enable Phase 1 Only; En-

able Phase 0,1 Only; Advanced; and Enable MMM Offset West.

Gen3 (Generation 3) Spec (Specifi cs) Mode

Use this item to set the Specifi cs mode for a PCI-E Gen. 3 device. The options

are Auto, 0.70 July, 0.70 Sept, and 0.71 Sept.

Gen3 (Generation 3) Phase2 Mode

Use this feature to confi gure the Loop-count settings for PCI-E Gen3 Phase 2.

The options are Hardware Adaptive and Manual.

Gen3 DN Tx Preset

This feature allows the user to select the preset setting for a downstream com-

ponent transmitter. The options are Auto, P0 (-6.0/0.0 dB), P1 (-3.5/0.0 dB), P2

(-4.5/0.0 dB), P3 (-2.5/0.0 dB), P4 (0.0/0.0 dB), P5 (0.0/2.0 dB), P6 (0.0/2.5 dB),

P7 (-6.0/3.5 dB), P8 (-3.5/3.5 dB), and P9 (0.0/3.5 dB).

4-11

X10DRG-O(T)+-CPU User’s Manual

Gen3 DN Rx Preset Hint

This feature allows the user to select a preset setting for a downstream compo-

nent receiver. The options are Auto, P0 (-6.0 dB), P1 (-7.0 dB), P2 (-8.0 dB),

P3 (-9.0 dB), P4 (-10.0 dB), P5 (-11.0 dB), and P6 (-12.0 dB).

Gen3 UP Tx Preset

This feature allows the user to select the preset setting for a upstream compo-

nent transmitter. The options are Auto, P0 (-6.0/0.0 dB), P1 (-3.5/0.0 dB), P2

(-4.5/0.0 dB), P3 (-2.5/0.0 dB), P4 (0.0/0.0 dB), P5 (0.0/2.0 dB), P6 (0.0/2.5 dB),

P7 (-6.0/3.5 dB), P8 (-3.5/3.5 dB), and P9 (0.0/3.5 dB).

Non-Transparent Bridge PCIe Port D (Port 3A only)

Select Transparent Bridge to confi gure the device installed on a PCI slot specifi ed

by the user as a transparent bridge (TB) device. Select NTB (Non-Transparent

Bridge) to NTB to confi gure the device installed on a PCI slot specifi ed by the

user as a non-transparent bridge (TB) device used to connect to another TB

device. The options are Transparent Bridge, NTB to NTB, and NTB to RP.

Hide Port?

Use this feature to hide the root port from the operating system. The options

are no and yes.

IIO1 Confi guration

IOU2 (IOU PCIe Port1)

This item confi gures the PCI-E port Bifuraction setting for a PCI-E port specifi ed

by the user. The options are x4x4, x8, and Auto.

IOU0 (IOU PCIe Port2)

This item confi gures the PCI-E port Bifuraction setting for a PCI-E port specifi ed

by the user. The options are x4x4x4x4, x4x4x8, x8x4x4, x8x8, x16, and Auto.

IOU1 (IOU PCIe Port3)

This item confi gures the PCI-E port Bifuraction setting for a PCI-E port specifi ed

by the user. The options are x4x4x4x4, x4x4x8, x8x4x4, x8x8, x16, and Auto.

No PCIe Port Active ECO

This item provides a workaround solution when there is no PCIe port active.

The options are PCU Squelch exit ignore option and Reset the SQ FLOP by

CSR option.

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Chapter 4: AMI BIOS

Socket 1 PCIED00F0 - Port 0/DMI / Port 1A / Port 2A /
Port 3A

PCI-E Port

Select Enable to enable a PCI-E port specifi ed by the user. Select Disable to

de-activate a PCI-E port specifi ed by the user. Select Auto for the BIOS ROM

to automatically discard a PCI-E port specifi ed by the user when there is no

HP-compatible device connected to this port or when there is no error detected

in this port. The options are Auto, Enable, and Disable.

Hot Plug Capable

Use this feature to enable or disable hot-plug support for a port specifi ed by the

user. The options are Disable and Enable.

PCI-E Port Link

Use this feature to disable the physical link connected to a PCI-E port specifi ed

by a user so that no training will take place on the component-level while the

PCI-E confi guration commands are still in full force. The options are Enable

and Disable.

Link Speed

Use this item to confi gure the link speed of a PCI-E port specifi ed by the user.

The options are Auto, Gen 1 (Generation 1) (2.5 GT/s), and Gen 2 (Generation

2) (5 GT/s).

PCI-E Port DeEmphasis

This item confi gures the De-Emphasis Control (LANKCON2 [6]) setting for this

computer. The options are -6.0 dB and -3.5 dB.

The following items will display:

PCI-E Port Link Status

PCI-E Port Link Max

PCI-E Port Link Speed

PCI-E Port L0s Exit Latency

Use this feature to set the length of time required for the port specifi ed by the

user to complete the transition from L0s to L0. The default setting is 4uS - 8uS.

PCI-E Port L1 Exit Latency

Use this feature to set the length of time required for the port specifi ed by the

user to complete the transition from L1 to L0. The default setting is <1uS, 1uS -

2uS, 2uS - 4uS, 4uS - 8uS, 8uS - 16uS, 16uS - 32uS, 32uS - 64uS, and >64uS.

Fatal Err (Error) Over

Select Enable to force fatal error propagation to the II0 core error logic for the

port specifi ed by the user. The options are Disable and Enable.

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X10DRG-O(T)+-CPU User’s Manual

Non-Fatal Err (Error) Over

Select Enable to force non-fatal error propagation to the II0 core error logic for

the port specifi ed by the user. The options are Disable and Enable.

Corr Err (Correctable Error) Over

Select Enable to force correctable error propagation to the II0 core error logic for

the port specifi ed by the user. The options are Disable and Enable.

L0s Support

When this item is set to Disable, II0 will not put its transmitter in the L0s state.

The default setting is Disable.

PM ACPI Mode

Select Enable to generate an _HPGPE message on a PM ACPI event. Select

Disable to generate an MSI message. The options are Disable and Enable.

Gen3 (Generation 3) Eq (Equalization) Mode

Use this item to set PCI-E Gen3 Adaptive Equalization mode. The options are

Auto; Enable Phase 0,1,2,3; Disable Phase 0,1,2,3; Enable Phase 1 Only; En-

able Phase 0,1 Only; Advanced; and Enable MMM Offset West.

Gen3 (Generation 3) Spec (Specifi cs) Mode

Use this item to set the Specifi cs mode for a PCI-E Gen. 3 device. The options

are Auto, 0.70 July, 0.70 Sept, and 0.71 Sept.

Gen3 (Generation 3) Phase2 Mode

Use this feature to confi gure the Loop-count settings for PCI-E Gen3 Phase 2.

The options are Hardware Adaptive and Manual.

Gen3 DN Tx Preset

This feature allows the user to select the preset setting for a downstream com-

ponent transmitter. The options are Auto, P0 (-6.0/0.0 dB), P1 (-3.5/0.0 dB), P2

(-4.5/0.0 dB), P3 (-2.5/0.0 dB), P4 (0.0/0.0 dB), P5 (0.0/2.0 dB), P6 (0.0/2.5 dB),

P7 (-6.0/3.5 dB), P8 (-3.5/3.5 dB), and P9 (0.0/3.5 dB).

Gen3 DN Rx Preset Hint

This feature allows the user to select a preset setting for a downstream compo-

nent receiver. The options are Auto, P0 (-6.0 dB), P1 (-7.0 dB), P2 (-8.0 dB),

P3 (-9.0 dB), P4 (-10.0 dB), P5 (-11.0 dB), and P6 (-12.0 dB).

Gen3 UP Tx Preset

This feature allows the user to select the preset setting for a upstream compo-

nent transmitter. The options are Auto, P0 (-6.0/0.0 dB), P1 (-3.5/0.0 dB), P2

(-4.5/0.0 dB), P3 (-2.5/0.0 dB), P4 (0.0/0.0 dB), P5 (0.0/2.0 dB), P6 (0.0/2.5 dB),

P7 (-6.0/3.5 dB), P8 (-3.5/3.5 dB), and P9 (0.0/3.5 dB).

4-14

Chapter 4: AMI BIOS

Non-Transparent Bridge PCIe Port D (Port 3A only)

Select Transparent Bridge to confi gure the device installed on a PCI slot specifi ed

by the user as a transparent bridge (TB) device. Select NTB (Non-Transparent

Bridge) to NTB to confi gure the device installed on a PCI slot specifi ed by the

user as a non-transparent bridge (TB) device used to connect to another TB

device. The options are Transparent Bridge, NTB to NTB, and NTB to RP.

Hide Port?

Use this feature to hide the root port from the operating system. The options

are no and yes.

IOAT (Intel® IO Acceleration) Confi guration

Enable IOAT

Select Enable to enable Intel I/OAT (I/O Acceleration Technology) support,

which will signifi cantly reduce CPU overhead by leveraging CPU architectural

improvements and freeing the system resource for other tasks. The options are

Disable and Enable.

No Snoop

Select Enable to support no-snoop mode for each CB device. The options are

Disable and Enable.

Relaxed Ordering

Select Enable to enable Relaxed Ordering support which will allow certain

transactions to violate the strict-ordering rules of PCI bus for a transaction to be

completed prior to other transactions that have already been enqueued earlier.

The options are Disable and Enable.

 Intel VT for Directed I/O (VT-d)

Intel VT for Direct I/O (VT-d)

Select Enable to use Intel Virtualization Technology support for Direct I/O VT-d

support

Monitor) through the DMAR ACPI Tables. This feature offers fully-protected I/O

resource sharing across Intel platforms, providing greater reliability, security and

availability in networking and data-sharing. The options are Enable and Disable.

by reporting the I/O device assignments to the VMM (Virtual Machine

Interrupt Remapping

Select Enable for Interrupt Remapping support to enhance system performance.

The options are Enable and Disable.

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X10DRG-O(T)+-CPU User’s Manual

QPI (Quick Path Interconnect) Confi guration

QPI General Confi guration

QPI Status

The following information will display:

• Number of CPU

• Number of IIO

• Current QPI Link Speed

• Current QPI Link Frequency

• QPI Global MMIO Low Base/Limit

• QPI Global MMIO High Base/Limit

• QPI PCIe Confi guration Base/Size

Link Frequency Select

Use this item to select the desired frequency for QPI Link connections. The op-

tions are 6.4GB/s, 8.0GB/s, 9.6GB/s, Auto, and Auto Limited.

Link L0p Enable

Select Enable for Link L0p support. The options are Disable and Enable.

Link L1 Enable

Select Enable for Link L1 support. The options are Disable and Enable.

COD Enable (Available when the OS and the CPU support this feature)

Select Enabled for Cluster-On-Die support to enhance system performance in

cloud computing. The options are Disable and Enable.

Early Snoop (Available when the OS and the CPU support this feature)

Select Enable for Early Snoop support to enhance system performance. The

options are Disable, Enable, and Auto.

Isoc Mode

Select Enable for Isochronous support to meet QoS (Quality of Service) require-

ments. This feature is especially important for Virtualization Technology. The

options are Disable and Enable.

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Chapter 4: AMI BIOS

Memory Confi guration

Enforce POR

Select Enable to enforce POR restrictions on memory frequency and voltage

programming. The options are Enabled and Disabled.

Memory Frequency

Use this feature to set the maximum memory frequency for onboard memory

modules. The options are Auto, 1333, 1400, 1600, 1800, 1867, 2000, 2133,

2200, 2400, 2600, 2667, 2800, 2993, 3000, 3200. and Reserved. (Do not select

Reserved.)

Data Scrambling

Select Enabled to enable data scrambling to enhance system performance and

data integrity. The options are Auto, Disabled, and Enabled.

Enable ADR

Select Enabled for ADR (Automatic Diagnostic Repository) support to enhance

memory performance. The options are Disabled and Enabled.

DRAM RAPL (Running Average Power Limit) Baseline

Use this feature to set the run-time power-limit baseline for the DRAM modules.

The options are Disable, DRAM RAPL Mode 0, and DRAM RAPL Mode 1.

Set Throttling Mode

Throttling improves reliability and reduces power consumption in processors via

automatic voltage control during processor idle states. The options are Disabled

and CLTT (Closed Loop Thermal Throttling).

A7 Mode

Select Enabled to support the A7 (Addressing) mode to improve memory per-

formance. The options are Disable and Enable.

DIMM Information

This item displays the status of a DIMM module as detected by the BIOS.

P1-DIMMA1/A2/A3, P1-DIMMB1/B2/B3, P1-DIMMC1/C2/C3, P1-DIMMD1/

D2/D3, P2-DIMME1/E2/E3, P2-DIMMF1/F2/F3, P2-DIMMG1/G2/G3, and P2-

DIMMH1/H2/H3.

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X10DRG-O(T)+-CPU User’s Manual

Memory RAS (Reliability Availability Serviceability)
Confi guration

Use this submenu to confi gure the following Memory RAS settings.

RAS Mode

When Disable is selected, RAS is not supported. When Mirror is selected, the

motherboard maintains two identical copies of all data in memory for data backup.

When Lockstep is selected, the motherboard uses two areas of memory to run

the same set of operations in parallel to boost performance. The options are

Disable, Mirror, and Lockstep Mode.

Memory Rank Sparing

Select Enable to enable memory-sparing support for memory ranks to improve

memory performance. The options are Disabled and Enabled.

Patrol Scrub

Patrol Scrubbing is a process that allows the CPU to correct correctable memory

errors detected on a memory module and send the correction to the requestor

(the original source). When this item is set to Enable, the PCH (Platform Control

Hub) will read and write-back one cache line every 16K cycles if there is no delay

caused by internal processing. By using this method, roughly 64 GB of memory

behind the PCH will be scrubbed every day. The options are Disable and Enable.

Patrol Scrub Interval

This feature allows you to decide how many hours the system should wait before

the next complete patrol scrub is performed. Use the keyboard to enter a value

from 0-24. The default setting is 24.

Demand Scrub

Demand Scrubbing is a process that allows the CPU to correct correctable

memory errors found on a memory module. When the CPU or I/O issues a

demand-read command, and the read data from memory turns out to be a

correctable error, the error is corrected and sent to the requestor (the original

source). Memory is updated as well. Select Enable to use Demand Scrubbing

for ECC memory correction. The options are Disable and Enable.

Device Tagging

Select Enable to support device tagging. The options are Disable and Enable.

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Chapter 4: AMI BIOS



South Bridge Confi guration

The following South Bridge information will display:



USB Confi guration

• USB Module Version

• USB Devices

Legacy USB Support

Select Enabled to support onboard legacy USB devices. Select Auto to disable

legacy support if there are no legacy USB devices present. Select Disable to have

all USB devices available for EFI applications only. The options are Enabled,

Disabled, and Auto.

XHCI (Extensible Host Controller Interface) Hand-Off

This is a work-around solution for operating systems that do not support XHCI (Ex-

tensible Host Controller Interface) hand-off. The XHCI ownership change should be

claimed by the XHCI driver. The settings are Enabled and Disabled.

EHCI (Enhanced Host Controller Interface) Hand-Off

This item is for operating systems that do not support Enhanced Host Controller

Interface (EHCI) hand-off. When this item is enabled, EHCI ownership change will

be claimed by the EHCI driver. The settings are Disabled and Enabled.

Port 60/64 Emulation



SATA Confi guration

When this submenu is selected, the AMI BIOS automatically detects the presence

of the SATA devices that are supported by the Intel PCH chip and displays the

following items:

SATA Controller

This item enables or disables the onboard SATA controller supported by the Intel

PCH chip. The options are Disabled and Enabled.

Confi gure SATA as

Select IDE to confi gure a SATA drive specifi ed by the user as an IDE drive. Select

AHCI to confi gure a SATA drive specifi ed by the user as an AHCI drive. Select

RAID to confi gure a SATA drive specifi ed by the user as a RAID drive. The options

are IDE, AHCI, and RAID.

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X10DRG-O(T)+-CPU User’s Manual

*If the item above "Confi gure SATA as" is set to AHCI, the following items will display:

Support Aggressive Link Power Management

When this item is set to Enabled, the SATA AHCI controller manages the power

usage of the SATA link. The controller will put the link to a low power state when

the I/O is inactive for an extended period of time, and the power state will return

to normal when the I/O becomes active. The options are Disabled and Enabled.

SATA Port 0-Port 5

This item displays the information detected on the installed SATA drive on the

particular SATA port.

• Model number of drive and capacity

• Software Preserve Support

Port 0-Port 5 Hot Plug

Select Enabled to support Hot-plugging for the selected SATA port which will al-

low the user to replace a device without shutting down the system. The options

are Disabled and Enabled.

Port 0-Port 5 Spin Up Device

On an edge detect from 0 to 1, set this item to allow the PCH to initialize the

device. The options are Disabled and Enabled.

Port 0-Port 5 SATA Device Type

Use this item to specify if the SATA port specifi ed by the user should be con-

nected to a Solid State drive or a Hard Disk Drive. The options are Hard Disk

Drive and Solid State Drive.

*If the item above "Confi gure SATA as" is set to IDE, the following items will
display:

SATA Port 0-Port 5

This item displays the information detected on the installed SATA drive on the

particular SATA port.

• Model number of drive and capacity

• Software Preserve Support

Port 0-Port 5 SATA Device Type (Available when a SATA port is detected)

Use this item to specify if the SATA port specifi ed by the user should be con-

nected to a Solid State drive or a Hard Disk Drive. The options are Hard Disk

Drive and Solid State Drive.

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Chapter 4: AMI BIOS

*If the item above "Confi gure SATA as" is set to RAID, the following items will
display:

Support Aggressive Link Power Management

When this item is set to Enabled, the SATA AHCI controller manages the power

usage of the SATA link. The controller will put the link to a low power state when

the I/O is inactive for an extended period of time, and the power state will return

to normal when the I/O becomes active. The options are Disabled and Enabled.

SATA RAID Option ROM/UEFI Driver

Select EFI to load the EFI driver for system boot. Select Legacy to load a legacy

driver for system boot. The options are Legacy, EFI, and Disabled.

SATA/sSATA RAID Boot Select

Select SATA Controller to boot the system from a SATA RAID device. Select

sSATA Controller to boot the system from a S-SATA RAID device. Select Both to

boot the system either from a SATA RAID device or from an sSATA RAID device.

Please note that the option-Both is not supported by the Windows Server 2012/

R2 OS. The options are None, SATA Controller, sSATA Controller, and Both.

Serial ATA Port 0-Port 5

This item displays the information detected on the installed SATA drives on the

particular SATA port.

• Model number of drive and capacity

• Software Preserve Support

Port 0-Port 5 Hot Plug

Select Enabled to support Hot-plugging for the selected SATA port which will al-

low the user to replace a device without shutting down the system. The options

are Disabled and Enabled.

Port 0-Port 5 Spin Up Device

On an edge detect from 0 to 1, set this item to allow the PCH to start a COMRE-

SET initialization to the device. The options are Disabled and Enabled.

Port 0-Port 5 SATA Device Type

Use this item to specify if the SATA port specifi ed by the user should be con-

nected to a Solid State drive or a Hard Disk Drive. The options are Hard Disk

Drive and Solid State Drive.

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X10DRG-O(T)+-CPU User’s Manual



sSATA Confi guration

When this submenu is selected, the AMI BIOS automatically detects the
presence of the SATA devices that are supported by the PCH-sSATA
controller and displays the following items:

sSATA Controller

This item enables or disables the onboard SATA controller supported by the
Intel PCH-sSATA controller. The options are Enabled and Disabled.

Confi gure sSATA as

Select IDE to confi gure an sSATA drive specifi ed by the user as an IDE drive.
Select AHCI to confi gure an sSATA drive specifi ed by the user as an AHCI
drive. Select RAID to confi gure an sSATA drive specifi ed by the user as a
RAID drive. The options are IDE, AHCI, and RAID.

*If the item above "Confi gure sSATA as" is set to AHCI, the following items
will display:

Support Aggressive Link Power Management

When this item is set to Enabled, the SATA AHCI controller manages the

power usage of the SATA link. The controller will put the link to a low power
state when the I/O is inactive for an extended period of time, and the power
state will return to normal when the I/O becomes active. The options are
Disabled and Enabled.

sSATA Port 0-Port 3

This item displays the information detected on the installed on the sSATA
port. specifi ed by the user.

• Model number of drive and capacity

• Software preserve support

Port 0-Port 3 Hot Plug

Select Enabled to support Hot-plugging for the selected SATA port which will
allow the user to replace a device without shutting down the system. The
options are Disabled and Enabled.

sSATA Port 0-Port 3 Spin Up Device

On an edge detect from 0 to 1, set this item to allow the PCH to start a
COMRESET initialization to the device. The options are Disabled and
Enabled.

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Chapter 4: AMI BIOS

Port 0-Port 3 sSATA Device Type

Use this item to specify if the sSATA port specifi ed by the user should be
connected to a Solid State drive or a Hard Disk Drive. The options are Hard
Disk Drive and Solid State Drive.

*If the item above "Confi gure sSATA as" is set to IDE, the following items will
display:

sSATA Port 0-Port 3

This item indicates that an sSATA port specifi ed by the user is installed
(present) or not.

Port 0-Port 3 sSATA Device Type (Available when a SATA port is
detected)

Use this item to specify if the sSATA port specifi ed by the user should be
connected to a Solid State drive or a Hard Disk Drive. The options are Hard
Disk Drive and Solid State Drive.

*If the item above "Confi gure sSATA as" is set to RAID, the following items
will display:

Support Aggressive Link Power Management

When this item is set to Enabled, the SATA AHCI controller manages the
power usage of the SATA link. The controller will put the link to a low power
state when the I/O is inactive for an extended period of time, and the power
state will return to normal when the I/O becomes active. The options are
Disabled and Enabled.

sSATA RAID Option ROM/UEFI Driver

Select EFI to load the EFI driver for system boot. Select Legacy to load a
legacy driver for system boot. The options are Legacy, EFI, and Disabled

SATA/sSATA RAID Boot Select

Select SATA Controller to use a device supported by the SATA connector for
system boot. Select sSATA Controller to use a device supported by the sSATA
connector for system boot. The options are None, SATA Controller, sSATA

Controller, and Both.

sSATA Port 0 ~ Port 3

This item displays the information detected on the installed sSATA drives on the

particular sSATA port.

• Model number of drive and capacity

• Software preserve support

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X10DRG-O(T)+-CPU User’s Manual

Port 0-Port 3 Hot Plug

Select Enabled to support Hot-plugging for the selected SATA port which will
allow the user to replace a device without shutting down the system. The
options are Disabled and Enabled.

sSATA Port 0-Port 3 Spin Up Device

On an edge detect from 0 to 1, set this item to allow the PCH to start a COMRE-

SET initialization to the device. The options are Disabled and Enabled.

Port 0-Port 3 sSATA Device Type

Use this item to specify if the sSATA port specifi ed by the user should be con-

nected to a Solid State drive or a Hard Disk Drive. The options are Hard Disk

Drive and Solid State Drive.

Server ME (Management Engine) Confi guration

This feature displays the following system ME confi guration settings.

• Operational Firmware Version

• Recovery Firmware Version

• ME Firmware Features

• ME Firmware Status #1

• ME Firmware Status #2

• Current State

• Error Code

Altitude

This feature indicates the altitude of the platform this machine is located above the

sea level. The value is shown in meters. If the value is unknown, enter the number

"80000000."

MCTP (Management Component Transport Protocol) Bus Owner

This feature indicates the location of the MCTP Bus owner. Enter 0s to all fi elds to

disable the MCTP Bus owner.

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Chapter 4: AMI BIOS

PCIe/PCI/PnP Confi guration

PCI Devices Common Settings

PCI Latency Timer

Select Enabled to set the latency timer for PCI. The options are 32 PCI Bus Clocks,

64 PCI Bus Clocks, 96 PCI Bus Clocks, 128 PCI Bus Clocks, 160 PCI Bus Clocks,

192 PCI Bus Clocks, 224 PCI Bus Clocks, and 248 PCI Bus Clocks.

PERR# Generation

Select Enabled to support PERR (PCI/PCI-E Parity Error)/SERR (System Error)

runtime error reporting for a PCI/PCI-E slot. The options are Disabled and Enabled.

SERR# Generation

Select Enabled to support PERR (PCI/PCI-E Parity Error)/SERR (System Error)

runtime error reporting for a PCI/PCI-E slot. The options are Disabled and Enabled.

PCI PERR/SERR Support

Select Enabled to support PERR (PCI/PCI-E Parity Error)/SERR (System Error)

runtime error reporting for a PCI/PCI-E slot. The options are Disabled and Enabled.

Above 4G Decoding (Available if the system supports 64-bit PCI decoding)

Select Enabled to decode a PCI device that supports 64-bit in the space above 4G

Address. The options are Disabled and Enabled.

SR-IOV (Available if the system supports Single-Root Virtualization)

Select Enabled for Single-Root IO Virtualization support. The options are Disabled

and Enabled.

Maximum Payload

Select Auto for the system BIOS to automatically set the maximum payload value

for a PCI-E device to enhance system performance. The options are Auto, 128

Bytes, and 256 Bytes.

Maximum Read Request

Select Auto for the system BIOS to automatically set the maximum size for a read

request for a PCI-E device to enhance system performance. The options are Auto,

128 Bytes, 256 Bytes, 512 Bytes, 1024 Bytes, 2048 Bytes, and 4096 Bytes.

ASPM Support

Use this item to set the Active State Power Management (ASPM) level for a PCI-E

device. Select Auto for the system BIOS to automatically set the ASPM level based

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X10DRG-O(T)+-CPU User’s Manual

on the system confi guration. Select Disabled to disable ASPM support. The options

are Disabled and Auto.

Warning: Enabling ASPM support may cause some PCI-E devices to fail!

MMIOHBase

Use this item to select the base memory size according to memory-address map-

ping for the PCH. The base memory size must be between 4032G to 4078G. The

options are 56T, 48T, 24T, 2T, 512G, and 256G.

MMIO High Size

Use this item to select the high memory size according to memory-address mapping

for the PCH. The options are 256G, 128G, 512G, and 1024G.

PCI Device Option ROM Setting

CPU2 Slot 1 PCI-E x16 OPROM (Option ROM)

Select Enabled to enable Option ROM support to boot the computer using a device

installed on slot 1. The options are Disabled, Legacy, and EFI.

CPU2 Slot 2 PCI-E x16 OPROM (Option ROM)

Select Enabled to enable Option ROM support to boot the computer using a device

installed on slot 2. The options are Disabled, Legacy, and EFI.

CPU2 Slot 3 PCI-E x16 OPROM (Option ROM)

Select Enabled to enable Option ROM support to boot the computer using a device

installed on slot 3. The options are Disabled, Legacy, and EFI.

CPU2 Slot 4 PCI-E x16 OPROM (Option ROM)

Select Enabled to enable Option ROM support to boot the computer using a device

installed on slot 4. The options are Disabled, Legacy, and EFI.

CPU2 Slot 5 PCI-E x8 OPROM (Option ROM)

Select Enabled to enable Option ROM support to boot the computer using a device

installed on slot 5. The options are Disabled, Legacy, and EFI.

CPU1 Slot 6 PCI-E x8 OPROM (Option ROM)

Select Enabled to enable Option ROM support to boot the computer using a device

installed on slot 5. The options are Disabled, Legacy, and EFI.

CPU1 Slot 7 PCI-E x4 OPROM (Option ROM)

Select Enabled to enable Option ROM support to boot the computer using a device

installed on slot 5. The options are Disabled, Legacy, and EFI.

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Chapter 4: AMI BIOS

CPU1 Slot 8 PCI-E x16 OPROM (Option ROM)

Select Enabled to enable Option ROM support to boot the computer using a device

installed on slot 5. The options are Disabled, Legacy, and EFI.

CPU1 Slot 9 PCI-E x16 OPROM (Option ROM)

Select Enabled to enable Option ROM support to boot the computer using a device

installed on slot 5. The options are Disabled, Legacy, and EFI.

CPU1 Slot 10 PCI-E x16 OPROM (Option ROM)

Select Enabled to enable Option ROM support to boot the computer using a device

installed on slot 5. The options are Disabled, Legacy, and EFI.

CPU1 Slot 11 PCI-E x16 OPROM (Option ROM)

Select Enabled to enable Option ROM support to boot the computer using a device

installed on slot 5. The options are Disabled, Legacy, and EFI.

Onboard Video OPROM (Option ROM)

Select Enabled to enable Option ROM support to boot the computer using a de-

vice installed on the slot specifi ed by the user. The options are Disabled, Legacy,

and EFI.

VGA Priority

Use this item to select the graphics device to be used as the primary video display

for system boot. The options are Onboard and Offboard.

Onboard LAN Option ROM Type

Select Legacy to boot the computer using a Legacy device installed on the moth-

erboard. The options are Legacy and EFI.

Onboard LAN1 Option ROM/Onboard LAN2 Option ROM

Use this option to select the type of device installed in LAN Port1, LAN Port2

or the onboard video device used for system boot. The options for LAN1 Option

ROM are PXE, iSCSI, and Disabled, and the options for LAN2 Option ROM are

PXE and Disabled.

Network Stack

Select Enabled to enable PXE (Preboot Execution Environment) or UEFI (Uni-

fi ed Extensible Firmware Interface) for network stack support. The options are

Disabled and Enabled.

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X10DRG-O(T)+-CPU User’s Manual



Super IO Confi guration

Super IO Chip AST2400



Serial Port 1 Confi guration/Serial Port 2 Confi guration

Serial Port

Select Enabled to enable the onboard serial port specifi ed by the user. The options

are Disabled and Enabled.

Change Port 1 Settings/Change Port 2 Settings

This feature specifi es the base I/O port address and the Interrupt Request address

of Serial Port 1 or Serial Port 2. Select Auto for the BIOS to automatically assign

the base I/O and IRQ address to a serial port specifi ed.

The options for Serial Port 1 are Auto, (IO=3F8h; IRQ=4), (IO=3F8h; IRQ=3, 4, 5,

6, 7, 10, 11, 12), (IO=2F8h; IRQ=3, 4, 5, 6, 7, 10, 11, 12); (IO=3E8h; IRQ=3, 4, 5,

6, 7, 10, 11, 12), and (IO=2E8h; IRQ=3, 4, 5, 6, 7, 10, 11, 12).

The options for Serial Port 2 are Auto, (IO=2F8h; IRQ=3), (IO=3F8h; IRQ=3, 4, 5,

6, 7, 10, 11, 12), (IO=2F8h; IRQ=3, 4, 5, 6, 7, 10, 11, 12); (IO=3E8h; IRQ=3, 4, 5,

6, 7, 10, 11, 12), and (IO=2E8h; IRQ=3, 4, 5, 6, 7,10, 11, 12).

Serial Port 2 Attribute

Select SOL to use COM Port 2 as a Serial_Over_LAN (SOL) port for console redi-

rection. The options are SOL and COM.



Serial Port Console Redirection

COM 1

COM 1 Console Redirection

Select Enabled to enable COM Port 1 Console Redirection, which will allow a client

machine to be connected to a host machine at a remote site for networking. The

options are Disabled and Enabled.

*If the item above set to Enabled, the following items will become available for

confi guration:

COM1 Console Redirection Settings

Terminal Type

This feature allows the user to select the target terminal emulation type for Con-

sole Redirection. Select VT100 to use the ASCII Character set. Select VT100+ to

add color and function key support. Select ANSI to use the Extended ASCII Char-

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Chapter 4: AMI BIOS

acter Set. Select VT-UTF8 to use UTF8 encoding to map Unicode characters

into one or more bytes. The options are VT100, VT100+, VT-UTF8, and ANSI.

Bits per second

Use this item to set the transmission speed for a serial port used in Console

Redirection. Make sure that the same speed is used in the host computer and the

client computer. A lower transmission speed may be required for long and busy

lines. The options are 9600, 19200, 38400, 57600, and 115200 (bits per second).

Data Bits

Use this feature to set the data transmission size for Console Redirection. The

options are 7 (Bits) and 8 (Bits).

Parity

A parity bit can be sent along with regular data bits to detect data transmission

errors. Select Even if the parity bit is set to 0, and the number of 1's in data bits

is even. Select Odd if the parity bit is set to 0, and the number of 1's in data bits

is odd. Select None if you do not want to send a parity bit with your data bits

in transmission. Select Mark to add a mark as a parity bit to be sent along with

the data bits. Select Space to add a Space as a parity bit to be sent with your

data bits. The options are None, Even, Odd, Mark, and Space.

Stop Bits

A stop bit indicates the end of a serial data packet. Select 1 Stop Bit for standard

serial data communication. Select 2 Stop Bits if slower devices are used. The

options are 1 and 2.

Flow Control

Use this item to set the fl ow control for Console Redirection to prevent data

loss caused by buffer overfl ow. Send a "Stop" signal to stop sending data when

the receiving buffer is full. Send a "Start" signal to start sending data when the

receiving buffer is empty. The options are None and Hardware RTS/CTS.

VT-UTF8 Combo Key Support

Select Enabled to enable VT-UTF8 Combination Key support for ANSI/VT100

terminals. The options are Disabled and Enabled.

Recorder Mode

Select Enabled to capture the data displayed on a terminal and send it as text

messages to a remote server. The options are Disabled and Enabled.

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X10DRG-O(T)+-CPU User’s Manual

Resolution 100x31

Select Enabled for extended-terminal resolution support. The options are Dis-

abled and Enabled.

Legacy OS Redirection Resolution

Use this item to select the number of rows and columns used in Console Redi-

rection for legacy OS support. The options are 80x24 and 80x25.

Putty KeyPad

This feature selects Function Keys and KeyPad settings for Putty, which is a

terminal emulator designed for the Windows OS. The options are VT100, LINUX,

XTERMR6, SCO, ESCN, and VT400.

Redirection After BIOS Post

Use this feature to enable or disable legacy Console Redirection after BIOS

POST. When the option BootLoader is selected, legacy Console Redirection is

disabled before booting the OS. When Always Enable is selected, legacy Console

Redirection remains enabled upon OS bootup. The options are Always Enable

and BootLoader.

SOL/COM2 Console Redirection

SOL/COM2 Console Redirection

Select Enabled to use the SOL/COM2 port for Console Redirection. The options

are Disabled and Enabled.

*If the item above is set to Enabled, the following items will become available for

user's confi guration:

SOL/COM2 Console Redirection Settings

Use this feature to specify how the host computer will exchange data with the client

computer, which is the remote computer used by the user.

Terminal Type

Use this feature to select the target terminal emulation type for Console Redirec-

tion. Select VT100 to use the ASCII Character set. Select VT100+ to add color

and function key support. Select ANSI to use the Extended ASCII Character Set.

Select VT-UTF8 to use UTF8 encoding to map Unicode characters into one or

more bytes. The options are VT100, VT100+, VT-UTF8, and ANSI.

4-30