Supermicro X10DRG-H, X10DRG-HT User Manual

USER’S MANUAL

Revision 1.0c

X10DRG-H

X10DRG-HT

Manual Revision 1.0c

Release Date: Feb. 27, 2015

Unless you request and receive written permission from Super Micro Computer, Inc., you may not
copy any part of this document.

Information in this document is subject to change without notice. Other products and companies
referred to herein are trademarks or registered trademarks of their respective companies or mark
holders.

Copyright © 2015 by Super Micro Computer, Inc.
All rights reserved.

Printed in the United States of America

The information in this user’s manual has been carefully reviewed and is believed to be accurate.
The vendor assumes no responsibility for any inaccuracies that may be contained in this document,
and makes no commitment to update or to keep current the information in this manual, or to notify
any person or organization of the updates. Please Note: For the most up-to-date version of this

manual, please see our website at www.supermicro.com.

Super Micro Computer, Inc. ("Supermicro") reserves the right to make changes to the product
described in this manual at any time and without notice. This product, including software and docu­mentation, is the property of Supermicro and/or its licensors, and is supplied only under a license.
Any use or reproduction of this product is not allowed, except as expressly permitted by the terms
of said license.

IN NO EVENT WILL SUPER MICRO COMPUTER, INC. BE LIABLE FOR DIRECT, INDIRECT,
SPECIAL, INCIDENTAL, SPECULATIVE OR CONSEQUENTIAL DAMAGES ARISING FROM THE
USE OR INABILITY TO USE THIS PRODUCT OR DOCUMENTATION, EVEN IF ADVISED OF
THE POSSIBILITY OF SUCH DAMAGES. IN PARTICULAR, SUPER MICRO COMPUTER, INC.
SHALL NOT HAVE LIABILITY FOR ANY HARDWARE, SOFTWARE, OR DATA STORED OR USED
WITH THE PRODUCT, INCLUDING THE COSTS OF REPAIRING, REPLACING, INTEGRATING,
INSTALLING OR RECOVERING SUCH HARDWARE, SOFTWARE, OR DATA.

Any disputes arising between the manufacturer and the customer shall be governed by the laws of
Santa Clara County in the State of California, USA. The State of California, County of Santa Clara
shall be the exclusive venue for the resolution of any such disputes. Supermicro's total liability for
all claims will not exceed the price paid for the hardware product.

FCC Statement: This equipment has been tested and found to comply with the limits for a Class
A digital device pursuant to Part 15 of the FCC Rules. These limits are designed to provide
reasonable protection against harmful interference when the equipment is operated in a commercial
environment. This equipment generates, uses, and can radiate radio frequency energy and, if not
installed and used in accordance with the manufacturer’s instruction manual, may cause harmful
interference with radio communications. Operation of this equipment in a residential area is likely
to cause harmful interference, in which case you will be required to correct the interference at your
own expense.

California Best Management Practices Regulations for Perchlorate Materials: This Perchlorate
warning applies only to products containing CR (Manganese Dioxide) Lithium coin cells. “Perchlorate
Material-special handling may apply. See www.dtsc.ca.gov/hazardouswaste/perchlorate”.

WARNING: Handling of lead solder materials used in this
product may expose you to lead, a chemical known to
the State of California to cause birth defects and other
reproductive harm.

Preface

This manual is written for system integrators, IT professionals, and

knowledgeable end users. It provides information for the installation and use of the

X10DRG-H/X10DRG-HT motherboard.

About This Motherboard

The Super X10DRG-H(T) motherboard supports dual Intel E5-2600v3 series pro-

cessors (Socket R3) that offer the new Intel Microarchitecture 22nm Processing

Technology, delivering the most balanced solution of performance, power efciency,

and features to address the diverse needs of next-generation data centers. With

the PCH C612 built in, the X10DRG-H(T) motherboard supports Intel® Manage-

ment Engine, Intel® Node Manager 3.0, and 2133 MHz (max.) DDR4 memory. This

motherboard is optimized for high-performance, high-density 6GPU 1U/2U server

platforms. Please refer to our website (http://www.supermicro.com) for CPU and

memory support updates.

Manual Organization

Chapter 1 describes the features, specications and performance of the moth-

erboard. It also provides detailed information about the Intel PCH C612 chipset.

Chapter 2 provides hardware installation instructions. Read this chapter when in-

stalling the processor, memory modules and other hardware components into the

system. If you encounter any problems, see Chapter 3, which describes trouble-

shooting procedures for video, memory, and system setup stored in the CMOS.

Chapter 4 includes an introduction to BIOS, and provides detailed information on

running the BIOS setup utility.

Appendix A provides BIOS error beep codes.

Appendix B lists software Installation Instructions.

Appendix C contains UEFI BIOS recovery instructions.

Preface

iii

iv

Conventions Used in the Manual

Pay special attention to the following symbols for proper system installation:

Warning: Important information given to ensure proper system installation or to prevent

damage to the components or injury to yourself;

Note: Additional information given to differentiate between models or

instructions provided for proper system setup.

X10DRG-H/X10DRG-HT Motherboard User’s Manual

Preface

v

Contacting Supermicro

Headquarters

Address: Super Micro Computer, Inc.

980 Rock Ave.

San Jose, CA 95131 U.S.A.

Tel: [phone]

Fax: [phone]

Email: [e-mail] (General Information)

[e-mail] (Technical Support)

Website: www.supermicro.com

Europe

Address: Super Micro Computer B.V.

Het Sterrenbeeld 28, 5215 ML

's-Hertogenbosch, The Netherlands

Tel: [phone]

Fax: [phone]

Email: [e-mail] (General Information)

[e-mail] (Technical Support)

[e-mail] (Customer Support)

Website: www.supermicro.nl

Asia-Pacic

Address: Super Micro Computer, Inc.

3F, No. 150, Jian 1st Rd.

Zhonghe Dist., New Taipei City 235

Taiwan (R.O.C)

Tel: [phone]

Fax: [phone]

Email: [e-mail]

Website: www.supermicro.com.tw

vi

Table of Contents

Preface

Chapter 1 Overview

1-1 Overview ......................................................................................................... 1-1

1-2 Processor and Chipset Overview...................................................................1-11

1-3 Special Features ........................................................................................... 1-12

1-4 System Health Monitoring ............................................................................. 1-12

1-5 ACPI Features ............................................................................................... 1-13

1-6 Power Supply ................................................................................................ 1-13

1-7 Advanced Power Management ..................................................................... 1-14

Intel® Intelligent Power Node Manager (NM) (Available when the Supermicro

Power Manager [SPM] is Installed) .............................................................. 1-14

Management Engine (ME) ............................................................................ 1-14

Chapter 2 Installation

2-1 Standardized Warning Statements ................................................................. 2-1

2-2 Static-Sensitive Devices .................................................................................. 2-4

2-3 Motherboard Installation .................................................................................. 2-5

2-4 Processor and Heatsink Installation................................................................ 2-7

Installing the LGA2011 Processor ................................................................. 2-7

Installing a Passive CPU Heatsink ................................................................2-11

Removing the Heatsink ................................................................................. 2-12

2-5 Installing and Removing the Memory Modules ............................................. 2-13

Installing & Removing DIMMs ....................................................................... 2-13

Removing Memory Modules ......................................................................... 2-13

2-6 Control Panel Connectors and I/O Ports ...................................................... 2-16

Back Panel Connectors and I/O Ports .......................................................... 2-16

Back Panel I/O Port Locations and Denitions ........................................... 2-16

Video Connection ..................................................................................... 2-17

Ethernet Ports .......................................................................................... 2-17

Universal Serial Bus (USB) ...................................................................... 2-18

Unit Identier Switches/UID LED Indicators ............................................. 2-19

Front Control Panel ....................................................................................... 2-20

Front Control Panel Pin Denitions............................................................... 2-21

NMI Button ............................................................................................... 2-21

Power LED .............................................................................................. 2-21

HDD/UID LED .......................................................................................... 2-22

NIC1/NIC2 LED Indicators ....................................................................... 2-22

Overheat (OH)/Fan Fail/PWR Fail/UID LED ............................................ 2-23

X10DRG-H/X10DRG-HT Motherboard User’s Manual

vii

Table of Contents

Power Fail LED ........................................................................................ 2-23

Reset Button ........................................................................................... 2-24

Power Button ........................................................................................... 2-24

2-7 Connecting Cables ........................................................................................ 2-25

Power Connectors ................................................................................... 2-25

Fan Headers ............................................................................................. 2-26

Internal Speaker ....................................................................................... 2-27

TPM/Port 80 Header ................................................................................ 2-27

I-SGPIO1/2/3 Headers ............................................................................. 2-28

Standby Power Header ............................................................................ 2-28

Serial Port Header .................................................................................... 2-29

Chassis Intrusion ..................................................................................... 2-29

2-8 Jumper Settings ............................................................................................ 2-30

Explanation of Jumpers ................................................................................ 2-30

LAN Enable/Disable ................................................................................. 2-30

CMOS Clear ............................................................................................. 2-31

Watch Dog Enable/Disable ...................................................................... 2-31

VGA Enable .............................................................................................. 2-32

BMC Enable ............................................................................................ 2-32

Manufacturer Mode Select ....................................................................... 2-33

2-9 Onboard LED Indicators ............................................................................... 2-34

LAN LEDs ................................................................................................. 2-34

IPMI Dedicated LAN LEDs ....................................................................... 2-34

Onboard Power LED ............................................................................... 2-35

BMC Heartbeat LED ................................................................................ 2-35

2-10 SATA Connections ......................................................................................... 2-36

SATA 3.0 Ports ......................................................................................... 2-36

Chapter 3 Troubleshooting

3-1 Troubleshooting Procedures ........................................................................... 3-1

3-2 Technical Support Procedures ........................................................................ 3-4

3-3 Battery Removal and Installation .................................................................... 3-6

3-4 Frequently Asked Questions ........................................................................... 3-7

3-5 Returning Merchandise for Service................................................................. 3-8

Chapter 4 BIOS

4-1 Introduction ...................................................................................................... 4-1

4-2 Main Setup ...................................................................................................... 4-2

4-3 Advanced Setup Congurations...................................................................... 4-4

4-4 Event Logs .................................................................................................... 4-30

viii

4-5 IPMI ............................................................................................................... 4-32

4-6 Security Settings ........................................................................................... 4-34

4-7 Boot Settings ................................................................................................. 4-35

4-8 Save & Exit ................................................................................................... 4-38

Appendix A BIOS Error Beep Codes

A-1 BIOS Error Beep Codes .................................................................................A-1

Appendix B Software Installation Instructions

B-1 Installing Software Programs ..........................................................................B-1

B-2 Conguring SuperDoctor 5 .............................................................................B-2

Appendix C UEFI BIOS Recovery Instructions

C-1 An Overview to the UEFI BIOS ......................................................................C-1

C-2 How to Recover the UEFI BIOS Image (-the Main BIOS Block)....................C-1

C-3 To Recover the Main BIOS Block Using a USB-Attached Device..................C-1

X10DRG-H/X10DRG-HT Motherboard User’s Manual

Chapter 1: Overview

1-1

Chapter 1

Overview

1-1 Overview

Checklist

Congratulations on purchasing your computer motherboard from an acknowledged

leader in the industry. Supermicro boards are designed with the utmost attention to

detail to provide you with the highest standards in quality and performance.

The X10DRG-H/HT motherboard was designed to be used with a Supermicro-

proprietary chassis as an integrated server platform. It is not to be used as a stand-

alone product and will not be shipped independently in a retail box. No motherboard

shipping package will be provided in your shipment.

Note 1: For your system to work properly, please follow the links below

to download all necessary drivers/utilities and the user's manual for your

motherboard.

•Supermicro product manuals: http://www.supermicro.com/support/manuals/

•Product Drivers and utilities: ftp://ftp.supermicro.com/

Note 2: For safety considerations, please refer to the complete list of

safety warnings posted on the Supermicro website at Safety: http://www.

supermicro.com/about/policies/safety_information.cfm (the US).

If you have any questions, please contact our support team at support@supermicro.

com.

1-2

X10DRG-H/X10DRG-HT Motherboard User’s Manual

X10DRG-H(T) Motherboard Image

Note: All graphics shown in this manual were based upon the latest PCB

Revision available at the time of publishing of the manual. The motherboard

you've received may or may not look exactly the same as the graphics

shown in this manual.

Chapter 1: Overview

1-3

X10DRG-H(T) Motherboard Layout

Note: For the latest CPU/Memory updates, please refer to our website at

http://www.supermicro.com/products/motherboard/ for details.

BIOS
LICENSE

BAR CODE

MAC CODE

JPW1

1 1

1

1

JPP0

JITP1

JSPK1

BT1

JTPM1

P1 DIMMA1

P1 DIMMA2

P1 DIMMB2

P1 DIMMB1

CPU1

CPU1 SLOT1 PCI-E 3.0 X16

USB2/3(3.0)

CPU2 SLOT2 PCI-E 3.0 X16

CPU1 SLOT3 PCI-E 3.0 X16

CPU2 SLOT4 PCI-E 3.0 X16

USB4/5 (3.0)

CPU2 SLOT5 PCI-E 3.0 X8 INX16

LAN1LAN2

USB0/1

JPL1

JPF1

JPF2

JPME2

JVRM1

JVRM2

VGA

JPG1

JPB1

JPCIE1_1

JWD1

LE4

SW1

JSTBY1

BIOS

JPCIE1_3

JBR1

JBT1

I-SATA0

I-SATA1

I-SATA3

I-SATA4I-SATA5

I-SATA2

S-SATA0

S-SATA2

S-SATA3

COM1

JPW6

FANCFAND

JPC1

P1 DIMMD2

P1 DIMMD1

P1 DIMMC1

P1 DIMMC2

S-SATA1

JPP1

JPW2

JPW7

FANH

FANF

FANE

FAN1

P2 DIMMF2

P2 DIMMF1

P2 DIMME1

P2 DIMME2

FAN2

FAN3

FAN4

FANA

FANB

JPW3

JPW4

JPW5

JL1

T-SGPIO1

T-SGPIO2

T-SGPIO3

LE2

JF1

Front Control Panel

J23

FANG

CLOSE 1st

OPEN 1st

CLOSE 1st

OPEN 1st

CPU2

P2 DIMMG1

P2 DIMMG2

P2 DIMMH2

P2 DIMMH1

X10DRG-H

Rev. 1.02

PCH

LAN
CTRL

BMC

IPMI_LAN

JOH1

LEDM1

1-4

X10DRG-H/X10DRG-HT Motherboard User’s Manual

X10DRG-H(T) Quick Reference

Notes:

•See Chapter 2 for detailed information on jumpers, I/O ports and JF1 front

panel connections.

•" " indicates the location of "Pin 1".

•Jumpers/LED Indicators not indicated are for internal testing only.

•Use only the correct type of onboard CMOS battery as specied by the manufac-

turer. Do not install the onboard battery upside down to avoid possible explosion.

BIOS
LICENSE

BAR CODE

MAC CODE

JPW1

1 1

1

1

JPP0

JITP1

JSPK1

BT1

JTPM1

P1 DIMMA1

P1 DIMMA2

P1 DIMMB2

P1 DIMMB1

CPU1

CPU1 SLOT1 PCI-E 3.0 X16

USB2/3(3.0)

CPU2 SLOT2 PCI-E 3.0 X16

CPU1 SLOT3 PCI-E 3.0 X16

CPU2 SLOT4 PCI-E 3.0 X16

USB4/5 (3.0)

CPU2 SLOT5 PCI-E 3.0 X8 INX16

LAN1LAN2

USB0/1

JPL1

JPF1

JPF2

JPME2

JVRM1

JVRM2

VGA

JPG1

JPB1

JPCIE1_1

JWD1

LE4

SW1

JSTBY1

BIOS

JPCIE1_3

JBR1

JBT1

I-SATA0

I-SATA1

I-SATA3

I-SATA4I-SATA5

I-SATA2

S-SATA0

S-SATA2

S-SATA3

COM1

JPW6

FANCFAND

JPC1

P1 DIMMD2

P1 DIMMD1

P1 DIMMC1

P1 DIMMC2

S-SATA1

JPP1

JPW2

JPW7

FANH

FANF

FANE

FAN1

P2 DIMMF2

P2 DIMMF1

P2 DIMME1

P2 DIMME2

FAN2

FAN3

FAN4

FANA

FANB

JPW3

JPW4

JPW5

JL1

T-SGPIO1

T-SGPIO2

T-SGPIO3

LE2

JF1

Front Control Panel

J23

FANG

CLOSE 1st

OPEN 1st

CLOSE 1st

OPEN 1st

CPU2

P2 DIMMG1

P2 DIMMG2

P2 DIMMH2

P2 DIMMH1

X10DRG-H

Rev. 1.02

PCH

LAN
CTRL

BMC

IPMI_LAN

JOH1

LEDM1

Chapter 1: Overview

1-5

X10DRG-H(T) Jumpers

Jumper Description Default Setting

JBT1 Clear CMOS/Reset BIOS Conguration See Chapter 2

JPB1 BMC Enable Pins 1-2 (Enabled)

JPG1 VGA Enable Pins 1-2 (Enabled)

JPL1 GLAN1/GLAN2 Enable (X10DRG-H)

10_GLAN1/10G_LAN2 Enable (X10DRG-HT)

Pins 1-2 (Enabled)

JPME2 Manufacture (ME) Mode Select Pins 1-2 (Normal)

JWD1 Watch-Dog Timer Enable Pins 1-2 (Reset)

X10DRG-H(T) Connectors

Connectors Description

Battery (BT1) Onboard CMOS Battery (See Chpt. 3 for used battery dis-

posal)

COM1 Backplane COM port

FAN 1/2/3/4, FAN
A/B/C/D/E/F/G/H

CPU/System fan headers (Fan 1-4, Fan A-H)

JF1 Front_Panel_Control header

JL1 Chassis intrusion header

JPC1 3-pin header

JPCIE1_1 SMC-proprietary SPEC Slot 1 (See Note 1 on Page 1-6.)

JPCIE1_3 SMC-proprietary SPEC Slot 1 (See Note 1 on Page 1-6.)

JPW1 SMCI-proprietary main power connector

JPW2 9-pin power header for motherboard power use

JPW3/JPW4/JPW5/
JPW6/JPW7

12V 8-Pin power connection headers used for HDD back­plane (BPN) or GPU add-on cards

JSPK1 Internal buzzer/speaker

JSTBY1 Standby power connector

JTPM1 TPM (Trusted Platform Module)/Port 80 header

LAN1/LAN2 G-bit Ethernet (GLAN) ports 1/2 (for X10DRG-H)

10 G-bit Ethernet (GLAN) ports 1/2 (for X10DRG-HT)

(IPMI)_LAN IPMI_Dedicated LAN support by the ASpeed controller

(I-)SATA 0-5 Intel SATA 3.0 connectors (0-5) from Intel PCH (I-SATA4/5

support Supermicro SuperDOMs [Devices-on-Module] with
power pins builtin)

(S)-SATA0-3 SATA connectors (0-3) from Intel SCU

T-SGPIO1/2/3 Seria_Link General-Purpose I/O (SGPIO) headers for I-

SATA connections (I-SGPIO1 for I-SATA0-3, I-SGPIO2 for
I-SATA4/5, I-SGPIO3 for S-SATA0-3)

(CPU1) SLOT1/3 PCI-Exp. 3.0 x16 Slot1/Slot3 supported by CPU1

(CPU2) SLOT2/4 PCI-Exp. 3.0 x16 Slot2/Slot4 supported by CPU2

1-6

X10DRG-H/X10DRG-HT Motherboard User’s Manual

(CPU2) SLOT5 PCI-Exp. 3.0 x8 in x16 slot supported by CPU2

SW1 UID Switch

(BP) USB 4/5 (3.0) Backpanel USB 3.0 Port 4/Port 5

(FP) 2/3 (3.0) Front-Accessible USB 3.0 header for two USB connections

USB 2/3

(FP) USB 0/1 (2.0) Front-Accessible USB 2.0 header for two USB connections

USB 0/1

VGA Backpanel VGA port

X10DRG-H(T) LED Indicators

LED Description State Status

LE4 Rear UID LED Blue: On Unit Identied

LE2 Onboard PWR LED On System Power On

LEDM1 BMC Heartbeat LED Green: Blinking BMC Normal

Note 1: For JPCIE1-1/JPCIE1-3 PCI-Exp. slots to work properly, please

use SMC-proprietary riser cards (eg. RSC-RIUW-2E16) in the slots.

Note 2: For the latest CPU/memory updates, please refer to our website

at http://www.supermicro.com/products/motherboard.

Warning! To avoid damaging the power supply or the motherboard, be sure to connect

the power supply to the SMCI-proprietary power (JPW1), the 9-pin power (JPW2), and

all ve 8-pin power connection headers (JPW3-JPW7) on the motherboard. Failure in

doing so may void the manufacturer warranty on your power supply and motherboard.

Chapter 1: Overview

1-7

Motherboard Features

CPU

• Dual Intel

®

E5-2600v3 Series Processors (Socket R3)

(LGA 2011); each processor supports dual full-width

Intel QuickPath Interconnect (QPI) links (of up to 9.6

GT/s one direction per QPI)

Memory

• Integrated memory controller supports DDR4 288-pin

memory modules: up to 1024 GB of Load Reduced

(LRDIMM), and up to 512 GB Registered (RDIMM)

ECC 2133/1866/1600 MHz in 16 slots

Note: Memory speed support is pending on

the CPUs used in the motherboard. For the

latest CPU/memory updates, please refer to

our website at http://www.supermicro.com/

products/motherboard.

DIMM sizes

• DIMM Up to 64GB @ 1.2V

Chipset

• Intel® PCH C612

Expansion

• Four (4) PCI-E 3.0 x16 slots (Slot1/Slot3: supported

by CPU1, Slot2/Slot4: supported by CPU2)

• One (1) PCI-E 3.0 x8 in x16 slot (Slot5: supported

by CPU2)

• Two (2) SMC-proprietary SPEC slots (JPCIE1_1/3)

(See Note 1 on Page 1-6.)

Slots

Graphics

• Graphics controller via the ASpeed AST2400 BMC

Network

• Intel i350 Gigabit (10/100/1000 Mb/s) Ethernet con-

troller for LAN 1/LAN 2 ports (X10DRG-H only),

• Intel X540 10_Gigabit Ethernet controller for LAN 1/

LAN 2 ports (X10DRG-HT only)

• ASpeed 2400 Baseboard Controller (BMC) supports

IPMI_LAN 2.0

I/O Devices

SATA Connections

• SATA Ports Ten (10) SATA 3.0 ports (I-SATA

0-5, S-SATA0-3),

Note: I-SATA4/5: support Super-

micro's SuperDOMs (Devices-on-

Module) with built-in power pins

• RAID RAID 0, 1, 10

IPMI 2.0

• IPMI 2.0 supported by ASpeed AST 2400

1-8

X10DRG-H/X10DRG-HT Motherboard User’s Manual

Serial (COM) Port Header

• One (1) Fast UART 16550 port Header

Peripheral
Devices

USB Devices

• Two (2) USB 3.0 ports on the rear I/O panel (USB 4/5)

• One (1) USB 3.0 headers for two USB 3.0 front-

accessible connections (USB 2/3)

• One (1) USB 2.0 headers for two USB 3.0 front-

accessible connections (USB 0/1

BIOS

• 128Mb SPI AMI BIOS

®

SM Flash UEFI BIOS

• APCI 2.3, ACPI 2.0/3.0/4.0, USB keyboard, Plug &

Play (PnP) and SMBIOS 2.3

Power

• ACPI power management

Management

• Main switch override mechanism

• Power-on mode for AC power recovery

• Intel

®

Intelligent Power Node Manager 3.0 (Avail-

able when the Supermicro Power Manager [SPM] is

installed and special power supply is used.)

• Management Engine (ME)

System
Health

System Health/CPU Monitoring

Monitoring

• Onboard voltage monitoring for +1.2V, +3.3V, 3.3V

standby, +5V, +5V standby, CPU core, memory,

chipset, BMC, and battery voltages

• CPU/System overheat LED and control

• CPU Thermal Trip support

• Status Monitor for speed control

• Status Monitor for On/Off control

Fan Control

• Fan status monitoring via IPMI connections

• Dual Cooling Zone

• Low noise fan speed control

• Pulse Width Modulation (PWM) fan control

System
Management

• PECI (Platform Environment Conguration Interface)

2.0 support

• UID (Unit Identication)/Remote UID

• System resource alert via SuperDoctor 5

• SuperDoctor® 5, Watch Dog, NMI

Chapter 1: Overview

1-9

• Chassis Intrusion header and detection

Dimensions

• 19.80" (L) x 9.20" (W) (502.92 mm x 233.68 mm)

1-10

X10DRG-H/X10DRG-HT Motherboard User’s Manual

System Block Diagram

Note: This is a general block diagram and may not represent the features

on your motherboard. See the "Motherboard Features" pages for the actual

specications of each motherboard.

SPI

LAN3

RGRMII

Debug Card

FRONT PANEL

SYSTEM POWER

CTRL

FAN SPEED

PCI-E X1 G2

USB 2.0

#12 USB2.0

#6/7/8

PCH

6.0 Gb/S

LPC

#1

#0

SATA

#5

#4

RTL8211E-VB-CG

#3

#2

RJ45

BIOS

SPI

SPI

Temp Sensor
EMC1402-1 *2 at diff SMBUS

TPM HEADER

USB 3.0

BIOS
HEADER

SPI

AST2400

BMC

#3

#2

#5

RMII/NCSI

COM
Header

VGA CONN

BMC Boot Flash

DDR3

SLOT 1

5 PHASE
145W

P1

P1

P0

VR12.5

P0

QPI

9.6G

SLOT 3

PCI-E X16 G3

DMI2

PCI-E X16

PCI-E X16 G3 (LAN REVERSE)

DDR4

DMI2

QPI

9.6G

4GB/s

5 PHASE
145W

VR12.5

PCI-E X16

#3

I350/X540

LAN

PCI-E X8

SLOT 4

PCI-E X16

PCI-E X16

SLOT2

PCI-E X8

PCI-EX8 G3(w/ Re-driver)

PCI-EX16 G3(LAN REVERSE)

PCI-EX16 G3

#1 #2 #3

#2 #1

#6

#7

#8

#9

<=1.758W (average)

2.3W (Peak)

MAX:12.5W
STBY:2.5W

TDP:6.5W (WORKSTATION)
5W (SERVER)
USB & SATA useage different

Idle:0.45W

5V:1.2A

3.3V:0.1A

3.3 STBY:0.2A

1.05 PCH

1.05 ASW

1.5 PCH

PVCCIO 1.0/0.95

3.3STBY:0.5A

VCCP1 12v

VCCP0 12v

PVCCIO
(1.05/0.95)
from 3.3v

P5V_AUX
PX2V5_I3V3
PX1V2_I1V8
PX0V8_I1V0
PX0V67_I1V0

P3V3_STBY
P1V5_AUX_BMC
P1V2_AUX_BMC

P3V3_PCH
P1V5_PCH 3.3v
P1V05_PCH 5v
P1V05_STBY 3.3v STBY

Sagevill: 9W

Processor 1

Processor 2

SLOT5

DMI2

DDR4

up to 2133

DDR4

#1-4

#1-3

#1-2

#1-1

#1-5

#1-6

#1-7

#1-8

#2-1

#2-2

#2-3

#2-4

#2-5

#2-6

#2-7

#2-8

up to 2133

DDR4

SATA

USB

SATA

Chapter 1: Overview

1-11

1-2 Processor and Chipset Overview

Built upon the functionality and capability of the Intel E5-2600v3 Series processors

(Socket R3) and the Intel C612 PCH, the X10DRG-H(T) motherboard provides the

best balanced solution for high-performance, high-density 6GPU 1U/2U server

platforms.

With support of the new Intel Microarchitecture 22nm Processing Technology,

the X10DRG-H(T) dramatically increases system performance for a multitude of

server applications.

The PCH C612 chip provides Enterprise SMbus and MCTP support with the fol-

lowing features included:

•DDR4 288-pin memory support

•Support for MCTP protocol and ME

•Support of SMBus speeds of up to 1 MHz for BMC connectivity

•Improved I/O capabilities to high-storage-capacity congurations

•SPI Enhancements

•Intel® Node Manager 3.0

•BMC supports remote management, virtualization, and the security package

for enterprise platforms

Note: Node Manager 3.0 support is dependent on the power supply used

in the system.

1-12

X10DRG-H/X10DRG-HT Motherboard User’s Manual

1-3 Special Features

Recovery from AC Power Loss

The Basic I/O System (BIOS) provides a setting that determines how the system will

respond when AC power is lost and then restored to the system. You can choose for

the system to remain powered off (in which case you must press the power switch

to turn it back on), or for it to automatically return to the power-on state. See the

Advanced BIOS Setup section for this setting. The default setting is Last State.

1-4 System Health Monitoring

This section describes the features of system health monitoring of the motherboard.

This motherboard has an onboard Baseboard Management Controller (BMC) that

monitors system health and scan the following onboard voltages continuously:

+1.2V, +3.3V, 3.3V standby, +5V, +5V standby, CPU core, memory, chipset, BMC,

and battery voltages. Once a voltage becomes unstable, a warning is given, or an

error message is sent to the screen. The user can adjust the voltage thresholds to

dene the sensitivity of the voltage monitoring.

Fan Status Monitor with Firmware Control

The system health monitoring support provided by the BMC controller can check

the RPM status of a cooling fan. The onboard CPU and chassis fan speeds are

controlled via the IPMI 2.0.

Environmental Temperature Control

A thermal control sensor in the BMC monitors the CPU temperature in real time

and will turn on the thermal control fan whenever the CPU temperature exceeds a

user-dened threshold. Once it detects that the CPU temperature is too high, it will

automatically turn on the thermal fan control to prevent the CPU from overheating.

Note: To avoid possible system overheating, please be sure to provide

adequate airow to your system.

System Resource Alert

This feature is available when used with SuperDoctor 5. SuperDoctor 5 is used

to notify the user of certain system events. For example, you can congure

SuperDoctor 5 to provide you with warnings when the system temperature, CPU

temperatures, voltages, and fan speeds go beyond a predened range.

Chapter 1: Overview

1-13

1-5 ACPI Features

ACPI stands for Advanced Conguration and Power Interface. The ACPI specica-

tion denes a exible and abstract hardware interface that provides a standard

way to integrate power management features throughout a PC system, including

its hardware, operating system and application software. This enables the system

to automatically turn on and off peripherals such as network cards, hard disk drives

and printers.

In addition to operating system-directed power management, ACPI also provides

a generic system event mechanism for Plug and Play, and an operating system-

independent interface for conguration control. ACPI leverages the Plug and Play

BIOS data structures, while providing a processor architecture-independent imple-

mentation that is compatible with Windows 8/R2 and Windows 2012/R2 operating

systems.

1-6 Power Supply

As with all computer products, a stable power source is necessary for proper and

reliable operation. It is even more important for processors that have high CPU

clock rates.

The X10DRG-H(T) motherboard accommodates SMCI-proprietary main power

(JPW1), a 9-pin power (JPW2), and ve 8-pin 12V power connections (JPW3/JPW4/

JPW5/JPW6/JPW7). The 9-pin power connection header located at JPW2 is used

to supply power to the motherboard, and the 8-pin power connections located at

JPW3-JPW7 are used for HDD backplane and GPU add-on cards. Be sure to con-

nect all these power connection headers to your power supply to ensure adequate

power supply to your system. Although most power supplies generally meet the

specications required by the CPU, some are inadequate. To ensure adequate

power supply to the system, the main power (JPW1), the 9-pin power (JPW2), and

all ve 12V 8-pin power connections (JPW3-JPW7) are required.

Warning! To avoid damaging the power supply or the motherboard, be sure to con-

nect the power supply to the SMCI-proprietary power (JPW1), the 9-pin power header

(JPW2), and all ve 8-pin power connections (JPW3-JPW7) on the motherboard.

Failure in doing so may void the manufacturer warranty on your power supply and

motherboard.

1-14

X10DRG-H/X10DRG-HT Motherboard User’s Manual

1-7 Advanced Power Management

The following new advanced power management features are supported by this

motherboard:

Intel® Intelligent Power Node Manager (NM) (Available
when the Supermicro Power Manager [SPM] is Installed)

The Intel® Intelligent Power Node Manager 3.0 (IPNM) provides your system with

real-time thermal control and power management for maximum energy efciency.

Although IPNM Specication Version 2.0/3.0 is supported by the BMC (Baseboard

Management Controller), your system must also have IPNM-compatible Manage-

ment Engine (ME) rmware installed to use this feature.

Note: IPNM support is dependent on the power supply used in the system.

Management Engine (ME)

Management Engine, an ARC controller embedded in the PCH, provides Server

Platform Services (SPS) support to your system. The services provided by SPS are

different from those provided by the ME on client platforms.

Chapter 2: Installation

2-1

Chapter 2

Installation

2-1 Standardized Warning Statements

The following statements are industry-standard warnings, provided to warn the user

of situations which have the potential for bodily injury. Should you have questions or

experience difculty, contact Supermicro's Technical Support department for assis-

tance. Only certied technicians should attempt to install or congure components.

Read this section in its entirety before installing or conguring components in the

Supermicro chassis.

Battery Handling

Warnung

Bei Einsetzen einer falschen Batterie besteht Explosionsgefahr. Ersetzen Sie die

Batterie nur durch den gleichen oder vom Hersteller empfohlenen Batterietyp.

Entsorgen Sie die benutzten Batterien nach den Anweisungen des Herstellers.

Warning!

There is a danger of explosion if the battery is replaced incorrectly. Replace the

battery only with the same or equivalent type recommended by the manufacturer.

Dispose of used batteries according to the manufacturer's instructions

電池の取り扱い

電池交換が正しく行われなかった場合、破裂の危険性があります。 交換する電池はメー
カーが推奨する型、または同等のものを使用下さい。 使用済電池は製造元の指示に従

って処分して下さい。

警告
电池更换不当会有爆炸危险。请只使用同类电池或制造商推荐的功能相当的电池更
换原有电池。请按制造商的说明处理废旧电池。

警告
電池更換不當會有爆炸危險。請使用製造商建議之相同或功能相當的電池更換原有
電池。請按照製造商的說明指示處理廢棄舊電池。

2-2

X10DRG-H/X10DRG-HT Motherboard User’s Manual

Attention

Danger d'explosion si la pile n'est pas remplacée correctement. Ne la remplacer

que par une pile de type semblable ou équivalent, recommandée par le fabricant.

Jeter les piles usagées conformément aux instructions du fabricant.

¡Advertencia!

Existe peligro de explosión si la batería se reemplaza de manera incorrecta. Re-

emplazar la batería exclusivamente con el mismo tipo o el equivalente recomen-

dado por el fabricante. Desechar las baterías gastadas según las instrucciones

del fabricante.

!הרהזא

תנכס תמייקץוציפ .הניקת אל ךרדב הפלחוהו הדימב הללוסה לש ףילחהל שי

גוסב הללוסה תא מ םאותה תרבחלמומ ןרציתצ.

תוללוסה קוליס תושמושמה עצבל שי .ןרציה תוארוה יפל









경고!

배터리가 올바르게 교체되지 않으면 폭발의 위험이 있습니다. 기존 배터리와 동일
하거나 제조사에서 권장하는 동등한 종류의 배터리로만 교체해야 합니다. 제조사
의 안내에 따라 사용된 배터리를 처리하여 주십시오.

Waarschuwing

Er is ontplofngsgevaar indien de batterij verkeerd vervangen wordt. Vervang de

batterij slechts met hetzelfde of een equivalent type die door de fabrikant aan-

bevolen wordt. Gebruikte batterijen dienen overeenkomstig fabrieksvoorschriften

afgevoerd te worden.

Chapter 2: Installation

2-3

Product Disposal

Warning!

Ultimate disposal of this product should be handled according to all national laws

and regulations.

製品の廃棄

この製品を廃棄処分する場合、国の関係する全ての法律・条例に従い処理する必要が
ありま す。

警告
本产品的废弃处理应根据所有国家的法律和规章进行。

警告
本產品的廢棄處理應根據所有國家的法律和規章進行。

Warnung

Die Entsorgung dieses Produkts sollte gemäß allen Bestimmungen und Gesetzen

des Landes erfolgen.

¡Advertencia!

Al deshacerse por completo de este producto debe seguir todas las leyes y regla-

mentos nacionales.

Attention

La mise au rebut ou le recyclage de ce produit sont généralement soumis à des

lois et/ou directives de respect de l'environnement. Renseignez-vous auprès de

l'organisme compétent.

רצומה קוליס

!הרהזא

ו תויחנהל םאתהב תויהל בייח הז רצומ לש יפוס קוליס.הנידמה יקוח

2-4

X10DRG-H/X10DRG-HT Motherboard User’s Manual

2-2 Static-Sensitive Devices

Electrostatic Discharge (ESD) can damage electronic com ponents. To avoid dam-

aging your system board, it is important to handle it very carefully. The following

measures are generally sufcient to protect your equipment from ESD.

Precautions

•Use a grounded wrist strap designed to prevent static discharge.

•Touch a grounded metal object before removing the board from the antistatic

bag.

•Handle the motherboard by its edges only; do not touch its components, periph-

eral chips, memory modules or gold contacts.

•When handling chips or modules, avoid touching their pins.

•Put the motherboard and peripherals back into their antistatic bags when not

in use.

•For grounding purposes, make sure that your system chassis provides excellent

conductivity between the power supply, the case, the mounting fasteners and

the motherboard.

Unpacking

The motherboard is shipped in antistatic packaging to avoid static damage.

When unpacking the motherboard, make sure that the person handling it is static

protected.

Waarschuwing

De uiteindelijke verwijdering van dit product dient te geschieden in overeenstemming

met alle nationale wetten en reglementen.

 

경고!

이 제품은 해당 국가의 관련 법규 및 규정에 따라 폐기되어야 합니다.

Chapter 2: Installation

2-5

BIOS
LICENSE

BAR CODE

MAC CODE

X10DRG-H

Rev. 1.02

2-3 Motherboard Installation

All motherboards have standard mounting holes to t different types of chassis.

Make sure that the locations of all the mounting holes for both motherboard and

chassis match. Although a chassis may have both plastic and metal mounting fas-

teners, metal ones are highly recommended because they ground the motherboard

to the chassis. Make sure that the metal standoffs click in or are screwed in tightly.

Then use a screwdriver to secure the motherboard onto the motherboard tray.

Tools Needed

•Phillips Screwdriver

•Pan head screws (9 pieces)

•Standoffs (9 pieces, if needed)

Location of Mounting Holes

There are nine (9) mounting holes on this motherboard indicated by the circles.

Caution: 1) To avoid damaging the motherboard and its components, please do

not use a force greater than 8 lb/inch on each mounting screw during motherboard

installation. 2) Some components are very close to the mounting holes. Please take

precautionary measures to prevent damage to these components when installing the

motherboard to the chassis.

2-6

X10DRG-H/X10DRG-HT Motherboard User’s Manual

Installing the Motherboard

Note: Always connect the power cord last, and always remove it before

adding, removing or changing any hardware components.

1. Install the I/O shield into the chassis.

2. Locate the mounting holes on the motherboard.

3. Locate the matching mounting holes on the chassis. Align the mounting holes

on the motherboard against the mounting holes on the chassis.

4. Install standoffs in the chassis as needed.

5. Install the motherboard into the chassis carefully to avoid damaging mother-

board components.

6. Using the Phillips screwdriver, insert a Pan head #6 screw into a mounting

hole on the motherboard and its matching mounting hole on the chassis.

7. Repeat Step 5 to insert #6 screws into all mounting holes.

8. Make sure that the motherboard is securely placed in the chassis.

Note: Images displayed are is for illustration only. Your chassis or compo-

nents might look different from those shown in this manual.

Chapter 2: Installation

2-7

2-4 Processor and Heatsink Installation

Warning: When handling the processor package, avoid placing direct pressure on

the label area. Also, improper CPU installation or socket/pin misalignment can cause

serious damage to the CPU or the motherboard that will require RMA repairs. Be sure

to read and follow all instructions thoroughly before installing your CPU and heatsink.

Notes:

Always connect the power cord last, and always remove it before adding,

removing or changing any hardware components. Make sure that you in-

stall the processor into the CPU socket before you install the CPU heatsink.

If you buy a CPU separately, make sure that you use an Intel-certied

multi-directional heatsink only.

Make sure to install the motherboard into the chassis before you install

the CPU heatsink.

When receiving a motherboard without a processor pre-installed, make

sure that the plastic CPU socket cap is in place and none of the socket

pins are bent; otherwise, contact your retailer immediately.

Refer to the Supermicro website for updates on CPU support.

Installing the LGA2011 Processor

1. There are two load levers on the LGA2011 socket. To open the socket cover,

rst press and release the load lever labeled 'Open 1st'.

Note: All graphics, drawings and pictures shown in this manual are for il-

lustration only. The components that came with your machine may or may

not look exactly the same as those shown in this manual.

Press down

on

Load Lever

labeled 'Open 1st'.

1

2

OPEN 1st

OPEN 1st

2-8

X10DRG-H/X10DRG-HT Motherboard User’s Manual

OPEN 1st

Gently push
down to pop the
load plate open.

2. Press the second load lever labeled 'Close 1st' to release the load plate that

covers the CPU socket from its locking position.

3. With the lever labeled 'Close 1st' fully retracted, gently push down on the

lever labeled 'Open 1st' to open the load plate. Lift the load plate to open it

completely.

1

2

Press down on

Load

Lever labeled 'Close 1st'

Pull lever away from
the socket

2

Note: All graphics, drawings and pictures shown in this manual are for il-

lustration only. The components that came with your machine may or may

not look exactly the same as those shown in this manual.

OPEN 1st

OPEN 1st

1

Chapter 2: Installation

2-9

4. Use your thumb and the index nger to loosen the lever and open the load

plate.

5. Using your thumb and index nger, hold the CPU on its edges. Align the CPU

keys, which are semi-circle cutouts, against the socket keys.

6. Once they are aligned, carefully lower the CPU straight down into the socket.

(Do not drop the CPU on the socket. Do not move the CPU horizontally or

vertically. Do not rub the CPU against the surface or against any pins of the

socket to avoid damaging the CPU or the socket.)

Socket Keys

CPU Keys

Warning: You can only install the CPU

inside the socket in one direction. Make

sure that it is properly inserted into the

CPU socket before closing the load

plate. If it doesn't close properly, do

not force it into the socket as it may

damage your CPU. Instead, open the

load plate again to make sure that the

CPU is aligned properly.

2-10

X10DRG-H/X10DRG-HT Motherboard User’s Manual

OPEN 1st

7. With the CPU inside the socket, inspect the four corners of the CPU to make

sure that the CPU is properly installed.

Lever Lock

Lever Lock

Push down and

lock the lever

labeled 'Open 1st'.

Push down and lock the

lever labeled 'Close 1st'.

Gently close

the load plate.

1 2

3

4

OPEN 1st

OPEN 1st

8. Close the load plate with the CPU inside the socket. Lock the lever labeled

'Close 1st' rst, then lock the lever labeled 'Open 1st' second. Using your

thumb gently push the load levers down to the lever locks.

Chapter 2: Installation

2-11

OPEN 1st

Screw#1

Screw#2

Installing a Passive CPU Heatsink

1. Do not apply any thermal grease to the heatsink or the CPU die -- the re-

quired amount has already been applied.

2. Place the heatsink on top of the CPU so that the four mounting holes are

aligned with those on the motherboard and the heatsink bracket underneath.

3. Screw in two diagonal screws (i.e., the #1 and the #2 screws) until just snug

(-do not over-tighten the screws to avoid possible damage to the CPU.)

4. Finish the installation by fully tightening all four screws.

Mounting Holes

Note: For optimized airow, please follow your chassis airow direction

to properly install the heatsink. Graphics included in this manual are for

reference only. They might look different from the components installed

in your system.

Direction of Airow

2-12

X10DRG-H/X10DRG-HT Motherboard User’s Manual

Removing the Heatsink

Warning: We do not recommend that the CPU or the heatsink be removed. However,

if you do need to uninstall the heatsink, please follow the instructions below to uninstall

the heatsink to prevent damage done to the CPU or the CPU socket.

1. Unscrew the heatsink screws from the motherboard in the sequence as

shown in the illustration below.

2. Gently wriggle the heatsink to loosen it from the CPU. (Do not use excessive

force when wriggling the heatsink!)

3. Once the heatsink is loosened from the CPU or CPU socket, remove the

heatsink from the socket.

4. Remove the used thermal grease and clean the surface of the CPU and the

heatsink. Reapply the proper amount of thermal grease on the surface before

reinstalling the CPU and the heatsink.

Loosen screws
in sequence as
shown.

Screw#2

Motherboard

Screw#1

Screw#3

Screw#4

Chapter 2: Installation

2-13

BIOS
LICENSE

BAR CODE

MAC CODE

X10DRG-H

Rev. 1.02

Release Tabs

Notches

2-5 Installing and Removing the Memory Modules

Note: Check Supermicro's website for recommended memory modules.

CAUTION

Exercise extreme care when installing or removing DIMM

modules to prevent any possible damage.

Installing & Removing DIMMs

1. Insert the desired number of DIMMs into the memory slots, starting with

P1-DIMMA1. (For best performance, please use the memory modules of the

same type and speed in the same bank.)

2. Push the release tabs outwards on both ends of the DIMM slot to unlock it.

Removing Memory Modules

Press both notches on the ends of the DIMM module to unlock it. Once the DIMM

module is loosened, remove it from the memory slot.

3. Align the key of the DIMM module with the receptive point on the memory

slot.

4. Align the notches on both ends of the module against the receptive points on

the ends of the slot.

5. Use two thumbs together to press the notches on both ends of the module

straight down into the slot until the module snaps into place.

6. Press the release tabs to the locking positions to secure the DIMM module

into the slot.

Press both notches straight

down into the memory slot at

the same time.

2-14

X10DRG-H/X10DRG-HT Motherboard User’s Manual

Memory Support for the X10DRG-H(T) Motherboard

This motherboard supports DDR4 288-pin memory modules of up to 1024 GB

of Load Reduced (LRDIMM), and up to 512 GB Registered (RDIMM) ECC

2133/1866/1600 MHz in 16 slots. Memory speed support is depending on the CPUs

used in the motherboard. For the latest CPU/memory updates, please refer to our

website at http://www.supermicro.com/products/motherboard.

Processor & Memory Module Population Conguration

For memory to work properly, follow the tables below for memory installation.

Processors and their Corresponding Memory Modules

CPU# Corresponding DIMM Modules

CPU 1 P1

DIMMA1P1DIMMB1P1DIMMC1P1DIMMD1P1DIMMA2P1DIMMB2P1DIMMC2P1DIMMD2

CPU2 P2

DIMME1P2DIMMF1P2DIMMG1P2DIMMH1P2DIMME2P2DIMM F2P2DIMMG2P2DIMMH2

Processor and Memory Module Population for Optimal Performance

Number of

CPUs+DIMMs

CPU and Memory Population Conguration Table

(For memory to work properly, please follow the instructions below.)

1 CPU &
2 DIMMs

CPU1
P1 DIMMA1/P1 DIMMB1

1 CPU &
4 DIMMs

CPU1
P1 DIMMA1/P1 DIMMB1, P1 DIMMC1/P1 DIMMD1

1 CPU &

5~8 DIMMs

CPU1
P1 DIMMA1/P1 DIMMB1, P1 DIMMC1/P1 DIMMD1 + Any memory pairs in
P1 DIMMA2/P1 DIMMB2/P1 DIMMC2/P1 DIMMD2 slots

2 CPUs &

4 DIMMs

CPU1 + CPU2
P1 DIMMA1/P1 DIMMB1, P2 DIMME1/P2 DIMMF1

2 CPUs &

6 DIMMs

CPU1 + CPU2
P1 DIMMA1/P1 DIMMB1/P1 DIMMC1/P1 DIMMD1, P2 DIMME1/P2 DIMMF1

2 CPUs &

8 DIMMs

CPU1 + CPU2
P1 DIMMA1/P1 DIMMB1/P1 DIMMC1/P1 DIMMD1, P2 DIMME1/P2 DIMMF1/P2
DIMMG1/P2 DIMMH1

2 CPUs &

9~16 DIMMs

CPU1/CPU2
P1 DIMMA1/P1 DIMMB1/P1 DIMMC1/P1 DIMMD1, P2 DIMME1/P2 DIMMF1/
P2 DIMMG1/P2 DIMMH1 + Any memory pairs in P1, P2 DIMM slots

2 CPUs &

16 DIMMs

CPU1/CPU2
P1 DIMMA1/P1 DIMMB1/P1 DIMMC1/P1 DIMMD1, P2 DIMME1/P2 DIMMF1/
P2 DIMMG1/P2 DIMMH1,P1 DIMMA2/P1 DIMMB2/P1 DIMMC2/P1 DIMMD2,
P2 DIMME2/P2 DIMMF2/P2 DIMMG2/P2 DIMMH2

An Important Note:

•For the memory modules to work properly, please install DIMM modules of the

same type, same speed and same operating frequency in the motherboard.

Mixing of DIMMs of different types or different speeds is not allowed.

Chapter 2: Installation

2-15

LRDIMM/LRDIMM DDR4 ECC Memory Conguration

Speed (MT/s), Slot per Channel
(SPC) & DIMM per Channel (DPC)

2-16

X10DRG-H/X10DRG-HT Motherboard User’s Manual

BIOS
LICENSE

BAR CODE

MAC CODE

X10DRG-H

Rev. 1.02

2-6 Control Panel Connectors and I/O Ports

The I/O ports are color coded in conformance with the industry standards. See

the picture below for the colors and locations of the various I/O ports.

Back Panel Connectors and I/O Ports

Back Panel I/O Port Locations and Denitions

1. Back Panel USB 3.0 Port 0

2. Back Panel USB 3.0 Port 1

3. IPMI_Dedicated LAN

4. Gigabit LAN 1 (X10DRG-H),
10G_LAN (X10DRG-TH)

5. Gigabit LAN 2 (X10DRG-H),
10G_LAN (X10DRG-TH)

6. VGA

7. UID Switch/UID LED (LED1)

123

4

567

Chapter 2: Installation

2-17

BIOS
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BAR CODE

MAC CODE

X10DRG-H

Rev. 1.02

Video Connection

A Video (VGA) port is located next to

LAN ports 0/1 on the I/O backplane.

Refer to the motherboard layout below

for the location.

1. VGA

2. LAN1 (10G-LAN for X10DRG-HT,

GLAN for X10DRG-H)

3. LAN2 (10G-LAN for X10DRG-HT,

GLAN for X10DRG-H)

4. IPMI_LAN (GLAN for X10DRG-H(T)

123

4

Ethernet Ports

Two Ethernet ports (LAN1, LAN2)

are located on the I/O backplane.

These Ethernet ports support 10G

LAN connections on the X10DRG-HT,

and Gigabit LAN connections on the

X10DRG-H. In addition, an IPMI_Ded-

icated LAN that supports Gigabit LAN

is located above USB 4/5 ports on the

backplane. All Ethernet ports accept

RJ45 type cables. Please refer to the

LED Indicator Section for LAN LED

information.

LAN Ports

Pin Denition

Pin# Denition

1 P2V5SB 10 SGND

2 TD0+ 11 Act LED

3 TD0- 12 P3V3SB

4 TD1+ 13 Link 100 LED

(Yellow, +3V3SB)

5 TD1- 14 Link 1000 LED

(Yellow, +3V3SB)

6 TD2+ 15 Ground

7 TD2- 16 Ground

8 TD3+ 17 Ground

9 TD3- 18 Ground

(NC: No Connection)

123

4

2-18

X10DRG-H/X10DRG-HT Motherboard User’s Manual

BIOS
LICENSE

BAR CODE

MAC CODE

X10DRG-H

Rev. 1.02

1. Backpanel USB4 (USB3.0)

2. Backpanel USB5 (USB3.0)

3. FP USB 0/1 (USB 2.0)

4. FP USB 2/3 (USB 3.0)

Universal Serial Bus (USB)

Two USB 3.0 ports (USB 4/5) are located on the I/O backpanel. In addition, an

internal USB 3.0 header, provides two USB 3.0 connections (USB 2/3) and another

internal USB 2.0 header provides two USB 2.0 connections (USB 0/1) for front

panel support. (Cables are not included). See the tables below for pin denitions.

BP USB (3.0) 4/5

Pin Denitions

Pin# Description

1 VBUS

2 SSRX-

3 SSRX+

4 Ground

5 SSTX-

6 SSTX+

7 GND_DRAIN

8 D-

9 D+

123

4

Front Panel USB (3.0) 2/3

Pin Denitions

Pin # Denition Pin # Denition

1 +5V 2 +5V

3 USB_PN2 4 USB_PN3

5 USB_PP2 6 USB_PP3

7 Ground 8 Ground

9 Key 10 Ground

Front Panel USB 2.0 (0/1)

Pin Denitions

USB 2, 4

Pin # Denition

USB 3, 5

Pin # Denition

1 +5V 1 +5V

2 PO- 2 PO-

3 PO+ 3 PO+

4 Ground 4 Ground

5 NC 5 Key

(NC= No connection)

Chapter 2: Installation

2-19

Unit Identier Switches/UID LED

Indicators

A rear Unit Identier (UID) switch and a rear

LED (LE4) are located next to the VGA port

on the I/O back panel. The front UID switch

is located at pin 13 of the Front Control Panel

(JF1), while the front UID LED is located on

pin 7 of JF1. When you press the front UID

switch or the rear one, both front and rear

UID LEDs will be turned on. Press the UID

button again to turn off the LED indicator.

The UID Indicators provide easy identica-

tion of a system unit that may be in need

of service.

Note: UID can also be triggered via

IPMI on the motherboard. For more

information on IPMI, please refer to

the IPMI User's Guide posted on

our website @http://www.super-

micro.com.

BIOS
LICENSE

BAR CODE

MAC CODE

X10DRG-H

Rev. 1.02

Power Button

OH/Fan Fail/
PWR Fail LED)

1

NIC1 Link LED

Reset Button

2

Power Fail LED

HDD LED

FP PWRLED

Reset

PWR

3.3 V

UID LED

Blue LED Cathode

Ground

Ground

1920

3.3V

X

Ground

NMI

X

NIC2 Link LED

NIC2 Activity LED

NIC1 Activity LED

1. Rear UID Switch

2. Rear UID LED

3. Front UID LED Header

4. Front UID Switch

3

UID Switch

Pin# Denition

1 Ground

2 Ground

3 Button In

4 Ground

UID LED

Status

Color/State Status

Blue: On Unit Identied

1

1

2

4

2-20

X10DRG-H/X10DRG-HT Motherboard User’s Manual

BIOS
LICENSE

BAR CODE

MAC CODE

JPW1

1 1

1

1

JPP0

JITP1

JSPK1

BT1

JTPM1

P1 DIMMA1

P1 DIMMA2

P1 DIMMB2

P1 DIMMB1

CPU1

CPU1 SLOT1 PCI-E 3.0 X16

USB2/3(3.0)

CPU2 SLOT2 PCI-E 3.0 X16

CPU1 SLOT3 PCI-E 3.0 X16

CPU2 SLOT4 PCI-E 3.0 X16

USB4/5 (3.0)

CPU2 SLOT5 PCI-E 3.0 X8 INX16

LAN1LAN2

USB0/1

JPL1

JPF1

JPF2

JPME2

JVRM1

JVRM2

VGA

JPG1

JPB1

JPCIE1_1

JWD1

LE4

SW1

JSTBY1

BIOS

JPCIE1_3

JBR1

JBT1

I-SATA0

I-SATA1

I-SATA3

I-SATA4I-SATA5

I-SATA2

S-SATA0

S-SATA2

S-SATA3

COM1

JPW6

FANCFAND

JPC1

P1 DIMMD2

P1 DIMMD1

P1 DIMMC1

P1 DIMMC2

S-SATA1

JPP1

JPW2

JPW7

FANH

FANF

FANE

FAN1

P2 DIMMF2

P2 DIMMF1

P2 DIMME1

P2 DIMME2

FAN2

FAN3

FAN4

FANA

FANB

JPW3

JPW4

JPW5

JL1

T-SGPIO1

T-SGPIO2

T-SGPIO3

LE2

JF1

Front Control Panel

J23

FANG

CLOSE 1st

OPEN 1st

CLOSE 1st

OPEN 1st

CPU2

P2 DIMMG1

P2 DIMMG2

P2 DIMMH2

P2 DIMMH1

X10DRG-H

Rev. 1.02

PCH

LAN
CTRL

BMC

IPMI_LAN

JOH1

LEDM1

Front Control Panel

JF1 contains header pins for various buttons and indicators that are normally located

on a control panel at the front of the chassis. These connectors are designed spe-

cically for use with Supermicro's chassis. See the gure below for the descriptions

of the control panel buttons and LED indicators. Refer to the following section for

descriptions and pin denitions.

JF1 Header Pins

Power Button

OH/Fan Fail/
PWR Fail LED)

1

NIC1 Link LED

Reset Button

2

Power Fail LED

HDD LED

FP PWRLED

Reset

PWR

3.3 V

UID LED

Blue LED Cathode

Ground

Ground

1920

3.3V

X

Ground

NMI

X

NIC2 Link LED

NIC2 Activity LED

NIC1 Activity LED

Chapter 2: Installation

2-21

Power Button

OH/Fan Fail/
PWR Fail LED)

1

NIC1 Link LED

Reset Button

2

Power Fail LED

HDD LED

FP PWRLED

Reset

PWR

3.3 V

UID LED

Blue LED Cathode

Ground

Ground

1920

3.3V

X

Ground

NMI

X

NIC2 Link LED

NIC2 Activity LED

NIC1 Activity LED

Power LED

The Power LED connection is located

on pins 15 and 16 of JF1. Refer to the

table on the right for pin denitions.

NMI Button

The non-maskable interrupt button

header is located on pins 19 and 20

of JF1. Refer to the table on the right

for pin denitions.

NMI Button

Pin Denitions (JF1)

Pin# Denition

19 Control

20 Ground

Power LED

Pin Denitions (JF1)

Pin# Denition

15 3.3V

16 PWR LED

Front Control Panel Pin Denitions

A. NMI

B. PWR LED

A

B

BIOS
LICENSE

BAR CODE

MAC CODE

JPW1

1 1

1

1

JPP0

JITP1

JSPK1

BT1

JTPM1

P1 DIMMA1

P1 DIMMA2

P1 DIMMB2

P1 DIMMB1

CPU1

CPU1 SLOT1 PCI-E 3.0 X16

USB2/3(3.0)

CPU2 SLOT2 PCI-E 3.0 X16

CPU1 SLOT3 PCI-E 3.0 X16

CPU2 SLOT4 PCI-E 3.0 X16

USB4/5 (3.0)

CPU2 SLOT5 PCI-E 3.0 X8 INX16

LAN1LAN2

USB0/1

JPL1

JPF1

JPF2

JPME2

JVRM1

JVRM2

VGA

JPG1

JPB1

JPCIE1_1

JWD1

LE4

SW1

JSTBY1

BIOS

JPCIE1_3

JBR1

JBT1

I-SATA0

I-SATA1

I-SATA3

I-SATA4I-SATA5

I-SATA2

S-SATA0

S-SATA2

S-SATA3

COM1

JPW6

FANCFAND

JPC1

P1 DIMMD2

P1 DIMMD1

P1 DIMMC1

P1 DIMMC2

S-SATA1

JPP1

JPW2

JPW7

FANH

FANF

FANE

FAN1

P2 DIMMF2

P2 DIMMF1

P2 DIMME1

P2 DIMME2

FAN2

FAN3

FAN4

FANA

FANB

JPW3

JPW4

JPW5

JL1

T-SGPIO1

T-SGPIO2

T-SGPIO3

LE2

JF1

Front Control Panel

J23

FANG

CLOSE 1st

OPEN 1st

CLOSE 1st

OPEN 1st

CPU2

P2 DIMMG1

P2 DIMMG2

P2 DIMMH2

P2 DIMMH1

X10DRG-H

Rev. 1.02

PCH

LAN
CTRL

BMC

IPMI_LAN

JOH1

LEDM1

2-22

X10DRG-H/X10DRG-HT Motherboard User’s Manual

Power Button

OH/Fan Fail/
PWR Fail LED)

1

NIC1 Link LED

Reset Button

2

Power Fail LED

HDD LED

FP PWRLED

Reset

PWR

3.3 V

UID LED

Blue LED Cathode

Ground

Ground

1920

3.3V

X

Ground

NMI

X

NIC2 Link LED

NIC2 Activity LED

NIC1 Activity LED

B

NIC1/NIC2 LED Indicators

The NIC (Network Interface Control-

ler) LED connection for LAN Port 1

is located on pins 11 and 12 of JF1,

and for LAN pPort 2 is on pins 9 and

10. Attach the NIC LED cables here to

display network activity. Refer to the

table on the right for pin denitions.

HDD/UID LED

The HDD LED connection is located

on pins 13 and 14 of JF1. Attach a

cable here to indicate HDD activity

and UID status. See the table on the

right for pin denitions.

HDD LED

Pin Denitions (JF1)

Pin# Denition

13 UID LED

14 HD Active

C

A. HDD/UUID LED

B. NIC1 LED

C. NIC2 LED

A

GLAN1/2 LED

Pin Denitions (JF1)

Pin# Denition

9 NIC 2 Activity LED

10 NIC 2 Link LED

11 NIC 1 Activity LED

12 NIC 1 Link LED

BIOS
LICENSE

BAR CODE

MAC CODE

JPW1

1 1

1

1

JPP0

JITP1

JSPK1

BT1

JTPM1

P1 DIMMA1

P1 DIMMA2

P1 DIMMB2

P1 DIMMB1

CPU1

CPU1 SLOT1 PCI-E 3.0 X16

USB2/3(3.0)

CPU2 SLOT2 PCI-E 3.0 X16

CPU1 SLOT3 PCI-E 3.0 X16

CPU2 SLOT4 PCI-E 3.0 X16

USB4/5 (3.0)

CPU2 SLOT5 PCI-E 3.0 X8 INX16

LAN1LAN2

USB0/1

JPL1

JPF1

JPF2

JPME2

JVRM1

JVRM2

VGA

JPG1

JPB1

JPCIE1_1

JWD1

LE4

SW1

JSTBY1

BIOS

JPCIE1_3

JBR1

JBT1

I-SATA0

I-SATA1

I-SATA3

I-SATA4I-SATA5

I-SATA2

S-SATA0

S-SATA2

S-SATA3

COM1

JPW6

FANCFAND

JPC1

P1 DIMMD2

P1 DIMMD1

P1 DIMMC1

P1 DIMMC2

S-SATA1

JPP1

JPW2

JPW7

FANH

FANF

FANE

FAN1

P2 DIMMF2

P2 DIMMF1

P2 DIMME1

P2 DIMME2

FAN2

FAN3

FAN4

FANA

FANB

JPW3

JPW4

JPW5

JL1

T-SGPIO1

T-SGPIO2

T-SGPIO3

LE2

JF1

Front Control Panel

J23

FANG

CLOSE 1st

OPEN 1st

CLOSE 1st

OPEN 1st

CPU2

P2 DIMMG1

P2 DIMMG2

P2 DIMMH2

P2 DIMMH1

X10DRG-H

Rev. 1.02

PCH

LAN
CTRL

BMC

IPMI_LAN

JOH1

LEDM1

Chapter 2: Installation

2-23

Power Fail LED

The Power Fail LED connection is

located on pins 5 and 6 of JF1. Re-

fer to the table on the right for pin

denitions.

A. OH/Fail/PWR Fail LED

B. PWR Supply Fail

PWR Fail LED

Pin Denitions (JF1)

Pin# Denition

5 3.3V

6 PWR Supply Fail

B

A

Overheat (OH)/Fan Fail/PWR Fail/
UID LED

Connect an LED cable to pins 7 and

8 of Front Control Panel to use the

Overheat/Fan Fail/Power Fail and

UID LED connections. The Red LED

on pin 8 provides warnings of over-

heating, fan failure or power failure.

The Blue LED on pin 7 works as

the front panel UID LED indicator.

Refer to the tables on the right for

pin denitions.

OH/Fan Fail/ PWR Fail/Blue_UID

LED Pin Denitions (JF1)

Pin# Denition

7 Blue_UID LED

8 OH/Fan Fail/Power Fail

OH/Fan Fail/PWR Fail

LED Status (Red LED)

State Denition

Off Normal

On Overheat

Flashing Fan Fail

Power Button

OH/Fan Fail/
PWR Fail LED)

1

NIC1 Link LED

Reset Button

2

Power Fail LED

HDD LED

FP PWRLED

Reset

PWR

3.3 V

UID LED

Blue LED Cathode

Ground

Ground

1920

3.3V

X

Ground

NMI

X

NIC2 Link LED

NIC2 Activity LED

NIC1 Activity LED

BIOS
LICENSE

BAR CODE

MAC CODE

JPW1

1 1

1

1

JPP0

JITP1

JSPK1

BT1

JTPM1

P1 DIMMA1

P1 DIMMA2

P1 DIMMB2

P1 DIMMB1

CPU1

CPU1 SLOT1 PCI-E 3.0 X16

USB2/3(3.0)

CPU2 SLOT2 PCI-E 3.0 X16

CPU1 SLOT3 PCI-E 3.0 X16

CPU2 SLOT4 PCI-E 3.0 X16

USB4/5 (3.0)

CPU2 SLOT5 PCI-E 3.0 X8 INX16

LAN1LAN2

USB0/1

JPL1

JPF1

JPF2

JPME2

JVRM1

JVRM2

VGA

JPG1

JPB1

JPCIE1_1

JWD1

LE4

SW1

JSTBY1

BIOS

JPCIE1_3

JBR1

JBT1

I-SATA0

I-SATA1

I-SATA3

I-SATA4I-SATA5

I-SATA2

S-SATA0

S-SATA2

S-SATA3

COM1

JPW6

FANCFAND

JPC1

P1 DIMMD2

P1 DIMMD1

P1 DIMMC1

P1 DIMMC2

S-SATA1

JPP1

JPW2

JPW7

FANH

FANF

FANE

FAN1

P2 DIMMF2

P2 DIMMF1

P2 DIMME1

P2 DIMME2

FAN2

FAN3

FAN4

FANA

FANB

JPW3

JPW4

JPW5

JL1

T-SGPIO1

T-SGPIO2

T-SGPIO3

LE2

JF1

Front Control Panel

J23

FANG

CLOSE 1st

OPEN 1st

CLOSE 1st

OPEN 1st

CPU2

P2 DIMMG1

P2 DIMMG2

P2 DIMMH2

P2 DIMMH1

X10DRG-H

Rev. 1.02

PCH

LAN
CTRL

BMC

IPMI_LAN

JOH1

LEDM1

2-24

X10DRG-H/X10DRG-HT Motherboard User’s Manual

Power Button

OH/Fan Fail/
PWR Fail LED)

1

NIC1 Link LED

Reset Button

2

Power Fail LED

HDD LED

FP PWRLED

Reset

PWR

3.3 V

UID LED

Blue LED Cathode

Ground

Ground

1920

3.3V

X

Ground

NMI

X

NIC2 Link LED

NIC2 Activity LED

NIC1 Activity LED

Power Button

The Power Button connection is located on pins

1 and 2 of JF1. Momentarily contacting both

pins will power on/off the system. To power on

or power off the system, press the button for 4

seconds or longer. Refer to the table on the right

for pin denitions.

Power Button

Pin Denitions (JF1)

Pin# Denition

1 Signal

2 Ground

Reset Button

The Reset Button connection is located on pins

3 and 4 of JF1. Attach it to a hardware reset

switch on the computer case. Refer to the table

on the right for pin denitions.

Reset Button

Pin Denitions (JF1)

Pin# Denition

3 Reset

4 Ground

A. Reset Button

B. PWR Button

A

B

BIOS
LICENSE

BAR CODE

MAC CODE

JPW1

1 1

1

1

JPP0

JITP1

JSPK1

BT1

JTPM1

P1 DIMMA1

P1 DIMMA2

P1 DIMMB2

P1 DIMMB1

CPU1

CPU1 SLOT1 PCI-E 3.0 X16

USB2/3(3.0)

CPU2 SLOT2 PCI-E 3.0 X16

CPU1 SLOT3 PCI-E 3.0 X16

CPU2 SLOT4 PCI-E 3.0 X16

USB4/5 (3.0)

CPU2 SLOT5 PCI-E 3.0 X8 INX16

LAN1LAN2

USB0/1

JPL1

JPF1

JPF2

JPME2

JVRM1

JVRM2

VGA

JPG1

JPB1

JPCIE1_1

JWD1

LE4

SW1

JSTBY1

BIOS

JPCIE1_3

JBR1

JBT1

I-SATA0

I-SATA1

I-SATA3

I-SATA4I-SATA5

I-SATA2

S-SATA0

S-SATA2

S-SATA3

COM1

JPW6

FANCFAND

JPC1

P1 DIMMD2

P1 DIMMD1

P1 DIMMC1

P1 DIMMC2

S-SATA1

JPP1

JPW2

JPW7

FANH

FANF

FANE

FAN1

P2 DIMMF2

P2 DIMMF1

P2 DIMME1

P2 DIMME2

FAN2

FAN3

FAN4

FANA

FANB

JPW3

JPW4

JPW5

JL1

T-SGPIO1

T-SGPIO2

T-SGPIO3

LE2

JF1

Front Control Panel

J23

FANG

CLOSE 1st

OPEN 1st

CLOSE 1st

OPEN 1st

CPU2

P2 DIMMG1

P2 DIMMG2

P2 DIMMH2

P2 DIMMH1

X10DRG-H

Rev. 1.02

PCH

LAN
CTRL

BMC

IPMI_LAN

JOH1

LEDM1

Chapter 2: Installation

2-25

BIOS
LICENSE

BAR CODE

MAC CODE

JPW1

1 1

1

1

JPP0

JITP1

JSPK1

BT1

JTPM1

P1 DIMMA1

P1 DIMMA2

P1 DIMMB2

P1 DIMMB1

CPU1

CPU1 SLOT1 PCI-E 3.0 X16

USB2/3(3.0)

CPU2 SLOT2 PCI-E 3.0 X16

CPU1 SLOT3 PCI-E 3.0 X16

CPU2 SLOT4 PCI-E 3.0 X16

USB4/5 (3.0)

CPU2 SLOT5 PCI-E 3.0 X8 INX16

LAN1LAN2

USB0/1

JPL1

JPF1

JPF2

JPME2

JVRM1

JVRM2

VGA

JPG1

JPB1

JPCIE1_1

JWD1

LE4

SW1

JSTBY1

BIOS

JPCIE1_3

JBR1

JBT1

I-SATA0

I-SATA1

I-SATA3

I-SATA4I-SATA5

I-SATA2

S-SATA0

S-SATA2

S-SATA3

COM1

JPW6

FANCFAND

JPC1

P1 DIMMD2

P1 DIMMD1

P1 DIMMC1

P1 DIMMC2

S-SATA1

JPP1

JPW2

JPW7

FANH

FANF

FANE

FAN1

P2 DIMMF2

P2 DIMMF1

P2 DIMME1

P2 DIMME2

FAN2

FAN3

FAN4

FANA

FANB

JPW3

JPW4

JPW5

JL1

T-SGPIO1

T-SGPIO2

T-SGPIO3

LE2

JF1

Front Control Panel

J23

FANG

CLOSE 1st

OPEN 1st

CLOSE 1st

OPEN 1st

CPU2

P2 DIMMG1

P2 DIMMG2

P2 DIMMH2

P2 DIMMH1

X10DRG-H

Rev. 1.02

PCH

LAN
CTRL

BMC

IPMI_LAN

JOH1

LEDM1

Warning! To avoid damaging the power supply or the

motherboard, be sure to connect the power supply to

the SMCI-proprietary power connector (JPW1), the

9-pin power connector (JPW2), and the ve 8-pin

power connectors (JPW3-7) on the motherboard.

Failure in doing so may void the manufacturer war-

ranty on your power supply and motherboard.

2-7 Connecting Cables

Power Connectors

The X10DRG-H(T) motherboard accommodates SMCI-proprietary main power

(JPW1), a 9-pin power connector (JPW2), and ve 8-pin 12V power connectors

(JPW3/JPW4/JPW5/JPW6/JPW7). The 9-pin power connector located at JPW2 is

used to supply power to the motherboard, and the other ve 8-pin power connec-

tors located at JPW3-JPW7 are used for HDD backplane and GPU add-on cards.

Be sure to connect all these power connectors to your power supply to ensure

adequate power supply to your system. See the table below for the pin denitions

for the 8-pin power connectors.

A. JPW1: SMCI-proprietary main PWR (Req'd)

B. JPW2: 9-pin Processor PWR (Req'd)

C. JPW3: 8-pin Processor PWR used for HDD

BPN/GPU cards (Req'd)

D. JPW4: 8-pin Processor PWR used for HDD

BPN/GPU cards (Req'd)

E. JPW5: 8-pin Processor PWR used for HDD

BPN/GPU cards (Req'd)

F. JPW6: 8-pin Processor PWR used for HDD

BPN/GPU cards (Req'd)

G. JPW7: 8-pin Processor PWR used for HDD

BPN/GPU cards (Req'd)

A

B

C

(Required)

12V 8-pin Power Connec-

tor Pin Denitions

Pins Denition

1 through 4 Ground

5 through 8 +12V

D

E

F

G

2-26

X10DRG-H/X10DRG-HT Motherboard User’s Manual

BIOS
LICENSE

BAR CODE

MAC CODE

JPW1

1 1

1

1

JPP0

JITP1

JSPK1

BT1

JTPM1

P1 DIMMA1

P1 DIMMA2

P1 DIMMB2

P1 DIMMB1

CPU1

CPU1 SLOT1 PCI-E 3.0 X16

USB2/3(3.0)

CPU2 SLOT2 PCI-E 3.0 X16

CPU1 SLOT3 PCI-E 3.0 X16

CPU2 SLOT4 PCI-E 3.0 X16

USB4/5 (3.0)

CPU2 SLOT5 PCI-E 3.0 X8 INX16

LAN1LAN2

USB0/1

JPL1

JPF1

JPF2

JPME2

JVRM1

JVRM2

VGA

JPG1

JPB1

JPCIE1_1

JWD1

LE4

SW1

JSTBY1

BIOS

JPCIE1_3

JBR1

JBT1

I-SATA0

I-SATA1

I-SATA3

I-SATA4I-SATA5

I-SATA2

S-SATA0

S-SATA2

S-SATA3

COM1

JPW6

FANCFAND

JPC1

P1 DIMMD2

P1 DIMMD1

P1 DIMMC1

P1 DIMMC2

S-SATA1

JPP1

JPW2

JPW7

FANH

FANF

FANE

FAN1

P2 DIMMF2

P2 DIMMF1

P2 DIMME1

P2 DIMME2

FAN2

FAN3

FAN4

FANA

FANB

JPW3

JPW4

JPW5

JL1

T-SGPIO1

T-SGPIO2

T-SGPIO3

LE2

JF1

Front Control Panel

J23

FANG

CLOSE 1st

OPEN 1st

CLOSE 1st

OPEN 1st

CPU2

P2 DIMMG1

P2 DIMMG2

P2 DIMMH2

P2 DIMMH1

X10DRG-H

Rev. 1.02

PCH

LAN
CTRL

BMC

IPMI_LAN

JOH1

LEDM1

C

A. Fan 1

B. Fan 2

C. Fan 3

D. Fan 4

E. Fan A

F. Fan B

G. Fan C

H. Fan D

I. Fan E

J. Fan F

K. Fan G

L. Fan H

D

E

F

Fan Headers

This motherboard has 12 system/CPU fan head-

ers (Fan 1 - Fan 4, Fan A - Fan H) on the mother-

board. All these 4-pin fans headers are backward

compatible with the traditional 3-pin fans. How-

ever, fan speed control is available for 4-pin fans

only via IPMI 2.0 interface. See the table on the

right for pin denitions.

Fan Header

Pin Denitions

Pin# Denition

1 Ground

2 +12V

3 Tachometer

4 PWR Modulation

A

B

H

I

G

J

K

L

Chapter 2: Installation

2-27

BIOS
LICENSE

BAR CODE

MAC CODE

JPW1

1 1

1

1

JPP0

JITP1

JSPK1

BT1

JTPM1

P1 DIMMA1

P1 DIMMA2

P1 DIMMB2

P1 DIMMB1

CPU1

CPU1 SLOT1 PCI-E 3.0 X16

USB2/3(3.0)

CPU2 SLOT2 PCI-E 3.0 X16

CPU1 SLOT3 PCI-E 3.0 X16

CPU2 SLOT4 PCI-E 3.0 X16

USB4/5 (3.0)

CPU2 SLOT5 PCI-E 3.0 X8 INX16

LAN1LAN2

USB0/1

JPL1

JPF1

JPF2

JPME2

JVRM1

JVRM2

VGA

JPG1

JPB1

JPCIE1_1

JWD1

LE4

SW1

JSTBY1

BIOS

JPCIE1_3

JBR1

JBT1

I-SATA0

I-SATA1

I-SATA3

I-SATA4I-SATA5

I-SATA2

S-SATA0

S-SATA2

S-SATA3

COM1

JPW6

FANCFAND

JPC1

P1 DIMMD2

P1 DIMMD1

P1 DIMMC1

P1 DIMMC2

S-SATA1

JPP1

JPW2

JPW7

FANH

FANF

FANE

FAN1

P2 DIMMF2

P2 DIMMF1

P2 DIMME1

P2 DIMME2

FAN2

FAN3

FAN4

FANA

FANB

JPW3

JPW4

JPW5

JL1

T-SGPIO1

T-SGPIO2

T-SGPIO3

LE2

JF1

Front Control Panel

J23

FANG

CLOSE 1st

OPEN 1st

CLOSE 1st

OPEN 1st

CPU2

P2 DIMMG1

P2 DIMMG2

P2 DIMMH2

P2 DIMMH1

X10DRG-H

Rev. 1.02

PCH

LAN
CTRL

BMC

IPMI_LAN

JOH1

LEDM1

B

A

A. Internal Speaker

(Buzzer)

B. TPM/80 Port

Internal Speaker

The Internal Speaker (JSPK1) pro-

vides audible indications for various

beep codes. See the table on the right

for pin denitions. Refer to the layout

below for the location.

Internal Buzzer

Pin Denition

Pin# Denitions

Pin 1 Pos. (+) Beep In

Pin 2 Neg. (-) Alarm Speaker

TPM/Port 80 Header

A Trusted Platform Module/Port 80

header, located at JTPM1, provides

TPM support and Port 80 connection.

Use this header to enhance system

performance and data security. See

the table on the right for pin denitions.

TPM/Port 80 Header

Pin Denitions

Pin # Denition Pin # Denition

1 LCLK 2 GND

3 LFRAME# 4 <(KEY)>

5 LRESET# 6 +5V (X)

7 LAD 3 8 LAD 2

9 +3.3V 10 LAD1

11 LAD0 12 GND

13 SMB_CLK4 14 SMB_DAT4

15 +3V_DUAL 16 SERIRQ

17 GND 18 CLKRUN# (X)

19 LPCPD# 20 LDRQ# (X)

2-28

X10DRG-H/X10DRG-HT Motherboard User’s Manual

BIOS
LICENSE

BAR CODE

MAC CODE

JPW1

1 1

1

1

JPP0

JITP1

JSPK1

BT1

JTPM1

P1 DIMMA1

P1 DIMMA2

P1 DIMMB2

P1 DIMMB1

CPU1

CPU1 SLOT1 PCI-E 3.0 X16

USB2/3(3.0)

CPU2 SLOT2 PCI-E 3.0 X16

CPU1 SLOT3 PCI-E 3.0 X16

CPU2 SLOT4 PCI-E 3.0 X16

USB4/5 (3.0)

CPU2 SLOT5 PCI-E 3.0 X8 INX16

LAN1LAN2

USB0/1

JPL1

JPF1

JPF2

JPME2

JVRM1

JVRM2

VGA

JPG1

JPB1

JPCIE1_1

JWD1

LE4

SW1

JSTBY1

BIOS

JPCIE1_3

JBR1

JBT1

I-SATA0

I-SATA1

I-SATA3

I-SATA4I-SATA5

I-SATA2

S-SATA0

S-SATA2

S-SATA3

COM1

JPW6

FANCFAND

JPC1

P1 DIMMD2

P1 DIMMD1

P1 DIMMC1

P1 DIMMC2

S-SATA1

JPP1

JPW2

JPW7

FANH

FANF

FANE

FAN1

P2 DIMMF2

P2 DIMMF1

P2 DIMME1

P2 DIMME2

FAN2

FAN3

FAN4

FANA

FANB

JPW3

JPW4

JPW5

JL1

T-SGPIO1

T-SGPIO2

T-SGPIO3

LE2

JF1

Front Control Panel

J23

FANG

CLOSE 1st

OPEN 1st

CLOSE 1st

OPEN 1st

CPU2

P2 DIMMG1

P2 DIMMG2

P2 DIMMH2

P2 DIMMH1

X10DRG-H

Rev. 1.02

PCH

LAN
CTRL

BMC

IPMI_LAN

JOH1

LEDM1

A.T-SGPIO1 (for I-SATA0-3)

B.T-SGPIO2 (for I-SATA4/5)

C. TGPIO3 (for S-SATA0-3)

D. Standby PWR

I-SGPIO1/2/3 Headers

Three SGPIO (Serial Link General Purpose

Input/Output) headers are located on the

motherboard. T-SGPIO1 supports I-SATA

0-3, T-SGPIO2 supports I-SATA 4/5. T-

SGPIO3 is used for S-SATA 0-3. See the

table on the right for pin denitions.

Note: NC= No Connection

T-SGPIO 1/2/3 Headers

Pin Denitions

Pin# Denition Pin Denition

1 NC 2 NC

3 Ground 4 Data

5 Load 6 Ground

7 Clock 8 NC

Standby Power Header

The +5V Standby Power header is located at

JSTBY1 on the motherboard. See the table

on the right for pin denitions. (You must also

have a card with a Standby Power connector

and a cable to use this feature.)

Standby PWR

Pin Denitions

Pin# Denition

1 +5V Standby

2 Ground

3 No Connection

C

D

A

B

Chapter 2: Installation

2-29

BIOS
LICENSE

BAR CODE

MAC CODE

JPW1

1 1

1

1

JPP0

JITP1

JSPK1

BT1

JTPM1

P1 DIMMA1

P1 DIMMA2

P1 DIMMB2

P1 DIMMB1

CPU1

CPU1 SLOT1 PCI-E 3.0 X16

USB2/3(3.0)

CPU2 SLOT2 PCI-E 3.0 X16

CPU1 SLOT3 PCI-E 3.0 X16

CPU2 SLOT4 PCI-E 3.0 X16

USB4/5 (3.0)

CPU2 SLOT5 PCI-E 3.0 X8 INX16

LAN1LAN2

USB0/1

JPL1

JPF1

JPF2

JPME2

JVRM1

JVRM2

VGA

JPG1

JPB1

JPCIE1_1

JWD1

LE4

SW1

JSTBY1

BIOS

JPCIE1_3

JBR1

JBT1

I-SATA0

I-SATA1

I-SATA3

I-SATA4I-SATA5

I-SATA2

S-SATA0

S-SATA2

S-SATA3

COM1

JPW6

FANCFAND

JPC1

P1 DIMMD2

P1 DIMMD1

P1 DIMMC1

P1 DIMMC2

S-SATA1

JPP1

JPW2

JPW7

FANH

FANF

FANE

FAN1

P2 DIMMF2

P2 DIMMF1

P2 DIMME1

P2 DIMME2

FAN2

FAN3

FAN4

FANA

FANB

JPW3

JPW4

JPW5

JL1

T-SGPIO1

T-SGPIO2

T-SGPIO3

LE2

JF1

Front Control Panel

J23

FANG

CLOSE 1st

OPEN 1st

CLOSE 1st

OPEN 1st

CPU2

P2 DIMMG1

P2 DIMMG2

P2 DIMMH2

P2 DIMMH1

X10DRG-H

Rev. 1.02

PCH

LAN
CTRL

BMC

IPMI_LAN

JOH1

LEDM1

A. COM1

B. Chassis In-

trusion

Serial Port Header

A COM header (COM1) is located next

to the BMC chip. This header provides

serial port connection support. See the

table on the right for pin denitions.

Serial COM) Ports

Pin Denitions

Pin # Denition Pin # Denition

1 DCD 6 DSR

2 RXD 7 RTS

3 TXD 8 CTS

4 DTR 9 RI

5 Ground 10 N/A

COM1

COM2

A

Chassis Intrusion

A Chassis Intrusion header is located

at JL1 on the motherboard. Attach an

appropriate cable from the chassis to

inform you of a chassis intrusion when

the chassis is opened.

Chassis Intrusion

Pin Denitions

Pin# Denition

1 Intrusion Input

2 Ground

B

2-30

X10DRG-H/X10DRG-HT Motherboard User’s Manual

BIOS
LICENSE

BAR CODE

MAC CODE

JPW1

1 1

1

1

JPP0

JITP1

JSPK1

BT1

JTPM1

P1 DIMMA1

P1 DIMMA2

P1 DIMMB2

P1 DIMMB1

CPU1

CPU1 SLOT1 PCI-E 3.0 X16

USB2/3(3.0)

CPU2 SLOT2 PCI-E 3.0 X16

CPU1 SLOT3 PCI-E 3.0 X16

CPU2 SLOT4 PCI-E 3.0 X16

USB4/5 (3.0)

CPU2 SLOT5 PCI-E 3.0 X8 INX16

LAN1LAN2

USB0/1

JPL1

JPF1

JPF2

JPME2

JVRM1

JVRM2

VGA

JPG1

JPB1

JPCIE1_1

JWD1

LE4

SW1

JSTBY1

BIOS

JPCIE1_3

JBR1

JBT1

I-SATA0

I-SATA1

I-SATA3

I-SATA4I-SATA5

I-SATA2

S-SATA0

S-SATA2

S-SATA3

COM1

JPW6

FANCFAND

JPC1

P1 DIMMD2

P1 DIMMD1

P1 DIMMC1

P1 DIMMC2

S-SATA1

JPP1

JPW2

JPW7

FANH

FANF

FANE

FAN1

P2 DIMMF2

P2 DIMMF1

P2 DIMME1

P2 DIMME2

FAN2

FAN3

FAN4

FANA

FANB

JPW3

JPW4

JPW5

JL1

T-SGPIO1

T-SGPIO2

T-SGPIO3

LE2

JF1

Front Control Panel

J23

FANG

CLOSE 1st

OPEN 1st

CLOSE 1st

OPEN 1st

CPU2

P2 DIMMG1

P2 DIMMG2

P2 DIMMH2

P2 DIMMH1

X10DRG-H

Rev. 1.02

PCH

LAN
CTRL

BMC

IPMI_LAN

JOH1

LEDM1

2-8 Jumper Settings

Explanation of Jumpers

To modify the operation of the mother-

board, jumpers can be used to choose

between optional settings. Jumpers create

shorts between two pins to change the

function of the connector. Pin 1 is identied

with a square solder pad on the printed

circuit board. See the motherboard layout

pages for jumper locations.

Note: On two pin jumpers,

"Closed" means the jumper is

on and "Open" means the jumper

is off the pins.

Connector

Pins

Jumper

Cap

Setting

Pin 1-2 short

3 2 1

3 2 1

LAN Enable/Disable

JPL1 enables or disables Gigabit_LAN

ports 1/2 on the X10DRG-H, and 10G_

LAN ports 1/2 on the X10DRG-HT. See

the table on the right for jumper settings.

The default setting is Enabled.

LAN Enable

Jumper Settings

Jumper Setting Denition

1-2 Enabled (default)

2-3 Disabled

A

A. GLAN1/2 Enable

(X10DRG-H)

A. 10G_LAN1/2 En-

able (X10DRG-HT)

Chapter 2: Installation

2-31

BIOS
LICENSE

BAR CODE

MAC CODE

JPW1

1 1

1

1

JPP0

JITP1

JSPK1

BT1

JTPM1

P1 DIMMA1

P1 DIMMA2

P1 DIMMB2

P1 DIMMB1

CPU1

CPU1 SLOT1 PCI-E 3.0 X16

USB2/3(3.0)

CPU2 SLOT2 PCI-E 3.0 X16

CPU1 SLOT3 PCI-E 3.0 X16

CPU2 SLOT4 PCI-E 3.0 X16

USB4/5 (3.0)

CPU2 SLOT5 PCI-E 3.0 X8 INX16

LAN1LAN2

USB0/1

JPL1

JPF1

JPF2

JPME2

JVRM1

JVRM2

VGA

JPG1

JPB1

JPCIE1_1

JWD1

LE4

SW1

JSTBY1

BIOS

JPCIE1_3

JBR1

JBT1

I-SATA0

I-SATA1

I-SATA3

I-SATA4I-SATA5

I-SATA2

S-SATA0

S-SATA2

S-SATA3

COM1

JPW6

FANCFAND

JPC1

P1 DIMMD2

P1 DIMMD1

P1 DIMMC1

P1 DIMMC2

S-SATA1

JPP1

JPW2

JPW7

FANH

FANF

FANE

FAN1

P2 DIMMF2

P2 DIMMF1

P2 DIMME1

P2 DIMME2

FAN2

FAN3

FAN4

FANA

FANB

JPW3

JPW4

JPW5

JL1

T-SGPIO1

T-SGPIO2

T-SGPIO3

LE2

JF1

Front Control Panel

J23

FANG

CLOSE 1st

OPEN 1st

CLOSE 1st

OPEN 1st

CPU2

P2 DIMMG1

P2 DIMMG2

P2 DIMMH2

P2 DIMMH1

X10DRG-H

Rev. 1.02

PCH

LAN
CTRL

BMC

IPMI_LAN

JOH1

LEDM1

CMOS Clear

JBT1 is used to clear CMOS. Instead of pins, this "jumper" consists of contact pads

to prevent accidental clearing of CMOS. To clear CMOS, use a metal object such

as a small screwdriver to touch both pads at the same time to short the connection.

Note: To clear CMOS, please completely shut down the system, and then

short JBT1 on the motherboard.

A

B

A. Clear CMOS

B. Watch Dog Enable

Watch Dog Enable/Disable

Watch Dog (JWD1) is a system monitor that will

reboot the system when a software application

hangs. Close pins 1-2 to reset the system if an

application hangs. Close pins 2-3 to generate a

non-maskable interrupt signal for the application

that hangs. See the table on the right for jumper

settings. Watch Dog must also be enabled in the

BIOS.

Watch Dog

Jumper Settings

Jumper Setting Denition

Pins 1-2 Reset (default)

Pins 2-3 NMI

Open Disabled

2-32

X10DRG-H/X10DRG-HT Motherboard User’s Manual

BIOS
LICENSE

BAR CODE

MAC CODE

JPW1

1 1

1

1

JPP0

JITP1

JSPK1

BT1

JTPM1

P1 DIMMA1

P1 DIMMA2

P1 DIMMB2

P1 DIMMB1

CPU1

CPU1 SLOT1 PCI-E 3.0 X16

USB2/3(3.0)

CPU2 SLOT2 PCI-E 3.0 X16

CPU1 SLOT3 PCI-E 3.0 X16

CPU2 SLOT4 PCI-E 3.0 X16

USB4/5 (3.0)

CPU2 SLOT5 PCI-E 3.0 X8 INX16

LAN1LAN2

USB0/1

JPL1

JPF1

JPF2

JPME2

JVRM1

JVRM2

VGA

JPG1

JPB1

JPCIE1_1

JWD1

LE4

SW1

JSTBY1

BIOS

JPCIE1_3

JBR1

JBT1

I-SATA0

I-SATA1

I-SATA3

I-SATA4I-SATA5

I-SATA2

S-SATA0

S-SATA2

S-SATA3

COM1

JPW6

FANCFAND

JPC1

P1 DIMMD2

P1 DIMMD1

P1 DIMMC1

P1 DIMMC2

S-SATA1

JPP1

JPW2

JPW7

FANH

FANF

FANE

FAN1

P2 DIMMF2

P2 DIMMF1

P2 DIMME1

P2 DIMME2

FAN2

FAN3

FAN4

FANA

FANB

JPW3

JPW4

JPW5

JL1

T-SGPIO1

T-SGPIO2

T-SGPIO3

LE2

JF1

Front Control Panel

J23

FANG

CLOSE 1st

OPEN 1st

CLOSE 1st

OPEN 1st

CPU2

P2 DIMMG1

P2 DIMMG2

P2 DIMMH2

P2 DIMMH1

X10DRG-H

Rev. 1.02

PCH

LAN
CTRL

BMC

IPMI_LAN

JOH1

LEDM1

A. VGA Enabled

B. BMC Enabled

A

B

VGA Enable

Jumper JPG1 allows the user to enable

the onboard VGA connector. The default

setting is on pins 1-2 to enable the con-

nection. See the table on the right for

jumper settings.

VGA Enable

Jumper Settings

Jumper Setting Denition

1-2 Enabled (Default)

2-3 Disabled

BMC Enable

Jumper JPB1 is used to enable or

disable the embedded AST2400 BMC

(Baseboard Management Controller)

that provides IPMI 2.0/KVM support on

the motherboard. See the table on the

right for jumper settings.

BMC Enable

Jumper Settings

Jumper Setting Denition

Pins 1-2 BMC Enable (Default)

Pins 2-3 Disabled

Chapter 2: Installation

2-33

BIOS
LICENSE

BAR CODE

MAC CODE

JPW1

1 1

1

1

JPP0

JITP1

JSPK1

BT1

JTPM1

P1 DIMMA1

P1 DIMMA2

P1 DIMMB2

P1 DIMMB1

CPU1

CPU1 SLOT1 PCI-E 3.0 X16

USB2/3(3.0)

CPU2 SLOT2 PCI-E 3.0 X16

CPU1 SLOT3 PCI-E 3.0 X16

CPU2 SLOT4 PCI-E 3.0 X16

USB4/5 (3.0)

CPU2 SLOT5 PCI-E 3.0 X8 INX16

LAN1LAN2

USB0/1

JPL1

JPF1

JPF2

JPME2

JVRM1

JVRM2

VGA

JPG1

JPB1

JPCIE1_1

JWD1

LE4

SW1

JSTBY1

BIOS

JPCIE1_3

JBR1

JBT1

I-SATA0

I-SATA1

I-SATA3

I-SATA4I-SATA5

I-SATA2

S-SATA0

S-SATA2

S-SATA3

COM1

JPW6

FANCFAND

JPC1

P1 DIMMD2

P1 DIMMD1

P1 DIMMC1

P1 DIMMC2

S-SATA1

JPP1

JPW2

JPW7

FANH

FANF

FANE

FAN1

P2 DIMMF2

P2 DIMMF1

P2 DIMME1

P2 DIMME2

FAN2

FAN3

FAN4

FANA

FANB

JPW3

JPW4

JPW5

JL1

T-SGPIO1

T-SGPIO2

T-SGPIO3

LE2

JF1

Front Control Panel

J23

FANG

CLOSE 1st

OPEN 1st

CLOSE 1st

OPEN 1st

CPU2

P2 DIMMG1

P2 DIMMG2

P2 DIMMH2

P2 DIMMH1

X10DRG-H

Rev. 1.02

PCH

LAN
CTRL

BMC

IPMI_LAN

JOH1

LEDM1

A

A. ME Select

Manufacturer Mode Select

Close pin 2 and pin 3 of Jumper JPME2 to

bypass SPI ash security and force the system

to operate in the Manufacturer mode, which will

allow the user to ash the system rmware from

a host server for system setting modications.

See the table on the right for jumper settings.

ME Mode Select

Jumper Settings

Jumper Setting Denition

1-2 Normal (Default)

2-3 Manufacture Mode

2-34

X10DRG-H/X10DRG-HT Motherboard User’s Manual

BIOS
LICENSE

BAR CODE

MAC CODE

JPW1

1 1

1

1

JPP0

JITP1

JSPK1

BT1

JTPM1

P1 DIMMA1

P1 DIMMA2

P1 DIMMB2

P1 DIMMB1

CPU1

CPU1 SLOT1 PCI-E 3.0 X16

USB2/3(3.0)

CPU2 SLOT2 PCI-E 3.0 X16

CPU1 SLOT3 PCI-E 3.0 X16

CPU2 SLOT4 PCI-E 3.0 X16

USB4/5 (3.0)

CPU2 SLOT5 PCI-E 3.0 X8 INX16

LAN1LAN2

USB0/1

JPL1

JPF1

JPF2

JPME2

JVRM1

JVRM2

VGA

JPG1

JPB1

JPCIE1_1

JWD1

LE4

SW1

JSTBY1

BIOS

JPCIE1_3

JBR1

JBT1

I-SATA0

I-SATA1

I-SATA3

I-SATA4I-SATA5

I-SATA2

S-SATA0

S-SATA2

S-SATA3

COM1

JPW6

FANCFAND

JPC1

P1 DIMMD2

P1 DIMMD1

P1 DIMMC1

P1 DIMMC2

S-SATA1

JPP1

JPW2

JPW7

FANH

FANF

FANE

FAN1

P2 DIMMF2

P2 DIMMF1

P2 DIMME1

P2 DIMME2

FAN2

FAN3

FAN4

FANA

FANB

JPW3

JPW4

JPW5

JL1

T-SGPIO1

T-SGPIO2

T-SGPIO3

LE2

JF1

Front Control Panel

J23

FANG

CLOSE 1st

OPEN 1st

CLOSE 1st

OPEN 1st

CPU2

P2 DIMMG1

P2 DIMMG2

P2 DIMMH2

P2 DIMMH1

X10DRG-H

Rev. 1.02

PCH

LAN
CTRL

BMC

IPMI_LAN

JOH1

LEDM1

2-9 Onboard LED Indicators

A. LAN1/2 LEDs

B. IPMI LAN LEDs

IPMI Dedicated LAN LEDs

In addition to LAN 1/LAN 2, an IPMI- LAN is

located on the I/O Backplane of the moth-

erboard. The amber LED on the right indi-

cates activity, while the other LED on the

left indicates the speed of the connection.

See the tables at right for more information.

LAN 1/LAN 2

Link LED Activity LED

IPMI LAN

IPMI LAN Link LED (Left) &

Activity LED (Right)

Color/State Denition

Link (Left) Green: Solid,

Orange: Solid

100 Mbps
1 Gbps

Activity (Right) Amber: Blinking Active

A

B

A

B

LAN LEDs

The LAN ports are located on the IO Back-

plane on the motherboard. Each Ethernet

LAN port has two LEDs. The yellow LED in-

dicates activity. Link LED, located on the left

side of the LAN port, may be green, amber

or off indicating the speed of the connection.

See the tables at right for more information.

Activity LED

Link LED

GLAN Activity Indicator (Left)

LED Settings

Color Status Denition

Yellow Flashing Active

Rear View (when facing the
rear side of the chassis)

LAN 1/2

LAN Link LED Settin

(X10DRG-HT)

Color Denition

Off No Connec-

tion, 10/100
Mbps

Green 10 Gbps

Amber 1 Gbps

LAN Link LED Set-

tings (X10DRG-H)

Color Denition

Off No connection,

10 Mbps

Green 100 Mbps

Amber 1 Gbps

Chapter 2: Installation

2-35

BIOS
LICENSE

BAR CODE

MAC CODE

JPW1

1 1

1

1

JPP0

JITP1

JSPK1

BT1

JTPM1

P1 DIMMA1

P1 DIMMA2

P1 DIMMB2

P1 DIMMB1

CPU1

CPU1 SLOT1 PCI-E 3.0 X16

USB2/3(3.0)

CPU2 SLOT2 PCI-E 3.0 X16

CPU1 SLOT3 PCI-E 3.0 X16

CPU2 SLOT4 PCI-E 3.0 X16

USB4/5 (3.0)

CPU2 SLOT5 PCI-E 3.0 X8 INX16

LAN1LAN2

USB0/1

JPL1

JPF1

JPF2

JPME2

JVRM1

JVRM2

VGA

JPG1

JPB1

JPCIE1_1

JWD1

LE4

SW1

JSTBY1

BIOS

JPCIE1_3

JBR1

JBT1

I-SATA0

I-SATA1

I-SATA3

I-SATA4I-SATA5

I-SATA2

S-SATA0

S-SATA2

S-SATA3

COM1

JPW6

FANCFAND

JPC1

P1 DIMMD2

P1 DIMMD1

P1 DIMMC1

P1 DIMMC2

S-SATA1

JPP1

JPW2

JPW7

FANH

FANF

FANE

FAN1

P2 DIMMF2

P2 DIMMF1

P2 DIMME1

P2 DIMME2

FAN2

FAN3

FAN4

FANA

FANB

JPW3

JPW4

JPW5

JL1

T-SGPIO1

T-SGPIO2

T-SGPIO3

LE2

JF1

Front Control Panel

J23

FANG

CLOSE 1st

OPEN 1st

CLOSE 1st

OPEN 1st

CPU2

P2 DIMMG1

P2 DIMMG2

P2 DIMMH2

P2 DIMMH1

X10DRG-H

Rev. 1.02

PCH

LAN
CTRL

BMC

IPMI_LAN

JOH1

LEDM1

Note: Refer to Page 2-19 for information on the rear UID LED (LE4).

Onboard Power LED

An Onboard Power LED is located at LE2 on

the motherboard. When this LED is on, the

system is on. Be sure to turn off the system

and unplug the power cord before removing or

installing components. See the tables at right

for more information.

Onboard PWR LED Indicator

LED States

LED Color Denition

Off System Off (PWR cable

not connected)

Green System On

Green:
Flashing
Quickly

ACPI S1 State

A. PWR LED

B. BMC LED

BMC Heartbeat LED

A BMC Heartbeat LED is located at LEDM1

on the motherboard. When LEDM1 is blink-

ing, BMC functions normally. See the table at

right for more information.

BMC Heartbeat LED

States

Color/State Denition

Green:
Blinking

BMC: Normal

A

B

2-36

X10DRG-H/X10DRG-HT Motherboard User’s Manual

Note: For more information on SATA HostRAID conguration, please refer

to the Intel SATA HostRAID User's Guide posted on our website @ http://

www.supermicro.com.

BIOS
LICENSE

BAR CODE

MAC CODE

JPW1

1 1

1

1

JPP0

JITP1

JSPK1

BT1

JTPM1

P1 DIMMA1

P1 DIMMA2

P1 DIMMB2

P1 DIMMB1

CPU1

CPU1 SLOT1 PCI-E 3.0 X16

USB2/3(3.0)

CPU2 SLOT2 PCI-E 3.0 X16

CPU1 SLOT3 PCI-E 3.0 X16

CPU2 SLOT4 PCI-E 3.0 X16

USB4/5 (3.0)

CPU2 SLOT5 PCI-E 3.0 X8 INX16

LAN1LAN2

USB0/1

JPL1

JPF1

JPF2

JPME2

JVRM1

JVRM2

VGA

JPG1

JPB1

JPCIE1_1

JWD1

LE4

SW1

JSTBY1

BIOS

JPCIE1_3

JBR1

JBT1

I-SATA0

I-SATA1

I-SATA3

I-SATA4I-SATA5

I-SATA2

S-SATA0

S-SATA2

S-SATA3

COM1

JPW6

FANCFAND

JPC1

P1 DIMMD2

P1 DIMMD1

P1 DIMMC1

P1 DIMMC2

S-SATA1

JPP1

JPW2

JPW7

FANH

FANF

FANE

FAN1

P2 DIMMF2

P2 DIMMF1

P2 DIMME1

P2 DIMME2

FAN2

FAN3

FAN4

FANA

FANB

JPW3

JPW4

JPW5

JL1

T-SGPIO1

T-SGPIO2

T-SGPIO3

LE2

JF1

Front Control Panel

J23

FANG

CLOSE 1st

OPEN 1st

CLOSE 1st

OPEN 1st

CPU2

P2 DIMMG1

P2 DIMMG2

P2 DIMMH2

P2 DIMMH1

X10DRG-H

Rev. 1.02

PCH

LAN
CTRL

BMC

IPMI_LAN

JOH1

LEDM1

A. I-SATA0

B. I-SATA1

C. I-SATA2

D. I-SATA3

E. I-SATA4 (used w/SuperDOM)

F. I-SATA5 (used w/SuperDOM)

G. S-SATA0

H. S-SATA1

I. S-SATA2

J. S-SATA3

SATA 3.0 Ports

There are ten SATA 3.0 (I-SATA 0-5 & S-SATA0-3) on the moth-

erboard. I-SATA ports are supported by the Intel PCH C612, and

S-SATA ports are supported by the Intel SCU chip. I-SATA 4/5,

colored in yellow, are used with Supermicro SuperDOM (Disk-

on-Module) connectors with power-pins built in. Supermicro

SuperDOM connectors are backward-compatible with regular

SATA HDDs and SATA DOMs. These SATA ports provide serial-

link signal connections, which are faster than the connections

of Parallel ATA. See the table on the right for pin denitions.

C

E

2-10 SATA Connections

B

F

A

G

H

J

D

SATA Connectors

Pin Denitions

Pin# Signal

1 Ground

2 SATA_TXP

3 SATA_TXN

4 Ground

5 SATA_RXN

6 SATA_RXP

7 Ground

I

3-1

Chapter 3: Troubleshooting

Chapter 3

Troubleshooting

3-1 Troubleshooting Procedures

Use the following procedures to troubleshoot your system. If you have followed all

of the procedures below and still need assistance, refer to the "Technical Support

Procedures" and/or "Returning Merchandise for Service" section(s) in this chapter.

Note: Always disconnect the power cord before adding, changing or install-

ing any hardware components.

Before Power On

1. Make sure that there are no short circuits between the motherboard and

chassis.

2. Disconnect all ribbon/wire cables from the motherboard, including those for

the keyboard and mouse.

3. Remove all add-on cards.

4. Install CPU 1 rst (making sure it is fully seated) and connect the front panel

connectors to the motherboard.

No Power

1. Make sure that no short circuits between the motherboard and the chassis.

2. Make sure that all power connectors are properly connected.

3. Check that the 115V/230V switch on the power supply is properly set, if avail-

able.

4. Turn the power switch on and off to test the system, if applicable.

5. The battery on your motherboard may be old. Check to verify that it still sup-

plies ~3VDC. If it does not, replace it with a new one.

3-2

X10DRG-H/X10DRG-HT Motherboard User’s Manual

No Video

1. If the power is on, but you have no video, remove all the add-on cards and

cables.

2. Use the speaker to determine if any beep codes exist. Refer to Appendix A

for details on beep codes.

System Boot Failure

If the system does not display POST or does not respond after the power is turned

on, check the following:

1. Check for any error beep from the motherboard speaker.

•If there is no error beep, try to turn on the system without DIMM modules in-

stalled. If there is still no error beep, try to turn on the system again with only

one processor installed in CPU Socket#1. If there is still no error beep, replace

the motherboard.

•If there are error beeps, clear the CMOS settings by unplugging the power

cord and contracting both pads on the CMOS Clear Jumper (JBT1). (Refer to

Section 2-8 in Chapter 2.)

2. Remove all components from the motherboard, especially the DIMM modules.

Make sure that system power is on, and memory error beeps are activated.

3. Turn on the system with only one DIMM module installed. If the system

boots, check for bad DIMM modules or slots by following the Memory Errors

Troubleshooting procedure in this Chapter.

Losing the System’s Setup Conguration

1. Make sure that you are using a high quality power supply. A poor quality

power supply may cause the system to lose the CMOS setup information.

Refer to Section 2-8 for details on recommended power supplies.

2. The battery on your motherboard may be old. Check to verify that it still sup-

plies ~3VDC. If it does not, replace it with a new one.

3. If the above steps do not x the Setup Conguration problem, contact your

vendor for repairs.

3-3

Chapter 3: Troubleshooting

Memory Errors

When a No-Memory Beep Code is issued by the system, check the following:

1. Make sure that the memory modules are compatible with the system and that

the DIMM modules are properly and fully installed. (For memory compatibility,

refer to the Memory Compatibility Chart posted on our website @ http://www.

supermicro.com.)

2. Check if different speeds of DIMMs have been installed. It is strongly recom-

mended that you use the same RAM type and speed for all DIMMs in the

system.

3. Make sure that you are using the correct type of Registered (RDIMM)/Load

Reduced (LRDIMM) DDR4 ECC modules recommended by the manufacturer.

4. Check for bad DIMM modules or slots by swapping a single module among

all memory slots and check the results.

5. Make sure that all memory modules are fully seated in their slots. Follow the

instructions given in Section 2-5 in Chapter 2.

6. Please follow the instructions given in the DIMM Population Tables listed in

Section 2-5 to install your memory modules.

When the System Becomes Unstable

A. When the system becomes unstable during or after OS installation, check

the following:

1. CPU/BIOS support: Make sure that your CPU is supported, and you have the

latest BIOS installed in your system.

2. Memory support: Make sure that the memory modules are supported by test-

ing the modules using memtest86 or a similar utility.

Note: Refer to the product page on our website http:\\www.supermicro.

com for memory and CPU support and updates.

3. HDD support: Make sure that all hard disk drives (HDDs) work properly. Re-

place the bad HDDs with good ones.

4. System cooling: Check system cooling to make sure that all heatsink fans,

and CPU/system fans, etc., work properly. Check Hardware Monitoring set-

tings in the IPMI to make sure that the CPU and System temperatures are

3-4

X10DRG-H/X10DRG-HT Motherboard User’s Manual

within the normal range. Also check the front panel Overheat LED, and make

sure that the Overheat LED is not on.

5. Adequate power supply: Make sure that the power supply provides adequate

power to the system. Make sure that all power connectors are connected.

Please refer to our website for more information on minimum power require-

ment.

6. Proper software support: Make sure that the correct drivers are used.

B. When the system becomes unstable before or during OS installation, check

the following:

1. Source of installation: Make sure that the devices used for installation are

working properly, including boot devices such as CD/DVD.

2. Cable connection: Check to make sure that all cables are connected and

working properly.

3. Using minimum conguration for troubleshooting: Remove all unnecessary

components (starting with add-on cards rst), and use minimum conguration

(with a CPU and a memory module installed) to identify the trouble areas.

Refer to the steps listed in Section A above for proper troubleshooting proce-

dures.

4. Identifying bad components by isolating them: If necessary, remove a compo-

nent in question from the chassis, and test it in isolation to make sure that it

works properly. Replace a bad component with a good one.

5. Check and change one component at a time instead of changing several

items at the same time. This will help isolate and identify the problem.

6. To nd out if a component is good, swap this component with a new one to

see if the system will work properly. If so, then the old component is bad.

You can also install the component in question in another system. If the new

system works, the component is good and the old system has problems.

3-2 Technical Support Procedures

Before contacting Technical Support, please take the following steps. Also, please

note that as a motherboard manufacturer, Supermicro also sells motherboards

through its channels, so it is best to rst check with your distributor or reseller for

3-5

Chapter 3: Troubleshooting

troubleshooting services. They should know of any possible problem(s) with the

specic system conguration that was sold to you.

1. Please go through the ‘Troubleshooting Procedures’ and 'Frequently Asked

Question' (FAQ) sections in this chapter or see the FAQs on our website

(http://www.supermicro.com/) before contacting Technical Support.

2. BIOS upgrades can be downloaded from our website (http://www.supermicro.

com).

3. If you still cannot resolve the problem, include the following information when

contacting Supermicro for technical support:

•Motherboard model and PCB revision number

•BIOS release date/version (This can be seen on the initial display when your

system rst boots up.)

•System conguration

4. An example of a Technical Support form is on our website at (http://www.

supermicro.com).

•Distributors: For immediate assistance, please have your account number ready

when placing a call to our technical support department. We can be reached by

e-mail at [e-mail].

3-6

X10DRG-H/X10DRG-HT Motherboard User’s Manual

Proper Battery Disposal

Warning! Please handle used batteries carefully. Do not damage the battery in any

way; a damaged battery may release hazardous materials into the environment. Do

not discard a used battery in the garbage or a public landll. Please comply with the

regulations set up by your local hazardous waste management agency to dispose of

your used battery properly.

3-3 Battery Removal and Installation

Battery Removal

To remove the onboard battery, follow the steps below:

1. Power off your system and unplug your power cable.

2. Locate the onboard battery as shown below.

3. Using a tool such as a pen or a small screwdriver, push the battery lock out-

wards to unlock it. Once unlocked, the battery will pop out from the holder.

4. Remove the battery.

OR

3-7

Chapter 3: Troubleshooting

3-4 Frequently Asked Questions

Question: What are the various types of memory that my motherboard can

support?

Answer: The motherboard supports Registered (RDIMM)/Load Reduced (LRDIMM)

ECC DDR4 DIMM modules. To enhance memory performance, do not mix memory

modules of different speeds and sizes. Please follow all memory installation instruc-

tions given on Section 2-5 in Chapter 2.

Question: How do I update my BIOS?

It is recommended that you do not upgrade your BIOS if you are not experiencing

any problems with your system. Updated BIOS les are located on our website

at http://www.supermicro.com. Please check our BIOS warning message and the

information on how to update your BIOS on our website. Select your motherboard

model and download the BIOS le to your computer. Also, check the current BIOS

revision to make sure that it is newer than your BIOS before downloading. You can

choose from the zip le and the .exe le. If you choose the zip BIOS le, please

unzip the BIOS le onto a bootable USB device. Run the batch le using the format

FLASH.BAT lename.rom from your bootable USB device to ash the BIOS. Then,

your system will automatically reboot.

Warning: Do not shut down or reset the system while updating the BIOS to prevent

possible system boot failure!)

Note: The SPI BIOS chip used on this motherboard cannot be removed.

Send your motherboard back to our RMA Department at Supermicro for

repair. For BIOS Recovery instructions, please refer to the AMI BIOS

Recovery Instructions posted at http://www.supermicro.com.

Question: How do I handle the used battery?

Answer: Please handle used batteries carefully. Do not damage the battery in any

way; a damaged battery may release hazardous materials into the environment.

Do not discard a used battery in the garbage or a public landll. Please comply

with the regulations set up by your local hazardous waste management agency to

dispose of your used battery properly.

3-8

X10DRG-H/X10DRG-HT Motherboard User’s Manual

3-5 Returning Merchandise for Service

A receipt or copy of your invoice marked with the date of purchase is required before

any warranty service will be rendered. You can obtain service by calling your ven-

dor for a Returned Merchandise Authorization (RMA) number. When returning the

motherboard to the manufacturer, the RMA number should be prominently displayed

on the outside of the shipping carton, and the shipping package is mailed prepaid

or hand-carried. Shipping and handling charges will be applied for all orders that

must be mailed when service is complete. For faster service, You can also request

a RMA authorization online (http://www.supermicro.com).

This warranty only covers normal consumer use and does not cover damages in-

curred in shipping or from failure due to the alternation, misuse, abuse or improper

maintenance of products.

During the warranty period, contact your distributor rst for any product problems.

Chapter 4: AMI BIOS

4-1

Chapter 4

BIOS

4-1 Introduction

This chapter describes the AMI BIOS setup utility for the X10DFG-H/HT. The ROM

BIOS is stored in a Flash EEPROM and can be easily updated. This chapter de-

scribes the basic navigation of the AMI BIOS setup utility screens.

Note: For AMI BIOS recovery, please refer to the UEFI BIOS Recovery

Instructions in Appendix C.

Starting BIOS Setup Utility

To enter the AMI BIOS setup utility screens, press the <Delete> key while the

system is booting up.

Note: In most cases, the <Delete> key is used to invoke the AMI BIOS

setup screen.

Each main BIOS menu option is described in this manual. The AMI BIOS setup

menu screen has two main frames. The left frame displays all the options that can

be congured. Grayed-out options cannot be congured. Options in blue can be

congured by the user. The right frame displays the key legend. Above the key

legend is an area reserved for a text message. When an option is selected in the

left frame, it is highlighted in white. Often a text message will accompany it.

Note: the AMI BIOS has default text messages built in. Supermicro retains

the option to include, omit, or change any of these text messages.

The AMI BIOS setup utility uses a key-based navigation system called "hot keys."

Most of the AMI BIOS setup utility "hot keys" can be used at any time during the

setup navigation process. These keys include <F1>, <F4>, <Enter>, <Esc>, arrow

keys, etc.

Note: Options printed in Bold are default settings.

How To Change the Conguration Data

The conguration data that determines the system parameters may be changed by

entering the AMI BIOS setup utility. This setup utility can be accessed by pressing

<Del> at the appropriate time during system boot.

4-2

X10DRG-H/X10DRG-HT Motherboard User’s Manual

How to Start the Setup Utility

Normally, the only visible Power-On Self-Test (POST) routine is the memory test.

As the memory is being tested, press the <Delete> key to enter the main menu of

the AMI BIOS setup utility. From the main menu, you can access the other setup

screens. An AMI BIOS identication string is displayed at the left bottom corner of

the screen, below the copyright message.

Warning: Do not upgrade the BIOS unless your system has a BIOS-related issue.

Flashing the wrong BIOS can cause irreparable damage to the system. In no event shall

Supermicro be liable for direct, indirect, special, incidental, or consequential damages

arising from a BIOS update. If you have to update the BIOS, do not shut down or reset

the system while the BIOS is updating to avoid possible boot failure.

4-2 Main Setup

When you rst enter the AMI BIOS setup utility, you will enter the Main setup screen.

You can always return to the Main setup screen by selecting the Main tab on the

top of the screen. The Main BIOS setup screen is shown below.

Chapter 4: AMI BIOS

4-3

The following Main menu items will be displayed:

System Date/System Time

Use this option to change the system date and time. Highlight System Date or

System Time using the arrow keys. Enter new values using the keyboard. Press the

<Tab> key or the arrow keys to move between elds. The date must be entered in

Day MM/DD/YYYY format. The time is entered in HH:MM:SS format.

Note: The time is in the 24-hour format. For example, 5:30 P.M. appears

as 17:30:00.

Supermicro X10DRG

BIOS Version: This item displays the version of the BIOS ROM used in the system.

Build Date: This item displays the date when the version of the BIOS ROM used

in the system was built.

Memory Information

Total Memory: This item displays the total size of memory available in the system.

Memory Speed: This item displays the default speed of the memory modules

installed in the system.

4-4

X10DRG-H/X10DRG-HT Motherboard User’s Manual

4-3 Advanced Setup Congurations

Use the arrow keys to select Advanced setup and press <Enter> to access the

submenu items:

Warning: Take Caution when changing the Advanced settings. An incorrect value, a

very high DRAM frequency or an incorrect BIOS timing setting may cause the system

to malfunction. When this occurs, restore the setting to the manufacture default setting.



Boot Feature

Quiet Boot

Use this feature to select the screen display between POST messages or the OEM

logo at bootup. Select Disabled to display the POST messages. Select Enabled

to display the OEM logo instead of the normal POST messages. The options are

Enabled and Disabled.

AddOn ROM Display Mode

Use this item to set the display mode for the Option ROM. Select Keep Current to

use the current AddOn ROM display setting. Select Force BIOS to use the Option

ROM display mode set by the system BIOS. The options are Force BIOS and

Keep Current.

Bootup Num-Lock State

Use this feature to set the Power-on state for the Numlock key. The options are

Off and On.

Chapter 4: AMI BIOS

4-5

Wait For 'F1' If Error

Select Enabled to force the system to wait until the 'F1' key is pressed if an error

occurs. The options are Disabled and Enabled.

INT19 (Interrupt 19) Trap Response

Interrupt 19 is the software interrupt that handles the boot disk function. When this

item is set to Immediate, the ROM BIOS of the host adaptors will "capture" Inter-

rupt 19 at bootup immediately and allow the drives that are attached to these host

adaptors to function as bootable disks. If this item is set to Postponed, the ROM

BIOS of the host adaptors will not capture Interrupt 19 immediately and allow the

drives attached to these adaptors to function as bootable devices at bootup. The

options are Immediate and Postponed.

Re-try Boot

When EFI Boot is selected, the system BIOS will automatically reboot the system

from an EFI boot device after its initial boot failure. Select Legacy Boot to allow

the BIOS to automatically reboot the system from a Legacy boot device after its

initial boot failure. The options are Disabled, Legacy Boot, and EFI Boot.

Power Conguration

Watch Dog Function

Select Enabled to allow the Watch Dog timer to reboot the system when it is inac-

tive for more than 5 minutes. The options are Enabled and Disabled.

Power Button Function

This feature controls how the system shuts down when the power button is pressed.

Select 4 Seconds Override for the user to power off the system after pressing and

holding the power button for 4 seconds or longer. Select Instant Off to instantly

power off the system as soon as the user presses the power button. The options

are 4 Seconds Override and Instant Off.

Restore on AC Power Loss

Use this feature to set the power state after a power outage. Select Power-Off for

the system power to remain off after a power loss. Select Power-On for the system

power to be turned on after a power loss. Select Last State to allow the system

to resume its last power state before a power loss. The options are Power-On,

Stay-Off and Last State.

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X10DRG-H/X10DRG-HT Motherboard User’s Manual

CPU Conguration

This submenu displays the following CPU information as detected by the BIOS. It

also allows the user to congure CPU settings.

•Processor Socket

•Processor ID

•Processor Frequency

•Processor Max Ratio

•Processor Min Ratio

•Microcode Revision

•L1 Cache RAM

•L2 Cache RAM

•L3 Cache RAM

•Processor 0 Version

•Processor 1 Version

Clock Spread Spectrum

Select Enable to allow the BIOS to monitor and attempt to reduce the level of

Electromagnetic Interference caused by the components whenever needed. The

options are Disable and Enable.

Hyper-Threading (All)

Select Enable to support Intel's Hyper-threading Technology to enhance CPU per-

formance. The options are Enable and Disable.

Cores Enabled

This feature allows the user to set the number of CPU cores to enable. Enter "0"

to enable all cores. The default setting is 0.

Execute-Disable Bit (Available if supported by the OS & the CPU)

Select Enable for Execute Disable Bit Technology support, which will allow the

processor to designate areas in the system memory where an application code can

execute and where it cannot, thus preventing a worm or a virus from ooding illegal

Chapter 4: AMI BIOS

4-7

codes to overwhelm the processor to damage the system during an attack. This

feature is used in conjunction with the items: "Clear MCA," "VMX," "Enable SMX,"

and "Lock Chipset" for Virtualization media support. The options are Enable and

Disable. (Refer to Intel and Microsoft websites for more information.)

PPIN Control

Select Unlock/Enable to use the Protected-Processor Inventory Number (PPIN) in

the system. The options are Unlock/Enable and Unlock/Disable.

Hardware Prefetcher (Available when supported by the CPU)

If set to Enable, the hardware prefetcher will prefetch streams of data and instruc-

tions from the main memory to the L2 cache to improve CPU performance. The

options are Disable and Enable.

Adjacent Cache Prefetch (Available when supported by the CPU)

Select Enable for the CPU to prefetch both cache lines for 128 bytes as comprised.

Select Disable for the CPU to prefetch both cache lines for 64 bytes. The options

are Disable and Enable.

Note: Please reboot the system for changes on this setting to take effect.

Please refer to Intel’s website for detailed information.

DCU (Data Cache Unit) Streamer Prefetcher (Available when supported by
the CPU)

If set to Enable, the DCU Streamer Prefetcher will prefetch data streams from the

cache memory to the DCU (Data Cache Unit) to speed up data accessing and

processing to enhance CPU performance. The options are Disable and Enable.

DCU IP Prefetcher

If set to Enable, the IP prefetcher in the DCU (Data Cache Unit) will prefetch IP

addresses to improve network connectivity and system performance. The options

are Enable and Disable.

Direct Cache Access (DCA)

Select Enable to use Intel DCA (Direct Cache Access) Technology to improve the

efciency of data transferring and accessing. The options are Auto, Enable, and

Disable.

X2APIC (Advanced Programmable Interrupt Controller)

Based on Intel's Hyper-Threading architecture, each logical processor (thread) is

assigned 256 APIC IDs (APIDs) in 8-bit bandwidth. When this feature is set to En-

able, the APIC ID will be expanded from 8 bits (X2) to 16 bits to provide 512 APIDs

to each thread to enhance CPU performance. The options are Disable and Enable.

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X10DRG-H/X10DRG-HT Motherboard User’s Manual

AES-NI

Select Enable to use the Intel Advanced Encryption Standard (AES) New Instruc-

tions (NI) to ensure data security. The options are Enable and Disable.

Intel Virtualization Technology

Select Enable to use Intel Virtualization Technology support for Direct I/O VT-d sup­port by reporting the I/O device assignments to the VMM (Virtual Machine Monitor)

through the DMAR ACPI tables. This feature offers fully-protected I/O resource

sharing across Intel platforms, providing greater reliability, security and availability

in networking and data-sharing. The options are Enable and Disable.

Chipset Conguration

Warning! Please set the correct settings for the items below. A wrong conguration

setting may cause the system to malfunction.

North Bridge

This feature allows the user to congure the settings for the Intel North Bridge.

IIO Conguration

EV DFX (Device Function On-Hide) Feature

When this feature is set to Enable, the EV_DFX Lock Bits that are located on a

processor will always remain clear during electric tuning. The options are Dis-

able and Enable.

IIO1 Conguration

IIO2 (IOU PCIe Port1)

This item congures the PCI-E port Bifuraction setting for a PCI-E port specied

by the user. The options are x4x4, x8, and Auto.

IIO0 (IOU PCIe Port2)

This item congures the PCI-E port Bifuraction setting for a PCI-E port specied

by the user. The options are x4x4x4x4, x4x4x8, x8x4x4, x8x8, x16, and Auto.

IIO 1 (IOU PCIe Port3)

This item congures the PCI-E port Bifuraction setting for a PCI-E port specied

by the user. The options are x4x4x4x4, x4x4x8, x8x4x4, x8x8, x16, and Auto.

Chapter 4: AMI BIOS

4-9

No PCIe Port Active ECO

This item provides a workaround solution when there is no PCIe port active.

The options are Reset the SQ FLOP by CSR Option and PCU Squelch Exit

Ignore Option.

Socket 0 PCIED00F0 Port 0/DMI

This submenu allows the user to congure the settings for the following PCI-E

prots: 0, 1A, 1B, 2A, 2B, 2C, 2D, 3A, 3B, 3C, and 3D.

Link Speed

Use this item to congure the link speed of a PCI-E device installed on the PCI-E

slot specied by the user. The options are Gen1, Gen2, and Gen3.

PCI-E Port DeEmphasis

DeEmphasis is used to decrease the magnitude of very high frequencies in

relation to the magnitude of very low frequencies to improve the overall signal-

to-noise ratio by reducing the level of all (signals) data bits transmitted except the

rst one, acting as a form of transmitter equalization to enhance signal transmis-

sion and audio performance. The options are -3.5 dB and -6.0 dB.

PCI-E Port L0s Exit Latency

Use this item to congure the exit latency of the PCI-E port L0s link state, measur-

ing the length of time needed to transition from the L0s link state to L0. The avail-

able latency option is 4uS - 8uS. (Note: "uS" is a stand-in for "microseconds.")

PCI-E Port L1 Exit Latency

Use this item to congure the exit latency of the PCI-E port L1 link state, measur-

ing the length of time needed to transition from the L1 link state to L0. The latency

options are <1uS, 1uS - 2uS, 2uS - 4uS, 4uS - 8uS, 8uS - 16uS, 16uS - 32uS,

32uS - 64uS, >64uS. (Note: "uS" is a stand-in for "microseconds.")

Fatal Err Over (Fatal Error Overwrite)

This item congures the option to overwrite fatal errors. The options are Dis-

able and Enable.

Non-Fatal Err Over (Non-Fatal Error Overwrite)

This item congures the option to overwrite non-fatal errors. The options are

Disable and Enable.

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X10DRG-H/X10DRG-HT Motherboard User’s Manual

Corr Err Over (Correctable Error Overwrite)

This item congures the option to overwrite correctable errors for ECC memory.

The options are Disable and Enable.

L0s Support

This item congures the option to enable support for the L0s PCI-E link state

(non supported in this motherboard). The only available option is Disable.

IOAT (Intel® IO Acceleration) Conguration

Enable IOAT

Select Enable to enable Intel I/OAT (I/O Acceleration Technology) support,

which will signicantly reduce CPU overhead by leveraging CPU architectural

improvements and freeing the system resource for other tasks. The options are

Enable and Disable.

No Snoop

Select Enable to support no-snoop mode for each CB device. The options are

Disable and Enable.

Relaxed Ordering

Select Enable to enable Relaxed Ordering support which will allow certain

transactions to violate the strict-ordering rules of PCI bus for a transaction to be

completed prior to other transactions that have already been enqueued earlier.

The options are Disable and Enable.

 Intel VT for Directed I/O (VT-d)

Intel VT for Direct I/O (VT-d)

Select Enable to use Intel Virtualization Technology support for Direct I/O VT-d
support by reporting the I/O device assignments to the VMM (Virtual Machine

Monitor) through the DMAR ACPI Tables. This feature offers fully-protected I/O

resource sharing across Intel platforms, providing greater reliability, security and

availability in networking and data-sharing. The options are Enable and Disable.

Interrupt Remapping

Select Enable for Interrupt Remapping support to enhance system performance.

The options are Enable and Disable.

Chapter 4: AMI BIOS

4-11

QPI (Quick Path Interconnect) Conguration

QPI General Conguration

QPI Status

The following information will display:

•Number of CPU

•Number of IIO

•Current QPI Link Speed

•Current QPI Link Frequency

•QPI Global MMIO Low Base/Limit

•QPI Global MMIO High Base/Limit

•QPI PCIe Conguration Base/Size

Link Frequency Select

Use this item to select the desired frequency for QPI Link connections. The op-

tions are 6.4GB/s, 8.0GB/s, 9.6GB/s, Auto, and Auto Limited.

Link L0p Enable

Select Enable for Link L0p support. The options are Enable and Disable.

Link L1 Enable

Select Enable for Link L1 support. The options are Enable and Disable.

COD Enable (Available when the OS and the CPU support this feature)

Select Enabled for Cluster-On-Die support to enhance system performance in

cloud computing. The options are Enable and Disable.

Early Snoop (Available when the OS and the CPU support this feature)

Select Enable for Early Snoop support to enhance system performance. The

options are Enable, Disable, and Auto.

Isoc Mode

Select Enable for Isochronous support to meet QoS (Quality of Service) require-

ments. This feature is especially important for Virtualization Technology. The

options are Enable and Disable.

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X10DRG-H/X10DRG-HT Motherboard User’s Manual

Memory Conguration

Enforce POR

Select Enable to enforce POR restrictions on memory frequency and voltage

programming. The options are Enabled and Disabled.

Memory Frequency

Use this feature to set the maximum memory frequency for onboard memory

modules. The options are Auto, 1333, 1400, 1600, 1800, 1867, 2000, 2133,

2200, 2400, 2600, 2667, 2800, 2993, 3000, 3200 and Reserved (Do not select

Reserved).

Data Scrambling

Select Enabled to enable data scrambling to enhance system performance and

data integrity. The options are Auto, Disabled, and Enabled.

DRAM RAPL (Running Average Power Limit) Baseline

Use this feature to set the run-time power-limit baseline for the DRAM modules.

The options are Disable, DRAM RAPL Mode 0, and DRAM RAPL Mode 1.

Set Throttling Mode

Throttling improves reliability and reduces power consumption in processors via

automatic voltage control during processor idle states. The options are Disabled

and CLTT (Closed Loop Thermal Throttling).

Socket Interleave Below 4GB

Select Enabled for the memory above the 4G Address space to be split between

two sockets. The options are Enable and Disable.

A7 Mode

Select Enabled to support the A7 (Addressing) mode to improve memory per-

formance. The options are Enable and Disable.

DIMM Information

This item displays the status of a DIMM module as detected by the BIOS.

P1-DIMMA1/A2, P1-DIMMB1/B2, P1-DIMMC1/C2, P1-DIMMD1/D2, P2-

DIMME1/E2, P2-DIMMF1/F2, P2-DIMMG1/G2, and P2-DIMMH1/H2

Memory RAS (Reliability_Availability_Serviceability)

Conguration

Use this submenu to congure the following Memory RAS settings.

Chapter 4: AMI BIOS

4-13

RAS Mode

When Disable is selected, RAS is not supported. When Mirror is selected, the

motherboard maintains two identical copies of all data in memory for data backup.

When Lockstep is selected, the motherboard uses two areas of memory to run

the same set of operations in parallel to boost performance. The options are

Disable, Mirror, and Lockstep Mode.

Memory Rank Sparing

Select Enable to enable memory-sparing support for memory ranks to improve

memory performance. The options are Disabled and Enabled.

Patrol Scrub

Patrol Scrubbing is a process that allows the CPU to correct correctable memory

errors detected on a memory module and send the correction to the requestor

(the original source). When this item is set to Enable, the PCH (Platform Control

Hub) will read and write-back one cache line every 16K cycles if there is no delay

caused by internal processing. By using this method, roughly 64 GB of memory

behind the PCH will be scrubbed every day. The options are Enable and Disable.

Patrol Scrub Interval

This feature allows you to decide how many hours the system should wait before

the next complete patrol scrub is performed. Use the keyboard to enter a value

from 0-24. The Default setting is 24.

Demand Scrub

Demand Scrubbing is a process that allows the CPU to correct correctable

memory errors found on a memory module. When the CPU or I/O issues a

demand-read command, and the read data from memory turns out to be a

correctable error, the error is corrected and sent to the requestor (the original

source). Memory is updated as well. Select Enable to use Demand Scrubbing

for ECC memory correction. The options are Enable and Disable.

Device Tagging

Select Enable to support device tagging. The options are Disable and Enable.



South Bridge Conguration

The following South Bridge information will display:



USB Conguration

•USB Module Version

4-14

X10DRG-H/X10DRG-HT Motherboard User’s Manual

•USB Devices

Legacy USB Support

Select Enabled to support onboard legacy USB devices. Select Auto to disable

legacy support if there are no legacy USB devices present. Select Disable to have

all USB devices available for EFI applications only. The options are Enabled,

Disabled, and Auto.

XHCI (Extensible Host Controller Interface) Hand-Off

This is a work-around solution for operating systems that do not support XHCI (Ex-

tensible Host Controller Interface) hand-off. The XHCI ownership change should be

claimed by the XHCI driver. The settings are Enabled and Disabled.

EHCI (Enhanced Host Controller Interface) Hand-Off

This item is for operating systems that do not support Enhanced Host Controller

Interface (EHCI) hand-off. When this item is enabled, EHCI ownership change will

be claimed by the EHCI driver. The settings are Enabled and Disabled.

Port 60/64 Emulation

Select Enabled for I/O port 60h/64h emulation support, which in turn, will provide

complete legacy USB keyboard support for the operating systems that do not sup-

port legacy USB devices. The options are Disabled and Enabled.

USB 3.0 Support

Select Enabled for USB 3.0 support. The options are Smart Auto, Auto, Enabled,

Disabled, and Manual.

EHCI1

Select Enabled to enable EHCI (Enhanced Host Controller Interface) support on

USB 2.0 connector #1 (-at least one USB 2.0 connector should be enabled for EHCI

support.) The options are Disabled and Enabled.

EHCI2

Select Enabled to enable EHCI (Enhanced Host Controller Interface) support on

USB 2.0 connector #2 (-at least one USB 2.0 connector should be enabled for EHCI

support.) The options are Disabled and Enabled.

Chapter 4: AMI BIOS

4-15



SATA Conguration

When this submenu is selected, AMI BIOS automatically detects the presence of

the SATA devices that are supported by the Intel PCH chip and displays the fol-

lowing items:

SATA Controller

This item enables or disables the onboard SATA controller supported by the Intel

PCH chip. The options are Enabled and Disabled.

Congure SATA as

Select IDE to congure a SATA drive specied by the user as an IDE drive. Select

AHCI to congure a SATA drive specied by the user as an AHCI drive. Select

RAID to congure a SATA drive specied by the user as a RAID drive. The options

are IDE, AHCI, and RAID.

*If the item above "Congure SATA as" is set to AHCI, the following items will display:

Support Aggressive Link Power Management

When this item is set to Enabled, the SATA AHCI controller manages the power

usage of the SATA link. The controller will put the link to a low power state when

the I/O is inactive for an extended period of time, and the power state will return

to normal when the I/O becomes active. The options are Enabled and Disabled.

SATA Port 0~ Port 5

This item displays the information detected on the installed SATA drive on the

particular SATA port.

•Model number of drive and capacity

•Software Preserve Support

Port 0 ~ Port 5

Select Enabled to enable a SATA port specied by the user. The options are

Disabled and Enabled.

Port 0 ~ Port 5 Spin Up Device

On an edge detect from 0 to 1, set this item to allow the PCH to initialize the

device. The options are Enabled and Disabled.

Port 0 ~ Port 5 SATA Device Type

Use this item to specify if the SATA port specied by the user should be con-

nected to a Solid State drive or a Hard Disk Drive. The options are Hard Disk

Drive and Solid State Drive.

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X10DRG-H/X10DRG-HT Motherboard User’s Manual

*If the item above "Congure SATA as" is set to IDE, the following items will

display:

Serial ATA Port 0 ~ Port 5

This item indicates that a SATA port specied by the user is installed (present)

or not.

Port 0 ~ Port 5 SATA Device Type (Available when a SATA port is
detected)

Use this item to specify if the SATA port specied by the user should be con-

nected to a Solid State drive or a Hard Disk Drive. The options are Hard Disk

Drive and Solid State Drive.

*If the item above "Congure SATA as" is set to RAID, the following items will

display:

Support Aggressive Link Power Management

When this item is set to Enabled, the SATA AHCI controller manages the power

usage of the SATA link. The controller will put the link to a low power state when

the I/O is inactive for an extended period of time, and the power state will return

to normal when the I/O becomes active. The options are Enabled and Disabled.

SATA RAID Option ROM/UEFI Driver

Select EFI to load the EFI driver for system boot. Select Legacy to load a legacy

driver for system boot. The options are Disabled, EFI, and Legacy.

SATA/sSATA RAID Boot Select

Select SATA Controller to boot the system from a SATA RAID device. Select

sSATA Controller to boot the system from a S-SATA RAID device. Select Both to

boot the system either from a SATA RAID device or from an sSATA RAID device.

Please note that the option-Both is not supported by the Windows Server 2012/

R2 OS. The options are None, Both, SATA Controller, and sSATA Controller.

Serial ATA Port 0 ~ Port 5

This item displays the information detected on the installed SATA drives on the

particular SATA port.

•Model number of drive and capacity

•Software Preserve Support

Port 0 ~ Port 5

Select Enabled to enable a SATA port specied by the user. The options are

Disabled and Enabled.

Chapter 4: AMI BIOS

4-17

Port 0 ~ Port 5 Spin Up Device

On an edge detect from 0 to 1, set this item to allow the PCH to start a COMRE-

SET initialization to the device. The options are Enabled and Disabled.

Port 0 ~ Port 5 SATA Device Type

Use this item to specify if the SATA port specied by the user should be con-

nected to a Solid State drive or a Hard Disk Drive. The options are Hard Disk

Drive and Solid State Drive.



sSATA Conguration

When this submenu is selected, AMI BIOS automatically detects the presence of

the SATA devices that are supported by the PCH-sSATA controller and displays

the following items:

sSATA Controller

This item enables or disables the onboard SATA controller supported by the Intel

PCH-sSATA controller. The options are Enabled and Disabled.

Congure sSATA as

Select IDE to congure an sSATA drive specied by the user as an IDE drive. Select

AHCI to congure an sSATA drive specied by the user as an AHCI drive. Select

RAID to congure an sSATA drive specied by the user as a RAID drive. The op-

tions are IDE, AHCI, and RAID.

*If the item above "Congure sSATA as" is set to AHCI, the following items will

display:

Support Aggressive Link Power Management

When this item is set to Enabled, the SATA AHCI controller manages the power

usage of the SATA link. The controller will put the link to a low power state when

the I/O is inactive for an extended period of time, and the power state will return

to normal when the I/O becomes active. The options are Enabled and Disabled.

sSATA Port 0 ~ Port 3

This item displays the information detected on the installed on the sSATA port.

specied by the user.

•Model number of drive and capacity

•Software Preserve Support

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X10DRG-H/X10DRG-HT Motherboard User’s Manual

sSATA Port 0 ~ Port 3 Spin Up Device

On an edge detect from 0 to 1, set this item to allow the PCH to start a COMRE-

SET initialization to the device. The options are Enabled and Disabled.

Port 0 ~ Port 3 sSATA Device Type

Use this item to specify if the sSATA port specied by the user should be con-

nected to a Solid State drive or a Hard Disk Drive. The options are Hard Disk

Drive and Solid State Drive.

*If the item above "Congure sSATA as" is set to IDE, the following items will

display:

sSATA Port 0 ~ Port 3

This item indicates that an sSATA port specied by the user is installed (pres-

ent) or not.

Port 0 ~ Port 3 sSATA Device Type (Available when a SATA port is
detected)

Use this item to specify if the sSATA port specied by the user should be con-

nected to a Solid State drive or a Hard Disk Drive. The options are Hard Disk

Drive and Solid State Drive.

*If the item above "Congure sSATA as" is set to RAID, the following items will

display:

Support Aggressive Link Power Management

When this item is set to Enabled, the SATA AHCI controller manages the power

usage of the SATA link. The controller will put the link to a low power state when

the I/O is inactive for an extended period of time, and the power state will return

to normal when the I/O becomes active. The options are Enabled and Disabled.

sSATA RAID Option ROM/UEFI Driver

Select EFI to load the EFI driver for system boot. Select Legacy to load a legacy

driver for system boot. The options are Disabled, EFI, and Legacy.

SATA/sSATA RAID Boot Select

Select SATA Controller to use a device supported by the SATA connector for

system boot. Select sSATA Controller to use a device supported by the sSATA

connector for system boot. The options are None, SATA Controller, sSATA

Controller, and Both.

sSATA Port 0 ~ Port 3

This item displays the information detected on the installed sSATA drives on the

particular sSATA port.

Chapter 4: AMI BIOS

4-19

•Model number of drive and capacity

•Software Preserve Support

sSATA Port 0 ~ Port 3

Select Enabled to enable an sSATA port specied by the user. The options are

Disabled and Enabled.

sSATA Port 0 ~ Port 3 Spin Up Device

On an edge detect from 0 to 1, set this item to allow the PCH to start a COMRE-

SET initialization to the device. The options are Enabled and Disabled.

Port 0 ~ Port 3 sSATA Device Type

Use this item to specify if the sSATA port specied by the user should be con-

nected to a Solid State drive or a Hard Disk Drive. The options are Hard Disk

Drive and Solid State Drive.

Server ME (Management Engine) Conguration

This feature displays the following system ME conguration settings.

•General ME Conguration

•Operational Firmware Version

•Recovery Firmware Version

•ME Firmware Features

•ME Firmware Status #1

•ME Firmware Status #2

•Current State

•Error Code

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X10DRG-H/X10DRG-HT Motherboard User’s Manual

PCIe/PCI/PnP Conguration

PCI Devices Common Settings

PCI Latency Timer

Select Enabled to set the latency timer for PCI. The options are 32 PCI Bus Clocks,

64 PCI Bus Clocks, 96 PCI Bus Clocks, 128 PCI Bus Clocks, 160 PCI Bus Clocks,

192 PCI Bus Clocks, 224 PCI Bus Clocks, and 248 PCI Bus Clocks.

PERR# Generation

Select Enabled to support PERR (PCI/PCI-E Parity Error)/SERR (System Error)

runtime error reporting for a PCI/PCI-E slot. The options are Enabled and Disabled.

SERR# Generation

Select Enabled to support PERR (PCI/PCI-E Parity Error)/SERR (System Error)

runtime error reporting for a PCI/PCI-E slot. The options are Enabled and Disabled.

PCI PERR/SERR Support

Select Enabled to support PERR (PCI/PCI-E Parity Error)/SERR (System Error)

runtime error reporting for a PCI/PCI-E slot. The options are Enabled and Disabled.

Above 4G Decoding (Available if the system supports 64-bit PCI decoding)

Select Enabled to decode a PCI device that supports 64-bit in the space above 4G

Address. The options are Enabled and Disabled.

SR-IOV (Available if the system supports Single-Root Virtualization)

Select Enabled for Single-Root IO Virtualization support. The options are Enabled

and Disabled.

Maximum Payload

Select Auto for the system BIOS to automatically set the maximum payload value

for a PCI-E device to enhance system performance. The options are Auto, 128

Bytes, and 256 Bytes.

Maximum Read Request

Select Auto for the system BIOS to automatically set the maximum size for a read

request for a PCI-E device to enhance system performance. The options are Auto,

128 Bytes, 256 Bytes, 512 Bytes, 1024 Bytes, 2048 Bytes, and 4096 Bytes.

Chapter 4: AMI BIOS

4-21

ASPM Support

Use this item to set the Active State Power Management (ASPM) level for a PCI-E

device. Select Auto for the system BIOS to automatically set the ASPM level based

on the system conguration. Select Disabled to disable ASPM support. The options

are Disabled and Auto.

Warning: Enabling ASPM support may cause some PCI-E devices to fail!

MMIOHBase

Use this item to select the base memory size according to memory-address map-

ping for the PCH. The base memory size must be between 4032G to 4078G. The

options are 56T, 48T, 24T, 2T, 512G, and 256G.

MMIO High Size

Use this item to select the high memory size according to memory-address mapping

for the PCH. The options are 256G, 128G, 512G, and 1024G.

PCI Device Option ROM Setting

CPU1 Slot 1 PCI-E x16 OPROM (Option ROM)

Select Enabled to enable Option ROM support to boot the computer using a device

installed on slot 1. The options are Disabled, Legacy, and EFI.

CPU1 Slot 2 PCI-E x16 OPROM (Option ROM)

Select Enabled to enable Option ROM support to boot the computer using a device

installed on slot 2. The options are Disabled, Legacy, and EFI.

CPU1 Slot 3 PCI-E x16 OPROM (Option ROM)

Select Enabled to enable Option ROM support to boot the computer using a device

installed on slot 3. The options are Disabled, Legacy, and EFI.

CPU1 Slot 4 PCI-E x16 OPROM (Option ROM)

Select Enabled to enable Option ROM support to boot the computer using a device

installed on slot 4. The options are Disabled, Legacy, and EFI.

CPU1 Slot 5 PCI-E x16 OPROM (Option ROM)

Select Enabled to enable Option ROM support to boot the computer using a device

installed on slot 5. The options are Disabled, Legacy, and EFI.

Onboard Video OPROM (Option ROM)

Select Enabled to enable Option ROM support to boot the computer using a device

installed on the slot specied by the user. The options are DISABLED, Legacy,

and EFI.

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X10DRG-H/X10DRG-HT Motherboard User’s Manual

VGA Priority

Use this item to select the graphics device to be used as the primary video display

for system boot. The options are Onboard and Offboard.

Onboard LAN Option ROM Type

Select Legacy to boot the computer using a Legacy device installed on the moth-

erboard. The options are Legacy and EFI.

Onboard LAN1 Option ROM/Onboard LAN2 Option ROM

Use this option to select the type of device installed in LAN Port1, LAN Port2 or

the onboard video device used for system boot. The options for LAN1 Option ROM

are PXE, iSCSI, and Disabled, and the options for LAN2 Option ROM are PXE

and Disabled. The other options are iSCSI and Disabled.

Network Stack

Select Enabled to enable PXE (Preboot Execution Environment) or UEFI (Uni-

ed Extensible Firmware Interface) for network stack support. The options are

Enabled and Disabled.



Super IO Conguration

Super IO Chip AST2400



Serial Port 1 Conguration/Serial Port 2 Conguration

Serial Port

Select Enabled to enable the onboard serial port specied by the user. The options

are Enabled and Disabled.

Change Port 1 Settings/Change Port 2 Settings

This feature species the base I/O port address and the Interrupt Request address

of Serial Port 1 or Serial Port 2. Select Auto for the BIOS to automatically assign

the base I/O and IRQ address to a serial port specied.

The options for Serial Port 1 are Auto, (IO=3F8h; IRQ=4), (IO=3F8h; IRQ=3, 4, 5,

6, 7, 10, 11, 12), (IO=2F8h; IRQ=3, 4, 5, 6, 7, 10, 11, 12); (IO=3E8h; IRQ=3, 4, 5,

6, 7, 10, 11, 12), and (IO=2E8h; IRQ=3, 4, 5, 6, 7, 10, 11, 12).

The options for Serial Port 2 are Auto, (IO=2F8h; IRQ=3), (IO=3F8h; IRQ=3, 4, 5,

6, 7, 10, 11, 12), (IO=2F8h; IRQ=3, 4, 5, 6, 7, 10, 11, 12); (IO=3E8h; IRQ=3, 4, 5,

6, 7, 10, 11, 12), and (IO=2E8h; IRQ=3, 4, 5, 6, 7,10, 11, 12).

Chapter 4: AMI BIOS

4-23

Serial Port 2 Attribute

Select SOL to use COM Port 2 as a Serial_Over_LAN (SOL) port for console redi-

rection. The options are COM and SOL.



Serial Port Console Redirection

COM 1

COM 1 Console Redirection

Select Enabled to enable COM Port 1 Console Redirection, which will allow a client

machine to be connected to a host machine at a remote site for networking. The

options are Disabled and Enabled.

*If the item above set to Enabled, the following items will become available for

conguration:

COM1 Console Redirection Settings

Terminal Type

This feature allows the user to select the target terminal emulation type for Con-

sole Redirection. Select VT100 to use the ASCII Character set. Select VT100+ to

add color and function key support. Select ANSI to use the Extended ASCII Char-

acter Set. Select VT-UTF8 to use UTF8 encoding to map Unicode characters

into one or more bytes. The options are ANSI, VT100, VT100+, and VT-UTF8.

Bits per second

Use this item to set the transmission speed for a serial port used in Console

Redirection. Make sure that the same speed is used in the host computer and the

client computer. A lower transmission speed may be required for long and busy

lines. The options are 9600, 19200, 38400, 57600, and 115200 (bits per second).

Data Bits

Use this feature to set the data transmission size for Console Redirection. The

options are 7 (Bits) and 8 (Bits).

Parity

A parity bit can be sent along with regular data bits to detect data transmission

errors. Select Even if the parity bit is set to 0, and the number of 1's in data bits

is even. Select Odd if the parity bit is set to 0, and the number of 1's in data bits

is odd. Select None if you do not want to send a parity bit with your data bits

in transmission. Select Mark to add a mark as a parity bit to be sent along with

4-24

X10DRG-H/X10DRG-HT Motherboard User’s Manual

the data bits. Select Space to add a Space as a parity bit to be sent with your

data bits. The options are None, Even, Odd, Mark, and Space.

Stop Bits

A stop bit indicates the end of a serial data packet. Select 1 Stop Bit for standard

serial data communication. Select 2 Stop Bits if slower devices are used. The

options are 1 and 2.

Flow Control

Use this item to set the ow control for Console Redirection to prevent data

loss caused by buffer overow. Send a "Stop" signal to stop sending data when

the receiving buffer is full. Send a "Start" signal to start sending data when the

receiving buffer is empty. The options are None and Hardware RTS/CTS.

VT-UTF8 Combo Key Support

Select Enabled to enable VT-UTF8 Combination Key support for ANSI/VT100

terminals. The options are Enabled and Disabled.

Recorder Mode

Select Enabled to capture the data displayed on a terminal and send it as text

messages to a remote server. The options are Disabled and Enabled.

Resolution 100x31

Select Enabled for extended-terminal resolution support. The options are Dis-

abled and Enabled.

Legacy OS Redirection Resolution

Use this item to select the number of rows and columns used in Console Redi-

rection for legacy OS support. The options are 80x24 and 80x25.

Putty KeyPad

This feature selects Function Keys and KeyPad settings for Putty, which is a

terminal emulator designed for the Windows OS. The options are VT100, LINUX,

XTERMR6, SCO, ESCN, and VT400.

Redirection After BIOS Post

Use this feature to enable or disable legacy Console Redirection after BIOS

POST. When the option BootLoader is selected, legacy Console Redirection is

disabled before booting the OS. When Always Enable is selected, legacy Console

Redirection remains enabled upon OS bootup. The options are Always Enable

and BootLoader.

Chapter 4: AMI BIOS

4-25

SOL/COM2 Console Redirection

SOL/COM2 Console Redirection

Select Enabled to use the SOL/COM2 port for Console Redirection. The options

are Enabled and Disabled.

*If the item above set to Enabled, the following items will become available for

user's conguration:

SOL/COM2 Console Redirection Settings

Use this feature to specify how the host computer will exchange data with the client

computer, which is the remote computer used by the user.

Terminal Type

Use this feature to select the target terminal emulation type for Console Redirec-

tion. Select VT100 to use the ASCII Character set. Select VT100+ to add color

and function key support. Select ANSI to use the Extended ASCII Character Set.

Select VT-UTF8 to use UTF8 encoding to map Unicode characters into one or

more bytes. The options are ANSI, VT100, VT100+, and VT-UTF8.

Bits Per second

Use this feature to set the transmission speed for a serial port used in Console

Redirection. Make sure that the same speed is used in the host computer and the

client computer. A lower transmission speed may be required for long and busy

lines. The options are 9600, 19200, 38400, 57600, and 115200 (bits per second).

Data Bits

Use this feature to set the data transmission size for Console Redirection. The

options are 7 (Bits) and 8 (Bits).

Parity

A parity bit can be sent along with regular data bits to detect data transmission

errors. Select Even if the parity bit is set to 0, and the number of 1's in data bits

is even. Select Odd if the parity bit is set to 0, and the number of 1's in data bits

is odd. Select None if you do not want to send a parity bit with your data bits

in transmission. Select Mark to add a mark as a parity bit to be sent along with

the data bits. Select Space to add a Space as a parity bit to be sent with your

data bits. The options are None, Even, Odd, Mark, and Space.

Stop Bits

A stop bit indicates the end of a serial data packet. Select 1 Stop Bit for standard

serial data communication. Select 2 Stop Bits if slower devices are used. The

options are 1 and 2.

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X10DRG-H/X10DRG-HT Motherboard User’s Manual

Flow Control

Use this feature to set the ow control for Console Redirection to prevent data

loss caused by buffer overow. Send a "Stop" signal to stop sending data when

the receiving buffer is full. Send a "Start" signal to start data-sending when the

receiving buffer is empty. The options are None and Hardware RTS/CTS.

VT-UTF8 Combo Key Support

Select Enabled to enable VT-UTF8 Combination Key support for ANSI/VT100

terminals. The options are Enabled and Disabled.

Recorder Mode

Select Enabled to capture the data displayed on a terminal and send it as text

messages to a remote server. The options are Disabled and Enabled.

Resolution 100x31

Select Enabled for extended-terminal resolution support. The options are Dis-

abled and Enabled.

Legacy OS Redirection Resolution

Use this feature to select the number of rows and columns used in Console

Redirection for legacy OS support. The options are 80x24 and 80x25.

Putty KeyPad

This feature selects Function Keys and KeyPad settings for Putty, which is a

terminal emulator designed for the Windows OS. The options are VT100, LINUX,

XTERMR6, SCO, ESCN, and VT400.

Redirection After BIOS Post

Use this feature to enable or disable legacy Console Redirection after BIOS

POST (Power-On Self-Test). When this feature is set to BootLoader, legacy

Console Redirection is disabled before booting the OS. When this feature is set

to Always Enable, legacy Console Redirection remains enabled upon OS boot.

The options are Always Enable and BootLoader.

Legacy Console Redirection Settings

Legacy Serial Redirection Port

Use this item to congure redirection for legacy serial ports. The options are

COM1 and SOL/COM2.

Chapter 4: AMI BIOS

4-27

Serial Port for Out-of-Band Management / Windows
Emergency Management Services (EMS)

The submenu allows the user to congure Console Redirection settings to support

Out-of-Band Serial Port management.

Console Redirection

Select Enabled to use a COM port selected by the user for EMS Console Redi-

rection. The options are Enabled and Disabled.

*If the item above set to Enabled, the following items will become available for

user's conguration:

EMS Console Redirection Settings (Available when EMS
Console Redirection is enabled)

Use this feature to specify how the host computer will exchange data with the client

computer, which is the remote computer used by the user.

Out-of-Band Management Port

The feature selects a serial port in a client server to be used by the Windows

Emergency Management Services (EMS) to communicate with a remote host

server. The options are COM1 (Console Redirection) and SOL (Console Re-

direction)/COM2.

Terminal Type

Use this feature to select the target terminal emulation type for Console Redirec-

tion. Select VT100 to use the ASCII character set. Select VT100+ to add color

and function key support. Select ANSI to use the extended ASCII character set.

Select VT-UTF8 to use UTF8 encoding to map Unicode characters into one or

more bytes. The options are ANSI, VT100, VT100+, and VT-UTF8.

Bits per second

This item sets the transmission speed for a serial port used in Console Redirec-

tion. Make sure that the same speed is used in both host computer and the client

computer. A lower transmission speed may be required for long and busy lines.

The options are 9600, 19200, 57600, and 115200 (bits per second).

Flow Control

Use this item to set the ow control for Console Redirection to prevent data

loss caused by buffer overow. Send a "Stop" signal to stop data-sending when

the receiving buffer is full. Send a "Start" signal to start data-sending when

the receiving buffer is empty. The options are None, Hardware RTS/CTS, and

Software Xon/Xoff.

4-28

X10DRG-H/X10DRG-HT Motherboard User’s Manual

The setting for each of the following features is displayed:

Data Bits, Parity, Stop Bits

Trusted Computing (Available when a TPM device is
installed and detected by the BIOS)

Conguration

Security Device Support

If this feature and the TPM jumper on the motherboard are both set to Enabled,

onboard security devices will be enabled for TPM (Trusted Platform Module) sup-

port to enhance data integrity and network security. Please reboot the system for

a change on this setting to take effect. The options are Enabled and Disabled.

TPM State

Select Enabled to use TPM (Trusted Platform Module) settings to enhance system

data security. Please reboot your system for any change on the TPM state to take

effect. The options are Disabled and Enabled.

Pending Operation

Use this item to schedule a TPM-related operation to be performed by a security

device for system data integrity. Your system will reboot to carry out a pending TPM

operation. The options are 0, Enable Take Ownership, Disable Take Ownership,

and TPM Clear.

Note: Your system will reboot to carry out a pending TPM operation.

Current Status Information

This item displays the status of the TPM support on this motherboard.



ACPI Settings

WHEA Support

Select Enabled to support the Windows Hardware Error Architecture (WHEA) plat-

form and provide a common infrastructure for the system to handle hardware errors

within the Windows OS environment to reduce system crashes and to enhance

system recovery and health monitoring. The options are Enabled and Disabled.

High Precision Timer

Select Enabled to activate the High Precision Event Timer (HPET) that produces

periodic interrupts at a much higher frequency than a Real-time Clock (RTC) does in

synchronizing multimedia streams, providing smooth playback and reducing the de-

Chapter 4: AMI BIOS

4-29

pendency on other timestamp calculation devices, such as an x86 RDTSC Instruc-

tion embedded in the CPU. The High Performance Event Timer is used to replace

the 8254 Programmable Interval Timer. The options are Enabled and Disabled.

NUMA (Available when the OS supports this feature)

Select Enabled to enable Non-Uniform Memory Access support to enhance system

performance. The options are Enabled and Disabled.

iSCSI Conguration

This item displays iSCSI conguration information:

iSCSI Initiator Name

This item displays the name of the iSCSI Initiator, which is a unique name used

in the world. The name must use the IQN format. The following actions can also

be performed:

Add an Attempt

Delete Attempts

Change Attempt Order

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X10DRG-H/X10DRG-HT Motherboard User’s Manual

4-4 Event Logs

Use this feature to congure Event Log settings.

Change SMBIOS Event Log Settings

This feature allows the user to congure SMBIOS Event settings.

Enabling/Disabling Options

SMBIOS Event Log

Select Enabled to enable SMBIOS (System Management BIOS) Event Logging

during system boot. The options are Enabled and Disabled.

Runtime Error Logging Support

Select Enable to support Runtime Error Logging. The options are Enable and Dis-

able. If this item is set to Enable, the following item will be available for conguration:

Chapter 4: AMI BIOS

4-31

Erasing Settings

Erase Event Log

Select Enabled to erase all error events in the SMBIOS (System Management BIOS)

log before an event logging is initialized at bootup. The options are No and Yes.

When Log is Full

Select Erase Immediately to immediately erase all errors in the SMBIOS event log

when the event log is full. Select Do Nothing for the system to do nothing when

the SMBIOS event log is full. The options are Do Nothing and Erase Immediately.

SMBIOS Event Log Standard Settings

Log System Boot Event

Select Enabled to log system boot events. The options are Disabled and Enabled.

MECI (Multiple Event Count Increment)

Enter the increment value for the multiple event counter. Enter a number between

1 to 255. The default setting is 1.

METW (Multiple Event Count Time Window)

This item is used to determine how long (in minutes) should the multiple event

counter wait before generating a new event log. Enter a number between 0 to 99.

The default setting is 60.

Note: Please reboot the system for the changes to take effect.

View SMBIOS Event Log

This item allows the user to view the event in the SMBIOS event log. Select this

item and press <Enter> to view the status of an event in the log. The following

categories are displayed:

Date/Time/Error Code/Severity

4-32

X10DRG-H/X10DRG-HT Motherboard User’s Manual

4-5 IPMI

Use this feature to congure Intelligent Platform Management Interface (IPMI)

settings.

IPMI Firmware Revision

This item indicates the IPMI rmware revision used in your system.

Status of BMC

This item indicates the status of the onboard BMC (Baseboard Management Con-

troller).

System Event Log

Enabling/Disabling Options

SEL Components

Select Enabled to enable all system event logging support at bootup. The options

are Enabled and Disabled.

Erasing Settings

Erase SEL

Select Yes, On next reset to erase all system event logs upon next system reboot.

Select Yes, On every reset to erase all system event logs upon each system reboot.

Select No to keep all system event logs after each system reboot. The options are

No, Yes, On next reset, and Yes, On every reset.

Chapter 4: AMI BIOS

4-33

When SEL is Full

This feature allows the user to determine what the AMI BIOS should do when the

system event log is full. Select Erase Immediately to erase all events in the log when

the system event log is full. The options are Do Nothing and Erase Immediately.

Note: After making changes on a setting, be sure to reboot the system for

the changes to take effect.

BMC Network Conguration

The following items will be displayed:

Update IPMI LAN Conguration

Select Yes for the system BIOS to automatically reset the following IPMI settings

at next system boot. The options are Yes and No.

Conguration Address Source (Available when the item above - Update
IPMI LAN Conguration is set to Yes)

Use this item to select the IP address source for this computer. If Static is selected,

you will need to know the IP address of this computer and enter it to the system

manually in the eld. If DHCP is selected, AMI BIOS will search for a DHCP (Dy-

namic Host Conguration Protocol) server attached to the network and request the

next available IP address for this computer. The options are DHCP, and Static.

Station IP Address

This item displays the Station IP address for this computer. This should be in decimal

and in dotted quad form (i.e., 192.168.10.253).

Subnet Mask

This item displays the sub-network that this computer belongs to. The value of each

three-digit number is separated by dots and it should not exceed 255.

Station MAC Address

This item displays the Station MAC address for this computer. Mac addresses are

6 two-digit hexadecimal numbers.

Gateway IP Address

This item displays the Gateway IP address for this computer. This should be in

decimal and in dotted quad form (i.e., 192.168.10.253).

4-34

X10DRG-H/X10DRG-HT Motherboard User’s Manual

4-6 Security Settings

This menu allows the user to congure the following security settings for the

system.

Administrator Password

Use this feature to set the administrator password which is required before the

user entering the BIOS setup utility. The length of the password should be from

3 characters to 20 characters long.

User Password

Use this feature to set the user password which is required to enter the BIOS

setup utility. The length of the password should be from 3 characters to 20 char-

acters long.