The information in this User’s Manual has been carefully reviewed and is believed to be accurate.
The vendor assumes no responsibility for any inaccuracies that may be contained in this document,
makes no commitment to update or to keep current the information in this manual, or to notify any
person or organization of the updates. Please Note: For the most up-to-date version of this
manual, please see our web site at www.supermicro.com.
Super Micro Computer, Inc. reserves the right to make changes to the product described in this
manual at any time and without notice. This product, including software, if any, and documentation may not, in whole or in part, be copied, photocopied, reproduced, translated or reduced to any
medium or machine without prior written consent.
IN NO EVENT WILL SUPERMICRO BE LIABLE FOR DIRECT, INDIRECT, SPECIAL, INCIDENTAL,
SPECULATIVE OR CONSEQUENTIAL DAMAGES ARISING FROM THE USE OR INABILITY TO
USE THIS PRODUCT OR DOCUMENTATION, EVEN IF ADVISED OF THE POSSIBILITY OF
SUCH DAMAGES. IN PARTICULAR, SUPERMICRO SHALL NOT HAVE LIABILITY FOR ANY
HARDWARE, SOFTWARE, OR DATA STORED OR USED WITH THE PRODUCT, INCLUDING THE
COSTS OF REPAIRING, REPLACING, INTEGRATING, INSTALLING OR RECOVERING SUCH
HARDWARE, SOFTWARE, OR DATA.
Any disputes arising between manufacturer and customer shall be governed by the laws of Santa
Clara County in the State of California, USA. The State of California, County of Santa Clara shall
be the exclusive venue for the resolution of any such disputes. Supermicro's total liability for
all claims will not exceed the price paid for the hardware product.
FCC Statement: This equipment has been tested and found to comply with the limits for a Class
A digital device pursuant to Part 15 of the FCC Rules. These limits are designed to provide
reasonable protection against harmful interference when the equipment is operated in a commercial
environment. This equipment generates, uses, and can radiate radio frequency energy and, if not
installed and used in accordance with the manufacturer’s instruction manual, may cause harmful
interference with radio communications. Operation of this equipment in a residential area is likely
to cause harmful interference, in which case you will be required to correct the interference at your
own expense.
California Best Management Practices Regulations for Perchlorate Materials: This Perchlorate
warning applies only to products containing CR (Manganese Dioxide) Lithium coin cells. “Perchlorate
Material-special handling may apply. See www.dtsc.ca.gov/hazardouswaste/perchlorate”
WARNING: Handling of lead solder materials used in this
product may expose you to lead, a chemical known to
the State of California to cause birth defects and other
reproductive harm.
Manual Revision 1.1
Release Date: May 2, 2008
Unless you request and receive written permission from Super Micro Computer, Inc., you may not
copy any part of this document.
Information in this document is subject to change without notice. Other products and companies
referred to herein are trademarks or registered trademarks of their respective companies or mark
holders.
4-2 Main Menu ...................................................................................................... 4-2
4-3 Advanced Settings Menu ............................................................................... 4-2
4-4 Boot Menu .................................................................................................... 4-17
4-5 Security Menu ............................................................................................... 4-17
4-6 Exit Menu ...................................................................................................... 4-18
Appendices:
Appendix A: BIOS Error Beep Codes
Appendix B: BIOS POST Checkpoint Codes
vi
Page 7
Chapter 1: Introduction
Chapter 1
Introduction
1-1 Overview
Checklist
Congratulations on purchasing your computer serverboard from an acknowledged
leader in the industry. Our boards are designed with the utmost attention to detail
to provide you with the highest standards in quality and performance.
Please check that the following items have all been included with your serverboard.
If anything listed here is damaged or missing, contact your retailer.
Included with retail box only
One (1) H8DM3-2/H8DMi-2 serverboard
One (1) IDE cable (CBL-036L-02)
One (1) fl oppy cable (CBL-022L)
One (1) COM port cable (CBL-010)
Two (2) SAS cables, H8DM3-2 only (CBL-0097L-02)
Four (4) SATA cables, H8DM3-2 only (CBL-044L)
Six (6) SATA cables, H8DMi-2 only (CBL-044L)
Two (2) heatsink retention modules with four (4) screws (BKT-0012L)
One (1) I/O shield for chassis (CSE-PT7L)
One (1) CD containing drivers and utilities
1-1
Page 8
H8DM3-2/H8DMi-2 User’s Manual
Contacting Supermicro
Headquarters
Address: Super Micro Computer, Inc. 980 Rock Ave. San Jose, CA 95131 U.S.A.
Tel: +1 (408) 503-8000
Fax: +1 (408) 503-8008
Email: marketing@supermicro.com (General Information) support@supermicro.com (Technical Support)
Web Site: www.supermicro.com
Europe
Address: Super Micro Computer B.V. Het Sterrenbeeld 28, 5215 ML 's-Hertogenbosch, The Netherlands
Tel: +31 (0) 73-6400390
Fax: +31 (0) 73-6416525
Email: sales@supermicro.nl (General Information) support@supermicro.nl (Technical Support) rma@supermicro.nl (Customer Support)
Asia-Pacifi c
Address: Super Micro, Taiwan
4F, No. 232-1, Liancheng Rd. Chung-Ho 235, Taipei County
Taiwan, R.O.C.
Tel: +886-(2) 8226-3990
Fax: +886-(2) 8226-3991
Web Site: www.supermicro.com.tw
Technical Support:
Email: support@supermicro.com.tw
Tel: 886-2-8228-1366, ext.132 or 139
1-2
Page 9
Figure 1-1. H8DM3-2/H8DMi-2 Image
Chapter 1: Introduction
Notes:
H8DM3-2 is pictured. The H8DMi-2 has the same layout as the H8DM3-2 but with
no SAS components or ports.
1-3
Page 10
H8DM3-2/H8DMi-2 User’s Manual
Figure 1-2. H8DM3-2/H8DMi-2 Serverboard Layout
Kb/
Mouse
USB0/1
COM1
COM1
FAN5
FAN6
FAN8/
JPW2
CPU FAN2
CPU2
(not drawn to scale)
J1B1
CPU1 DIMM 1B
CPU1 DIMM 1A
CPU1 DIMM 2B
CPU1 DIMM 2A
JPW1
J3P
JPI2C
JOH1
FAN2
JPWF
FAN1
JF1
VGA
LAN1
LAN2
2
JI
C3
2
JI
C4
Slot 6: PCI-E x8
Slot 5: PCI-E x8
Slot 4: PCI-E x4
ATI
ES1000
Battery
SUPER H8DM3-2
JPG1
JPXA1
JPXB1
JWOL
CPU2 DIMM 2A
CPU2 DIMM 2B
CPU2 DIMM 1A
CPU2 DIMM 1B
SIMLP
SEPC
nFAN1
Slot 3: PCI-X 133 MHz
Slot 2: PCI-X 133/100 MHz
2
JI
C2
2
C1
JI
Slot 1: PCI-X 133/100 MHz
USB4/5 USB2/3
nVidia
MCP55 Pro
SATA1 SATA3
SATA0
FAN7 /
CPU FAN1
JBT1
JWOR
AMD
8132
SATA2 SATA4 SATA5
I-Button
COM2
JL1
CPU1
JAR
JWD
BIOS
Speaker
LSI SAS
1068E
SGPIO1
SGPIO2
FAN4
SAS4~7
SAS0~3
FAN3
JCF1
JWF1
JF2
DP2
Floppy
JPS1
IDE#1
Notes:
1. Jumpers not indicated are for test purposes only.
2. The H8DMi-2 has the same layout as the H8DM3-2 but with no SAS components
or ports or I-button.
3. The I-Button (optional) is used to enable RAID 5.
1-4
Page 11
Chapter 1: Introduction
H8DM3-2/H8DMi-2 Quick Reference
Jumpers Description Default Setting
J3P Power Supply Fail Detect Closed (Enabled)
JBT1 CMOS Clear See Section 2-7
JCF1 Compact Flash Master/Slave Closed (Master)
2
C1/2 I2C to PCI-X Enable/Disable Pins 2-3 (Disabled)
JI
2
JI
C3/4 I2C to PCI-E Enable/Disable Pins 2-3 (Disabled)
JPG1 VGA Enable/Disable Pins 1-2 (Enabled)
JPS1* SAS RAID Select Closed (SR RAID)
JPXA1/JPXB1 PCI-X Slot 1&2 Freq. Open (Auto)
JWD Watch Dog Pins 1-2 (Reset)
ConnectorsDescription
COM1, COM2 COM1/COM2 Serial Port/Header
FAN 1-8 System Fan Headers
Floppy Floppy Disk Drive Connector
I-Button* RAID 5 Enable Button (optional)
IDE#1 IDE Drive Connector
J1B1 24-Pin ATX Power Connector
JAR Power Fail Alarm Reset Header
JF1 Front Panel Connector
JF2 Onboard Speaker/Keylock/Power LED
JL1 Chassis Intrusion Header
JOH1 Overheat Warning Header
2
JPI
C Power Supply I2C Header
JPW1 8-Pin Processor Power Connector
JPW2 4-pin Auxiliary Power Connector
JPWF Power Supply Fail Alarm Header
JWF1 Compact Flash Card Power Connector
JWOL Wake-On-LAN Header
JWOR Wake-On-Ring Header
LAN1/2 Gigabit Ethernet (RJ45) Ports
nFAN1 Chipset Heatsink Fan Header
SAS0~3, SAS4~7* SAS Ports
SATA0 ~ SATA5 Serial ATA Ports
SGPIO1/SGPIO2 SGPIO Headers
SIMLP IPMI 2.0 Card Slot
USB0/1 Universal Serial Bus (USB) Ports 0/1
USB2/3, USB4/5 USB Headers
IndicatorsDescription
DP2 Onboard Power LED
*H8DM3-2 only
1-5
Page 12
H8DM3-2/H8DMi-2 User’s Manual
Serverboard Features
CPU
• Single or dual AMD Opteron 2000 Series Socket F type processors
Memory
• Eight dual/single channel DIMM slots supporting up to 32 GB of DDR2-
667/533/400 registered ECC SDRAM
Note: Memory capacities are halved for single CPU systems. Refer to Section 2-4 before installing.
Chipset
• nVidia MCP55 Pro
• AMD-8132
Expansion Slots
• Two (2) PCI-Express x8 slots
• One (1) PCI-Express x4 slot
• One (1) PCI-X 133 MHz slot
• Two (2) PCI-X 133/100 MHz slots*
• One (1) low-profi le SIMLP slot (for IPMI card)
*These slots share a bus and so can only support up to 100 MHz when cards
are installed in both slots.
BIOS
• 8 Mb AMIBIOS
• APM 1.2, DMI 2.3, PCI 2.2, ACPI 2.0, SMBIOS 2.3, Plug and Play (PnP)
®
LPC Flash ROM
PC Health Monitoring
• Onboard voltage monitors for two CPU cores, 3.3V, +5Vin, +12Vin, 5V stby and
battery voltage
• Fan status monitor with fi rmware/software on/off and speed control
• Watch Dog
• Environmental temperature monitoring via BIOS
• Power-up mode control for recovery from AC power loss
• System resource alert (via included utility program)
• Pulse Width Modulated (PWM) fan connectors (FAN7 and FAN8 only)
• Auto-switching voltage regulator for the CPU core
1-6
Page 13
Chapter 1: Introduction
ACPI Features
• Microsoft OnNow
• Slow blinking LED for suspend state indicator
• BIOS support for USB keyboard
• Main switch override mechanism
• Internal/external modem ring-on
Onboard I/O
• On-chip SATA controller supporting six (6) SATA ports (RAID 0, 1, 0+1, 5 and
JBOD)
• LSI 1068E SAS controller (H8DM3-2 only, RAID 0, 1, 10 and JBOD; optional
RAID 5 support with I-Button installed)
• One (1) UltraDMA (ATA) 133/100 IDE port
• One (1) fl oppy port interface (up to 2.88 MB)
• Two (2) Fast UART 16550 compatible serial ports
• On-chip (nVidia MCP55) Ethernet controller supports two Gigabit LAN ports
• PS/2 mouse and PS/2 keyboard ports
• Six (6) USB (Universal Serial Bus) 2.0 ports/headers
Other
• Wake-on-Ring (JWOR)
• Wake-on-LAN (JWOL)
• Onboard +5V power LED
• Chassis intrusion detection
CD Utilities
• BIOS fl ash upgrade utility
Dimensions
• Extended ATX form factor, 12" x 13.05" (305 x 332 mm)
1-7
Page 14
H8DM3-2/H8DMi-2 User’s Manual
DIMM 2A
DIMM 2B
DIMM 1A
DIMM 1B
Slot 1: PCI-X 133/100 MH z
Slot 2: PCI-X 133/100 MH z
Slot 3: PCI-X 133 MHz
128-bit data + 16-bi t ECC
AMD Socket F
AMD
8132
CPU2
16 x 16 HT link (1 GHz)
16 x 16 HT lin k ( 800 M Hz)
ATI ES1000
SIMLP
H/W Mon itor
Fan Conn.
Floppy
PCI-32
128-bit data + 16-bit ECCDDR2- 667/533/400
AMD Socket F
CPU1
16 x 16 HT lin k ( 1 GHz )
nVidia
MCP55Pro
LPC
S I/OBIOS
Kybd/
Mouse
Serial Ports
(2)
DDR2-667/533/400
DIMM 2A
DIMM 2B
DIMM 1A
DIMM 1B
SATA Por ts (6)
ATA133 Port (1)
USB Ports (6)
GLAN Por ts (2)
Slot 4: PCI-E x4
Slot 5: PCI-E x8
Slot 6: PCI-E x8SEPC
Figure 1-3. nVidia MCP55 Pro/AMD-8132 Chipset:
System Block Diagram
Note: This is a general block diagram and may not exactly represent
the features on your serverboard. See the previous pages for the
actual specifi cations of your serverboard.
1-8
Page 15
Chapter 1: Introduction
1-2 Chipset Overview
The H8DM3-2/H8DMi-2 serverboard is based on the nVidia MCP55 Pro/AMD-8132
chipset. The nVidia MCP55 Pro functions as Media and Communications Proces-
sor (MCP). Controllers for the system memory are integrated directly into the AMD
Opteron processors.
MCP55 Pro Media and Communications Processor
The MCP55 Pro is a single-chip, high-performance HyperTransport peripheral con-
troller. It includes a 28-lane PCI Express interface, an AMD Opteron 16-bit Hyper
Transport interface link, a six-port Serial ATA interface, a dual-port Gb Ethernet
interface, a dual ATA133 bus master interface and a USB 2.0 interface. This hub
connects directly to CPU#1 and through that to CPU#2.
8132 HyperTransport PCI-X Tunnel
This hub includes AMD-specifi c technology that provides two PCI-X bridges with
each bridge supporting a 64-bit data bus as well as separate PCI-X operational
modes and independent transfer rates. Each bridge supports up to fi ve PCI mas-
ters that include clock, request and grant signals. The 8132 tunnel connects to the
processors and through them to system memory. It also interfaces directly with the
Serial ATA and Ethernet controllers.
HyperTransport Technology
HyperTransport technology is a high-speed, low latency point to point link that was
designed to increase the communication speed by a factor of up to 48x between
integrated circuits. This is done partly by reducing the number of buses in the
chipset to reduce bottlenecks and by enabling a more effi cient use of memory in
multi-processor systems. The end result is a signifi cant increase in bandwidth
within the chipset.
1-9
Page 16
H8DM3-2/H8DMi-2 User’s Manual
1-3 PC Health Monitoring
This section describes the PC health monitoring features of the H8DM3-2/H8DMi-
2. The serverboard has an onboard System Hardware Monitor chip that supports
PC health monitoring.
Onboard Voltage Monitors for two CPU cores, 3.3V, +5Vin, +12Vin,
+5V standby and battery
The onboard voltage monitor will scan these voltages continuously. Once a voltage
becomes unstable, it will give a warning or send an error message to the screen.
Users can adjust the voltage thresholds to defi ne the sensitivity of the voltage moni-
tor. Real time readings of these voltage levels are all displayed in BIOS.
Fan Status Monitor with Firmware/Software Speed Control
The PC health monitor can check the RPM status of the cooling fans. The onboard
fans are controlled by thermal management via BIOS.
CPU Overheat/Fan Fail LED and Control
This feature is available when the user enables the CPU overheat/Fan Fail warning
function in the BIOS. This allows the user to defi ne an overheat temperature. When
this temperature is exceeded or when a fan failure occurs, then, the Overheat/Fan
Fail warning LED is triggered.
Auto-Switching Voltage Regulator for the CPU Core
The 3-phase-switching voltage regulator for the CPU core can support up to 80A and
auto-sense voltage IDs ranging from 0.8 V to 1.55V. This will allow the regulator
to run cooler and thus make the system more stable.
1-10
Page 17
Chapter 1: Introduction
1-4 Power Confi guration Settings
This section describes the features of your serverboard that deal with power and
power settings.
Microsoft OnNow
The OnNow design initiative is a comprehensive, system-wide approach to system
and device power control. OnNow is a term for a PC that is always on but appears
to be off and responds immediately to user or other requests.
Slow Blinking LED for Suspend-State Indicator
When the CPU goes into a suspend state, the chassis power LED will start blinking
to indicate that the CPU is in suspend mode. When the user presses any key, the
CPU will wake-up and the LED will automatically stop blinking and remain on.
BIOS Support for USB Keyboard
If a USB keyboard is the only keyboard in the system, it will function like a normal
keyboard during system boot-up.
Main Switch Override Mechanism
When an ATX power supply is used, the power button can function as a system
suspend button. When the user depresses the power button, the system will enter
a SoftOff state. The monitor will be suspended and the hard drive will spin down.
Depressing the power button again will cause the whole system to wake-up. Dur-
ing the SoftOff state, the ATX power supply provides power to keep the required
circuitry in the system alive. In case the system malfunctions and you want to turn
off the power, just depress and hold the power button for 4 seconds. The power
will turn off and no power will be provided to the serverboard.
Wake-On-LAN (JWOL)
Wake-On-LAN is defi ned as the ability of a management application to remotely
power up a computer that is powered off. Remote PC setup, up-dates and access
tracking can occur after hours and on weekends so that daily LAN traffi c is kept
to a minimum and users are not interrupted. The serverboard has a 3-pin header
(JWOL) to connect to the 3-pin header on a Network Interface Card (NIC) that has
WOL capability. Wake-On-LAN must be enabled in BIOS. Note that Wake-On-LAN
can only be used with an ATX 2.01 (or above) compliant power supply.
1-11
Page 18
H8DM3-2/H8DMi-2 User’s Manual
Wake-On-Ring Header (JWOR)
Wake-up events can be triggered by a device such as the external modem ringing
when the system is in the SoftOff state. Note that external modem ring-on can only
be used with an ATX 2.01 (or above) compliant power supply.
1-5 Power Supply
As with all computer products, a stable power source is necessary for proper and
reliable operation. It is even more important for processors that have high CPU
clock rates.
The H8DM3-2/H8DMi-2 accommodates 12V ATX power supplies. Although most
power supplies generally meet the specifi cations required by the CPU, some
are inadequate. A 2 amp current supply on a 5V Standby rail is strongly recom-
mended.
It is strongly recommended that you use a high quality power supply that meets
12V ATX power supply Specifi cation 1.1 or above. Additionally, in areas where
noisy power transmission is present, you may choose to install a line fi lter to shield
the computer from noise. It is recommended that you also install a power surge
protector to help avoid problems caused by power surges.
Warning: To prevent the possibility of explosion, do not use the wrong type of
onboard CMOS battery or install it upside down.
1-12
Page 19
Chapter 1: Introduction
1-6 Super I/O
The disk drive adapter functions of the Super I/O chip include a fl oppy disk drive
controller that is compatible with industry standard 82077/765, a data separator,
write pre-compensation circuitry, decode logic, data rate selection, a clock genera-
tor, drive interface control logic and interrupt and DMA logic. The wide range of
functions integrated onto the Super I/O greatly reduces the number of components
required for interfacing with fl oppy disk drives. The Super I/O supports two 360
K, 720 K, 1.2 M, 1.44 M or 2.88 M disk drives and data transfer rates of 250 Kb/s,
500 Kb/s or 1 Mb/s.
It also provides two high-speed, 16550 compatible serial communication ports
(UARTs), one of which supports serial infrared communication. Each UART in-
cludes a 16-byte send/receive FIFO, a programmable baud rate generator, complete
modem control capability and a processor interrupt system. Both UARTs provide
legacy speed with baud rate of up to 115.2 Kbps as well as an advanced speed
with baud rates of 250 K, 500 K, or 1 Mb/s, which support higher speed modems.
The Super I/O supports one PC-compatible printer port (SPP), Bi-directional Printer
Port (BPP) , Enhanced Parallel Port (EPP) or Extended Capabilities Port (ECP).
The Super I/O provides functions that comply with ACPI (Advanced Confi guration
and Power Interface), which includes support of legacy and ACPI power manage-
ment through a SMI or SCI function pin. It also features auto power management
to reduce power consumption.
The IRQs, DMAs and I/O space resources of the Super I/O can be fl exibly adjusted
to meet ISA PnP requirements, which support ACPI and APM (Advanced Power
Management).
1-13
Page 20
H8DM3-2/H8DMi-2 User’s Manual
Notes
1-14
Page 21
Chapter 2: Installation
Chapter 2
Installation
2-1 Static-Sensitive Devices
Electrostatic Discharge (ESD) can damage electronic com ponents. To prevent dam-
age to your system board, it is important to handle it very carefully. The following
measures are generally suffi cient to protect your equipment from ESD.
Precautions
• Use a grounded wrist strap designed to prevent static discharge.
• Touch a grounded metal object before removing the board from the antistatic
bag.
• Handle the board by its edges only; do not touch its components, peripheral
chips, memory modules or gold contacts.
• When handling chips or modules, avoid touching their pins.
• Put the serverboard and peripherals back into their antistatic bags when not in
use.
• For grounding purposes, make sure your computer chassis provides excellent
conductivity between the power supply, the case, the mounting fasteners and
the serverboard.
• Use only the correct type of CMOS onboard battery as specifi ed by the manufac-
turer. Do not install the CMOS onboard battery upside down, which may result
in a possible explosion.
Unpacking
The serverboard is shipped in antistatic packaging to avoid static damage. When
unpacking the board, make sure the person handling it is static protected.
Installation Procedures
Follow the procedures as listed below to install the serverboard into a chassis:
1. Install the processor(s) and the heatsink(s).
2. Install the serverboard in the chassis.
3. Install the memory and add-on cards.
4. Finally, connect the cables and install the drivers.
2-1
Page 22
H8DM3-2/H8DMi-2 User's Manual
2-2 Processor and Heatsink Installation
Exercise extreme caution when handling and installing the proces-
!
Installing the CPU Backplates
Two CPU backplates (BKT-0011L) have been preinstalled to the serverboard to
prevent the CPU area of the serverboard from bending and to provide a base for
attaching the heatsink retention modules.
sor. Always connect the power cord last and always remove it be-
fore adding, removing or changing any hardware components.
Installing the Processor (install to the CPU#1 socket fi rst)
1. Begin by removing the cover plate
that protects the CPU. Lift the lever
on CPU socket #1 until it points straight
up. With the lever raised, lift open the
silver CPU retention plate.
Triangles
2. Use your thumb and your index
fi nger to hold the CPU. Locate and
align pin 1 of the CPU socket with pin
1 of the CPU. Both are marked with
a triangle.
2-2
Page 23
3. Align pin 1 of the CPU with pin 1
of the socket. Once aligned, carefully
place the CPU into the socket. Do not
drop the CPU on the socket, move the
CPU horizontally or vertically or rub the
CPU against the socket or against any
pins of the socket, which may damage
the CPU and/or the socket.
Chapter 2: Installation
4. With the CPU inserted into the
socket, inspect the four corners of the
CPU to make sure that it is properly in-
stalled and fl ush with the socket. Then,
gently lower the silver CPU retention
plate into place.
5. Carefully press the CPU socket
lever down until it locks into its reten-
tion tab. For a dual-processor system,
repeat these steps to install another
CPU into the CPU#2 socket.
Note: if using a single processor, only
the CPU1 DIMM slots are addressable
for a maximum of 16 GB memory.
2-3
Page 24
H8DM3-2/H8DMi-2 User's Manual
Installing the Heatsink Retention Modules
Two heatsink retention modules (BKT-0012L) and four screws are included in the
retail box. Once installed, these are used to help attach the heatsinks to the CPUs.
To install, align the module with the standoffs of the preinstalled CPU backplate and
with the four feet on the module contacting the serverboard. Secure the retention
module to the backplate with two of the screws provided. See Figure 2-1. Repeat
for the second CPU socket.
Note: BKT-0012L is included for use with non-proprietary heatsinks only. When
installing Supermicro heatsinks, only BKT-0011L (the CPU backplate) is needed.
The BKT-0012L retention module was designed to provide compatibility with clip-
and-cam type heatsinks from third parties.
Figure 2-1. CPU Heatsink Retention Module Installation
Installing the Heatsink
The use of active type heatsinks are recommended (except for 1U systems). Con-
nect the heatsink fans to the appropriate fan headers on the serverboard. To install
the heatsinks, please follow the installation instructions included with your heatsink
package (not included).
2-4
Page 25
Chapter 2: Installation
2-3 Mounting the Serverboard into a Chassis
All serverboards and motherboards have standard mounting holes to fi t different
types of chassis. Make sure that the locations of all the mounting holes for both
the serverboard and the chassis match. Although a chassis may have both plastic
and metal mounting fasteners, metal ones are highly recommended because they
ground the serverboard to the chassis. Make sure that the metal standoffs click in
or are screwed in tightly.
1. Check the compatibility of the serverboard ports and the I/O shield
The H8DM3-2/H8DMi-2 serverboard requires a chassis that can support extended
ATX boards of 12" x 13.05" in size. Make sure that the I/O ports on the serverboard
align with their respective holes in the I/O shield at the rear of the chassis.
2. Mounting the serverboard onto the mainboard tray in the chassis
Carefully mount the serverboard onto the mainboard tray by aligning the serverboard
mounting holes with the raised metal standoffs in the tray. Insert screws into all
the mounting holes in the serverboard that line up with the standoffs. Then use a
screwdriver to secure the serverboard to the mainboard tray - tighten until just snug
(if too tight you might strip the threads). Metal screws provide an electrical contact
to the serverboard ground to provide a continuous ground for the system.
2-4 Installing Memory
CAUTION
Exercise extreme care when installing or removing memory modules
to prevent any possible damage.
1. Insert each memory module vertically into its slot, paying attention to the notch
along the bottom of the module to prevent inserting the module incorrectly (see
Figure 2-2). See support information below.
2. Gently press down on the memory module until it snaps into place.
Note: each processor has its own built-in memory controller, so the CPU2 DIMMs
cannot be addressed if only a single CPU is installed. 128 MB, 256 MB, 512 MB,
1 GB, 2 GB and 4 GB memory modules are supported. It is highly recommended
that you remove the power cord from the system before installing or changing any
memory modules.
2-5
Page 26
H8DM3-2/H8DMi-2 User's Manual
Support
The H8DM3-2/H8DMi-2 supports single or dual-channel, DDR2-667/533/400 reg-
istered ECC SDRAM.
Both interleaved and non-interleaved memory are supported, so you may populate
any number of DIMM slots (see note on previous page and charts on following
page). The CPU2 DIMM slots can only be accessed when two CPUs are installed
(however, the CPU2 DIMM slots are not required to be populated when two CPUs
are installed).
Populating two adjacent slots at a time with memory modules of the same size and
type will result in interleaved (128-bit) memory, which is faster than non-interleaved
(64-bit) memory. See charts on following page.
Optimizing memory performance
If two processors are installed, it is better to stagger pairs of DIMMs across both
sets of CPU DIMM slots, e.g. fi rst populate CPU1 slots 1A and 1B, then CPU2 slots
1A, and 1B, then the next two CPU1 slots, etc. This balances the load over both
CPUs to optimize performance.
Maximum memory: 32 GB of registered ECC DDR2-667/533/400. If only one CPU
is installed, maximum supported memory is halved (16 GB).
Figure 2-2. Side and Top Views of DDR Installation
To Install:
Insert module vertically
and press down until it
snaps into place. The
release tabs should
close - if they do not
you should close them
yourself.
Notch
Release
Tab
Note: Notch
should align
with its
receptive point
on the slot
Note the notch in the slot and on the bottom of the DIMM.
These prevent the DIMM from being installed incorrectly.
Notch
Release
Tab
To Remove:
Use your thumbs to
gently push each release tab outward to
release the DIMM from
the slot.
2-6
Page 27
Chapter 2: Installation
Populating Memory Banks for 128-bit Operation
CPU1
DIMM1A
XX
XXXX
XXXX
XXXXXX
XXXX
XXXXXX
XXXXXX
XXXXXXXX
CPU1
DIMM1B
CPU1
DIMM2A
XX
XXXX
XXXX
XXXXXX
CPU1
DIMM2B
CPU2
DIMM1A
CPU2
DIMM1B
CPU2
DIMM2A
CPU2
DIMM2B
Notes: X indicates a populated DIMM slot. If adding at least four DIMMs (with two CPUs
installed), the confi gurations with DIMMs spread over both CPUs (and not like the confi guration in row 5) will result in optimized performance. Note that the fi rst two DIMMs
must be installed in the CPU1 memory slots.
Populating Memory Banks for 64-bit Operation
CPU1
DIMM1A
X
XX
XX
XX
CPU1
DIMM1B
CPU1
DIMM2A
X
XX
XX
CPU1
DIMM2B
CPU2
DIMM1A
CPU2
DIMM1B
CPU2
DIMM2A
CPU2
DIMM2B
2-7
Page 28
H8DM3-2/H8DMi-2 User's Manual
2-5 I/O Port and Control Panel Connections
The I/O ports are color coded in conformance with the PC99 specifi cation to make
setting up your system easier. See Figure 2-3 below for the colors and locations
of the various I/O ports.
Figure 2-3. I/O Port Locations and Defi nitions
Front Control Panel
JF1 contains header pins for various front control panel connectors. See Figure 2-4
for the pin defi nitions of the various connectors. Refer to Section 2-6 for details.
Figure 2-4. JF1: Front Control Panel Header (JF1)
20 19
Ground
x (key)
Power LED
HDD LED
NIC1
NIC2
OH/Fan Fail LED
Power Fail LED
Ground
NMI
x (key)
Vcc
Vcc
Vcc
Vcc
Vcc
Vcc
Reset
Ground
Power
2 1
2-8
Page 29
Chapter 2: Installation
2-6 Connecting Cables
ATX Power Connector
The primary ATX power supply con-
nector (J1B1) meets the SSI (Super-
set ATX) 24-pin specifi cation. Refer to
the table on the right for the pin defi ni-
tions of the ATX 24-pin power connec-
tor. This connection supplies power to
the chipset, fans and memory.
Note: You must also connect the 8-
pin (JPW1) and 4-pin (JPW2) power
connectors to your power supply (see
below).
Processor Power Connector
In addition to the primary ATX power
connector (above), the 12v, 8-pin
processor power connector at JPW1
must also be connected to your power
supply. This connection supplies
power to the CPUs. See the table on
the right for pin defi nitions.
ATX Power 24-pin Connector
Pin Defi nitions (J1B1)
Pin# Defi nition Pin # Defi nition
13+3.3V1+3.3V
14-12V2+3.3V
15COM3COM
16PS_ON4+5V
17COM5COM
18COM6+5V
19COM7COM
20Res (NC)8PWR_OK
21+5V95VSB
22+5V10+12V
23+5V11+12V
24COM12+3.3V
Processor Power
Connector
Pin Defi nitions (JPW1)
Pins Defi nition
1 through 4Ground
5 through 8+12V
Required Connection
Auxiliary Power Connector
The 4-pin auxiliary power connector
at JPW2 must also be connected to
your power supply. This connection
supplies extra power that may be
needed for high loads. See the table
on the right for pin defi nitions.
Power LED
The Power LED connection is located
on pins 15 and 16 of JF1. Refer to the
table on the right for pin defi nitions.
Auxiliary Power
Connector
Pin Defi nitions (JPW2)
Pins Defi nition
1 & 2Ground
3 & 4+12V
Required Connection
Power LED
Pin Defi nitions (JF1)
Pin# Defi nition
15Vcc
16Control
2-9
Page 30
H8DM3-2/H8DMi-2 User's Manual
HDD LED
The HDD (IDE Hard Disk Drive) LED
connection is located on pins 13 and
14 of JF1. Attach the IDE hard drive
LED cable to display disk activity.
Refer to the table on the right for pin
defi nitions.
NIC1 LED
The NIC1 (Network Interface Control-
ler) LED connection is located on pins
11 and 12 of JF1. Attach the NIC1
LED cable to display network activity.
Refer to the table on the right for pin
defi nitions.
NIC2 LED
The NIC2 (Network Interface Control-
ler) LED connection is located on pins
9 and 10 of JF1. Attach the NIC2
LED cable to display network activity.
Refer to the table on the right for pin
defi nitions.
HDD LED
Pin Defi nitions (JF1)
Pin# Defi nition
13Vcc
14HD Active
NIC1 LED
Pin Defi nitions (JF1)
Pin# Defi nition
11Vcc
12NIC1 Active
NIC2 LED
Pin Defi nitions (JF1)
Pin# Defi nition
9Vcc
10NIC2 Active
Overheat/Fan Fail LED
Connect an LED to the OH connection
on pins 7 and 8 of JF1 to provide ad-
vanced warning of chassis overheat-
ing. Refer to the table on the right for
pin defi nitions and status indicators.
Power Fail LED
The Power Fail LED connection is
located on pins 5 and 6 of JF1. Refer
to the table on the right for pin defi ni-
tions. This feature is only available
for systems with redundant power
supplies.
2-10
OH/Fan Fail LED
Pin Defi nitions (JF1)
Pin# Defi nition
7Vcc
8Control
Pin# Defi nition
5Vcc
6Control
OH/Fan Fail
LED Status
State Indication
SolidOverheat
BlinkingFan fail
Power Fail LED
Pin Defi nitions (JF1)
Page 31
Reset Button
The Reset Button connection is lo-
cated on pins 3 and 4 of JF1. Attach
it to the hardware reset switch on the
computer case. Refer to the table on
the right for pin defi nitions.
Power Button
The Power Button connection is
located on pins 1 and 2 of JF1. Mo-
mentarily contacting both pins will
power on/off the system. This button
can also be confi gured to function
as a suspend button (see the Power
Button Mode setting in BIOS). To turn
off the power when set to suspend
mode, depress the button for at least
4 seconds. Refer to the table on the
right for pin defi nitions.
Chapter 2: Installation
Reset Button
Pin Defi nitions (JF1)
Pin# Defi nition
3Reset
4Ground
Power Button
Pin Defi nitions (JF1)
Pin# Defi nition
1PW_ON
2Ground
Universal Serial Bus Ports
(USB0/1)
Two Universal Serial Bus ports
(USB2.0) are located beside the
LAN1/2 ports. See the table on the
right for pin defi nitions.
USB Headers
Four additional USB2.0 headers
(USB2/3 and USB4/5) are included on
the serverboard. These may be con-
nected to provide front side access.
A USB cable (not included) is needed
for the connection. See the table on
the right for pin defi nitions.
Universal Serial Bus Ports
Pin Defi nitions (USB0/1)
USB0
Pin # Defi nition
1+5V1+5V
2PO-2PO-
3PO+3PO+
4Ground4Ground
Universal Serial Bus Headers
Pin Defi nitions (USB2/3/4/5)
USB2
Pin # Defi nition
1+5V1+5V
2PO-2PO-
3PO+3PO+
4Ground4Ground
5Key5No connection
USB1
Pin # Defi nition
USB3/4
Pin # Defi nition
2-11
Page 32
H8DM3-2/H8DMi-2 User's Manual
ATX PS/2 Keyboard and
PS/2 Mouse Ports
The ATX PS/2 keyboard and the
PS/2 mouse ports are located on the
IO backplane. The mouse is the top
(green) port. See the table on the
right for pin defi nitions.
Serial Ports
The COM1 port is located under the
parallel port. COM2 is a header
located beside the SATA5 port. See
the serverboard layout for locations
and the table on the right for pin
defi nitions.
PS/2 Keyboard and
Mouse Port Pin
Defi nitions
Pin# Defi nition
1Data
2NC
3Ground
4VCC
5Clock
6NC
Serial Port Pin Defi nitions
(COM1/COM2)
Pin # Defi nitionPin # Defi nition
1DCD6DSR
2RXD7RTS
3TXD8CTS
4DTR9 RI
5Ground10NC
Note: NC indicates no connection.
Fan Headers
The H8DM3-2/H8DMi-2 has eight fan
headers, which are designated FAN1
through FAN8. FAN7 and FAN8
are for 4-pin Pulse Width Modulated
(PWM) fans and are to be connected
to the CPU heatsink fans. Their speed
is controlled via Thermal Management
with a BIOS setting. FAN1 through
FAN6 are 3-pin, non-PWM fans. See
the tables on the right for pin defi ni-
tions.
Note: The nFAN1 header connects to
the heatsink fan on the nVidia MCP 55
Pro chip. Do not disconnect this fan
or the chipset may overheat. See the
table on the right for pin defi nitions.
4-pin Fan Header
Pin Defi nitions
(FAN7/FAN8)
Pin# Defi nition
1Ground (Black)
2+12V (Red)
3Tachometer
4PWM Control
3-pin Fan Header
Pin Defi nitions
(FAN1-FAN6)
Pin# Defi nition
1Ground (Black)
2+12V (Red)
3Tachometer
2-12
Page 33
Chapter 2: Installation
Power LED/Speaker/Keylock
On JF2, pins 2, 4, and 6 are for the
power LED, pins 1, 3, 5 and 7 are for
the speaker and pins 8 and 10 are for
the keylock. See the tables on the
right for pin defi nitions.
Note: The speaker connector pins are
for use with an external speaker. If
you wish to use the onboard speaker,
you should close pins 5 and 7 with a
jumper. Utilizing the keylock header
allows you to inhibit any actions made
on the keyboard, effectively "locking"
it.
Overheat LED
Connect an LED to the JOH1 header
to provide warning of chassis over-
heating. See the table on the right for
pin defi nitions.
PWR LED Connector
Pin Defi nitions (JF2)
Pin# Defi nition
2+Vcc
4Control
6Control
Speaker Connector
Pin Defi nitions (JF2)
Pin# Defi nition
1Red wire, +5V
3No connection
5Buzzer signal
7Speaker data
Overheat LED
Pin Defi nitions (JOH1)
Pin# Defi nition
13.3V
2OH Active
Chassis Intrusion
A Chassis Intrusion header is located
at JL1. Attach the appropriate cable
to inform you of a chassis intrusion.
Wake-On-LAN
The Wake-On-LAN header is desig-
nated JWOL. See the table on the
right for pin defi nitions. You must
have a LAN card with a Wake-On-LAN
connector and cable to use the Wake-
On-LAN feature.
(Note: Wake-On-LAN from S3, S4, S5
are supported by LAN1. LAN2 sup-
ports Wake-On-LAN from S1 only.)
Chassis Intrusion
Pin Defi nitions (JL1)
Pin# Defi nition
1Battery voltage
2Intrusion signal
Wake-On-LAN
Pin Defi nitions
(JWOL)
Pin# Defi nition
1+5V Standby
2Ground
3Wake-up
2-13
Page 34
H8DM3-2/H8DMi-2 User's Manual
Wake-On-Ring
The Wake-On-Ring header is desig-
nated JWOR. This function allows
your computer to receive and "wake-
up" by an incoming call to the modem
when in suspend state. See the table
on the right for pin defi nitions. You
must have a Wake-On-Ring card and
cable to use this feature.
Power Supply I2C Header
The JPI2C header is for I2C, which
may be used to monitor the status of
the power supply, fans and system
temperature. See the table on the right
for pin defi nitions.
Wake-On-Ring
Pin Defi nitions
(JWOR)
Pin# Defi nition
1Ground (Black)
2Wake-up
I2C Header
Pin Defi nitions (JPI2C)
Pin# Defi nition
1Clock
2Data
3PWR Fail
4Gnd
5+3.3V
LAN1/2 (Ethernet Ports)
Two Gigabit Ethernet ports (desig-
nated LAN1 and LAN2) are located
beside the VGA port. These Ethernet
ports accept RJ45 type cables.
Power Supply Fail Alarm
Reset Header
Connect JAR to the alarm reset but-
ton on your chassis (if available) or to
a microswitch to allow you to turn off
the alarm that sounds when a power
supply module fails. See the table on
the right for pin defi nitions.
Alarm Reset Header
Pin Defi nitions (JAR)
Pin# Defi nition
1Ground
2Reset Signal
2-14
Page 35
Power Supply Fail Alarm
Header
Connect a cable from your power
supply to JPWF to provide you with
warning of a power supply failure.
The warning signal is passed through
the PWR_LED pin to indicate a power
failure. See the table on the right for
pin defi nitions.
Chapter 2: Installation
Power Supply Fail
Alarm Header
Pin Defi nitions (JPWF)
Pin# Defi nition
1P/S 1 Fail Signal
2P/S 2 Fail Signal
3P/S 3 Fail Signal
4Reset (from MB)
Note: This feature is only available when using
redundant power supplies.
Compact Flash Power
Header
A Compact Flash Card Power header
is located at JWF1. For the Compact
Flash Card to work properly, you will
fi rst need to connect the device's power
cable to JWF1 and correctly set the
Compact Flash Jumper (JCF1).
SGPIO
SGPIO1 and SGPIO2 (Serial General
Purpose Input/Output) provide a bus
between the SATA controller and
the SATA drive backplane to provide
SATA enclosure management func-
tions. Connect the appropriate cables
from the backplane to the SGPIO1
and SGPIO2 header(s) to utilize
SATA management functions on your
system.
Compact Flash
Power Header
Pin Defi nitions (JWF1)
Pin# Defi nition
1+5V
2Ground
3Signal
SGPIO Header
Pin Defi nitions (SGPIO1, SGPIO2)
Pin# Defi nition Pin # Defi nition
1NC2 NC
3Ground4Data
5Load6Ground
7NC8 NC
Note: NC indicates no connection.
2-15
Page 36
H8DM3-2/H8DMi-2 User's Manual
2-7 Jumper Settings
Explanation of
Jumpers
To modify the operation of the
serverboard, jumpers can be used to
choose between optional settings.
Jumpers create shorts between two
pins to change the function of the
connector. Pin 1 is identifi ed with
a square solder pad on the printed
circuit board. See the diagram at
right for an example of jumping pins
1 and 2. Refer to the serverboard
layout page for jumper locations.
Note: O n t w o - p i n j u m p e r s , " C l o s e d "
means the jumper is on and "Open"
means the jumper is off the pins.
CMOS Clear
Connector
321
Pins
Jumper
321
Setting
JBT1 is used to clear CMOS and will also clear any passwords. Instead of pins,
this jumper consists of contact pads to prevent accidentally clearing the contents
of CMOS.
To clear CMOS,
1) First power down the system and unplug the power cord(s).
2) With the power disconnected, short the CMOS pads with a metal object such as
a small screwdriver for at least four seconds.
3) Remove the screwdriver (or shorting device).
4) Reconnect the power cord(s) and power on the system.
Notes:
Do not use the PW_ON connector to clear CMOS.
The onboard battery does not need to be removed when clearing CMOS, however
you must short JBT1 for at least four seconds.
JBT1 contact pads
2-16
Page 37
I2C to PCI-X Enable/Disable
The JI2C1/2 pair of jumpers allows you
to connect the System Management
Bus to the PCI-X expansion slots. The
default setting is disabled. Both con-
2
nectors must be set the same (JI
for data and JI
2
C2 is for the clock). See
C1 is
the table on right for jumper settings.
I2C to PCI-E Enable/Disable
The JI2C3/4 pair of jumpers allows you
to connect the System Management
Bus to the PCI-Express expansion
slots. The default setting is disabled.
Both connectors must be set the same
2
(JI
C3 is for data and JI2C4 is for the
clock). See the table on right for jump-
er settings.
Chapter 2: Installation
I2C to PCI-X Enable/Disable
Jumper Settings
(JI2C1/2)
Jumper Setting Defi nition
Pins 1-2Enabled
Pins 2-3Disabled
I2C to PCI-E Enable/Disable
Jumper Settings
(JI2C3/4)
Jumper Setting Defi nition
Pins 1-2Enabled
Pins 2-3Disabled
Watch Dog
JWD controls Watch Dog, a system
monitor that takes action when a soft-
ware application freezes the system.
Jumping pins 1-2 will cause WD to
reset the system if an application is
hung up. Jumping pins 2-3 will gen-
erate a non-maskable interrupt signal
for the application that is hung up.
See the table on the right for jumper
settings. Watch Dog must also be
enabled in BIOS.
VGA Enable/Disable
JPG1 allows you to enable or disable
the VGA port. The default position
is on pins 1 and 2 to enable VGA.
See the table on the right for jumper
settings.
Watch Dog
Jumper Settings (JWD)
Jumper Setting Defi nition
Pins 1-2Reset
Pins 2-3NMI
OpenDisabled
VGA Enable/Disable
Jumper Settings (JPG1)
Jumper Setting Defi nition
Pins 1-2Enabled
Pins 2-3Disabled
2-17
Page 38
H8DM3-2/H8DMi-2 User's Manual
PCI-X Slot Speed
Jumper JPXA1 on the H8DM3-2/
H8DMi-2 is used to change the speed
of PCI-X slots #1 & 2. Jumper JPXB1
is used to change the speed of PCI-X
slot #3. See the tables on the right for
jumper settings.
Note: JPXA1 controls the speed for PCI-X slots #1
and #2. JPXB1 controls the speed for PCI-X slot #3.
The default setting for both is Open (Auto).
Compact Flash Master/Slave
The JCF1 jumper allows you to assign
either master or slave status a compact
fl ash card installed in IDE1. See the
table on the right for jumper settings.
PCI-X Slot Speed Jumper Settings
(JPX1A/JPX1B)
Jumper Setting Defi nition
OpenAuto
Pins 1-2PCI-X 66 MHz
Pins 2-3PCI 66 MHz
Compact Flash
Master/Slave
Jumper Settings (JCF1)
Jumper Setting Defi nition
ClosedMaster
OpenSlave
Power Supply Fail Detect
Enable/Disable
The system can notify you in the event
of a power supply failure. This feature
assumes that redundant power supply
modules are installed in the chassis. If
you only have a single power supply
installed, you should disable this func-
tion with J3P to prevent false alarms.
See the table on the right for jumper
settings.
SAS RAID Select
JPS1 allows you to select between
SR RAID, which is the default and
enables SAS RAID, or IT RAID, which
treats SAS drives as non-RAID drives
and requires a fi rmware fl ash. See
the table on the right for jumper set-
tings and the following page for the IT
fi rmware fl ash procedure.
Power Supply Fail Detect
Jumper Settings (J3P)
Jumper Setting Defi nition
OpenDisabled
ClosedEnabled
SAS RAID Select
Jumper Settings (JPS1)
Jumper Setting Defi nition
OpenIT RAID
ClosedSR RAID
Note: SR = Sof t ware RAID IT = I nte gra te
Tar g e t mode
2-18
Page 39
Chapter 2: Installation
Flashing IT Firmware
1. Download the appropriate IT fi rmware from the web site: