SUMMIT SMT4004F Datasheet

SUMMIT

MICROELECTRONICS, Inc.

Quad Power Supply Controller

FEATURES DESCRIPTION

SMT4004

l Programmable Voltage and Current Monitoring

w Monitors 4 independent supplies w Programmable Host-side Under- and Over-

Voltage Thresholds

w Programmable Card-side Under-Voltage

Monitors

w Programmable Card-side Circuit Breaker

Delay and QuickTrip™ Threshold Levels

l Programmable Card-side Trakker Function

w Programmable Slew Rate Control w Guarantees and Enforces Supply Differential

Tracking

l Programmable Watchdog and Longdog Timers

(0 to 6.4 seconds)

l Operates From Any One of Four Supply Voltages l Nonvolatile Fault Register

w Records Source of Any Interrupt w Readable in “Dead Board” Environment

l All Communications to Configuration Registers

and Memory Array are via I2C Interface

The SMT4004 is a fully integrated programmable voltage manager IC, providing supervisory functions and tracking control for up to four independent power supplies. The four internal managers perform the following functions: Monitor source (bus-side) voltages for under- and overvoltage conditions, monitor each supply for over-current conditions, monitor back end (card-side) voltages for two staged levels of under-voltage conditions, insure power to the card-side logic tracks within the specified parametric limits, and provide supply status information to a host processor.

The SMT4004 incorporates nonvolatile programmable circuits for setting all of the monitored thresholds for each manager. Individual functions are also programmable allowing interrupts or reset conditions to be generated by any combination of events. Because of a proprietary EEPROM technology that it employs it is also able to store fault conditions as they occur. In the case of a catastrophic failure the fault is recorded in the registers and then can be read for analysis.

Programming of configuration, control and calibration values by the user can be simplified with the interface adapter and Windows GUI software obtainable from Summit Microelectronics.

SIMPLIFIED APPLICATION DIAGRAM

3.3V

2.5V

1.8V

OPTIONAL

VI1

VI2

VI3

VI4

CB1

CB2

VDD_CAP

SDA

GND4

SCLA0A1

GND1

GND2

GND3

I2C

©SUMMIT MICROELECTRONICS, Inc., 2001 • 300 Orchard City Dr., Suite 131 • Campbell, CA 95008 • Phone 408-378-6461 • FAX 408-378-6586 • www.summitmicro.com

VG1

CB3

CB4

SMT4004

VG2

VG3

GND

VG4

CROWBAR

VO1

CROWBAR

VO2

VO3

VO4

100Ω

Characteristics subject to change without notice 2049 3.1 3/19/01

FUNCTIONAL BLOCK DIAGRAM

SMT4004

UV_OVERRIDE

VO1 CB1

VI1

VO2 CB2

VI2

VO3 CB3

VI3

VO4 CB4

VI4

PWR_ON

20 37

21 36 40

22 35 39

23 34 38

SUPPLY

MANAGER

SUPPLY

MANAGER

SUPPLY

MANAGER

SUPPLY

MANAGER

FORCE_SD

SEQUENCE

ENABLE

LOGIC

All Resistors

are 100kΩ

SEATED1#

SEATED2#

MR#

IRQ_CLR#

RESET &

STATUS

OUTPUT

CONTROL

LOGIC

CHARGE

PUMP &

VGATE

CONTROL

TRAKKER

LOGIC

TIMER LOGIC

IRQ#

RST1#

13 14

RST2# RST3#

15 16

RST4# CROWBAR

CBFAULT

HEALTHY#

VGATE1

VGATE2

VGATE3

VGATE4

VGG_CAP

ENABLE

TRKR_IRQ#

WLDI

LDO#

WDO#

REF

SDA

SCL

2049 BD 2.2

VDD_CAP

2049 3.1 3/19/01

POWER SUPPLY

ARBITRATION

PGND

DGND

AGND

MEMORY & 2-WIRE

BUS

INTERFACE

PGND

SUMMIT MICROELECTRONICS, Inc.

1.25V

PIN CONFIGURATION

WLDI

SCL

48-Pin TQFP

SDAA2A1A0V

_CAP

VI1

VI2

VI3

VI4

SMT4004

CB1

LDO#

WDO#

CROWBAR

1.25V

REF

MR#

IRQ_CLR#

IRQ#

PGND

TRKR_IRQ#

SEATED1# SEATED2#

UV_OVERRIDE

4847464544434241403938

1 2 3 4 5 6 7 8

9 10 11 12

1314151617181920212223

VO1

PGND

DGND

RST1#

RST2#

RST3#

RST4#

AGND

VO2

VO3

36 35 34 33 32 31 30 29 28 27 26 25

VO4

ENABLE

CB2 CB3 CB4 PWR_ON VGATE1 VGATE2 VGATE3 VGATE4 VGG_CAP FORCE_SD HEALTHY# CBFAULT

2049 PCon 2.1

ABSOLUTE MAXIMUM RATINGS*

Temperature Under Bias .......................-55°C to 125°C

Storage Temperature ............................-65°C to 150°C

Lead Solder Temperature (10 secs) ...................300 °C

Terminal Voltage with Respect to GND:

V0, V1, V2, and V3........... -0.3V to 6.0V

All Others........................ -0.3V to 6.0V

RECOMMENDED OPERATING CONDITIONS

Temperature –40ºC to 85ºC. Voltage 2.7V to 5.5V

SUMMIT MICROELECTRONICS, Inc.

2049 3.1 3/19/01

*COMMENT

Stresses listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions outside those listed in the operational sections of this specification is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability.

DC OPERATING CHARACTERISTICS

(Over Recommended Operating Conditions; Voltages are relative to GND)

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DAOL

00 52sµ 01 05sµ

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10 001sµ

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10 001Vm

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KNIS

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00 04001041s/V 01 001052053s/V

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V7.2=IV9.0 × IVIVV

V5=IV7.0 × IVIVV

V7.2=IV1.0– 1.0 × IVV

V5=IV1.0– 3.0 × IVV

Am2=04.0V

SMT4004

7.25.5V

001Vm

2049 Elect Table 1.1

2049 3.1 3/19/01

SUMMIT MICROELECTRONICS, Inc.

PIN DESCRIPTIONS AND DEVICE OPERATION

THE

TRAKKER

SUPPLY VOLTAGES

SMT4004

SUPPLY MANAGERS

The VI inputs of all four supply managers are diode ORed and tied to the device's internal VDD node. The will use the highest VI input for its supply voltage. At least one VI input must be at or above 2.7V for proper device operation.

VDD_CAP — Charge storage connection for the chip's internal power supply. For most applications a 10µF capacitor should be connected to his pin.

VGG_CAP — This pin should be tied to a capacitor to be charged by the charge pump. The capacitor should be of sufficient size so as to provide current to the VGATE outputs under varying load conditions.

PGND — Power ground DGND — Digital Ground AGND — Analog Ground

TRAKKER

TIMERS

LDO# — The longdog timer output is an active-low open-

drain output that can be wire-ORed with other open-drain signals. The longdog timer is generally programmed to generate an output at a time interval longer than the watchdog timer. The time interval is programmed in Register

WDO# — The watchdog timer output is an active-low open-drain output that can be wire-ORed with other opendrain signals. The watchdog timer is generally programmed to generate an output at a time interval shorter than the longdog timer. The time interval is programmed in Register

R1C

The electrical placement of the SMT4004 on a printed circuit card is such that it separates the host power supply and any on-board DC-to-DC converters (or LDOs) from the backend circuitry such as multiple DSPs, microprocessors and associated glue logic. The host supplies, and any other regulated voltages that will be “switched” by the device, are referred to as bus-side voltages. The voltages that are on the backend circuitry side of the switches are referred to as card-side voltages.

The four supply manager blocks are identical. Each contains three primary functional blocks: the first monitors the bus-side voltages, the second monitors the card-side voltages, and the third monitors over-current conditions for that particular supply.

BUS-SIDE MANAGEMENT

Figure 1 illustrates the functional blocks of the four supply managers. Each manager block can be independently enabled or electrically removed from the device.

The VI input monitors the bus-side voltage for both undervoltage and over-voltage conditions. The thresholds for the under-voltage detection for VI inputs are programmed in Registers the V designed so that the threshold can be determined by multiplying the binary value of the Register times 20mV and adding that to 0.9V in the formula P × n), where n is the register value (0 - 255 decimal). This allows very precise monitoring of voltages in the range of

0.9V to 6V without the use of external resistor divider networks.

R00

through

of a nonvolatile DAC. The DAC has been

REF

R03

. The VI input is effectively

= 0.9V + (0.2mV

VIT

WLDI — Watchdog and longdog timer reset input. A low- to-high transition on this pin will reset both the watchdog timer and the longdog timer.

The watchdog and longdog work in tandem: resetting one resets the other. Generally, the longdog will be programmed to time out sometime after the watchdog. As an example, the WDO# output could be used to generate a warning interrupt and the LDO# output could be tied to a system reset line.

Both timers can be turned off, facilitating system debug and also allowing operating systems to ‘boot up’ and configure themselves without interrupts or resets.

SUMMIT MICROELECTRONICS, Inc.

2049 3.1 3/19/01

The over-voltage level is determined by the value in registers SMT4004 GUI. All enabled manager blocks must ensure their respective VI inputs are within the programmed limits before the VGATE outputs can be turned on and the

TRAKKER

also be used to generate a general interrupt. It should be noted that either one or both of the bus-side

monitors could be disabled via Registers

R07

R04

through

logic enabled. The VI comparator outputs can

R07

, and is selected by the

R04

through

SMT4004

–

REF

Programmable

Delay

Programmable

Quick Trip Threshold

25mV

–

Comparator

–

Comparator

Circuit

Breaker

Comparator

Quick

Trip

UV1

Comparator

Quick Trip

VGATE Enable

( = Programmable)

To IRQ

VGATE and

TRAKKER

Logic

To Crowbar

To RST

REF

–

UV2

Comparator

Figure 1. Supply Manager Circuit

CARD-SIDE MANAGEMENT

On the card-side the mable under-voltage thresholds on the VO inputs: UV1 and UV2. UV1 can be used to generate a warning interrupt that the supply is decaying, and UV2 can be used to generate a reset condition or a crowbar output. The cardside under-voltage (UV1) threshold value is programmed in Registers R08 through R0B. Like the bus-side thresholds the levels can be programmed in 20mV increments (on top of 0.9V). The second level (UV2) is determined by

TRAKKER

monitors two program-

2049 3.1 3/19/01

2049 Fig01 1.0

the value in Registers R0C through R0F, and is selected by the SMT4004 GUI.

It should be noted that either one or both of the card-side monitors can be disabled via Registers

R0C

through

R0F

OVER-CURRENT PROTECTION

The CB inputs are the circuit breaker inputs for the supply voltages. With a series resistor placed in the supply path between VI and CB the circuit breaker will trip whenever the voltage across the resistor exceeds 25mV.

SUMMIT MICROELECTRONICS, Inc.

SMT4004

The on-board electronic circuit breaker can be programmed to application specific levels. The circuit breaker delay defines the period of time the voltage drop across RS is greater than 25mV but less than V

QCB

before the VGATE output will be shut down. This is effectively a filter to prevent spurious shutdowns of VGATE. The delays that can be programmed are 25µs, 50µs, 100µs and 200µs. The programmable delay bits are located in Register

The Quick-Trip circuit breaker threshold (V to 150mV, 100mV, 75mV or off (Register

R1B

) can be set

QCB

R1A

). This is the threshold voltage drop across RS that is placed between V

and CBSENSE. If the voltage drop exceeds the

programmed threshold, the electronic circuit breaker will immediately trigger with no delay.

The outputs of these comparators can be used to generate interrupts and reset conditions and toggle the crowbar output.

POWER-ON SEQUENCING

In order to begin sequencing of the card-side supplies (ramping the VGATE outputs) a number of conditions must be met. All enabled bus-side voltages must be above their respective under-voltage thresholds, the card-side

voltages ( be near zero volts, and the following inputs must be properly set.

ENABLE — When active the ENABLE input brings

the IC out of a standby mode where the charge pump supplying the VGATE outputs is turned on (and begins charging the VGG_CAP) and the bandgap reference is turned on. The ENABLE input can be programmed to be either active low (default from the factory) or active high (Register

SEATED1# and SEATED2# — the SEATED inputs are effectively two additional enable inputs that must be low to enable the sequencing of the card-side voltages. In a staggered pin environment these inputs can be tied to the “short” pins, insuring the card is fully seated before any power is applied to the cardside logic. These inputs can also be tied to card insertion switches to indicate proper seating.

PWR_ON — the PWR_ON input is the last input that will typically be driven to enable power sequencing to the card-side. The PWR_ON input can be programmed to be either active low (default from the factory) or active high (Register

e.g.

, residual capacitor stored potentials) must

R1B

TRAKKING

AND SOFTSTART CONTROL

VGATE — The VGATE outputs are used to control the

“turning-on” of the card-side voltages. The ramp rate (for both turn-on and turn-off) of the outputs is programmable from 100V/s to 1000V/s (Register

R10

). The four outputs ramp at the same slew-rate, so normally there will be no differential voltage between any of the supplies until each reaches its maximum level.

The ramp rates are inherently adaptive. That is, if the difference between any VO input is greater than 100mV in the linear region, the slew rate will be increased or decreased to minimize the differential. The comparisons are made between VO1 and VO2, VO2 and VO3, VO3 and VO4, and VO4 and VO1. If at any time a differential of greater than 300mV is detected a pre-programmed (Register

R10

) action can be taken. The

TRAKKER

can shut down the offending supply, generate an interrupt output, or ignore the situation.

If SoftStart is enabled (Registers

R0C

through

R0F

) the supply or supplies designated will be ramped as soon as the input conditions are met and no Trakking will be performed. Any supply not designated as a softstart supply will not be ramped until the designated supply has reached its VO threshold. This type of operation would commonly be used where a bus voltage (

e.g.

, 5V) is first switched to a DC-to-DC converter or group of LDOs; and then their outputs would be switched in a Trakking mode to the card-side logic.

Supply managers designated for Trakking will not begin start-up until the soft start channels are fully turned on. The delay is approximated by the formula tD =16,000 ÷ SR, where tD is the time delay in milliseconds between the PWR_ON signal going high and the start of the tracking ramp-up, and SR is the programmed start-up slew rate in V/s. For example, the time delay for a programmed slew rate of 500V/s is: tD = 16,000 ÷ 500 = 32ms.

POWER MANAGEMENT STATUS OUTPUTS

The

TRAKKER

provides to the host system or host processor resident on its board. One type of output is “hardwired” internally and the other is programmable.

HEALTHY# — The HEALTHY output is an active-low open-drain output that can be wire-ORed with other opendrain signals. It is driven low when all of the enabled managers’ card-side voltages are valid and there are no over-current conditions. The signal is used to indicate the power supplies are within their programmed operating limits.

has two types of status outputs that it

SUMMIT MICROELECTRONICS, Inc.

2049 3.1 3/19/01

SMT4004

CBFAULT — CBFAULT is driven active whenever an

over-current condition is detected. It is a programmable output that can be either an active high or active low (factory default) output.

RESETS

RST1# to RST4# — Associated with each manager is a

reset output. They are active-low open-drain outputs that can be wire-ORed with other open-drain signals. The user can select UV1, UV2 and/or an over-current condition as the trigger for the reset pulse by programming Registers

R11

and

R12

(the default condition from the factory is all conditions generate a reset). The reset pulse width is adjustable by writing to Register from the factory is pulse of 200ms).

MR# — When driven low the manual reset input will automatically drive all four reset outputs low. During programming the MR# input must be pulled low.

R1C

(default condition

INTERRUPTS

IRQ# — the IRQ# output is an active low open-drain output

that is driven low whenever one or more of its programmed triggers is active. There are twenty programmable sources for generating the interrupt: bus-side over- and under-voltage, card-side under-voltage 1 and 2, and an over-current condition. Each source is individually enabled by writing to Registers default from the factory is to enable all sources. The IRQ# output can only be cleared by bringing IRQ_CLR# low, or after a power-down/power-up sequence.

TRKR_IRQ# — the was a skew of greater than 300mV during the power on cycle. The source of the TRKR_IRQ# is programmable and can be initiated by any one of the managers. The configuration Registers interrupt. Configuration Register TRKR_IRQ# output (or one of three other options). The default from the factory is to enable all sources. The TRKR_IRQ# output can only be cleared by bringing IRQ_CLR# low or after a power-down/power-up sequence.

In order to avoid false interrupts during a power-on sequence there is a programmable “power-on interrupt holdoff” register. The delay can be programmed from 200ms to 1600ms. The interrupt hold-off is in Register its default value from the factory will be 1600ms.

TRAKKER

R11

R13, R14

interrupt indicates there

and

R12

and

R15

select the source of

R10

enables the

. The

R15

and

FAULT REGISTER

Whenever an interrupt is generated the cause of the fault will be recorded in the nonvolatile status Register. In order to avoid false recordings during power-down situations, no faults will be recorded if the PWR_ON input has been deactivated. The fault Registers are located at through assigned bit location. Overwriting the fault Register with “0’s” is the only way to clear a recorded fault condition.

CROWBAR — The CROWBAR output is another form of status output. The conditions to generate a crowbar output are programmable in Register of the conditions occurs the CROWBAR output will strobe. Rapid shutdown of the card-side supplies may be required to prevent damage to the DSP’s or microprocessors. The VGATE outputs will be shut down when CROWBAR occurs. SCRs with a fast turn-on time make excellent crowbar devices and only need a pulse of gate current to ‘trigger.’

R1F

. The fault source is indicated by a “1” in the

R19

. Whenever one

R1D

MEMORY AND REGISTER ACCESS

A0, A1 & A2 — The address pins are biased either to the

highest VI pin or GND, and provide a mechanism for assigning a unique address to the SMT4004.

SDA — SDA is a bidirectional serial data pin. It is configured as an open drain output and will require a pullup to the highest VI pin.

SCL — SCL is the serial clock input.

MISCELLANEOUS MANAGER SIGNALS

1.25V

be used in conjunction with external circuitry. UV_OVERRIDE — The Under-Voltage Override input will

disable the under-voltage comparators. This can be used for board test and also during system margining.

FORCE_SD — When asserted the Force Shut Down input will immediately clamp the VGATE outputs to ground. This can be used in conjunction with the CROWBAR. The active level for FORCE_SD is programmable and accessible in Register

— This pin is a 1.25V Reference output that can

REF

R1B

2049 3.1 3/19/01

SUMMIT MICROELECTRONICS, Inc.

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