SUMMIT SMS24S1R1R1R0R0, SMS24S2R1R1R0R0, SMS24S3R1R1R0R0, SMS24S4R1R1R0R0, SMS24S5R1R1R0R0 Datasheet

1

Characteristics subject to change without notice

2048 2.4. 3/1/01

SMS24

SUMMIT

MICROELECTRONICS, Inc.

©SUMMIT MICROELECTRONICS, Inc., 2001 • 300 Orchard City Dr., Suite 131 • Campbell, CA 95008 • Phone [phone] • FAX [phone] • www.summitmicro.com

l User Programmable Device Configuration
l Guaranteed Reset Valid to VCC = 1V
l Immune to Short Negative VCC Transients
l Six Unique Pin Configurations
l User Programmable Feature Options:

w Reset Threshold Voltages
w Reset Pulse Widths
w Programmable Watchdog Timeouts
w Programmable Over- or Under-Voltage Sens-

ing

l High Reliability

w Endurance: 100,000 erase/write cycles
w Data retention: 100 years

Highly Programmble Voltage Supervisor y Circuit

FEATURES

DEVICE TYPES

INTRODUCTION

The SMS24 is a configurable and in-system program­mable second generation 8 pin supervisory circuit. This
single device is adaptable to provide the optimum func­tionality for a given system or sub-system. User program­mable functions available — reset pulse width, watchdog
delays, and voltage monitor thresholds — eliminate exter­nal components and allow standardization to enhance
system reliability. Additionally, 4K bits of general purpose
EEPROM is available on all configurations. The SMS24
is available in six pin configurations, and is compatible with
all Summit programmable devices and other I2C compo­nents.

Programming of configuration, control and calibration
values by the user can be simplified with the interface
adapter and Windows GUI software obtainable from Sum­mit Microelectronics.

2048 DTTable 2.1

NC

RESET#

NC

GND

V

CC

RESET
SCL
SDA

Device

Code

001

NC

RESET#

NC

GND

V

CC

WP
SCL
SDA

Device

Code

010

WDI

RESET#

NC

GND

V

CC

RESET
SCL
SDA

Device

Code

011

RESET#2
RESET#1

V

SENSE

GND

V

CC

MR#
SCL
SDA

Device

Code

100

V

LOW

#

RESET#

V

SENSE

GND

V

CC

RESET
SCL
SDA

Device

Code

101

V

LOW

#

RESET#

V

SENSE

GND

V

CC

WDI
SCL
SDA

Device

Code

110

2046 DT 1.0

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#teseRteseRgodhctaW

erawtfoS

IDW

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100

✔✔✔✔ ✔

010

✔✔✔✔ ✔

110

✔✔✔ ✔ ✔

001

✔✔✔ ✔✔

101

✔✔✔✔ ✔ ✔

011

✔✔✔✔✔

2

SMS24

2048 2.4. 3/1/01

SUMMIT MICROELECTRONICS, Inc.

FUNCTIONAL BLOCK DIAGRAMS

Block Diagram Device Code 010

Block Diagram Device Code 001

+

–

GND

V

CC
8

4

V

TRIP

RESET

CONTROL

1.25V

SCL

6

SDA

5

2046 BD001 2.1

WRITE

CONTROL

NONVOLATILE

MEMORY

ARRAY

RESET#

2

RESET

7

PROGRAMMABLE

RESET PULSE

GENERATOR

PROGRAMMABLE

WATCHDOG

TIMER

+

–

GND

V

CC
8

4

RESET#

2

V

TRIP

RESET

CONTROL

WP

7

1.25V

SCL

6

SDA

5

2046 BD010 2.1

WRITE

CONTROL

NONVOLATILE

MEMORY

ARRAY

PROGRAMMABLE

RESET PULSE

GENERATOR

PROGRAMMABLE

WATCHDOG

TIMER

3

2048 2.4. 3/1/01

SMS24

SUMMIT MICROELECTRONICS, Inc.

Block Diagram Device Code 100

Block Diagram Device Code 011

+

–

GND

V

CC

8

4

RESET#

2

V

TRIP

RESET

CONTROL

RESET

7

1.25V

SCL

6

SDA

5

2046 BD011 1.0

WRITE

CONTROL

NONVOLATILE

MEMORY

ARRAY

PROGRAMMABLE

RESET PULSE

GENERATOR

WDI

1

PROGRAMMABLE

WATCHDOG

TIMER

+

–

GND

V

CC
8

4

RESET#1

2

V

TRIP

RESET

CONTROL

MR#

1.25V

SCL

6

SDA

5

2046 BD100 1.1

WRITE

CONTROL

NONVOLATILE

MEMORY

ARRAY

PROGRAMMABLE

RESET PULSE

GENERATOR

V

SENSE

3

1

+

–

RESET#2

7

PROGRAMMABLE

WATCHDOG

TIMER

4

SMS24

2048 2.4. 3/1/01

SUMMIT MICROELECTRONICS, Inc.

Block Diagram Device Code 110

Block Diagram Device Code 101

+

–

GND

V

CC
8

4

RESET#

2

V

TRIP

RESET

CONTROL

RESET

7

1.25V

SCL

6

SDA

5

2046 BD101 1.0

WRITE

CONTROL

NONVOLATILE

MEMORY

ARRAY

PROGRAMMABLE

RESET PULSE

GENERATOR

V

SENSE

3

V

LOW

#

1

PROGRAMMABLE

WATCHDOG

TIMER

+

–

OV

UV

+

–

GND

V

CC
8

4

RESET#

2

V

TRIP

RESET

CONTROL

WDI

7

1.25V

SCL

6

SDA

5

2046 BD110 1.0

WRITE

CONTROL

NONVOLATILE

MEMORY

ARRAY

PROGRAMMABLE

RESET PULSE

GENERATOR

V

SENSE

3

V

LOW

#

1

PROGRAMMABLE

WATCHDOG

TIMER

+

–

OV

UV

5

2048 2.4. 3/1/01

SMS24

SUMMIT MICROELECTRONICS, Inc.

*COMMENT

Stresses listed under Absolute Maximum Ratings may cause perma­nent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions
outside those listed in the operational sections of this specification is not
implied. Exposure to any absolute maximum rating for extended
periods may affect device performance and reliability.

Temperature Under Bias .......................-55°C to 125°C

Storage Temperature ............................ -65°C to 150°C

Lead Solder Temperature (10 secs) ...................300 °C

Terminal Voltage with Respect to GND:

V

CC

................................. -0.3V to 6.0V

All Others........................ -0.3V to 6.0V

DC OPERATING CHARACTERISTICS

ABSOLUTE MAXIMUM RATINGS*

(Over Recommended Operating Conditions; Voltages are relative to GND)

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CC

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I

CC

tnerrucylppuS

<V6.3V

CC

V5.5<05Aµ

<V7.2V

CC

V6.3<02Aµ

sseccayromeM3Aµ

V

TSRP

dlohserhtteserelbammargorP

4RR3RR2RR1RR0RR
00001 570.251.252.2V
00010 55.256.27.2V
00100 8.29.20.3V
01000 52.4573.45.4V

10000 5.4526.457.4V

V

T

V

ESNES

dlohserhttupni32.152.172.1V

V

LO

V,2#TESER,1#TESER

WOL

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I

KNIS

V,Am2.1=

CC

V=

TSRP

.nim

3.0V

I

KNIS

V,Am002=

CC

V2.1=3.0V

I

RM

tnerrucpullup#RM 001Aµ

V

Ll

VnonoitcejeresioN

CC

3.0 × V

CC

V

V

HI

otgnissorcdlohserhtyaleD

tuoTESER

7.0 × V

CC

V

2046 DCElect Table 2.0

RECOMMENDED OPERATING CONDITIONS

Temperature –40ºC to 85ºC.
Voltage 2.7V to 5.5V

ENDURANCE AND DATA RETENTION

The SMS24 is designed for applications requiring
100,000 erase/write cycles and unlimited read cycles. It
provides 100 years of secure data retention, with or
without power applied, after the execution of 100,000
erase/write cycles.

6

SMS24

2048 2.4. 3/1/01

SUMMIT MICROELECTRONICS, Inc.

PIN DESCRIPTIONS

RESET#

This signal is an active-low open drain I/O. Whenever the
voltage on VCC is below the programmed threshold volt­age the RESET# pin will be driven low. After VCC passes
through the threshold (in a positive direction) the RESET#
output will continue to be driven for the programmed time­out period (t

PTO

). In most configurations RESET# is also
an input. Whenever it is driven low it will activate the reset
timer. The RESET# output will then be driven low by the
device for the programmed period. If the input pulse is of
shorter duration than t

PTO

, RESET# will continue to be

driven. If it is longer than t

PTO

, RESET# will be released

and follow the input back high.

RESET

This signal is an active-high open drain I/O. Whenever the
voltage on VCC is below the programmed threshold volt­age the RESET pin will be driven high. After VCC passes
through the threshold (in a positive direction) the RESET
output will continue to be driven for the programmed time­out period. In all configurations using RESET it is also an
input. Whenever it is driven high it will activate the reset
timer. The RESET output will then be driven high by the
device for the programmed period. If the input pulse is of
shorter duration than t

PTO

, RESET will continue to be

driven. If it is longer than t

PTO

, RESET will be released and

follow the input back low.

RESET#1 & RESET#2

These signals are active-low open drain outputs (not I/Os).
These outputs are only available to Device Code 100, and
are both set to a low state by any one of three events: V

CC

below trip level, V

SENSE

< 1.25V, or MR# strobed low.

MR#

Manual Reset input is an active low input. Whenever it is
taken low it will generate a reset time-out.

V

SENSE

This is a second voltage sense input connected to its own
comparator that has reference of 1.25V. The comparator
can be programmed to activate the V

LOW

# output either for

an over-voltage or under-voltage condition.

V

LOW

#

This is an active-low open-drain output that can be wire­ORed with the RESET# output or tied directly to an
interrupt input.

WDI

This is the Watchdog Interrupt input. Whenever a transi­tion occurs on WDI the watchdog timer will be cleared. If
the device does not receive an interrupt before t

WDTO

the

device will drive the reset output(s). The period t

WDTO

is
programmable for four basic values. It can also be placed
into an idle mode, facilitating system debug, and allowing
a system time to configure itself after a power-on.

WP

This is an auxilliary Write lockout input pin. When held high
no writes will occur.

SCL

The serial interface clock input.

SDA

The serial interface data I/O.