SUMMIT SMH4804F, SMH4804S Datasheet

1Characteristics subject to change without notice

2050 3.0 10/01/01

SMH4804

Preliminary

SUMMIT

MICROELECTRONICS, Inc.

©SUMMIT MICROELECTRONICS, Inc., 2001 • 300 Orchard City Dr., Suite 131 • Campbell, CA 95008 • Phone [phone] • FAX [phone] • www.summitmicro.com

!!

!!

! Soft Starts Main Power Supply on Card Insertion

or System Power Up

!!

!!

! Senses Card Insertion via Short Pins or Ejector

Switches

!!

!!

! Master Enable to Allow System Control of Power

Up or Down

""

""

" Can be used as a Temperature Sense Input

!!

!!

! Programmable Independent Controls of 4 DC/DC

Converters

""

""

" Not Enabled until Host Supply Fully Soft

Started

""

""

" Programmable Time Delay Between each

Enable Signal

""

""

" Available Input to hold off Dependant Enables

until Conditions are Satisfied

!!

!!

! Highly Programmable Circuit Breaker

""

""

" Programmable Quick-Trip

TM

Values

""

""

" Programmable Current Limiting

User-Programmable Nonvolatile Distributed Power
Hot Swap Controller with Forced Shutdown

FEATURES

SIMPLIFIED APPLICATION DRAWING

""

""

" Programmable Circuit Breaker Mode:

Latched (Volatile or Nonvolatile)

""

""

" Programmable Duty Cycle Times

""

""

" Programmable Over-current Filter

!!

!!

! Programmable Host Voltage Fault Monitoring

""

""

" Programmable Under- voltage Hysteresis

""

""

" Programmable UV/OV Voltage Filter

""

""

" Programmable Fault Mode: Latched or Duty

Cycle

!!

!!

! Programmable Forced Shutdown Timer

!!

!!

! 2.5V and 5.0V Reference Outputs

""

""

" Eliminates the Need or Other Primary Volt-

ages

""

""

" Easy Expansion of External Monitor Func-

tions

!!

!!

! Internal Shunt Regulator Allows a Wide Supply

Range

VDD

VSS

CBSENSE

PD1#

PD2#

UV

OV

PG3#

2.5VREF

PG2#

PG1#

5.0VREF

PG4#

2050 SAD

0V

–48V

I

2

C

SDA

SCL

A2

A1

A0

VGATE

Pin Detect

Pin Detect

DC/DC

SMH4804

DC/DC

DC/DC

DC/DC

FS#

Pinout is from
28 pin SOIC
package

3

2

20

6

5

12

1110

13

16

15

14

28

17

19

26

27

25

18

24

2

SMH4804

2050 3.0 10/01/01

Preliminary

SUMMIT MICROELECTRONICS, Inc.

FUNCTIONAL BLOCK DIAGRAM

Pinout is from the 28 pin SOIC package.

PROGRAMM-

ABLE

DELAY

PROGRAMM-

ABLE

DELAY

PROGRAMM-

ABLE

DELAY

PROGRAMM-

ABLE

DELAY

+
–

+
–

+
–

Programmable

Quick Response

Ref. Voltage

50mV

FAULT
LATCH

AND

DUTY

CYCLE

TIMER

P. D.

FILTER

+
–

+
–

5V

2.5V

12V

VGATE
SENSE

+
–

VDD

VSS

MODE

RESET#

CBSENSE

EN/TS

PD1#

PD2#

UV

OV

PG3#

ENPGA

ENPGB

2.5VREF

PG2#

PG1#

DRAIN

SENSE

VGATE

FAULT#

5.0VREF

12VREF

50kΩ

200kΩ

50kΩ

PROG

REF

SDA

SCL

PROGRAMMING

STEERING

LOGIC

ENPGC

DEVICE

ADDRESS

DECODE

A2

A1

A0

PG4#

10µA

2050 BD

50kΩ

50kΩ

50kΩ

50kΩ

50kΩ

Programmable

Shutdown

Timer

FS#

Three

@ 50kΩ

50kΩ50kΩ

OV/UV

FILTER

P. D.

FILTER

27

24

26

25

19

18

7

3

28

4

5

6

1

15

17

14

13
16

8

9

2

12

10

11 20 23

22 21

3

2050 3.0 10/01/01

SMH4804

Preliminary

SUMMIT MICROELECTRONICS, Inc.

PIN CONFIGURATIONS

DRAIN SENSE

A0

VGATE

EN/TS

PD1#
PD2#

FAULT#

RESET#

MODE

SDA

SCL

CBSENSE

A1

VSS

VDD
PG4#
PG2#
PG1#
PG3#
ENPGA
ENPGB
ENPGC

2.5VREF
5VREF
FS#
OV
A2
UV

1
2
3
4
5
6
7
8
9
10
11
12
13
14

28
27
26
25
24
23
22
21
20
19
18
17
16
15

2050 SOIC PCon 2.1

28-Pin SOIC

EN/TS

PD1#
PD2#

FAULT#

RESET#

MODE

SDA

SCL

PG1#

PG3#

ENPGA

ENPGB
ENPGC

2.5VREF

5VREF
FS#

48-Pin TQFP

2050 TQFP PCon 2.1

CBSENSE

A1

VSS

VSS

UV

A2

OV

VGATEA0DRAIN SENSE

VDD

PG4#

PG2#

1
2
3
4
5
6
7
8

9
10
11
12

1314151617181920212223

24

36
35
34
33
32
31
30
29
28
27
26
25

4847464544434241403938

37

Note: TQFP pins left blank are all no connect.

4

SMH4804

2050 3.0 10/01/01

Preliminary

SUMMIT MICROELECTRONICS, Inc.

PIN DESCRIPTIONS

PD1# & PD2#

These are logic level active low inputs that can optionally
be employed to enable VGATE and the PG outputs when
they are at V

SS

. These pins each have an internal 50kΩ

pull-up to 5V.

UV

The UV pin is used as an under-voltage supply monitor,
typically in conjunction with an external resistor ladder.
VGATE will be disabled if UV is less than 2.5V. Program­mable internal hysteresis is available on the UV input,
adjustable in increments of 62.5mV. Also available is a
filter delay on the UV input.

OV

The OV pin is used as an over-voltage supply monitor,
typically in conjunction with an external resistor ladder.
VGATE will be disabled if OV is greater than 2.5V. A filter
delay is available on the OV input.

MODE

The state of the MODE signal determines how fault
conditions are cleared. The device is in the latched mode
when the signal is held at VSS, and the cycle mode when
held at 5V or left floating. This pin has an internal 50kΩ
pull-up to 5V.

RESET#

RESET# is used to clear latched fault conditions. When
this pin is held low the VGATE and PG outputs are
disabled. Refer to the Circuit Breaker Operation and the
associated timing diagrams for detailed characteristics.
This pin has an internal 50kΩ pull-up to 5V.

CBSENSE

The circuit breaker sense input is used to detect over­current conditions across an external, low value sense
resistor (RS) tied in series with the Power MOSFET. A
voltage drop of greater than 50mV across the resistor for
longer than t

CBD

will trip the circuit breaker. A program-

mable Quick-Trip™ sense point is also available.

DRAIN SENSE

The DRAIN SENSE input monitors the voltage at the drain
of the external power MOSFET switch with respect to VSS.
An internal 10µA source pulls the DRAIN SENSE signal
towards the 5V reference level. DRAIN SENSE must be
held below 2.5V to enable the PG outputs.

EN/TS

The Enable/Temperature Sense input is the master en­able input. If EN/TS is less than 2.5V, VGATE will be
disabled. This pin has an internal 200kΩ pull-up to 5V.

5VREF

This is a precision 5V output reference voltage that may be
used to expand the logic input functions on the SMH4804.
The reference output is with respect to VSS.

2.5VREF

This is a precision 2.5V output reference voltage that may
be used to expand the logic input functions on the
SMH4804. The reference output is with respect to VSS.

FAULT#

FAULT# is an open-drain, active-low output that indicates
the fault status of the device.

The SMH4804 is designed to control hot swapping of plug­in cards operating in a distributed power environment.
The distributed power rail can range from 20V to 500V.
The SMH4804 hot-swap controller provides under-volt­age and over-voltage monitoring of the host power supply.
It also drives an external power MOSFET switch that
connects the supply to the load and protects against over­current conditions that might disrupt the host supply.
When the source and drain voltages of the external
MOSFET are within specification the SMH4804 provides
Power Good logic outputs that may be used to enable DC­DC converters. The four separate Power Good outputs

DESCRIPTION

activate loads in a timed sequence. Additional features
of the device include: temperature sense or master
enable input, 2.5V and 5V reference outputs for expanding
monitor functions, two Pin-Detect enable inputs for card
insertion verification, and duty-cycle or latched over­current protection modes. All of these features can be
programmed through the two-wire interface.

Programming of configuration, control and calibration
values by the user can be simplified with the interface
adapter and Windows GUI software obtainable from Sum­mit Microelectronics.

5

2050 3.0 10/01/01

SMH4804

Preliminary

SUMMIT MICROELECTRONICS, Inc.

VGATE

The VGATE output activates an external power MOSFET
switch. This signal supplies a constant current output
(100µA typical), which allows easy adjustment of the
MOSFET turn on slew rate.

ENPGA

This is an active high input that controls the PG2#, PG3#
and PG4# outputs. When ENPGA is pulled low the PG2#,
PG3# and PG4# outputs are immediately placed in a high
impedance state. When ENPGA is driven high or left
floating PG2# will be driven low at a time period of t

PGD

after PG1# has been active. This pin has an internal 50kΩ
pull-up to 5V.

ENPGB

This is an active high input that controls the PG3# and
PG4# outputs. When ENPGB is pulled low the PG3# and
PG4# outputs are immediately placed in a high impedance
state. When ENPGB is driven high or left floating PG3# will
be driven low at a time period of t

PGD

after PG2# has been

active. This pin has an internal 50kΩ pull-up to 5V.

ENPGC

This is an active high input that controls the PG4# output.
When ENPGC is pulled low the PG4# output is immedi­ately placed in a high impedance state. When ENPGC is
driven high or left floating PG4# will be driven low at a time
period of t

PGD

after PG3# has been active. This pin has an

internal 50kΩ pull-up to 5V.

PG1# / PG2# / PG3# / PG4#

The PGn# pins are open-drain, active-low outputs with no
internal pull-up resistor. They can be used to switch a load
or enable a DC/DC converter. PG1# is enabled immedi­ately after VGATE reaches VDD – VGT and the DRAIN

SENSE voltage is less than 2.5V. Each successive PG
output is enabled t

PGD

after its predecessor, provided also
that the appropriate ENPGx input(s) are high. Voltage on
these pins cannot exceed 12V, as referenced to V

SS.

FS#

The Forced Shutdown (FS#) pin is an active low input that
causes VGATE and PG outputs to be shut down at any
time after an internal hold-off timer has expired. The hold­off timer allows supervisory circuits on the secondary side
(which are not powered up initially) to control shut down of
the SMH4804 via an opto-isolator. This input has no pull­up resistor.

A0 / A1 / A2

These are logic level inputs used for decoding multiple
devices on the serial bus. These pins each have an
internal 50kΩ pull-up to 5V.

SDA

SDA is a bidirectional serial data I/O port. This pin has an
internal 50kΩ pull-up to 5V.

SCL

SCL is the serial clock input. This pin has an internal 50kΩ
pull-up to 5V.

V

DD

This is the positive supply input. An internal shunt regula­tor limits the voltage on this pin to approximately 12V with
respect to VSS. A resistor must be placed in series with
the VDD pin to limit the regulator current (RD in the
application illustrations).

V

SS

This is connected to the negative side of the supply.

Note: The pin numbers for each signal are
different on the two packages.

RECOMMENDED OPERATING CONDITIONS

Temperature –40°C to 85°C.

6

SMH4804

2050 3.0 10/01/01

Preliminary

SUMMIT MICROELECTRONICS, Inc.

*Comment

Stresses listed under Absolute Maximum Ratings may cause perma­nent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions
outside those listed in the operational sections of this specification is not
implied. Exposure to any absolute maximum rating for extended
periods may affect device performance and reliability.

Temperature Under Bias ...................... –55°C to 125°C

Storage Temperature ........................... –65°C to 150°C

Lead Solder Temperature (10 seconds) ............. 300 °C

Terminal Voltage with Respect to VSS:

VGATE ........................................ VDD + 0.7V

A0, A1, A2, MODE, RESET,
ENPGA, ENPGB, ENPGC, FS#

SDA, and SCL ........................................... 7V

DC OPERATING CHARACTERISTICS

ABSOLUTE MAXIMUM RATINGS*

(Over Recommended Operating Conditions; Voltages are relative to VSS, except VGT)

2050 Elect Table

PD1#, PD2#, VDD, UV, OV, CBSENSE,
DRAIN SENSE, EN/TS, FAULT#, PG1#,

PG2#, PG3#, and PG4# .......................... 15V

Note: (1) TA = 25ºC.

(2) This value is set by the RD resistor.

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7

2050 3.0 10/01/01

SMH4804

Preliminary

SUMMIT MICROELECTRONICS, Inc.

FUNCTIONAL DESCRIPTION

GENERAL OPERATION

The SMH4804 is an integrated power controller for hot
swappable add-in cards. The device operates from a wide
supply range and generates the signals necessary to drive
isolated output DC/DC converters. A physical connection
must first be made with the chassis to discharge any
electrostatic voltage potentials when a typical add-in
board is inserted into the powered backplane. The board
then contacts the long pins on the backplane that provide
power and ground. As soon as power is applied the device
starts up, but does not immediately apply power to the
output load. Under-voltage and over-voltage circuits
inside the controller verify that the input voltage is within
a user-specified range, and pin detection signals deter­mine whether the card is seated properly.

These requirements must be met for a Pin Detect Delay
period of t

PDD

, after which time the hot-swap controller
enables VGATE to turn on the external power MOSFET
switch. The VGATE output is current limited to I

VGATE

,
allowing the slew rate to be easily modified using external
passive components. During the controlled turn-on period
the VDS of the MOSFET is monitored by the drain sense
input. When drain sense drops below 2.5V, and VGATE
gets above VDD – VGT, the power good outputs can begin
turning on the DC/DC controllers. Power Good Enable
inputs may be used to activate or deactivate specific
output loads.

Steady state operation is maintained as long as all condi­tions are normal. Any of the following events may cause
the device to disable the DC/DC controllers by shutting
down the power MOSFET: an under-voltage or over­voltage condition on the host power supply; an over­current event detected on the CBSENSE input; a failure of
the power MOSFET sensed via the DRAIN SENSE pin;
the pin detect signals becoming invalid; the master enable
(EN/TS) falling below 2.5V; the FS# input being driven low
by events on the secondary side of the DC/DC controllers.
The SMH4804 may be configured so that after any of
these events occur the VGATE output shuts off and either
latches into an off state or recycles power after a cooling
down period, t

CYC

.

Powering V

DD

The SMH4804 contains a shunt regulator on the VDD pin
that prevents the voltage from exceeding 12V. It is
necessary to use a dropper resistor (RD) between the host
power supply and the VDD pin in order to limit current into
the device and prevent possible damage. The dropper
resistor allows the device to operate across a wide range
of system supply voltages, and also helps protect the

device against common-mode power surges. Refer to the
Applications Section for help on calculating the R

D

resis-

tance value.

System Enables

There are several enabling inputs, which allow a host
system to control the SMH4804. The Pin Detect pins
(PD1# & PD2#) are two active low enables that are
generally used to indicate that the add-in circuit card is
properly seated. These inputs must be held low for a
period of t

PDD

before a power-up sequence may be
initiated. This is typically done by clamping the inputs to
VSS through the implementation of an injector switch, or
alternatively through the use of a staggered pins at the
card-cage interface. Two shorter pins arrayed at opposite
ends of the connector force the card to be fully seated (not
canted) before both pin detects are enabled. Care must
be taken not to exceed the maximum voltage rating of
these pins during the insertion process. Refer to details
in the Applications Section for proper circuit implementa­tion.

The EN/TS input provides an active high comparator input
that may be used as a master enable or temperature
sense input. This input signal must exceed 2.5V (nomi­nal) for proper operation.

Under-/Over-Voltage Sensing

The Under-Voltage (UV) and Over-Voltage (OV) inputs
provide a set of comparators that act in conjunction with an
external resistive divider ladder to sense whether or not
the host supply voltage is within the user-defined limits.
The power-up sequence will be initiated if the input to the
UV pin rises above 2.5V or if the input to the OV pin falls
below 2.5V for a period of at least t

PDD

. The t

PDD

filter helps
prevent spurious start-up sequences while the card is
being inserted. If UV falls below 2.5V or OV rises above

2.5V, the PG and VGATE outputs will be shut down
immediately.

Under-/Over-Voltage Filtering

The SMH4804 may also be configured so that an out of
tolerance condition on UV/OV will not shut off the output
immediately. Instead, a filter delay may be inserted so
that only sustained under-voltage or over-voltage condi­tions will shut off the output. An out of tolerance condition
on UV/OV for longer than the filter delay time (t

UOFLTR

)
causes the VGATE and PG outputs to shut off when the
UV/OV filter option is enabled. The Under-/Over-Voltage
Filtering feature is disabled in the default configuration of
the device.

8

SMH4804

2050 3.0 10/01/01

Preliminary

SUMMIT MICROELECTRONICS, Inc.

TIMING RELATIONSHIPS

Figure 1 illustrates some of the power on sequences,
including the UV and OV differentials to their reference,
and Power Good cascading.

Figures 2, 3, 4, and 5 indicate the affect on the VGATE
signal caused by different Circuit Breaker inputs. In
Figure 2 RESET# and MODE are high; in Figure 3
MODE is high; in Figure 4 MODE is low. Figure 5 shows
the Quick Trip mode.

Figure 1. Power On Timing Sequence

2050 Fig01 2.1

V

DD

UV

OV

PD1#/
PD2#

VGATE

DRAIN

SENSE

2.5V

REF

2.5V

REF

11 ≤ VDD ≤ 13

t

PDD

PG1#

PG2#

PG3#

t

PGD

<t

PUVF

50mV

REF

<t

CBD

CBSENSE

5V

V

DD

VDD – V

GT

t

PGD

t

PGD

PG4#

9

2050 3.0 10/01/01

SMH4804

Preliminary

SUMMIT MICROELECTRONICS, Inc.

Under-/Over-Voltage Latching

An additional option for an out of tolerance condition on
UV/OV is to latch the VGATE and PG outputs off such that
a return to normal UV/OV operation will not turn them back
on. The FAULT# output will be set. Refer to the following
section titled "Resetting FAULT#".

Under-Voltage Hysteresis

The Under-Voltage comparator input may be configured
with a programmable level of hysteresis. The falling
voltage compare level may be set in steps of 62.5mV
below 2.5V. The rising voltage compare level is fixed at

2.5V. The default under-voltage hysteresis level is set to

62.5mV. In default conditions the SMH4804 is not in an
under-voltage state once the UV voltage rises above

2.5V; and after that an under-voltage occurrence is not
recognized until the UV voltage falls below 2.4375V (2.5V
– 62.5mV).

Soft Start Slew Rate Control

Once all of the preconditions for powering up the DC/DC
controllers have been met, the SMH4804 provides a
means to soft start the external power FET. It is important
to limit in-rush current to prevent damage to the add-in
card or disruptions to the host power supply. For example,
charging the filter capacitance (normally required at the
input of the DC/DC controllers) too quickly may generate
very high current. The VGATE output of the SMH4804 is
current limited to I

VGATE

, allowing the slew rate to be easily
modified using external passive components. The slew
rate may be found by dividing I

VGATE

by the gate-to-drain
capacitance placed on the external FET. A complete
design example is given in the Applications Section.

Load Control — Sequencing the Secondary Sup­plies

Once power has been ramped to the DC/DC controllers,
two conditions must be met before the PGn# outputs can
be enabled: the Drain Sense voltage must be below 2.5V,
and the VGATE voltage must be greater than VDD – VGT.
The Drain Sense input helps ensure that the power
MOSFET is not absorbing too much steady state power
from operating at a high VDS. This sensor remains active
at all times (except during the current regulation period).
The VGATE sensor makes sure that the power MOSFET
is operating well into its saturation region before allowing
the loads to be switched on. Once VGATE reaches V

DD

– VGT this sensor is latched.

When the external MOSFET is properly switched on the
PGn# outputs may be enabled (if ENPGA, ENPGB, and
ENPGC are all high). Output PG1# is activated first,

followed by PG2# after a delay of t

PGD

, PG3# after another

t

PGD

delay, and PG4# after a final t

PGD

delay. The delays
built into the SMH4804 allow timed sequencing of power
to the loads. The delay times are programmable from
50µs to 160ms.

Figure 2. PG Output and ENPG Input Relationship

Figure 3. Circuit Breaker Cycle Mode, RESET# High

CBSENSE

VGATE

T

CBD

T

CBD

T

CYC

2050 Fig03 1.0

50mV

2050 Fig02 2.1

PG1#

PG2#

PG3#

PG4#

ENPGA

ENPGC

ENPGB

t

PGD

t

PGD

t

PGD