SUMMIT S9418P, S9418S Datasheet

SUMMIT MICROELECTRONICS, Inc. • 300 Orchard City Drive, Suite 131 • Campbell, CA 95008 • Telephone [phone] • Fax [phone] • www.summitmicro.com

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© SUMMIT MICROELECTRONICS, Inc. 2000
2023 2.2 8/2/00

Characteristics subject to change without notice

SUMMIT

MICROELECTRONICS, Inc.

FEATURES

• Four 8-Bit DACs
— Differential Non-linearity: ±0.5LSB max

— Integral Non-Linearity Error: ±1LSB max

• Each DAC has Independent Reference Inputs
— Output Buffer Amplifiers Swing Rail-to-Rail

— Ground to VDD Reference Input Range

• Each DAC’s Digital Inputs Maintained in

EEPROM

• Power-On Reset Reloads Registers with Non-

volatile Data

• Simple Serial Interface for Reading and Writing

DAC values, SPI™ and QSPI™ compatible.

• Fully operational from 2.7V to 5.5V

• Low Power, 4mW max at +5V

Quad 8-Bit Nonvolatile DACPOT™ Electronic Potentiometer
With a Mute Control Input

S9418

OVERVIEW

The S9418 DACPOT™ is a serial input, voltage output,
quad 8-bit digital to analog converter (DAC). The S9418

operates from a single 2.7V to 5.5V supply. Internal
precision buffers swing rail-to-rail and the reference input

range includes both ground and the positive supply.
The S9418 integrates four 8-bit DACs and their associ-

ated circuits which include; an enhanced unity gain opera­tional amplifier output, an 8-bit data latch, an 8-bit non­volatile register and an industry standard serial interface
for reading and writing data to the DACs’ data latches and
registers. The DACs are independently programmable

and each has its own electrically isolated Vreference
inputs.

BLOCK DIAGRAM

V

REFH0

V

OUT0

18

2

8-Bit E2PROM

8-Bit Data Register

Serial

Data In

Serial Data Out

8-Bit DAC

AMP

V

DD

3

RDY/BSY#

4

V

REFL0

9

11

CS#

DI

7

6

MUTE

CLK

5

V

REFH1

V

OUT1

17

1

V

REFL1

12

V

REFH2

V

OUT2

16

20

V

REFL2

13

V

REFH3

V

OUT3

15

19

V

REFL3

14

DAC SECTION 0

DAC SECTION 1

DAC SECTION 2

DAC SECTION 3

DO

8

Memory Control

Programming

Memory

Controller

Control

Logic

GND 10

2

S9418

2023 2.2 8/2/00

The analog outputs of the S9418 can be programmed to
any one of 256 individual voltage steps. Each step value

is 1/256th of the voltage differential between V

REFH

and

V

REFL

of the respective DAC. Once programmed these

settings can be retained in nonvolatile memory during all
power conditions and will be automatically recalled upon
a power-up sequence. Each DAC can be independently
read without affecting the output voltage during the read
cycle. In addition each output can be adjusted an unlim­ited number of times without altering the value stored in
the nonvolatile memory.

DEVICE OPERATION

Analog Section

The S9418 is an 8-bit, voltage output digital-to-analog
converter (DAC). The DAC consists of a resistor network
that converts 8-bit digital inputs into equivalent analog

output voltages in proportion to the applied reference
voltage.

Reference inputs

The voltage differential between the V

REFL

and V

REFH

inputs sets the full-scale output voltage for its respective
DAC. V

REFL

must be equal to or greater than ground

(positive voltage). V

REFH

must be greater (more positive)

than V

REFL

or equal to VDD.

PINOUT and SIGNAL DEFINITION

Pin Name Function

1, 2 V

REFH

Vreference High:

19, 20 V

REFH

- VDD > V

REFL

3V

DD

Power Supply Voltage

4 RDY/ Ready/Busy#: open drain output

BSY# indicating status of nonvolatile

write operations

5 CLK Clock Input Pin: used for serial

data communication

6 CS# Chip Select: When high deselects

the device and places it in a low

power mode
7 DI Data Input: serial data input pin
8 DO Data Output: serial data output pin
9 MUTE When active forces V

OUT

to V

REFL

10 GND Power Supply Ground

11, 12 V

REFL

Vreference Low

13, 14
15, 16 V

OUT

DAC Output: buffered D to A

17, 18 converter output

Output Buffer Amplifiers

The voltage outputs are from precision unity-gain follow­ers that can slew up to 1V/µs. The outputs can swing from
V

REFL

to V

REFH

. With a 0V to 5V output transition the

amplifier outputs typically settle to 1LSB in 40µs.

DIGITAL INTERFACE

The S9418 employs a common 4-wire serial interface. It
is comprised of a Clock (CLK), Chip Select (CS#), Data

input (DI) and Data output (DO). Data is clocked into the
device on the clock’s rising edge and out of the device on
the clock’s falling edge. Data is shifted in and out MSB first.
DO only becomes active after the device has been se­lected and after a valid read command and address has
been received.

All data transfers are initiated after CS# goes low and a
logic ‘1’ is clocked into the device. This first data transfer

is the start bit and must precede all operations. Following
the start bit are two command bits used to specify which
of four commands to execute. The next two bits are the
address bits used to select one of the four DACs. The
action of the next eight clock cycles will be dependent
upon the command issued.

V

REFH1

V

REFH0

V

DD

RDY/BSY#

CLK

CS#

DI

DO

MUTE

GND

V

REFH2

V

REFH3

V

OUT0

V

OUT1

V

OUT2

V

OUT3

V

REFL3

V

REFL2

V

REFL1

V

REFL0

1
2
3
4
5
6
7
8
9
10

20
19
18
17
16
15
14
13
12
11

2023 T PCon 2.0

20-Pin PDIP

or 20-Pin SOIC

S9418

3

2023 2.2 8/2/00

Internally there are four DACs and associated with each
are two registers. There is one data register that is used

by the DAC to hold the digital value it converts. There is
also one nonvolatile register that holds the default value
that can be recalled into the data register during power­up or by executing the Recall command.

READ

Read operations are initiated by taking CS# low and
clocking in a start bit followed by the read command and

the address of the data register to be read. The next eight
clocks will output on the DO pin the contents of the

selected data register. This read will not affect the contents
of the register or the output of the DAC. Refer to Figure 1
for an illustration of the sequence of bus conditions for a
read operation.

WRITE

Write operations are initiated by taking CS# low and
clocking in a start bit followed by the write command and

the address of the data register to be written. This action
is followed by the host clocking eight bits of data into the
register, MSB first. The output of the selected DAC will
change as the last bit is clocked into the device. At this
point the clock counter will reset the command register,
requiring a full sequence to be initiated in order to write to

the DAC again. Refer to Figure 2 for an illustration of the
sequence of bus conditions for a write operation.

NOTE: This write operation does not affect the contents of
the nonvolatile register. Therefore, the nonvolatile register
can contain the power-on default settings (e.g. volume),
and the write DAC command can be used to make
situational adjustments.

FIGURE 1. READ SEQUENCE

TABLE 1.

tratSC1C

0

A1A

0

dnammoC

100AA elbanEetirWVN
10 1AA nIataD—etirW
110AA tuOataD—daeR
111AA llaceR

S
T
A
R
T

CACA

1100

CLK

DI

DO

Hi Z

DD

10345672

DDDDDD

Hi Z

2023 T fig01 2.0

RDY/BSY#

CS#

(Pulled up to VDD)