SUMMIT S9408P, S9408S Datasheet

SUMMIT

MICROELECTRONICS, Inc.

Serial Input, Quad 8-Bit Nonvolatile DACPOT™

S9408

FEATURES

• Four 8-Bit DACS
– Differential Non-linearity - ±0.5LSB max

– Integral Non-Linearity - ±1LSB max

• Each DAC has Independent Reference Inputs
– Output Buffer Amplifiers Swing Rail-to-Rail

– Ground to VDD Reference Input Range

• Each DAC’s Digital Input Data Maintained in
Nonvolatile EEPROM

• Power-On Reset Reloads Registers with
Nonvolatile Data

• Simple Serial Interface for Reading and Writing
DAC values, SPI™ and QSPI™ compatible.

• Fully operational from 2.7V to 5.5V

• Low Power: <1mW @ 2.7V

FUNCTIONAL BLOCK DIAGRAM

Memory Control

8-Bit E2PROM

OVERVIEW

The S9408 DACPOT™ is a serial input, voltage output,
quad 8-bit digital to analog converter. The S9408 oper-

ates from a single +2.7V to +5.5V supply. Internal preci­sion buffers swing rail-to-rail and the reference input
range includes both ground and the positive supply.

The S9408 integrates four 8-bit DACs and their associ­ated circuits which include an enhanced unity-gain opera-

tional amplifier output, an 8-bit data latch, an 8-bit non­volatile register, and an industry-standard serial interface
for reading and writing data to the DACs’ data latches and
registers. The DACs are independently programmable
and each has its own electrically isolated Vreference
inputs.

DAC SECTION 0

2

V

REFH0

V

DD

RDY/BSY#

CS#

CLK

00/REG#

GND 10

Serial

3

Programming

4

6
7

DI

5

9

Memory

Controller

Control

Logic

Data In

Serial Data Out

8-Bit Data Register

8-Bit DAC

DAC SECTION 1

DAC SECTION 2

DAC SECTION 3

AMP

2015 T BD 2.0

V

18

OUT0

11

V

REFL0

1

V

REFH1

V

17

OUT1

12

V

REFL1

20

V

REFH2

V

16

OUT2

13

V

REFL2

19

V

REFH3

V

15

OUT3

14

V

REFL3

8

DO

© SUMMIT MICROELECTRONICS, Inc. 2000 • 300 Orchard City Drive, Suite 131 • Campbell, CA 95008 • Phone [phone] • Fax [phone] • www.summitmicro.com

Characteristics subject to change without notice

2015 2.2 8/2/00

1

PINOUT and SIGNAL DEFINITION

S9408

Pin Name Function

V

REFH1

V

REFH0

V

DD

RDY/BSY#

CLK

CS#

DI

DO

00/REG#

GND

20-Pin PDIP

or 20-Pin SOIC

1
2
3
4
5
6
7
8
9
10

20
19
18
17
16
15
14
13
12
11

V

REFH2

V

REFH3

V

OUT0

V

OUT1

V

OUT2

V

OUT3

V

REFL3

V

REFL2

V

REFL1

V

REFL0

2015 T PCon 2.0

1, 2 V

REFH

20, 19 V

3V

DD

Vreference High:

REFL

< V

REFH

- V

DD

Power Supply Voltage

4 RDY/BSY# Ready/Busy: open drain output

indicating status of nonvolatile
write operations

5 CLK Clock Input Pin: used for serial

data communication

6 CS# Chip Select: When high deselects

the device and places it in a low

power mode
7 DI Data Input: serial data input pin
8 DO Data Output: serial data output pin

9 00/REG# Power On Recall Option Input

10 GND Power Supply Ground

11, 12 V

REFL

13, 14 V
15, 16 V

OUT

Vreference Low:

REFH

> V

REFL

• GND

DAC Output: buffered D to A

17, 18 converter output

The analog outputs of the S9408 can be programmed to
any one of 256 individual voltage steps. Each step value
is 1/256th of the voltage differential between V
V

of the respective DAC. Once programmed these

REFL

REFH

and

settings can be retained in nonvolatile memory during all
power conditions and will be automatically recalled upon
a power-up sequence. Each DAC can be independently
read without affecting the output voltage during the read

cycle. In addition, each output can be adjusted an unlim­ited number of times without altering the value stored in

the nonvolatile memory.

DEVICE OPERATION

Analog Section

The S9804 is an 8-bit, voltage output digital-to-analog
converter (DAC). The DAC consists of a resistor network
that converts 8-bit digital inputs into equivalent analog
output voltages in proportion to the applied reference
voltage.

Reference inputs

The voltage differential between the V

REFL

and V

REFH

inputs sets the full-scale output voltage for its respective
DAC. V
(positive voltage). V
than V

must be equal to or greater than ground

REFL

must be greater (more positive)

REFH

and less than or equal to VDD.

REFL

Output Buffer Amplifiers

The voltage outputs are precision unity-gain followers that
slew up to 1V/µs. The outputs can swing from V
V

. With a 0V to 5V output transition the amplifier

REFH

REFL

to

outputs typically settle to 1LSB in 40µs.

DIGITAL INTERFACE

The S9408 employs a common 4-wire serial interface. It
is comprised of a Clock (CLK), Chip Select (CS#), Data In

(DI) and Data Out (DO). Data is clocked into the device on
the clock’s rising edge and out of the device on the clock’s
falling edge. Data is shifted in and out MSB first. DO only
becomes active after the device has been selected and
after a valid read command and address has been re­ceived.

All data transfers are initiated after CS# goes low and a
logic ‘1’ is clocked into the device. This first data transfer
is the start bit and must precede all operations. Following
the start bit are two command bits used to specify which
of four commands to execute. The next two bits are the
address bits used to select one of the four DACs. The
action of the next eight clock cycles will be dependent
upon the command issued.

2

2015 2.2 8/2/00

SUMMIT MICROELECTRONICS, Inc.

S9408

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TABLE 1. COMMAND FORMAT

Internally there are four DACs and associated with each
are two registers. There is one data register that is used
by the DAC to hold the digital value it converts. There is

also one nonvolatile register that holds the default value
that can be recalled into the data register during power­up or by executing the Recall command.

READ

Read operations are initiated by taking CS# low and
clocking in a start bit followed by the read command and
the address of the data register to be read. The next eight
clocks will output on the DO pin the contents of the

selected data register. This read will not affect the contents
of the register or the output of the DAC. Refer to Figure 1
for an illustration of the sequence of bus conditions for a
read operation.

WRITE

Write operations are initiated by taking CS# low and
clocking in a start bit followed by the write command and
the address of the data register to be written. This action
is followed by the host clocking eight bits of data into the

register, MSB first. The output of the selected DAC will
change as the last bit is clocked into the device. At this
point the clock counter will reset the command register,
requiring a full sequence to be initiated in order to write to

the DAC again.

NOTE: This write operation does not affect the
contents of the nonvolatile register. Therefore, the
nonvolatile register can contain the power-on default
settings (e.g. volume), and the write DAC command
can be used to make situational adjustments.

Refer to Figure 2 for an illustration of the sequence of bus
conditions for a write operation.

CS#

CLK

DI

S
T
A
R
T

DO

RDY/BSY#

SUMMIT MICROELECTRONICS, Inc.

CACA

1100

Hi Z

(Pulled up to VDD)

FIGURE 1. READ SEQUENCE

DD

2015 2.2 8/2/00

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2015 T fig01 2.0

Hi Z

3